Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / f913fd6eb0c228041b77a645d76993760d3b1421 / . / llvm / test / CodeGen / AMDGPU / annotate-kernel-features-hsa-call.ll
blob: ca6739f5d37e24c6896cdf7256cf8cfc14cce829 [file] [log] [blame]
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]1; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=HSA %s
2
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]3declare i32 @llvm.amdgcn.workgroup.id.x() #0
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]4declare i32 @llvm.amdgcn.workgroup.id.y() #0
5declare i32 @llvm.amdgcn.workgroup.id.z() #0
6
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]7declare i32 @llvm.amdgcn.workitem.id.x() #0
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]8declare i32 @llvm.amdgcn.workitem.id.y() #0
9declare i32 @llvm.amdgcn.workitem.id.z() #0
10
Yaxun Liu0124b542018-02-13 18:00:25 +0000[diff] [blame]11declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
12declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
13declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
14declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]15declare i64 @llvm.amdgcn.dispatch.id() #0
16
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]17; HSA: define void @use_workitem_id_x() #1 {
18define void @use_workitem_id_x() #1 {
19 %val = call i32 @llvm.amdgcn.workitem.id.x()
20 store volatile i32 %val, i32 addrspace(1)* undef
21 ret void
22}
23
24; HSA: define void @use_workitem_id_y() #2 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]25define void @use_workitem_id_y() #1 {
26 %val = call i32 @llvm.amdgcn.workitem.id.y()
27 store volatile i32 %val, i32 addrspace(1)* undef
28 ret void
29}
30
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]31; HSA: define void @use_workitem_id_z() #3 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]32define void @use_workitem_id_z() #1 {
33 %val = call i32 @llvm.amdgcn.workitem.id.z()
34 store volatile i32 %val, i32 addrspace(1)* undef
35 ret void
36}
37
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]38; HSA: define void @use_workgroup_id_x() #4 {
39define void @use_workgroup_id_x() #1 {
40 %val = call i32 @llvm.amdgcn.workgroup.id.x()
41 store volatile i32 %val, i32 addrspace(1)* undef
42 ret void
43}
44
45; HSA: define void @use_workgroup_id_y() #5 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]46define void @use_workgroup_id_y() #1 {
47 %val = call i32 @llvm.amdgcn.workgroup.id.y()
48 store volatile i32 %val, i32 addrspace(1)* undef
49 ret void
50}
51
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]52; HSA: define void @use_workgroup_id_z() #6 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]53define void @use_workgroup_id_z() #1 {
54 %val = call i32 @llvm.amdgcn.workgroup.id.z()
55 store volatile i32 %val, i32 addrspace(1)* undef
56 ret void
57}
58
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]59; HSA: define void @use_dispatch_ptr() #7 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]60define void @use_dispatch_ptr() #1 {
Yaxun Liu0124b542018-02-13 18:00:25 +0000[diff] [blame]61 %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
62 store volatile i8 addrspace(4)* %dispatch.ptr, i8 addrspace(4)* addrspace(1)* undef
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]63 ret void
64}
65
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]66; HSA: define void @use_queue_ptr() #8 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]67define void @use_queue_ptr() #1 {
Yaxun Liu0124b542018-02-13 18:00:25 +0000[diff] [blame]68 %queue.ptr = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
69 store volatile i8 addrspace(4)* %queue.ptr, i8 addrspace(4)* addrspace(1)* undef
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]70 ret void
71}
72
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]73; HSA: define void @use_dispatch_id() #9 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]74define void @use_dispatch_id() #1 {
75 %val = call i64 @llvm.amdgcn.dispatch.id()
76 store volatile i64 %val, i64 addrspace(1)* undef
77 ret void
78}
79
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]80; HSA: define void @use_workgroup_id_y_workgroup_id_z() #10 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]81define void @use_workgroup_id_y_workgroup_id_z() #1 {
82 %val0 = call i32 @llvm.amdgcn.workgroup.id.y()
83 %val1 = call i32 @llvm.amdgcn.workgroup.id.z()
84 store volatile i32 %val0, i32 addrspace(1)* undef
85 store volatile i32 %val1, i32 addrspace(1)* undef
86 ret void
87}
88
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]89; HSA: define void @func_indirect_use_workitem_id_x() #1 {
90define void @func_indirect_use_workitem_id_x() #1 {
91 call void @use_workitem_id_x()
92 ret void
93}
94
95; HSA: define void @kernel_indirect_use_workitem_id_x() #1 {
96define void @kernel_indirect_use_workitem_id_x() #1 {
97 call void @use_workitem_id_x()
98 ret void
99}
100
101; HSA: define void @func_indirect_use_workitem_id_y() #2 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]102define void @func_indirect_use_workitem_id_y() #1 {
103 call void @use_workitem_id_y()
104 ret void
105}
106
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]107; HSA: define void @func_indirect_use_workitem_id_z() #3 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]108define void @func_indirect_use_workitem_id_z() #1 {
109 call void @use_workitem_id_z()
110 ret void
111}
112
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]113; HSA: define void @func_indirect_use_workgroup_id_x() #4 {
114define void @func_indirect_use_workgroup_id_x() #1 {
115 call void @use_workgroup_id_x()
116 ret void
117}
118
119; HSA: define void @kernel_indirect_use_workgroup_id_x() #4 {
120define void @kernel_indirect_use_workgroup_id_x() #1 {
121 call void @use_workgroup_id_x()
122 ret void
123}
124
125; HSA: define void @func_indirect_use_workgroup_id_y() #5 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]126define void @func_indirect_use_workgroup_id_y() #1 {
127 call void @use_workgroup_id_y()
128 ret void
129}
130
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]131; HSA: define void @func_indirect_use_workgroup_id_z() #6 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]132define void @func_indirect_use_workgroup_id_z() #1 {
133 call void @use_workgroup_id_z()
134 ret void
135}
136
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]137; HSA: define void @func_indirect_indirect_use_workgroup_id_y() #5 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]138define void @func_indirect_indirect_use_workgroup_id_y() #1 {
139 call void @func_indirect_use_workgroup_id_y()
140 ret void
141}
142
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]143; HSA: define void @indirect_x2_use_workgroup_id_y() #5 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]144define void @indirect_x2_use_workgroup_id_y() #1 {
145 call void @func_indirect_indirect_use_workgroup_id_y()
146 ret void
147}
148
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]149; HSA: define void @func_indirect_use_dispatch_ptr() #7 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]150define void @func_indirect_use_dispatch_ptr() #1 {
151 call void @use_dispatch_ptr()
152 ret void
153}
154
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]155; HSA: define void @func_indirect_use_queue_ptr() #8 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]156define void @func_indirect_use_queue_ptr() #1 {
157 call void @use_queue_ptr()
158 ret void
159}
160
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]161; HSA: define void @func_indirect_use_dispatch_id() #9 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]162define void @func_indirect_use_dispatch_id() #1 {
163 call void @use_dispatch_id()
164 ret void
165}
166
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]167; HSA: define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #11 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]168define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #1 {
169 call void @func_indirect_use_workgroup_id_y_workgroup_id_z()
170 ret void
171}
172
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]173; HSA: define void @recursive_use_workitem_id_y() #2 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]174define void @recursive_use_workitem_id_y() #1 {
175 %val = call i32 @llvm.amdgcn.workitem.id.y()
176 store volatile i32 %val, i32 addrspace(1)* undef
177 call void @recursive_use_workitem_id_y()
178 ret void
179}
180
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]181; HSA: define void @call_recursive_use_workitem_id_y() #2 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]182define void @call_recursive_use_workitem_id_y() #1 {
183 call void @recursive_use_workitem_id_y()
184 ret void
185}
186
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]187; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #8 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]188define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 {
Matt Arsenault72d27f52018-09-10 02:54:25 +0000[diff] [blame]189 %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
190 store volatile i32 0, i32 addrspace(4)* %stof
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]191 ret void
192}
193
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]194; HSA: define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #12 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]195define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 {
Matt Arsenault72d27f52018-09-10 02:54:25 +0000[diff] [blame]196 %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
197 store volatile i32 0, i32 addrspace(4)* %stof
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]198 ret void
199}
200
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]201; HSA: define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #13 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]202define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #2 {
Matt Arsenault72d27f52018-09-10 02:54:25 +0000[diff] [blame]203 %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
204 store volatile i32 0, i32 addrspace(4)* %stof
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]205 call void @func_indirect_use_queue_ptr()
206 ret void
207}
208
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]209; HSA: define void @indirect_use_group_to_flat_addrspacecast() #8 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]210define void @indirect_use_group_to_flat_addrspacecast() #1 {
211 call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null)
212 ret void
213}
214
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]215; HSA: define void @indirect_use_group_to_flat_addrspacecast_gfx9() #11 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]216define void @indirect_use_group_to_flat_addrspacecast_gfx9() #1 {
217 call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null)
218 ret void
219}
220
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]221; HSA: define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #8 {
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]222define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #1 {
223 call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null)
224 ret void
225}
226
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]227; HSA: define void @use_kernarg_segment_ptr() #14 {
Matt Arsenault23e4df62017-07-14 00:11:13 +0000[diff] [blame]228define void @use_kernarg_segment_ptr() #1 {
Yaxun Liu0124b542018-02-13 18:00:25 +0000[diff] [blame]229 %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
230 store volatile i8 addrspace(4)* %kernarg.segment.ptr, i8 addrspace(4)* addrspace(1)* undef
Matt Arsenault23e4df62017-07-14 00:11:13 +0000[diff] [blame]231 ret void
232}
233
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]234; HSA: define void @func_indirect_use_kernarg_segment_ptr() #14 {
Matt Arsenault23e4df62017-07-14 00:11:13 +0000[diff] [blame]235define void @func_indirect_use_kernarg_segment_ptr() #1 {
236 call void @use_kernarg_segment_ptr()
237 ret void
238}
239
Matt Arsenault9166ce82017-07-28 15:52:08 +0000[diff] [blame]240; HSA: define amdgpu_kernel void @kern_use_implicitarg_ptr() #15 {
241define amdgpu_kernel void @kern_use_implicitarg_ptr() #1 {
Yaxun Liu0124b542018-02-13 18:00:25 +0000[diff] [blame]242 %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
243 store volatile i8 addrspace(4)* %implicitarg.ptr, i8 addrspace(4)* addrspace(1)* undef
Matt Arsenault9166ce82017-07-28 15:52:08 +0000[diff] [blame]244 ret void
245}
246
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]247; HSA: define void @use_implicitarg_ptr() #16 {
Matt Arsenault23e4df62017-07-14 00:11:13 +0000[diff] [blame]248define void @use_implicitarg_ptr() #1 {
Yaxun Liu0124b542018-02-13 18:00:25 +0000[diff] [blame]249 %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
250 store volatile i8 addrspace(4)* %implicitarg.ptr, i8 addrspace(4)* addrspace(1)* undef
Matt Arsenault23e4df62017-07-14 00:11:13 +0000[diff] [blame]251 ret void
252}
253
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]254; HSA: define void @func_indirect_use_implicitarg_ptr() #16 {
Matt Arsenault23e4df62017-07-14 00:11:13 +0000[diff] [blame]255define void @func_indirect_use_implicitarg_ptr() #1 {
256 call void @use_implicitarg_ptr()
257 ret void
258}
259
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]260; HSA: declare void @external.func() #17
Matt Arsenault254ad3d2017-07-18 16:44:58 +0000[diff] [blame]261declare void @external.func() #3
262
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]263; HSA: define internal void @defined.func() #17 {
Matt Arsenault254ad3d2017-07-18 16:44:58 +0000[diff] [blame]264define internal void @defined.func() #3 {
265 ret void
266}
267
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]268; HSA: define void @func_call_external() #17 {
Matt Arsenault254ad3d2017-07-18 16:44:58 +0000[diff] [blame]269define void @func_call_external() #3 {
270 call void @external.func()
271 ret void
272}
273
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]274; HSA: define void @func_call_defined() #17 {
Matt Arsenault254ad3d2017-07-18 16:44:58 +0000[diff] [blame]275define void @func_call_defined() #3 {
276 call void @defined.func()
277 ret void
278}
279
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]280; HSA: define void @func_call_asm() #18 {
Matt Arsenault254ad3d2017-07-18 16:44:58 +0000[diff] [blame]281define void @func_call_asm() #3 {
282 call void asm sideeffect "", ""() #3
283 ret void
284}
285
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]286; HSA: define amdgpu_kernel void @kern_call_external() #19 {
Matt Arsenault254ad3d2017-07-18 16:44:58 +0000[diff] [blame]287define amdgpu_kernel void @kern_call_external() #3 {
288 call void @external.func()
289 ret void
290}
291
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]292; HSA: define amdgpu_kernel void @func_kern_defined() #19 {
Matt Arsenault254ad3d2017-07-18 16:44:58 +0000[diff] [blame]293define amdgpu_kernel void @func_kern_defined() #3 {
294 call void @defined.func()
295 ret void
296}
297
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]298attributes #0 = { nounwind readnone speculatable }
299attributes #1 = { nounwind "target-cpu"="fiji" }
300attributes #2 = { nounwind "target-cpu"="gfx900" }
Matt Arsenault254ad3d2017-07-18 16:44:58 +0000[diff] [blame]301attributes #3 = { nounwind }
Matt Arsenault6b930462017-07-13 21:43:42 +0000[diff] [blame]302
303; HSA: attributes #0 = { nounwind readnone speculatable }
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]304; HSA: attributes #1 = { nounwind "amdgpu-work-item-id-x" "target-cpu"="fiji" "uniform-work-group-size"="false" }
305; HSA: attributes #2 = { nounwind "amdgpu-work-item-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" }
306; HSA: attributes #3 = { nounwind "amdgpu-work-item-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
307; HSA: attributes #4 = { nounwind "amdgpu-work-group-id-x" "target-cpu"="fiji" "uniform-work-group-size"="false" }
308; HSA: attributes #5 = { nounwind "amdgpu-work-group-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" }
309; HSA: attributes #6 = { nounwind "amdgpu-work-group-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
310; HSA: attributes #7 = { nounwind "amdgpu-dispatch-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" }
311; HSA: attributes #8 = { nounwind "amdgpu-queue-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" }
312; HSA: attributes #9 = { nounwind "amdgpu-dispatch-id" "target-cpu"="fiji" "uniform-work-group-size"="false" }
Matt Arsenaulte15855d2017-07-17 22:35:50 +0000[diff] [blame]313; HSA: attributes #10 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "target-cpu"="fiji" }
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]314; HSA: attributes #11 = { nounwind "target-cpu"="fiji" "uniform-work-group-size"="false" }
315; HSA: attributes #12 = { nounwind "target-cpu"="gfx900" "uniform-work-group-size"="false" }
316; HSA: attributes #13 = { nounwind "amdgpu-queue-ptr" "target-cpu"="gfx900" "uniform-work-group-size"="false" }
317; HSA: attributes #14 = { nounwind "amdgpu-kernarg-segment-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" }
Matt Arsenault9166ce82017-07-28 15:52:08 +0000[diff] [blame]318; HSA: attributes #15 = { nounwind "amdgpu-implicitarg-ptr" "target-cpu"="fiji" }
Aakanksha Patilc56d2af2019-03-07 00:54:04 +0000[diff] [blame]319; HSA: attributes #16 = { nounwind "amdgpu-implicitarg-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" }
320; HSA: attributes #17 = { nounwind "uniform-work-group-size"="false" }
321; HSA: attributes #18 = { nounwind }
322; HSA: attributes #19 = { nounwind "amdgpu-flat-scratch" "uniform-work-group-size"="false" }