Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 1 | ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s |
| 2 | ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s |
Tom Stellard | 4489b85 | 2013-05-03 17:21:31 +0000 | [diff] [blame] | 3 | |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 4 | ; EG-LABEL: @or_v2i32 |
| 5 | ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} |
| 6 | ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} |
Tom Stellard | 4489b85 | 2013-05-03 17:21:31 +0000 | [diff] [blame] | 7 | |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 8 | ; SI-LABEL: @or_v2i32 |
| 9 | ; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} |
| 10 | ; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} |
Aaron Watry | 2fa162e | 2013-06-25 13:55:29 +0000 | [diff] [blame] | 11 | |
| 12 | define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { |
| 13 | %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 |
| 14 | %a = load <2 x i32> addrspace(1) * %in |
| 15 | %b = load <2 x i32> addrspace(1) * %b_ptr |
| 16 | %result = or <2 x i32> %a, %b |
| 17 | store <2 x i32> %result, <2 x i32> addrspace(1)* %out |
| 18 | ret void |
| 19 | } |
| 20 | |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 21 | ; EG-LABEL: @or_v4i32 |
| 22 | ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} |
| 23 | ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} |
| 24 | ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} |
| 25 | ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} |
Aaron Watry | 2fa162e | 2013-06-25 13:55:29 +0000 | [diff] [blame] | 26 | |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 27 | ; SI-LABEL: @or_v4i32 |
| 28 | ; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} |
| 29 | ; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} |
| 30 | ; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} |
| 31 | ; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} |
Aaron Watry | 2fa162e | 2013-06-25 13:55:29 +0000 | [diff] [blame] | 32 | |
| 33 | define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { |
| 34 | %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 |
| 35 | %a = load <4 x i32> addrspace(1) * %in |
| 36 | %b = load <4 x i32> addrspace(1) * %b_ptr |
Tom Stellard | 4489b85 | 2013-05-03 17:21:31 +0000 | [diff] [blame] | 37 | %result = or <4 x i32> %a, %b |
| 38 | store <4 x i32> %result, <4 x i32> addrspace(1)* %out |
| 39 | ret void |
| 40 | } |
Tom Stellard | fb96169 | 2013-10-23 00:44:19 +0000 | [diff] [blame] | 41 | |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 42 | ; SI-LABEL: @scalar_or_i32 |
| 43 | ; SI: S_OR_B32 |
Matt Arsenault | 8e2581b | 2014-03-21 18:01:18 +0000 | [diff] [blame] | 44 | define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { |
| 45 | %or = or i32 %a, %b |
| 46 | store i32 %or, i32 addrspace(1)* %out |
| 47 | ret void |
| 48 | } |
| 49 | |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 50 | ; SI-LABEL: @vector_or_i32 |
| 51 | ; SI: V_OR_B32_e32 v{{[0-9]}} |
Matt Arsenault | 8e2581b | 2014-03-21 18:01:18 +0000 | [diff] [blame] | 52 | define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) { |
| 53 | %loada = load i32 addrspace(1)* %a |
| 54 | %or = or i32 %loada, %b |
| 55 | store i32 %or, i32 addrspace(1)* %out |
| 56 | ret void |
| 57 | } |
| 58 | |
Matt Arsenault | fabf545 | 2014-08-15 18:42:22 +0000 | [diff] [blame^] | 59 | ; SI-LABEL: @scalar_or_literal_i32 |
| 60 | ; SI: S_OR_B32 s0, s0, 0x1869f |
| 61 | define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) { |
| 62 | %or = or i32 %a, 99999 |
| 63 | store i32 %or, i32 addrspace(1)* %out, align 4 |
| 64 | ret void |
| 65 | } |
| 66 | |
| 67 | ; SI-LABEL: @vector_or_literal_i32 |
| 68 | ; SI: V_OR_B32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}} |
| 69 | define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) { |
| 70 | %loada = load i32 addrspace(1)* %a, align 4 |
| 71 | %or = or i32 %loada, 65535 |
| 72 | store i32 %or, i32 addrspace(1)* %out, align 4 |
| 73 | ret void |
| 74 | } |
| 75 | |
| 76 | ; SI-LABEL: @vector_or_inline_immediate_i32 |
| 77 | ; SI: V_OR_B32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}} |
| 78 | define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) { |
| 79 | %loada = load i32 addrspace(1)* %a, align 4 |
| 80 | %or = or i32 %loada, 4 |
| 81 | store i32 %or, i32 addrspace(1)* %out, align 4 |
| 82 | ret void |
| 83 | } |
| 84 | |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 85 | ; EG-LABEL: @scalar_or_i64 |
| 86 | ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y |
| 87 | ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z |
| 88 | ; SI-LABEL: @scalar_or_i64 |
| 89 | ; SI: S_OR_B64 |
Matt Arsenault | f35182c | 2014-03-24 20:08:05 +0000 | [diff] [blame] | 90 | define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { |
| 91 | %or = or i64 %a, %b |
| 92 | store i64 %or, i64 addrspace(1)* %out |
| 93 | ret void |
| 94 | } |
| 95 | |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 96 | ; SI-LABEL: @vector_or_i64 |
| 97 | ; SI: V_OR_B32_e32 v{{[0-9]}} |
| 98 | ; SI: V_OR_B32_e32 v{{[0-9]}} |
Matt Arsenault | f35182c | 2014-03-24 20:08:05 +0000 | [diff] [blame] | 99 | define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { |
| 100 | %loada = load i64 addrspace(1)* %a, align 8 |
| 101 | %loadb = load i64 addrspace(1)* %a, align 8 |
| 102 | %or = or i64 %loada, %loadb |
| 103 | store i64 %or, i64 addrspace(1)* %out |
| 104 | ret void |
| 105 | } |
| 106 | |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 107 | ; SI-LABEL: @scalar_vector_or_i64 |
| 108 | ; SI: V_OR_B32_e32 v{{[0-9]}} |
| 109 | ; SI: V_OR_B32_e32 v{{[0-9]}} |
Matt Arsenault | f35182c | 2014-03-24 20:08:05 +0000 | [diff] [blame] | 110 | define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) { |
| 111 | %loada = load i64 addrspace(1)* %a |
| 112 | %or = or i64 %loada, %b |
| 113 | store i64 %or, i64 addrspace(1)* %out |
| 114 | ret void |
Tom Stellard | fb96169 | 2013-10-23 00:44:19 +0000 | [diff] [blame] | 115 | } |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 116 | |
| 117 | ; SI-LABEL: @vector_or_i64_loadimm |
Matt Arsenault | 4d7d383 | 2014-04-15 22:32:49 +0000 | [diff] [blame] | 118 | ; SI-DAG: S_MOV_B32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f |
| 119 | ; SI-DAG: S_MOV_B32 [[HI_S_IMM:s[0-9]+]], 0x146f |
Matt Arsenault | 684dc80 | 2014-03-24 20:08:13 +0000 | [diff] [blame] | 120 | ; SI-DAG: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, |
| 121 | ; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] |
| 122 | ; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] |
Matt Arsenault | 248b7b6 | 2014-03-24 20:08:09 +0000 | [diff] [blame] | 123 | ; SI: S_ENDPGM |
| 124 | define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { |
| 125 | %loada = load i64 addrspace(1)* %a, align 8 |
| 126 | %or = or i64 %loada, 22470723082367 |
| 127 | store i64 %or, i64 addrspace(1)* %out |
| 128 | ret void |
| 129 | } |
| 130 | |
| 131 | ; FIXME: The or 0 should really be removed. |
| 132 | ; SI-LABEL: @vector_or_i64_imm |
| 133 | ; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, |
| 134 | ; SI: V_OR_B32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]] |
| 135 | ; SI: V_OR_B32_e32 {{v[0-9]+}}, 0, {{.*}} |
| 136 | ; SI: S_ENDPGM |
| 137 | define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { |
| 138 | %loada = load i64 addrspace(1)* %a, align 8 |
| 139 | %or = or i64 %loada, 8 |
| 140 | store i64 %or, i64 addrspace(1)* %out |
| 141 | ret void |
| 142 | } |
Matt Arsenault | b517c81 | 2014-03-27 17:23:31 +0000 | [diff] [blame] | 143 | |
| 144 | ; SI-LABEL: @trunc_i64_or_to_i32 |
Chandler Carruth | 9f4530b | 2014-07-24 22:15:28 +0000 | [diff] [blame] | 145 | ; SI: S_LOAD_DWORD s[[SREG0:[0-9]+]] |
| 146 | ; SI: S_LOAD_DWORD s[[SREG1:[0-9]+]] |
| 147 | ; SI: S_OR_B32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]] |
| 148 | ; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]] |
Matt Arsenault | b517c81 | 2014-03-27 17:23:31 +0000 | [diff] [blame] | 149 | ; SI: BUFFER_STORE_DWORD [[VRESULT]], |
| 150 | define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { |
| 151 | %add = or i64 %b, %a |
| 152 | %trunc = trunc i64 %add to i32 |
| 153 | store i32 %trunc, i32 addrspace(1)* %out, align 8 |
| 154 | ret void |
| 155 | } |
Matt Arsenault | 0d89e84 | 2014-07-15 21:44:37 +0000 | [diff] [blame] | 156 | |
| 157 | ; EG-CHECK: @or_i1 |
| 158 | ; EG-CHECK: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}} |
| 159 | |
| 160 | ; SI-CHECK: @or_i1 |
| 161 | ; SI-CHECK: S_OR_B64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] |
| 162 | define void @or_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) { |
| 163 | %a = load float addrspace(1) * %in0 |
| 164 | %b = load float addrspace(1) * %in1 |
| 165 | %acmp = fcmp oge float %a, 0.000000e+00 |
| 166 | %bcmp = fcmp oge float %b, 0.000000e+00 |
| 167 | %or = or i1 %acmp, %bcmp |
| 168 | %result = select i1 %or, float %a, float %b |
| 169 | store float %result, float addrspace(1)* %out |
| 170 | ret void |
| 171 | } |