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Ahmed Bougacha6756a2c2016-07-27 14:31:55 +00001//===- AArch64InstructionSelector.cpp ----------------------------*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the targeting of the InstructionSelector class for
11/// AArch64.
12/// \todo This should be generated by TableGen.
13//===----------------------------------------------------------------------===//
14
15#include "AArch64InstructionSelector.h"
16#include "AArch64InstrInfo.h"
17#include "AArch64RegisterBankInfo.h"
18#include "AArch64RegisterInfo.h"
19#include "AArch64Subtarget.h"
Tim Northoverbdf16242016-10-10 21:50:00 +000020#include "AArch64TargetMachine.h"
Tim Northover9ac0eba2016-11-08 00:45:29 +000021#include "MCTargetDesc/AArch64AddressingModes.h"
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +000022#include "llvm/CodeGen/MachineBasicBlock.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstr.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/IR/Type.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/raw_ostream.h"
30
31#define DEBUG_TYPE "aarch64-isel"
32
33using namespace llvm;
34
35#ifndef LLVM_BUILD_GLOBAL_ISEL
36#error "You shouldn't build this"
37#endif
38
39AArch64InstructionSelector::AArch64InstructionSelector(
Tim Northoverbdf16242016-10-10 21:50:00 +000040 const AArch64TargetMachine &TM, const AArch64Subtarget &STI,
41 const AArch64RegisterBankInfo &RBI)
42 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +000043 TRI(*STI.getRegisterInfo()), RBI(RBI) {}
44
Tim Northoverfb8d9892016-10-12 22:49:15 +000045// FIXME: This should be target-independent, inferred from the types declared
46// for each class in the bank.
47static const TargetRegisterClass *
48getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
49 const RegisterBankInfo &RBI) {
50 if (RB.getID() == AArch64::GPRRegBankID) {
51 if (Ty.getSizeInBits() <= 32)
52 return &AArch64::GPR32RegClass;
53 if (Ty.getSizeInBits() == 64)
54 return &AArch64::GPR64RegClass;
55 return nullptr;
56 }
57
58 if (RB.getID() == AArch64::FPRRegBankID) {
59 if (Ty.getSizeInBits() == 32)
60 return &AArch64::FPR32RegClass;
61 if (Ty.getSizeInBits() == 64)
62 return &AArch64::FPR64RegClass;
63 if (Ty.getSizeInBits() == 128)
64 return &AArch64::FPR128RegClass;
65 return nullptr;
66 }
67
68 return nullptr;
69}
70
Ahmed Bougacha59e160a2016-08-16 14:37:40 +000071/// Check whether \p I is a currently unsupported binary operation:
72/// - it has an unsized type
73/// - an operand is not a vreg
74/// - all operands are not in the same bank
75/// These are checks that should someday live in the verifier, but right now,
76/// these are mostly limitations of the aarch64 selector.
77static bool unsupportedBinOp(const MachineInstr &I,
78 const AArch64RegisterBankInfo &RBI,
79 const MachineRegisterInfo &MRI,
80 const AArch64RegisterInfo &TRI) {
Tim Northover0f140c72016-09-09 11:46:34 +000081 LLT Ty = MRI.getType(I.getOperand(0).getReg());
Tim Northover32a078a2016-09-15 10:09:59 +000082 if (!Ty.isValid()) {
83 DEBUG(dbgs() << "Generic binop register should be typed\n");
Ahmed Bougacha59e160a2016-08-16 14:37:40 +000084 return true;
85 }
86
87 const RegisterBank *PrevOpBank = nullptr;
88 for (auto &MO : I.operands()) {
89 // FIXME: Support non-register operands.
90 if (!MO.isReg()) {
91 DEBUG(dbgs() << "Generic inst non-reg operands are unsupported\n");
92 return true;
93 }
94
95 // FIXME: Can generic operations have physical registers operands? If
96 // so, this will need to be taught about that, and we'll need to get the
97 // bank out of the minimal class for the register.
98 // Either way, this needs to be documented (and possibly verified).
99 if (!TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
100 DEBUG(dbgs() << "Generic inst has physical register operand\n");
101 return true;
102 }
103
104 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
105 if (!OpBank) {
106 DEBUG(dbgs() << "Generic register has no bank or class\n");
107 return true;
108 }
109
110 if (PrevOpBank && OpBank != PrevOpBank) {
111 DEBUG(dbgs() << "Generic inst operands have different banks\n");
112 return true;
113 }
114 PrevOpBank = OpBank;
115 }
116 return false;
117}
118
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000119/// Select the AArch64 opcode for the basic binary operation \p GenericOpc
120/// (such as G_OR or G_ADD), appropriate for the register bank \p RegBankID
121/// and of size \p OpSize.
122/// \returns \p GenericOpc if the combination is unsupported.
123static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
124 unsigned OpSize) {
125 switch (RegBankID) {
126 case AArch64::GPRRegBankID:
Tim Northover55782222016-10-18 20:03:48 +0000127 if (OpSize <= 32) {
128 assert((OpSize == 32 || (GenericOpc != TargetOpcode::G_SDIV &&
129 GenericOpc != TargetOpcode::G_UDIV &&
130 GenericOpc != TargetOpcode::G_LSHR &&
131 GenericOpc != TargetOpcode::G_ASHR)) &&
132 "operation should have been legalized before now");
133
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000134 switch (GenericOpc) {
135 case TargetOpcode::G_OR:
136 return AArch64::ORRWrr;
Ahmed Bougacha6db3cfe2016-07-29 16:56:25 +0000137 case TargetOpcode::G_XOR:
138 return AArch64::EORWrr;
Ahmed Bougacha61a79282016-07-28 16:58:31 +0000139 case TargetOpcode::G_AND:
140 return AArch64::ANDWrr;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000141 case TargetOpcode::G_ADD:
142 return AArch64::ADDWrr;
Ahmed Bougachad7748d62016-07-28 16:58:35 +0000143 case TargetOpcode::G_SUB:
144 return AArch64::SUBWrr;
Ahmed Bougacha2ac5bf92016-08-16 14:02:47 +0000145 case TargetOpcode::G_SHL:
146 return AArch64::LSLVWr;
147 case TargetOpcode::G_LSHR:
148 return AArch64::LSRVWr;
149 case TargetOpcode::G_ASHR:
150 return AArch64::ASRVWr;
Ahmed Bougacha1d0560b2016-08-18 15:17:13 +0000151 case TargetOpcode::G_SDIV:
152 return AArch64::SDIVWr;
153 case TargetOpcode::G_UDIV:
154 return AArch64::UDIVWr;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000155 default:
156 return GenericOpc;
157 }
Tim Northover55782222016-10-18 20:03:48 +0000158 } else if (OpSize == 64) {
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000159 switch (GenericOpc) {
160 case TargetOpcode::G_OR:
161 return AArch64::ORRXrr;
Ahmed Bougacha6db3cfe2016-07-29 16:56:25 +0000162 case TargetOpcode::G_XOR:
163 return AArch64::EORXrr;
Ahmed Bougacha61a79282016-07-28 16:58:31 +0000164 case TargetOpcode::G_AND:
165 return AArch64::ANDXrr;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000166 case TargetOpcode::G_ADD:
Tim Northover2fda4b02016-10-10 21:49:49 +0000167 case TargetOpcode::G_GEP:
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000168 return AArch64::ADDXrr;
Ahmed Bougachad7748d62016-07-28 16:58:35 +0000169 case TargetOpcode::G_SUB:
170 return AArch64::SUBXrr;
Ahmed Bougacha2ac5bf92016-08-16 14:02:47 +0000171 case TargetOpcode::G_SHL:
172 return AArch64::LSLVXr;
173 case TargetOpcode::G_LSHR:
174 return AArch64::LSRVXr;
175 case TargetOpcode::G_ASHR:
176 return AArch64::ASRVXr;
Ahmed Bougacha1d0560b2016-08-18 15:17:13 +0000177 case TargetOpcode::G_SDIV:
178 return AArch64::SDIVXr;
179 case TargetOpcode::G_UDIV:
180 return AArch64::UDIVXr;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000181 default:
182 return GenericOpc;
183 }
184 }
Ahmed Bougacha33e19fe2016-08-18 16:05:11 +0000185 case AArch64::FPRRegBankID:
186 switch (OpSize) {
187 case 32:
188 switch (GenericOpc) {
189 case TargetOpcode::G_FADD:
190 return AArch64::FADDSrr;
191 case TargetOpcode::G_FSUB:
192 return AArch64::FSUBSrr;
193 case TargetOpcode::G_FMUL:
194 return AArch64::FMULSrr;
195 case TargetOpcode::G_FDIV:
196 return AArch64::FDIVSrr;
197 default:
198 return GenericOpc;
199 }
200 case 64:
201 switch (GenericOpc) {
202 case TargetOpcode::G_FADD:
203 return AArch64::FADDDrr;
204 case TargetOpcode::G_FSUB:
205 return AArch64::FSUBDrr;
206 case TargetOpcode::G_FMUL:
207 return AArch64::FMULDrr;
208 case TargetOpcode::G_FDIV:
209 return AArch64::FDIVDrr;
Quentin Colombet0e531272016-10-11 00:21:11 +0000210 case TargetOpcode::G_OR:
211 return AArch64::ORRv8i8;
Ahmed Bougacha33e19fe2016-08-18 16:05:11 +0000212 default:
213 return GenericOpc;
214 }
215 }
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000216 };
217 return GenericOpc;
218}
219
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000220/// Select the AArch64 opcode for the G_LOAD or G_STORE operation \p GenericOpc,
221/// appropriate for the (value) register bank \p RegBankID and of memory access
222/// size \p OpSize. This returns the variant with the base+unsigned-immediate
223/// addressing mode (e.g., LDRXui).
224/// \returns \p GenericOpc if the combination is unsupported.
225static unsigned selectLoadStoreUIOp(unsigned GenericOpc, unsigned RegBankID,
226 unsigned OpSize) {
227 const bool isStore = GenericOpc == TargetOpcode::G_STORE;
228 switch (RegBankID) {
229 case AArch64::GPRRegBankID:
230 switch (OpSize) {
Tim Northover020d1042016-10-17 18:36:53 +0000231 case 8:
232 return isStore ? AArch64::STRBBui : AArch64::LDRBBui;
233 case 16:
234 return isStore ? AArch64::STRHHui : AArch64::LDRHHui;
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000235 case 32:
236 return isStore ? AArch64::STRWui : AArch64::LDRWui;
237 case 64:
238 return isStore ? AArch64::STRXui : AArch64::LDRXui;
239 }
Quentin Colombetd2623f8e2016-10-11 00:21:14 +0000240 case AArch64::FPRRegBankID:
241 switch (OpSize) {
Tim Northover020d1042016-10-17 18:36:53 +0000242 case 8:
243 return isStore ? AArch64::STRBui : AArch64::LDRBui;
244 case 16:
245 return isStore ? AArch64::STRHui : AArch64::LDRHui;
Quentin Colombetd2623f8e2016-10-11 00:21:14 +0000246 case 32:
247 return isStore ? AArch64::STRSui : AArch64::LDRSui;
248 case 64:
249 return isStore ? AArch64::STRDui : AArch64::LDRDui;
250 }
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000251 };
252 return GenericOpc;
253}
254
Quentin Colombetcb629a82016-10-12 03:57:49 +0000255static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
256 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
257 const RegisterBankInfo &RBI) {
258
259 unsigned DstReg = I.getOperand(0).getReg();
260 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
261 assert(I.isCopy() && "Generic operators do not allow physical registers");
262 return true;
263 }
264
265 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
266 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
267 unsigned SrcReg = I.getOperand(1).getReg();
268 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
269 (void)SrcSize;
270 assert((!TargetRegisterInfo::isPhysicalRegister(SrcReg) || I.isCopy()) &&
271 "No phys reg on generic operators");
272 assert(
273 (DstSize == SrcSize ||
274 // Copies are a mean to setup initial types, the number of
275 // bits may not exactly match.
276 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
277 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI)) ||
278 // Copies are a mean to copy bits around, as long as we are
279 // on the same register class, that's fine. Otherwise, that
280 // means we need some SUBREG_TO_REG or AND & co.
281 (((DstSize + 31) / 32 == (SrcSize + 31) / 32) && DstSize > SrcSize)) &&
282 "Copy with different width?!");
283 assert((DstSize <= 64 || RegBank.getID() == AArch64::FPRRegBankID) &&
284 "GPRs cannot get more than 64-bit width values");
285 const TargetRegisterClass *RC = nullptr;
286
287 if (RegBank.getID() == AArch64::FPRRegBankID) {
288 if (DstSize <= 32)
289 RC = &AArch64::FPR32RegClass;
290 else if (DstSize <= 64)
291 RC = &AArch64::FPR64RegClass;
292 else if (DstSize <= 128)
293 RC = &AArch64::FPR128RegClass;
294 else {
295 DEBUG(dbgs() << "Unexpected bitcast size " << DstSize << '\n');
296 return false;
297 }
298 } else {
299 assert(RegBank.getID() == AArch64::GPRRegBankID &&
300 "Bitcast for the flags?");
301 RC =
302 DstSize <= 32 ? &AArch64::GPR32allRegClass : &AArch64::GPR64allRegClass;
303 }
304
305 // No need to constrain SrcReg. It will get constrained when
306 // we hit another of its use or its defs.
307 // Copies do not have constraints.
308 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
309 DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
310 << " operand\n");
311 return false;
312 }
313 I.setDesc(TII.get(AArch64::COPY));
314 return true;
315}
316
Tim Northover69271c62016-10-12 22:49:11 +0000317static unsigned selectFPConvOpc(unsigned GenericOpc, LLT DstTy, LLT SrcTy) {
318 if (!DstTy.isScalar() || !SrcTy.isScalar())
319 return GenericOpc;
320
321 const unsigned DstSize = DstTy.getSizeInBits();
322 const unsigned SrcSize = SrcTy.getSizeInBits();
323
324 switch (DstSize) {
325 case 32:
326 switch (SrcSize) {
327 case 32:
328 switch (GenericOpc) {
329 case TargetOpcode::G_SITOFP:
330 return AArch64::SCVTFUWSri;
331 case TargetOpcode::G_UITOFP:
332 return AArch64::UCVTFUWSri;
333 case TargetOpcode::G_FPTOSI:
334 return AArch64::FCVTZSUWSr;
335 case TargetOpcode::G_FPTOUI:
336 return AArch64::FCVTZUUWSr;
337 default:
338 return GenericOpc;
339 }
340 case 64:
341 switch (GenericOpc) {
342 case TargetOpcode::G_SITOFP:
343 return AArch64::SCVTFUXSri;
344 case TargetOpcode::G_UITOFP:
345 return AArch64::UCVTFUXSri;
346 case TargetOpcode::G_FPTOSI:
347 return AArch64::FCVTZSUWDr;
348 case TargetOpcode::G_FPTOUI:
349 return AArch64::FCVTZUUWDr;
350 default:
351 return GenericOpc;
352 }
353 default:
354 return GenericOpc;
355 }
356 case 64:
357 switch (SrcSize) {
358 case 32:
359 switch (GenericOpc) {
360 case TargetOpcode::G_SITOFP:
361 return AArch64::SCVTFUWDri;
362 case TargetOpcode::G_UITOFP:
363 return AArch64::UCVTFUWDri;
364 case TargetOpcode::G_FPTOSI:
365 return AArch64::FCVTZSUXSr;
366 case TargetOpcode::G_FPTOUI:
367 return AArch64::FCVTZUUXSr;
368 default:
369 return GenericOpc;
370 }
371 case 64:
372 switch (GenericOpc) {
373 case TargetOpcode::G_SITOFP:
374 return AArch64::SCVTFUXDri;
375 case TargetOpcode::G_UITOFP:
376 return AArch64::UCVTFUXDri;
377 case TargetOpcode::G_FPTOSI:
378 return AArch64::FCVTZSUXDr;
379 case TargetOpcode::G_FPTOUI:
380 return AArch64::FCVTZUUXDr;
381 default:
382 return GenericOpc;
383 }
384 default:
385 return GenericOpc;
386 }
387 default:
388 return GenericOpc;
389 };
390 return GenericOpc;
391}
392
Tim Northover6c02ad52016-10-12 22:49:04 +0000393static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
394 switch (P) {
395 default:
396 llvm_unreachable("Unknown condition code!");
397 case CmpInst::ICMP_NE:
398 return AArch64CC::NE;
399 case CmpInst::ICMP_EQ:
400 return AArch64CC::EQ;
401 case CmpInst::ICMP_SGT:
402 return AArch64CC::GT;
403 case CmpInst::ICMP_SGE:
404 return AArch64CC::GE;
405 case CmpInst::ICMP_SLT:
406 return AArch64CC::LT;
407 case CmpInst::ICMP_SLE:
408 return AArch64CC::LE;
409 case CmpInst::ICMP_UGT:
410 return AArch64CC::HI;
411 case CmpInst::ICMP_UGE:
412 return AArch64CC::HS;
413 case CmpInst::ICMP_ULT:
414 return AArch64CC::LO;
415 case CmpInst::ICMP_ULE:
416 return AArch64CC::LS;
417 }
418}
419
Tim Northover7dd378d2016-10-12 22:49:07 +0000420static void changeFCMPPredToAArch64CC(CmpInst::Predicate P,
421 AArch64CC::CondCode &CondCode,
422 AArch64CC::CondCode &CondCode2) {
423 CondCode2 = AArch64CC::AL;
424 switch (P) {
425 default:
426 llvm_unreachable("Unknown FP condition!");
427 case CmpInst::FCMP_OEQ:
428 CondCode = AArch64CC::EQ;
429 break;
430 case CmpInst::FCMP_OGT:
431 CondCode = AArch64CC::GT;
432 break;
433 case CmpInst::FCMP_OGE:
434 CondCode = AArch64CC::GE;
435 break;
436 case CmpInst::FCMP_OLT:
437 CondCode = AArch64CC::MI;
438 break;
439 case CmpInst::FCMP_OLE:
440 CondCode = AArch64CC::LS;
441 break;
442 case CmpInst::FCMP_ONE:
443 CondCode = AArch64CC::MI;
444 CondCode2 = AArch64CC::GT;
445 break;
446 case CmpInst::FCMP_ORD:
447 CondCode = AArch64CC::VC;
448 break;
449 case CmpInst::FCMP_UNO:
450 CondCode = AArch64CC::VS;
451 break;
452 case CmpInst::FCMP_UEQ:
453 CondCode = AArch64CC::EQ;
454 CondCode2 = AArch64CC::VS;
455 break;
456 case CmpInst::FCMP_UGT:
457 CondCode = AArch64CC::HI;
458 break;
459 case CmpInst::FCMP_UGE:
460 CondCode = AArch64CC::PL;
461 break;
462 case CmpInst::FCMP_ULT:
463 CondCode = AArch64CC::LT;
464 break;
465 case CmpInst::FCMP_ULE:
466 CondCode = AArch64CC::LE;
467 break;
468 case CmpInst::FCMP_UNE:
469 CondCode = AArch64CC::NE;
470 break;
471 }
472}
473
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000474bool AArch64InstructionSelector::select(MachineInstr &I) const {
475 assert(I.getParent() && "Instruction should be in a basic block!");
476 assert(I.getParent()->getParent() && "Instruction should be in a function!");
477
478 MachineBasicBlock &MBB = *I.getParent();
479 MachineFunction &MF = *MBB.getParent();
480 MachineRegisterInfo &MRI = MF.getRegInfo();
481
Tim Northovercdf23f12016-10-31 18:30:59 +0000482 unsigned Opcode = I.getOpcode();
483 if (!isPreISelGenericOpcode(I.getOpcode())) {
484 // Certain non-generic instructions also need some special handling.
485
486 if (Opcode == TargetOpcode::LOAD_STACK_GUARD)
487 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
Tim Northover7d88da62016-11-08 00:34:06 +0000488
489 if (Opcode == TargetOpcode::PHI) {
490 const unsigned DefReg = I.getOperand(0).getReg();
491 const LLT DefTy = MRI.getType(DefReg);
492
493 const TargetRegisterClass *DefRC = nullptr;
494 if (TargetRegisterInfo::isPhysicalRegister(DefReg)) {
495 DefRC = TRI.getRegClass(DefReg);
496 } else {
497 const RegClassOrRegBank &RegClassOrBank =
498 MRI.getRegClassOrRegBank(DefReg);
499
500 DefRC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
501 if (!DefRC) {
502 if (!DefTy.isValid()) {
503 DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
504 return false;
505 }
506 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
507 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI);
508 if (!DefRC) {
509 DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
510 return false;
511 }
512 }
513 }
514
515 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
516 }
517
518 if (I.isCopy())
Tim Northovercdf23f12016-10-31 18:30:59 +0000519 return selectCopy(I, TII, MRI, TRI, RBI);
Tim Northover7d88da62016-11-08 00:34:06 +0000520
521 return true;
Tim Northovercdf23f12016-10-31 18:30:59 +0000522 }
523
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000524
525 if (I.getNumOperands() != I.getNumExplicitOperands()) {
526 DEBUG(dbgs() << "Generic instruction has unexpected implicit operands\n");
527 return false;
528 }
529
Tim Northover32a078a2016-09-15 10:09:59 +0000530 LLT Ty =
531 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000532
Tim Northover69271c62016-10-12 22:49:11 +0000533 switch (Opcode) {
Ahmed Bougacha85505092016-07-28 17:15:15 +0000534 case TargetOpcode::G_BR: {
535 I.setDesc(TII.get(AArch64::B));
Ahmed Bougacha85505092016-07-28 17:15:15 +0000536 return true;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000537 }
538
Tim Northover5e3dbf32016-10-12 22:49:01 +0000539 case TargetOpcode::G_BRCOND: {
540 if (Ty.getSizeInBits() > 32) {
541 // We shouldn't need this on AArch64, but it would be implemented as an
542 // EXTRACT_SUBREG followed by a TBNZW because TBNZX has no encoding if the
543 // bit being tested is < 32.
544 DEBUG(dbgs() << "G_BRCOND has type: " << Ty
545 << ", expected at most 32-bits");
546 return false;
547 }
548
549 const unsigned CondReg = I.getOperand(0).getReg();
550 MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
551
552 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW))
553 .addUse(CondReg)
554 .addImm(/*bit offset=*/0)
555 .addMBB(DestMBB);
556
557 I.eraseFromParent();
558 return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI);
559 }
560
Tim Northover4494d692016-10-18 19:47:57 +0000561 case TargetOpcode::G_FCONSTANT:
Tim Northover4edc60d2016-10-10 21:49:42 +0000562 case TargetOpcode::G_CONSTANT: {
Tim Northover4494d692016-10-18 19:47:57 +0000563 const bool isFP = Opcode == TargetOpcode::G_FCONSTANT;
564
565 const LLT s32 = LLT::scalar(32);
566 const LLT s64 = LLT::scalar(64);
567 const LLT p0 = LLT::pointer(0, 64);
568
569 const unsigned DefReg = I.getOperand(0).getReg();
570 const LLT DefTy = MRI.getType(DefReg);
571 const unsigned DefSize = DefTy.getSizeInBits();
572 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
573
574 // FIXME: Redundant check, but even less readable when factored out.
575 if (isFP) {
576 if (Ty != s32 && Ty != s64) {
577 DEBUG(dbgs() << "Unable to materialize FP " << Ty
578 << " constant, expected: " << s32 << " or " << s64
579 << '\n');
580 return false;
581 }
582
583 if (RB.getID() != AArch64::FPRRegBankID) {
584 DEBUG(dbgs() << "Unable to materialize FP " << Ty
585 << " constant on bank: " << RB << ", expected: FPR\n");
586 return false;
587 }
588 } else {
589 if (Ty != s32 && Ty != s64 && Ty != p0) {
590 DEBUG(dbgs() << "Unable to materialize integer " << Ty
591 << " constant, expected: " << s32 << ", " << s64 << ", or "
592 << p0 << '\n');
593 return false;
594 }
595
596 if (RB.getID() != AArch64::GPRRegBankID) {
597 DEBUG(dbgs() << "Unable to materialize integer " << Ty
598 << " constant on bank: " << RB << ", expected: GPR\n");
599 return false;
600 }
601 }
602
603 const unsigned MovOpc =
604 DefSize == 32 ? AArch64::MOVi32imm : AArch64::MOVi64imm;
605
606 I.setDesc(TII.get(MovOpc));
607
608 if (isFP) {
609 const TargetRegisterClass &GPRRC =
610 DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass;
611 const TargetRegisterClass &FPRRC =
612 DefSize == 32 ? AArch64::FPR32RegClass : AArch64::FPR64RegClass;
613
614 const unsigned DefGPRReg = MRI.createVirtualRegister(&GPRRC);
615 MachineOperand &RegOp = I.getOperand(0);
616 RegOp.setReg(DefGPRReg);
617
618 BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),
619 TII.get(AArch64::COPY))
620 .addDef(DefReg)
621 .addUse(DefGPRReg);
622
623 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) {
624 DEBUG(dbgs() << "Failed to constrain G_FCONSTANT def operand\n");
625 return false;
626 }
627
628 MachineOperand &ImmOp = I.getOperand(1);
629 // FIXME: Is going through int64_t always correct?
630 ImmOp.ChangeToImmediate(
631 ImmOp.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
Tim Northover9267ac52016-12-05 21:47:07 +0000632 } else {
633 uint64_t Val = I.getOperand(1).getCImm()->getZExtValue();
634 I.getOperand(1).ChangeToImmediate(Val);
Tim Northover4494d692016-10-18 19:47:57 +0000635 }
636
637 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
638 return true;
Tim Northover4edc60d2016-10-10 21:49:42 +0000639 }
640
Ahmed Bougacha0306b5e2016-08-16 14:02:42 +0000641 case TargetOpcode::G_FRAME_INDEX: {
642 // allocas and G_FRAME_INDEX are only supported in addrspace(0).
Tim Northover5ae83502016-09-15 09:20:34 +0000643 if (Ty != LLT::pointer(0, 64)) {
Tim Northover0f140c72016-09-09 11:46:34 +0000644 DEBUG(dbgs() << "G_FRAME_INDEX pointer has type: " << Ty
Tim Northover5ae83502016-09-15 09:20:34 +0000645 << ", expected: " << LLT::pointer(0, 64) << '\n');
Ahmed Bougacha0306b5e2016-08-16 14:02:42 +0000646 return false;
647 }
648
649 I.setDesc(TII.get(AArch64::ADDXri));
Ahmed Bougacha0306b5e2016-08-16 14:02:42 +0000650
651 // MOs for a #0 shifted immediate.
652 I.addOperand(MachineOperand::CreateImm(0));
653 I.addOperand(MachineOperand::CreateImm(0));
654
655 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
656 }
Tim Northoverbdf16242016-10-10 21:50:00 +0000657
658 case TargetOpcode::G_GLOBAL_VALUE: {
659 auto GV = I.getOperand(1).getGlobal();
660 if (GV->isThreadLocal()) {
661 // FIXME: we don't support TLS yet.
662 return false;
663 }
664 unsigned char OpFlags = STI.ClassifyGlobalReference(GV, TM);
Tim Northoverfe7c59a2016-12-13 18:25:38 +0000665 if (OpFlags & AArch64II::MO_GOT) {
Tim Northoverbdf16242016-10-10 21:50:00 +0000666 I.setDesc(TII.get(AArch64::LOADgot));
Tim Northoverfe7c59a2016-12-13 18:25:38 +0000667 I.getOperand(1).setTargetFlags(OpFlags);
668 } else {
Tim Northoverbdf16242016-10-10 21:50:00 +0000669 I.setDesc(TII.get(AArch64::MOVaddr));
670 I.getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_PAGE);
671 MachineInstrBuilder MIB(MF, I);
672 MIB.addGlobalAddress(GV, I.getOperand(1).getOffset(),
673 OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
674 }
675 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
676 }
677
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000678 case TargetOpcode::G_LOAD:
679 case TargetOpcode::G_STORE: {
Tim Northover0f140c72016-09-09 11:46:34 +0000680 LLT MemTy = Ty;
681 LLT PtrTy = MRI.getType(I.getOperand(1).getReg());
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000682
Tim Northover5ae83502016-09-15 09:20:34 +0000683 if (PtrTy != LLT::pointer(0, 64)) {
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000684 DEBUG(dbgs() << "Load/Store pointer has type: " << PtrTy
Tim Northover5ae83502016-09-15 09:20:34 +0000685 << ", expected: " << LLT::pointer(0, 64) << '\n');
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000686 return false;
687 }
688
689#ifndef NDEBUG
690 // Sanity-check the pointer register.
691 const unsigned PtrReg = I.getOperand(1).getReg();
692 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
693 assert(PtrRB.getID() == AArch64::GPRRegBankID &&
694 "Load/Store pointer operand isn't a GPR");
Tim Northover0f140c72016-09-09 11:46:34 +0000695 assert(MRI.getType(PtrReg).isPointer() &&
696 "Load/Store pointer operand isn't a pointer");
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000697#endif
698
699 const unsigned ValReg = I.getOperand(0).getReg();
700 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
701
702 const unsigned NewOpc =
703 selectLoadStoreUIOp(I.getOpcode(), RB.getID(), MemTy.getSizeInBits());
704 if (NewOpc == I.getOpcode())
705 return false;
706
707 I.setDesc(TII.get(NewOpc));
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000708
709 I.addOperand(MachineOperand::CreateImm(0));
710 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
711 }
712
Ahmed Bougachae4c03ab2016-08-16 14:37:46 +0000713 case TargetOpcode::G_MUL: {
714 // Reject the various things we don't support yet.
715 if (unsupportedBinOp(I, RBI, MRI, TRI))
716 return false;
717
718 const unsigned DefReg = I.getOperand(0).getReg();
719 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
720
721 if (RB.getID() != AArch64::GPRRegBankID) {
722 DEBUG(dbgs() << "G_MUL on bank: " << RB << ", expected: GPR\n");
723 return false;
724 }
725
726 unsigned ZeroReg;
727 unsigned NewOpc;
Tim Northover55782222016-10-18 20:03:48 +0000728 if (Ty.isScalar() && Ty.getSizeInBits() <= 32) {
Ahmed Bougachae4c03ab2016-08-16 14:37:46 +0000729 NewOpc = AArch64::MADDWrrr;
730 ZeroReg = AArch64::WZR;
731 } else if (Ty == LLT::scalar(64)) {
732 NewOpc = AArch64::MADDXrrr;
733 ZeroReg = AArch64::XZR;
734 } else {
735 DEBUG(dbgs() << "G_MUL has type: " << Ty << ", expected: "
736 << LLT::scalar(32) << " or " << LLT::scalar(64) << '\n');
737 return false;
738 }
739
740 I.setDesc(TII.get(NewOpc));
Ahmed Bougachae4c03ab2016-08-16 14:37:46 +0000741
742 I.addOperand(MachineOperand::CreateReg(ZeroReg, /*isDef=*/false));
743
744 // Now that we selected an opcode, we need to constrain the register
745 // operands to use appropriate classes.
746 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
747 }
748
Ahmed Bougacha33e19fe2016-08-18 16:05:11 +0000749 case TargetOpcode::G_FADD:
750 case TargetOpcode::G_FSUB:
751 case TargetOpcode::G_FMUL:
752 case TargetOpcode::G_FDIV:
753
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000754 case TargetOpcode::G_OR:
Ahmed Bougacha6db3cfe2016-07-29 16:56:25 +0000755 case TargetOpcode::G_XOR:
Ahmed Bougacha61a79282016-07-28 16:58:31 +0000756 case TargetOpcode::G_AND:
Ahmed Bougacha2ac5bf92016-08-16 14:02:47 +0000757 case TargetOpcode::G_SHL:
758 case TargetOpcode::G_LSHR:
759 case TargetOpcode::G_ASHR:
Ahmed Bougacha1d0560b2016-08-18 15:17:13 +0000760 case TargetOpcode::G_SDIV:
761 case TargetOpcode::G_UDIV:
Ahmed Bougachad7748d62016-07-28 16:58:35 +0000762 case TargetOpcode::G_ADD:
Tim Northover2fda4b02016-10-10 21:49:49 +0000763 case TargetOpcode::G_SUB:
764 case TargetOpcode::G_GEP: {
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000765 // Reject the various things we don't support yet.
Ahmed Bougacha59e160a2016-08-16 14:37:40 +0000766 if (unsupportedBinOp(I, RBI, MRI, TRI))
767 return false;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000768
Ahmed Bougacha59e160a2016-08-16 14:37:40 +0000769 const unsigned OpSize = Ty.getSizeInBits();
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000770
771 const unsigned DefReg = I.getOperand(0).getReg();
772 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
773
774 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize);
775 if (NewOpc == I.getOpcode())
776 return false;
777
778 I.setDesc(TII.get(NewOpc));
779 // FIXME: Should the type be always reset in setDesc?
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000780
781 // Now that we selected an opcode, we need to constrain the register
782 // operands to use appropriate classes.
783 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
784 }
Tim Northover3d38b3a2016-10-11 20:50:21 +0000785
Tim Northover037af52c2016-10-31 18:31:09 +0000786 case TargetOpcode::G_PTRTOINT:
Tim Northoverfb8d9892016-10-12 22:49:15 +0000787 case TargetOpcode::G_TRUNC: {
788 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
789 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
790
791 const unsigned DstReg = I.getOperand(0).getReg();
792 const unsigned SrcReg = I.getOperand(1).getReg();
793
794 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
795 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
796
797 if (DstRB.getID() != SrcRB.getID()) {
798 DEBUG(dbgs() << "G_TRUNC input/output on different banks\n");
799 return false;
800 }
801
802 if (DstRB.getID() == AArch64::GPRRegBankID) {
803 const TargetRegisterClass *DstRC =
804 getRegClassForTypeOnBank(DstTy, DstRB, RBI);
805 if (!DstRC)
806 return false;
807
808 const TargetRegisterClass *SrcRC =
809 getRegClassForTypeOnBank(SrcTy, SrcRB, RBI);
810 if (!SrcRC)
811 return false;
812
813 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
814 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
815 DEBUG(dbgs() << "Failed to constrain G_TRUNC\n");
816 return false;
817 }
818
819 if (DstRC == SrcRC) {
820 // Nothing to be done
821 } else if (DstRC == &AArch64::GPR32RegClass &&
822 SrcRC == &AArch64::GPR64RegClass) {
823 I.getOperand(1).setSubReg(AArch64::sub_32);
824 } else {
825 return false;
826 }
827
828 I.setDesc(TII.get(TargetOpcode::COPY));
829 return true;
830 } else if (DstRB.getID() == AArch64::FPRRegBankID) {
831 if (DstTy == LLT::vector(4, 16) && SrcTy == LLT::vector(4, 32)) {
832 I.setDesc(TII.get(AArch64::XTNv4i16));
833 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
834 return true;
835 }
836 }
837
838 return false;
839 }
840
Tim Northover3d38b3a2016-10-11 20:50:21 +0000841 case TargetOpcode::G_ANYEXT: {
842 const unsigned DstReg = I.getOperand(0).getReg();
843 const unsigned SrcReg = I.getOperand(1).getReg();
844
Quentin Colombetcb629a82016-10-12 03:57:49 +0000845 const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI);
846 if (RBDst.getID() != AArch64::GPRRegBankID) {
847 DEBUG(dbgs() << "G_ANYEXT on bank: " << RBDst << ", expected: GPR\n");
848 return false;
849 }
Tim Northover3d38b3a2016-10-11 20:50:21 +0000850
Quentin Colombetcb629a82016-10-12 03:57:49 +0000851 const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI);
852 if (RBSrc.getID() != AArch64::GPRRegBankID) {
853 DEBUG(dbgs() << "G_ANYEXT on bank: " << RBSrc << ", expected: GPR\n");
Tim Northover3d38b3a2016-10-11 20:50:21 +0000854 return false;
855 }
856
857 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
858
859 if (DstSize == 0) {
860 DEBUG(dbgs() << "G_ANYEXT operand has no size, not a gvreg?\n");
861 return false;
862 }
863
Quentin Colombetcb629a82016-10-12 03:57:49 +0000864 if (DstSize != 64 && DstSize > 32) {
Tim Northover3d38b3a2016-10-11 20:50:21 +0000865 DEBUG(dbgs() << "G_ANYEXT to size: " << DstSize
866 << ", expected: 32 or 64\n");
867 return false;
868 }
Quentin Colombetcb629a82016-10-12 03:57:49 +0000869 // At this point G_ANYEXT is just like a plain COPY, but we need
870 // to explicitly form the 64-bit value if any.
871 if (DstSize > 32) {
872 unsigned ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass);
873 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
874 .addDef(ExtSrc)
875 .addImm(0)
876 .addUse(SrcReg)
877 .addImm(AArch64::sub_32);
878 I.getOperand(1).setReg(ExtSrc);
Tim Northover3d38b3a2016-10-11 20:50:21 +0000879 }
Quentin Colombetcb629a82016-10-12 03:57:49 +0000880 return selectCopy(I, TII, MRI, TRI, RBI);
Tim Northover3d38b3a2016-10-11 20:50:21 +0000881 }
882
883 case TargetOpcode::G_ZEXT:
884 case TargetOpcode::G_SEXT: {
885 unsigned Opcode = I.getOpcode();
886 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
887 SrcTy = MRI.getType(I.getOperand(1).getReg());
888 const bool isSigned = Opcode == TargetOpcode::G_SEXT;
889 const unsigned DefReg = I.getOperand(0).getReg();
890 const unsigned SrcReg = I.getOperand(1).getReg();
891 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
892
893 if (RB.getID() != AArch64::GPRRegBankID) {
894 DEBUG(dbgs() << TII.getName(I.getOpcode()) << " on bank: " << RB
895 << ", expected: GPR\n");
896 return false;
897 }
898
899 MachineInstr *ExtI;
900 if (DstTy == LLT::scalar(64)) {
901 // FIXME: Can we avoid manually doing this?
902 if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass, MRI)) {
903 DEBUG(dbgs() << "Failed to constrain " << TII.getName(Opcode)
904 << " operand\n");
905 return false;
906 }
907
908 const unsigned SrcXReg =
909 MRI.createVirtualRegister(&AArch64::GPR64RegClass);
910 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
911 .addDef(SrcXReg)
912 .addImm(0)
913 .addUse(SrcReg)
914 .addImm(AArch64::sub_32);
915
916 const unsigned NewOpc = isSigned ? AArch64::SBFMXri : AArch64::UBFMXri;
917 ExtI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
918 .addDef(DefReg)
919 .addUse(SrcXReg)
920 .addImm(0)
921 .addImm(SrcTy.getSizeInBits() - 1);
Tim Northovera9105be2016-11-09 22:39:54 +0000922 } else if (DstTy.isScalar() && DstTy.getSizeInBits() <= 32) {
Tim Northover3d38b3a2016-10-11 20:50:21 +0000923 const unsigned NewOpc = isSigned ? AArch64::SBFMWri : AArch64::UBFMWri;
924 ExtI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
925 .addDef(DefReg)
926 .addUse(SrcReg)
927 .addImm(0)
928 .addImm(SrcTy.getSizeInBits() - 1);
929 } else {
930 return false;
931 }
932
933 constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
934
935 I.eraseFromParent();
936 return true;
937 }
Tim Northoverc1d8c2b2016-10-11 22:29:23 +0000938
Tim Northover69271c62016-10-12 22:49:11 +0000939 case TargetOpcode::G_SITOFP:
940 case TargetOpcode::G_UITOFP:
941 case TargetOpcode::G_FPTOSI:
942 case TargetOpcode::G_FPTOUI: {
943 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
944 SrcTy = MRI.getType(I.getOperand(1).getReg());
945 const unsigned NewOpc = selectFPConvOpc(Opcode, DstTy, SrcTy);
946 if (NewOpc == Opcode)
947 return false;
948
949 I.setDesc(TII.get(NewOpc));
950 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
951
952 return true;
953 }
954
955
Tim Northoverc1d8c2b2016-10-11 22:29:23 +0000956 case TargetOpcode::G_INTTOPTR:
Quentin Colombet9de30fa2016-10-12 03:57:52 +0000957 case TargetOpcode::G_BITCAST:
958 return selectCopy(I, TII, MRI, TRI, RBI);
Tim Northover6c02ad52016-10-12 22:49:04 +0000959
Tim Northover5f7dea82016-11-08 17:44:07 +0000960 case TargetOpcode::G_FPEXT: {
961 if (MRI.getType(I.getOperand(0).getReg()) != LLT::scalar(64)) {
962 DEBUG(dbgs() << "G_FPEXT to type " << Ty
963 << ", expected: " << LLT::scalar(64) << '\n');
964 return false;
965 }
966
967 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(32)) {
968 DEBUG(dbgs() << "G_FPEXT from type " << Ty
969 << ", expected: " << LLT::scalar(32) << '\n');
970 return false;
971 }
972
973 const unsigned DefReg = I.getOperand(0).getReg();
974 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
975
976 if (RB.getID() != AArch64::FPRRegBankID) {
977 DEBUG(dbgs() << "G_FPEXT on bank: " << RB << ", expected: FPR\n");
978 return false;
979 }
980
981 I.setDesc(TII.get(AArch64::FCVTDSr));
982 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
983
984 return true;
985 }
986
987 case TargetOpcode::G_FPTRUNC: {
988 if (MRI.getType(I.getOperand(0).getReg()) != LLT::scalar(32)) {
989 DEBUG(dbgs() << "G_FPTRUNC to type " << Ty
990 << ", expected: " << LLT::scalar(32) << '\n');
991 return false;
992 }
993
994 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(64)) {
995 DEBUG(dbgs() << "G_FPTRUNC from type " << Ty
996 << ", expected: " << LLT::scalar(64) << '\n');
997 return false;
998 }
999
1000 const unsigned DefReg = I.getOperand(0).getReg();
1001 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
1002
1003 if (RB.getID() != AArch64::FPRRegBankID) {
1004 DEBUG(dbgs() << "G_FPTRUNC on bank: " << RB << ", expected: FPR\n");
1005 return false;
1006 }
1007
1008 I.setDesc(TII.get(AArch64::FCVTSDr));
1009 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1010
1011 return true;
1012 }
1013
Tim Northover9ac0eba2016-11-08 00:45:29 +00001014 case TargetOpcode::G_SELECT: {
1015 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) {
1016 DEBUG(dbgs() << "G_SELECT cond has type: " << Ty
1017 << ", expected: " << LLT::scalar(1) << '\n');
1018 return false;
1019 }
1020
1021 const unsigned CondReg = I.getOperand(1).getReg();
1022 const unsigned TReg = I.getOperand(2).getReg();
1023 const unsigned FReg = I.getOperand(3).getReg();
1024
1025 unsigned CSelOpc = 0;
1026
1027 if (Ty == LLT::scalar(32)) {
1028 CSelOpc = AArch64::CSELWr;
1029 } else if (Ty == LLT::scalar(64)) {
1030 CSelOpc = AArch64::CSELXr;
1031 } else {
1032 return false;
1033 }
1034
1035 MachineInstr &TstMI =
1036 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
1037 .addDef(AArch64::WZR)
1038 .addUse(CondReg)
1039 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1040
1041 MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc))
1042 .addDef(I.getOperand(0).getReg())
1043 .addUse(TReg)
1044 .addUse(FReg)
1045 .addImm(AArch64CC::NE);
1046
1047 constrainSelectedInstRegOperands(TstMI, TII, TRI, RBI);
1048 constrainSelectedInstRegOperands(CSelMI, TII, TRI, RBI);
1049
1050 I.eraseFromParent();
1051 return true;
1052 }
Tim Northover6c02ad52016-10-12 22:49:04 +00001053 case TargetOpcode::G_ICMP: {
1054 if (Ty != LLT::scalar(1)) {
1055 DEBUG(dbgs() << "G_ICMP result has type: " << Ty
1056 << ", expected: " << LLT::scalar(1) << '\n');
1057 return false;
1058 }
1059
1060 unsigned CmpOpc = 0;
1061 unsigned ZReg = 0;
1062
1063 LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
1064 if (CmpTy == LLT::scalar(32)) {
1065 CmpOpc = AArch64::SUBSWrr;
1066 ZReg = AArch64::WZR;
1067 } else if (CmpTy == LLT::scalar(64) || CmpTy.isPointer()) {
1068 CmpOpc = AArch64::SUBSXrr;
1069 ZReg = AArch64::XZR;
1070 } else {
1071 return false;
1072 }
1073
1074 const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
1075 (CmpInst::Predicate)I.getOperand(1).getPredicate());
1076
1077 MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
1078 .addDef(ZReg)
1079 .addUse(I.getOperand(2).getReg())
1080 .addUse(I.getOperand(3).getReg());
1081
1082 MachineInstr &CSetMI =
1083 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
1084 .addDef(I.getOperand(0).getReg())
1085 .addUse(AArch64::WZR)
1086 .addUse(AArch64::WZR)
1087 .addImm(CC);
1088
1089 constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
1090 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
1091
1092 I.eraseFromParent();
1093 return true;
1094 }
1095
Tim Northover7dd378d2016-10-12 22:49:07 +00001096 case TargetOpcode::G_FCMP: {
1097 if (Ty != LLT::scalar(1)) {
1098 DEBUG(dbgs() << "G_FCMP result has type: " << Ty
1099 << ", expected: " << LLT::scalar(1) << '\n');
1100 return false;
1101 }
1102
1103 unsigned CmpOpc = 0;
1104 LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
1105 if (CmpTy == LLT::scalar(32)) {
1106 CmpOpc = AArch64::FCMPSrr;
1107 } else if (CmpTy == LLT::scalar(64)) {
1108 CmpOpc = AArch64::FCMPDrr;
1109 } else {
1110 return false;
1111 }
1112
1113 // FIXME: regbank
1114
1115 AArch64CC::CondCode CC1, CC2;
1116 changeFCMPPredToAArch64CC(
1117 (CmpInst::Predicate)I.getOperand(1).getPredicate(), CC1, CC2);
1118
1119 MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
1120 .addUse(I.getOperand(2).getReg())
1121 .addUse(I.getOperand(3).getReg());
1122
1123 const unsigned DefReg = I.getOperand(0).getReg();
1124 unsigned Def1Reg = DefReg;
1125 if (CC2 != AArch64CC::AL)
1126 Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1127
1128 MachineInstr &CSetMI =
1129 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
1130 .addDef(Def1Reg)
1131 .addUse(AArch64::WZR)
1132 .addUse(AArch64::WZR)
1133 .addImm(CC1);
1134
1135 if (CC2 != AArch64CC::AL) {
1136 unsigned Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1137 MachineInstr &CSet2MI =
1138 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
1139 .addDef(Def2Reg)
1140 .addUse(AArch64::WZR)
1141 .addUse(AArch64::WZR)
1142 .addImm(CC2);
1143 MachineInstr &OrMI =
1144 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr))
1145 .addDef(DefReg)
1146 .addUse(Def1Reg)
1147 .addUse(Def2Reg);
1148 constrainSelectedInstRegOperands(OrMI, TII, TRI, RBI);
1149 constrainSelectedInstRegOperands(CSet2MI, TII, TRI, RBI);
1150 }
1151
1152 constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
1153 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
1154
1155 I.eraseFromParent();
1156 return true;
1157 }
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +00001158 }
1159
1160 return false;
1161}