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Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/platform_device.h>
17#include <linux/msm_rotator.h>
18#include <linux/clkdev.h>
Hemant Kumard86c4882012-01-24 19:39:37 -080019#include <linux/dma-mapping.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070020#include <mach/irqs-8064.h>
21#include <mach/board.h>
22#include <mach/msm_iomap.h>
Yan He06913ce2011-08-26 16:33:46 -070023#include <mach/usbdiag.h>
24#include <mach/msm_sps.h>
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -070025#include <mach/dma.h>
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -080026#include <sound/msm-dai-q6.h>
27#include <sound/apr_audio.h>
Gagan Mac8a7a5d32011-11-11 16:43:06 -070028#include <mach/msm_bus_board.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060029#include <mach/rpm.h>
Joel Kingdacbc822012-01-25 13:30:57 -080030#include <mach/mdm2.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031#include "clock.h"
32#include "devices.h"
Jeff Ohlstein7e668552011-10-06 16:17:25 -070033#include "msm_watchdog.h"
Praveen Chidambaram78499012011-11-01 17:15:17 -060034#include "rpm_stats.h"
35#include "rpm_log.h"
36#include "mpm.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070037
38/* Address of GSBI blocks */
Stepan Moskovchenko2701a442011-08-19 13:47:22 -070039#define MSM_GSBI1_PHYS 0x12440000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070040#define MSM_GSBI3_PHYS 0x16200000
Harini Jayaramanc4c58692011-07-19 14:50:10 -060041#define MSM_GSBI4_PHYS 0x16300000
42#define MSM_GSBI5_PHYS 0x1A200000
43#define MSM_GSBI6_PHYS 0x16500000
44#define MSM_GSBI7_PHYS 0x16600000
45
Kenneth Heitke748593a2011-07-15 15:45:11 -060046/* GSBI UART devices */
Stepan Moskovchenko2701a442011-08-19 13:47:22 -070047#define MSM_UART1DM_PHYS (MSM_GSBI1_PHYS + 0x10000)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070048#define MSM_UART3DM_PHYS (MSM_GSBI3_PHYS + 0x40000)
49
Harini Jayaramanc4c58692011-07-19 14:50:10 -060050/* GSBI QUP devices */
51#define MSM_GSBI3_QUP_PHYS (MSM_GSBI3_PHYS + 0x80000)
52#define MSM_GSBI4_QUP_PHYS (MSM_GSBI4_PHYS + 0x80000)
53#define MSM_GSBI5_QUP_PHYS (MSM_GSBI5_PHYS + 0x80000)
54#define MSM_GSBI6_QUP_PHYS (MSM_GSBI6_PHYS + 0x80000)
55#define MSM_GSBI7_QUP_PHYS (MSM_GSBI7_PHYS + 0x80000)
56#define MSM_QUP_SIZE SZ_4K
57
Kenneth Heitke36920d32011-07-20 16:44:30 -060058/* Address of SSBI CMD */
59#define MSM_PMIC1_SSBI_CMD_PHYS 0x00500000
60#define MSM_PMIC2_SSBI_CMD_PHYS 0x00C00000
61#define MSM_PMIC_SSBI_SIZE SZ_4K
Harini Jayaramanc4c58692011-07-19 14:50:10 -060062
Hemant Kumarcaa09092011-07-30 00:26:33 -070063/* Address of HS USBOTG1 */
Hemant Kumard86c4882012-01-24 19:39:37 -080064#define MSM_HSUSB1_PHYS 0x12500000
65#define MSM_HSUSB1_SIZE SZ_4K
Hemant Kumarcaa09092011-07-30 00:26:33 -070066
Jeff Ohlstein7e668552011-10-06 16:17:25 -070067static struct msm_watchdog_pdata msm_watchdog_pdata = {
68 .pet_time = 10000,
69 .bark_time = 11000,
70 .has_secure = true,
71};
72
73struct platform_device msm8064_device_watchdog = {
74 .name = "msm_watchdog",
75 .id = -1,
76 .dev = {
77 .platform_data = &msm_watchdog_pdata,
78 },
79};
80
Joel King0581896d2011-07-19 16:43:28 -070081static struct resource msm_dmov_resource[] = {
82 {
Jeff Ohlstein4af72692011-11-07 15:59:17 -080083 .start = ADM_0_SCSS_1_IRQ,
Joel King0581896d2011-07-19 16:43:28 -070084 .flags = IORESOURCE_IRQ,
85 },
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -070086 {
Jeff Ohlstein4af72692011-11-07 15:59:17 -080087 .start = 0x18320000,
88 .end = 0x18320000 + SZ_1M - 1,
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -070089 .flags = IORESOURCE_MEM,
90 },
91};
92
93static struct msm_dmov_pdata msm_dmov_pdata = {
Jeff Ohlstein4af72692011-11-07 15:59:17 -080094 .sd = 1,
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -070095 .sd_size = 0x800,
Joel King0581896d2011-07-19 16:43:28 -070096};
97
Stepan Moskovchenkodf13d342011-08-03 19:01:25 -070098struct platform_device apq8064_device_dmov = {
Joel King0581896d2011-07-19 16:43:28 -070099 .name = "msm_dmov",
100 .id = -1,
101 .resource = msm_dmov_resource,
102 .num_resources = ARRAY_SIZE(msm_dmov_resource),
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -0700103 .dev = {
104 .platform_data = &msm_dmov_pdata,
105 },
Joel King0581896d2011-07-19 16:43:28 -0700106};
107
Stepan Moskovchenko2701a442011-08-19 13:47:22 -0700108static struct resource resources_uart_gsbi1[] = {
109 {
110 .start = APQ8064_GSBI1_UARTDM_IRQ,
111 .end = APQ8064_GSBI1_UARTDM_IRQ,
112 .flags = IORESOURCE_IRQ,
113 },
114 {
115 .start = MSM_UART1DM_PHYS,
116 .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1,
117 .name = "uartdm_resource",
118 .flags = IORESOURCE_MEM,
119 },
120 {
121 .start = MSM_GSBI1_PHYS,
122 .end = MSM_GSBI1_PHYS + PAGE_SIZE - 1,
123 .name = "gsbi_resource",
124 .flags = IORESOURCE_MEM,
125 },
126};
127
128struct platform_device apq8064_device_uart_gsbi1 = {
129 .name = "msm_serial_hsl",
130 .id = 0,
131 .num_resources = ARRAY_SIZE(resources_uart_gsbi1),
132 .resource = resources_uart_gsbi1,
133};
134
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700135static struct resource resources_uart_gsbi3[] = {
136 {
137 .start = GSBI3_UARTDM_IRQ,
138 .end = GSBI3_UARTDM_IRQ,
139 .flags = IORESOURCE_IRQ,
140 },
141 {
142 .start = MSM_UART3DM_PHYS,
143 .end = MSM_UART3DM_PHYS + PAGE_SIZE - 1,
144 .name = "uartdm_resource",
145 .flags = IORESOURCE_MEM,
146 },
147 {
148 .start = MSM_GSBI3_PHYS,
149 .end = MSM_GSBI3_PHYS + PAGE_SIZE - 1,
150 .name = "gsbi_resource",
151 .flags = IORESOURCE_MEM,
152 },
153};
154
155struct platform_device apq8064_device_uart_gsbi3 = {
156 .name = "msm_serial_hsl",
157 .id = 0,
158 .num_resources = ARRAY_SIZE(resources_uart_gsbi3),
159 .resource = resources_uart_gsbi3,
160};
161
Kenneth Heitke748593a2011-07-15 15:45:11 -0600162static struct resource resources_qup_i2c_gsbi4[] = {
163 {
164 .name = "gsbi_qup_i2c_addr",
165 .start = MSM_GSBI4_PHYS,
Harini Jayaramane1554a92011-09-15 14:43:02 -0600166 .end = MSM_GSBI4_PHYS + 4 - 1,
Kenneth Heitke748593a2011-07-15 15:45:11 -0600167 .flags = IORESOURCE_MEM,
168 },
169 {
170 .name = "qup_phys_addr",
171 .start = MSM_GSBI4_QUP_PHYS,
Harini Jayaramane1554a92011-09-15 14:43:02 -0600172 .end = MSM_GSBI4_QUP_PHYS + MSM_QUP_SIZE - 1,
Kenneth Heitke748593a2011-07-15 15:45:11 -0600173 .flags = IORESOURCE_MEM,
174 },
175 {
176 .name = "qup_err_intr",
177 .start = GSBI4_QUP_IRQ,
178 .end = GSBI4_QUP_IRQ,
179 .flags = IORESOURCE_IRQ,
180 },
181};
182
183struct platform_device apq8064_device_qup_i2c_gsbi4 = {
184 .name = "qup_i2c",
185 .id = 4,
186 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi4),
187 .resource = resources_qup_i2c_gsbi4,
188};
189
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700190static struct resource resources_qup_spi_gsbi5[] = {
191 {
192 .name = "spi_base",
193 .start = MSM_GSBI5_QUP_PHYS,
194 .end = MSM_GSBI5_QUP_PHYS + SZ_4K - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 {
198 .name = "gsbi_base",
199 .start = MSM_GSBI5_PHYS,
200 .end = MSM_GSBI5_PHYS + 4 - 1,
201 .flags = IORESOURCE_MEM,
202 },
203 {
204 .name = "spi_irq_in",
205 .start = GSBI5_QUP_IRQ,
206 .end = GSBI5_QUP_IRQ,
207 .flags = IORESOURCE_IRQ,
208 },
209};
210
211struct platform_device apq8064_device_qup_spi_gsbi5 = {
212 .name = "spi_qsd",
213 .id = 0,
214 .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi5),
215 .resource = resources_qup_spi_gsbi5,
216};
217
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800218struct platform_device apq_pcm = {
219 .name = "msm-pcm-dsp",
220 .id = -1,
221};
222
223struct platform_device apq_pcm_routing = {
224 .name = "msm-pcm-routing",
225 .id = -1,
226};
227
228struct platform_device apq_cpudai0 = {
229 .name = "msm-dai-q6",
230 .id = 0x4000,
231};
232
233struct platform_device apq_cpudai1 = {
234 .name = "msm-dai-q6",
235 .id = 0x4001,
236};
237
238struct platform_device apq_cpudai_hdmi_rx = {
239 .name = "msm-dai-q6",
240 .id = 8,
241};
242
243struct platform_device apq_cpudai_bt_rx = {
244 .name = "msm-dai-q6",
245 .id = 0x3000,
246};
247
248struct platform_device apq_cpudai_bt_tx = {
249 .name = "msm-dai-q6",
250 .id = 0x3001,
251};
252
253struct platform_device apq_cpudai_fm_rx = {
254 .name = "msm-dai-q6",
255 .id = 0x3004,
256};
257
258struct platform_device apq_cpudai_fm_tx = {
259 .name = "msm-dai-q6",
260 .id = 0x3005,
261};
262
263/*
264 * Machine specific data for AUX PCM Interface
265 * which the driver will be unware of.
266 */
267struct msm_dai_auxpcm_pdata apq_auxpcm_rx_pdata = {
268 .clk = "pcm_clk",
269 .mode = AFE_PCM_CFG_MODE_PCM,
270 .sync = AFE_PCM_CFG_SYNC_INT,
271 .frame = AFE_PCM_CFG_FRM_256BPF,
272 .quant = AFE_PCM_CFG_QUANT_LINEAR_NOPAD,
273 .slot = 0,
274 .data = AFE_PCM_CFG_CDATAOE_MASTER,
275 .pcm_clk_rate = 2048000,
276};
277
278struct platform_device apq_cpudai_auxpcm_rx = {
279 .name = "msm-dai-q6",
280 .id = 2,
281 .dev = {
282 .platform_data = &apq_auxpcm_rx_pdata,
283 },
284};
285
286struct platform_device apq_cpudai_auxpcm_tx = {
287 .name = "msm-dai-q6",
288 .id = 3,
289};
290
291struct platform_device apq_cpu_fe = {
292 .name = "msm-dai-fe",
293 .id = -1,
294};
295
296struct platform_device apq_stub_codec = {
297 .name = "msm-stub-codec",
298 .id = 1,
299};
300
301struct platform_device apq_voice = {
302 .name = "msm-pcm-voice",
303 .id = -1,
304};
305
306struct platform_device apq_voip = {
307 .name = "msm-voip-dsp",
308 .id = -1,
309};
310
311struct platform_device apq_lpa_pcm = {
312 .name = "msm-pcm-lpa",
313 .id = -1,
314};
315
316struct platform_device apq_pcm_hostless = {
317 .name = "msm-pcm-hostless",
318 .id = -1,
319};
320
321struct platform_device apq_cpudai_afe_01_rx = {
322 .name = "msm-dai-q6",
323 .id = 0xE0,
324};
325
326struct platform_device apq_cpudai_afe_01_tx = {
327 .name = "msm-dai-q6",
328 .id = 0xF0,
329};
330
331struct platform_device apq_cpudai_afe_02_rx = {
332 .name = "msm-dai-q6",
333 .id = 0xF1,
334};
335
336struct platform_device apq_cpudai_afe_02_tx = {
337 .name = "msm-dai-q6",
338 .id = 0xE1,
339};
340
341struct platform_device apq_pcm_afe = {
342 .name = "msm-pcm-afe",
343 .id = -1,
344};
345
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700346static struct resource resources_ssbi_pmic1[] = {
347 {
348 .start = MSM_PMIC1_SSBI_CMD_PHYS,
349 .end = MSM_PMIC1_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
350 .flags = IORESOURCE_MEM,
351 },
352};
353
Sagar Dharia8bdcdaf2011-09-16 16:01:15 -0600354#define LPASS_SLIMBUS_PHYS 0x28080000
355#define LPASS_SLIMBUS_BAM_PHYS 0x28084000
356/* Board info for the slimbus slave device */
357static struct resource slimbus_res[] = {
358 {
359 .start = LPASS_SLIMBUS_PHYS,
360 .end = LPASS_SLIMBUS_PHYS + 8191,
361 .flags = IORESOURCE_MEM,
362 .name = "slimbus_physical",
363 },
364 {
365 .start = LPASS_SLIMBUS_BAM_PHYS,
366 .end = LPASS_SLIMBUS_BAM_PHYS + 8191,
367 .flags = IORESOURCE_MEM,
368 .name = "slimbus_bam_physical",
369 },
370 {
371 .start = SLIMBUS0_CORE_EE1_IRQ,
372 .end = SLIMBUS0_CORE_EE1_IRQ,
373 .flags = IORESOURCE_IRQ,
374 .name = "slimbus_irq",
375 },
376 {
377 .start = SLIMBUS0_BAM_EE1_IRQ,
378 .end = SLIMBUS0_BAM_EE1_IRQ,
379 .flags = IORESOURCE_IRQ,
380 .name = "slimbus_bam_irq",
381 },
382};
383
384struct platform_device apq8064_slim_ctrl = {
385 .name = "msm_slim_ctrl",
386 .id = 1,
387 .num_resources = ARRAY_SIZE(slimbus_res),
388 .resource = slimbus_res,
389 .dev = {
390 .coherent_dma_mask = 0xffffffffULL,
391 },
392};
393
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700394struct platform_device apq8064_device_ssbi_pmic1 = {
395 .name = "msm_ssbi",
396 .id = 0,
397 .resource = resources_ssbi_pmic1,
398 .num_resources = ARRAY_SIZE(resources_ssbi_pmic1),
399};
400
401static struct resource resources_ssbi_pmic2[] = {
402 {
403 .start = MSM_PMIC2_SSBI_CMD_PHYS,
404 .end = MSM_PMIC2_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
405 .flags = IORESOURCE_MEM,
406 },
407};
408
409struct platform_device apq8064_device_ssbi_pmic2 = {
410 .name = "msm_ssbi",
411 .id = 1,
412 .resource = resources_ssbi_pmic2,
413 .num_resources = ARRAY_SIZE(resources_ssbi_pmic2),
414};
415
416static struct resource resources_otg[] = {
417 {
Hemant Kumard86c4882012-01-24 19:39:37 -0800418 .start = MSM_HSUSB1_PHYS,
419 .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700420 .flags = IORESOURCE_MEM,
421 },
422 {
423 .start = USB1_HS_IRQ,
424 .end = USB1_HS_IRQ,
425 .flags = IORESOURCE_IRQ,
426 },
427};
428
Stepan Moskovchenko14aa6492011-08-08 15:15:01 -0700429struct platform_device apq8064_device_otg = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700430 .name = "msm_otg",
431 .id = -1,
432 .num_resources = ARRAY_SIZE(resources_otg),
433 .resource = resources_otg,
434 .dev = {
435 .coherent_dma_mask = 0xffffffff,
436 },
437};
438
439static struct resource resources_hsusb[] = {
440 {
Hemant Kumard86c4882012-01-24 19:39:37 -0800441 .start = MSM_HSUSB1_PHYS,
442 .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700443 .flags = IORESOURCE_MEM,
444 },
445 {
446 .start = USB1_HS_IRQ,
447 .end = USB1_HS_IRQ,
448 .flags = IORESOURCE_IRQ,
449 },
450};
451
Stepan Moskovchenko14aa6492011-08-08 15:15:01 -0700452struct platform_device apq8064_device_gadget_peripheral = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700453 .name = "msm_hsusb",
454 .id = -1,
455 .num_resources = ARRAY_SIZE(resources_hsusb),
456 .resource = resources_hsusb,
457 .dev = {
458 .coherent_dma_mask = 0xffffffff,
459 },
460};
461
Hemant Kumard86c4882012-01-24 19:39:37 -0800462static struct resource resources_hsusb_host[] = {
463 {
464 .start = MSM_HSUSB1_PHYS,
465 .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1,
466 .flags = IORESOURCE_MEM,
467 },
468 {
469 .start = USB1_HS_IRQ,
470 .end = USB1_HS_IRQ,
471 .flags = IORESOURCE_IRQ,
472 },
473};
474
Hemant Kumara945b472012-01-25 15:08:06 -0800475static struct resource resources_hsic_host[] = {
476 {
477 .start = 0x12510000,
478 .end = 0x12510000 + SZ_4K - 1,
479 .flags = IORESOURCE_MEM,
480 },
481 {
482 .start = USB2_HSIC_IRQ,
483 .end = USB2_HSIC_IRQ,
484 .flags = IORESOURCE_IRQ,
485 },
486 {
487 .start = MSM_GPIO_TO_INT(49),
488 .end = MSM_GPIO_TO_INT(49),
489 .name = "peripheral_status_irq",
490 .flags = IORESOURCE_IRQ,
491 },
492};
493
Hemant Kumard86c4882012-01-24 19:39:37 -0800494static u64 dma_mask = DMA_BIT_MASK(32);
495struct platform_device apq8064_device_hsusb_host = {
496 .name = "msm_hsusb_host",
497 .id = -1,
498 .num_resources = ARRAY_SIZE(resources_hsusb_host),
499 .resource = resources_hsusb_host,
500 .dev = {
501 .dma_mask = &dma_mask,
502 .coherent_dma_mask = 0xffffffff,
503 },
504};
505
Hemant Kumara945b472012-01-25 15:08:06 -0800506struct platform_device apq8064_device_hsic_host = {
507 .name = "msm_hsic_host",
508 .id = -1,
509 .num_resources = ARRAY_SIZE(resources_hsic_host),
510 .resource = resources_hsic_host,
511 .dev = {
512 .dma_mask = &dma_mask,
513 .coherent_dma_mask = DMA_BIT_MASK(32),
514 },
515};
516
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700517#define MSM_SDC1_BASE 0x12400000
518#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
519#define MSM_SDC1_BAM_BASE (MSM_SDC1_BASE + 0x2000)
520#define MSM_SDC2_BASE 0x12140000
521#define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800)
522#define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000)
523#define MSM_SDC3_BASE 0x12180000
524#define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800)
525#define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000)
526#define MSM_SDC4_BASE 0x121C0000
527#define MSM_SDC4_DML_BASE (MSM_SDC4_BASE + 0x800)
528#define MSM_SDC4_BAM_BASE (MSM_SDC4_BASE + 0x2000)
529
530static struct resource resources_sdc1[] = {
531 {
532 .name = "core_mem",
533 .flags = IORESOURCE_MEM,
534 .start = MSM_SDC1_BASE,
535 .end = MSM_SDC1_DML_BASE - 1,
536 },
537 {
538 .name = "core_irq",
539 .flags = IORESOURCE_IRQ,
540 .start = SDC1_IRQ_0,
541 .end = SDC1_IRQ_0
542 },
543#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
544 {
545 .name = "sdcc_dml_addr",
546 .start = MSM_SDC1_DML_BASE,
547 .end = MSM_SDC1_BAM_BASE - 1,
548 .flags = IORESOURCE_MEM,
549 },
550 {
551 .name = "sdcc_bam_addr",
552 .start = MSM_SDC1_BAM_BASE,
553 .end = MSM_SDC1_BAM_BASE + (2 * SZ_4K) - 1,
554 .flags = IORESOURCE_MEM,
555 },
556 {
557 .name = "sdcc_bam_irq",
558 .start = SDC1_BAM_IRQ,
559 .end = SDC1_BAM_IRQ,
560 .flags = IORESOURCE_IRQ,
561 },
562#endif
563};
564
565static struct resource resources_sdc2[] = {
566 {
567 .name = "core_mem",
568 .flags = IORESOURCE_MEM,
569 .start = MSM_SDC2_BASE,
570 .end = MSM_SDC2_DML_BASE - 1,
571 },
572 {
573 .name = "core_irq",
574 .flags = IORESOURCE_IRQ,
575 .start = SDC2_IRQ_0,
576 .end = SDC2_IRQ_0
577 },
578#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
579 {
580 .name = "sdcc_dml_addr",
581 .start = MSM_SDC2_DML_BASE,
582 .end = MSM_SDC2_BAM_BASE - 1,
583 .flags = IORESOURCE_MEM,
584 },
585 {
586 .name = "sdcc_bam_addr",
587 .start = MSM_SDC2_BAM_BASE,
588 .end = MSM_SDC2_BAM_BASE + (2 * SZ_4K) - 1,
589 .flags = IORESOURCE_MEM,
590 },
591 {
592 .name = "sdcc_bam_irq",
593 .start = SDC2_BAM_IRQ,
594 .end = SDC2_BAM_IRQ,
595 .flags = IORESOURCE_IRQ,
596 },
597#endif
598};
599
600static struct resource resources_sdc3[] = {
601 {
602 .name = "core_mem",
603 .flags = IORESOURCE_MEM,
604 .start = MSM_SDC3_BASE,
605 .end = MSM_SDC3_DML_BASE - 1,
606 },
607 {
608 .name = "core_irq",
609 .flags = IORESOURCE_IRQ,
610 .start = SDC3_IRQ_0,
611 .end = SDC3_IRQ_0
612 },
613#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
614 {
615 .name = "sdcc_dml_addr",
616 .start = MSM_SDC3_DML_BASE,
617 .end = MSM_SDC3_BAM_BASE - 1,
618 .flags = IORESOURCE_MEM,
619 },
620 {
621 .name = "sdcc_bam_addr",
622 .start = MSM_SDC3_BAM_BASE,
623 .end = MSM_SDC3_BAM_BASE + (2 * SZ_4K) - 1,
624 .flags = IORESOURCE_MEM,
625 },
626 {
627 .name = "sdcc_bam_irq",
628 .start = SDC3_BAM_IRQ,
629 .end = SDC3_BAM_IRQ,
630 .flags = IORESOURCE_IRQ,
631 },
632#endif
633};
634
635static struct resource resources_sdc4[] = {
636 {
637 .name = "core_mem",
638 .flags = IORESOURCE_MEM,
639 .start = MSM_SDC4_BASE,
640 .end = MSM_SDC4_DML_BASE - 1,
641 },
642 {
643 .name = "core_irq",
644 .flags = IORESOURCE_IRQ,
645 .start = SDC4_IRQ_0,
646 .end = SDC4_IRQ_0
647 },
648#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
649 {
650 .name = "sdcc_dml_addr",
651 .start = MSM_SDC4_DML_BASE,
652 .end = MSM_SDC4_BAM_BASE - 1,
653 .flags = IORESOURCE_MEM,
654 },
655 {
656 .name = "sdcc_bam_addr",
657 .start = MSM_SDC4_BAM_BASE,
658 .end = MSM_SDC4_BAM_BASE + (2 * SZ_4K) - 1,
659 .flags = IORESOURCE_MEM,
660 },
661 {
662 .name = "sdcc_bam_irq",
663 .start = SDC4_BAM_IRQ,
664 .end = SDC4_BAM_IRQ,
665 .flags = IORESOURCE_IRQ,
666 },
667#endif
668};
669
670struct platform_device apq8064_device_sdc1 = {
671 .name = "msm_sdcc",
672 .id = 1,
673 .num_resources = ARRAY_SIZE(resources_sdc1),
674 .resource = resources_sdc1,
675 .dev = {
676 .coherent_dma_mask = 0xffffffff,
677 },
678};
679
680struct platform_device apq8064_device_sdc2 = {
681 .name = "msm_sdcc",
682 .id = 2,
683 .num_resources = ARRAY_SIZE(resources_sdc2),
684 .resource = resources_sdc2,
685 .dev = {
686 .coherent_dma_mask = 0xffffffff,
687 },
688};
689
690struct platform_device apq8064_device_sdc3 = {
691 .name = "msm_sdcc",
692 .id = 3,
693 .num_resources = ARRAY_SIZE(resources_sdc3),
694 .resource = resources_sdc3,
695 .dev = {
696 .coherent_dma_mask = 0xffffffff,
697 },
698};
699
700struct platform_device apq8064_device_sdc4 = {
701 .name = "msm_sdcc",
702 .id = 4,
703 .num_resources = ARRAY_SIZE(resources_sdc4),
704 .resource = resources_sdc4,
705 .dev = {
706 .coherent_dma_mask = 0xffffffff,
707 },
708};
709
710static struct platform_device *apq8064_sdcc_devices[] __initdata = {
711 &apq8064_device_sdc1,
712 &apq8064_device_sdc2,
713 &apq8064_device_sdc3,
714 &apq8064_device_sdc4,
715};
716
717int __init apq8064_add_sdcc(unsigned int controller,
718 struct mmc_platform_data *plat)
719{
720 struct platform_device *pdev;
721
722 if (!plat)
723 return 0;
724 if (controller < 1 || controller > 4)
725 return -EINVAL;
726
727 pdev = apq8064_sdcc_devices[controller-1];
728 pdev->dev.platform_data = plat;
729 return platform_device_register(pdev);
730}
731
Yan He06913ce2011-08-26 16:33:46 -0700732static struct resource resources_sps[] = {
733 {
734 .name = "pipe_mem",
735 .start = 0x12800000,
736 .end = 0x12800000 + 0x4000 - 1,
737 .flags = IORESOURCE_MEM,
738 },
739 {
740 .name = "bamdma_dma",
741 .start = 0x12240000,
742 .end = 0x12240000 + 0x1000 - 1,
743 .flags = IORESOURCE_MEM,
744 },
745 {
746 .name = "bamdma_bam",
747 .start = 0x12244000,
748 .end = 0x12244000 + 0x4000 - 1,
749 .flags = IORESOURCE_MEM,
750 },
751 {
752 .name = "bamdma_irq",
753 .start = SPS_BAM_DMA_IRQ,
754 .end = SPS_BAM_DMA_IRQ,
755 .flags = IORESOURCE_IRQ,
756 },
757};
758
Gagan Mac8a7a5d32011-11-11 16:43:06 -0700759struct platform_device msm_bus_8064_sys_fabric = {
760 .name = "msm_bus_fabric",
761 .id = MSM_BUS_FAB_SYSTEM,
762};
763struct platform_device msm_bus_8064_apps_fabric = {
764 .name = "msm_bus_fabric",
765 .id = MSM_BUS_FAB_APPSS,
766};
767struct platform_device msm_bus_8064_mm_fabric = {
768 .name = "msm_bus_fabric",
769 .id = MSM_BUS_FAB_MMSS,
770};
771struct platform_device msm_bus_8064_sys_fpb = {
772 .name = "msm_bus_fabric",
773 .id = MSM_BUS_FAB_SYSTEM_FPB,
774};
775struct platform_device msm_bus_8064_cpss_fpb = {
776 .name = "msm_bus_fabric",
777 .id = MSM_BUS_FAB_CPSS_FPB,
778};
779
Yan He06913ce2011-08-26 16:33:46 -0700780static struct msm_sps_platform_data msm_sps_pdata = {
781 .bamdma_restricted_pipes = 0x06,
782};
783
784struct platform_device msm_device_sps_apq8064 = {
785 .name = "msm_sps",
786 .id = -1,
787 .num_resources = ARRAY_SIZE(resources_sps),
788 .resource = resources_sps,
789 .dev.platform_data = &msm_sps_pdata,
790};
791
Jeff Hugo0c0f5e92011-09-28 13:55:45 -0600792struct platform_device msm_device_smd_apq8064 = {
793 .name = "msm_smd",
794 .id = -1,
795};
796
Ramesh Masavarapuf46be1b2011-11-03 11:13:41 -0700797#ifdef CONFIG_HW_RANDOM_MSM
798/* PRNG device */
799#define MSM_PRNG_PHYS 0x1A500000
800static struct resource rng_resources = {
801 .flags = IORESOURCE_MEM,
802 .start = MSM_PRNG_PHYS,
803 .end = MSM_PRNG_PHYS + SZ_512 - 1,
804};
805
806struct platform_device apq8064_device_rng = {
807 .name = "msm_rng",
808 .id = 0,
809 .num_resources = 1,
810 .resource = &rng_resources,
811};
812#endif
813
Matt Wagantall292aace2012-01-26 19:12:34 -0800814static struct resource msm_gss_resources[] = {
815 {
816 .start = 0x10000000,
817 .end = 0x10000000 + SZ_256 - 1,
818 .flags = IORESOURCE_MEM,
819 },
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800820 {
821 .start = 0x10008000,
822 .end = 0x10008000 + SZ_256 - 1,
823 .flags = IORESOURCE_MEM,
824 },
Matt Wagantall292aace2012-01-26 19:12:34 -0800825};
826
827struct platform_device msm_gss = {
828 .name = "pil_gss",
829 .id = -1,
830 .num_resources = ARRAY_SIZE(msm_gss_resources),
831 .resource = msm_gss_resources,
832};
833
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700834static struct clk_lookup msm_clocks_8064_dummy[] = {
835 CLK_DUMMY("pll2", PLL2, NULL, 0),
836 CLK_DUMMY("pll8", PLL8, NULL, 0),
837 CLK_DUMMY("pll4", PLL4, NULL, 0),
838
839 CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
840 CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
841 CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
842 CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
843 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
844 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
845 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
846 CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
847 CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
848 CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
849 CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
850 CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
851 CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
852 CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
853 CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
854 CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
855
Matt Wagantalle2522372011-08-17 14:52:21 -0700856 CLK_DUMMY("core_clk", GSBI1_UART_CLK, NULL, OFF),
857 CLK_DUMMY("core_clk", GSBI2_UART_CLK, NULL, OFF),
858 CLK_DUMMY("core_clk", GSBI3_UART_CLK,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700859 "msm_serial_hsl.0", OFF),
Matt Wagantalle2522372011-08-17 14:52:21 -0700860 CLK_DUMMY("core_clk", GSBI4_UART_CLK, NULL, OFF),
861 CLK_DUMMY("core_clk", GSBI5_UART_CLK, NULL, OFF),
862 CLK_DUMMY("core_clk", GSBI6_UART_CLK, NULL, OFF),
863 CLK_DUMMY("core_clk", GSBI7_UART_CLK, NULL, OFF),
864 CLK_DUMMY("core_clk", GSBI8_UART_CLK, NULL, OFF),
865 CLK_DUMMY("core_clk", GSBI9_UART_CLK, NULL, OFF),
866 CLK_DUMMY("core_clk", GSBI10_UART_CLK, NULL, OFF),
867 CLK_DUMMY("core_clk", GSBI11_UART_CLK, NULL, OFF),
868 CLK_DUMMY("core_clk", GSBI12_UART_CLK, NULL, OFF),
Matt Wagantall62cf63e2011-08-17 16:34:47 -0700869 CLK_DUMMY("core_clk", GSBI1_QUP_CLK, NULL, OFF),
870 CLK_DUMMY("core_clk", GSBI2_QUP_CLK, NULL, OFF),
871 CLK_DUMMY("core_clk", GSBI3_QUP_CLK, NULL, OFF),
Matt Wagantallac294852011-08-17 15:44:58 -0700872 CLK_DUMMY("core_clk", GSBI4_QUP_CLK, "qup_i2c.4", OFF),
873 CLK_DUMMY("core_clk", GSBI5_QUP_CLK, "spi_qsd.0", OFF),
Matt Wagantall62cf63e2011-08-17 16:34:47 -0700874 CLK_DUMMY("core_clk", GSBI6_QUP_CLK, NULL, OFF),
875 CLK_DUMMY("core_clk", GSBI7_QUP_CLK, NULL, OFF),
Matt Wagantallb86ad262011-10-24 19:50:29 -0700876 CLK_DUMMY("core_clk", PDM_CLK, NULL, OFF),
Matt Wagantalld86d6832011-08-17 14:06:55 -0700877 CLK_DUMMY("mem_clk", PMEM_CLK, NULL, OFF),
Ramesh Masavarapuf46be1b2011-11-03 11:13:41 -0700878 CLK_DUMMY("core_clk", PRNG_CLK, "msm_rng.0", OFF),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700879 CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF),
880 CLK_DUMMY("core_clk", SDC2_CLK, NULL, OFF),
881 CLK_DUMMY("core_clk", SDC3_CLK, NULL, OFF),
882 CLK_DUMMY("core_clk", SDC4_CLK, NULL, OFF),
Matt Wagantall640e5fd2011-08-17 16:08:53 -0700883 CLK_DUMMY("ref_clk", TSIF_REF_CLK, NULL, OFF),
Matt Wagantallb86ad262011-10-24 19:50:29 -0700884 CLK_DUMMY("core_clk", TSSC_CLK, NULL, OFF),
Manu Gautam5143b252012-01-05 19:25:23 -0800885 CLK_DUMMY("alt_core_clk", USB_HS1_XCVR_CLK, NULL, OFF),
886 CLK_DUMMY("alt_core_clk", USB_HS3_XCVR_CLK, NULL, OFF),
887 CLK_DUMMY("alt_core_clk", USB_HS4_XCVR_CLK, NULL, OFF),
888 CLK_DUMMY("phy_clk", USB_PHY0_CLK, NULL, OFF),
889 CLK_DUMMY("src_clk", USB_FS1_SRC_CLK, NULL, OFF),
890 CLK_DUMMY("alt_core_clk", USB_FS1_XCVR_CLK, NULL, OFF),
891 CLK_DUMMY("sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -0700892 CLK_DUMMY("core_clk", CE2_CLK, NULL, OFF),
893 CLK_DUMMY("core_clk", CE1_CORE_CLK, NULL, OFF),
894 CLK_DUMMY("core_clk", CE3_CORE_CLK, NULL, OFF),
895 CLK_DUMMY("iface_clk", CE3_P_CLK, NULL, OFF),
Tianyi Gou86bb4722011-08-09 13:28:02 -0700896 CLK_DUMMY("pcie_pclk", PCIE_P_CLK, NULL, OFF),
897 CLK_DUMMY("pcie_alt_ref_clk", PCIE_ALT_REF_CLK, NULL, OFF),
898 CLK_DUMMY("sata_rxoob_clk", SATA_RXOOB_CLK, NULL, OFF),
899 CLK_DUMMY("sata_pmalive_clk", SATA_PMALIVE_CLK, NULL, OFF),
Matt Wagantallb86ad262011-10-24 19:50:29 -0700900 CLK_DUMMY("ref_clk", SATA_PHY_REF_CLK, NULL, OFF),
Matt Wagantall62cf63e2011-08-17 16:34:47 -0700901 CLK_DUMMY("iface_clk", GSBI1_P_CLK, NULL, OFF),
902 CLK_DUMMY("iface_clk", GSBI2_P_CLK, NULL, OFF),
Matt Wagantalle2522372011-08-17 14:52:21 -0700903 CLK_DUMMY("iface_clk", GSBI3_P_CLK, "msm_serial_hsl.0", OFF),
Matt Wagantallac294852011-08-17 15:44:58 -0700904 CLK_DUMMY("iface_clk", GSBI4_P_CLK, "qup_i2c.4", OFF),
905 CLK_DUMMY("iface_clk", GSBI5_P_CLK, "spi_qsd.0", OFF),
Matt Wagantalle2522372011-08-17 14:52:21 -0700906 CLK_DUMMY("iface_clk", GSBI6_P_CLK, NULL, OFF),
Matt Wagantall62cf63e2011-08-17 16:34:47 -0700907 CLK_DUMMY("iface_clk", GSBI7_P_CLK, NULL, OFF),
Matt Wagantall640e5fd2011-08-17 16:08:53 -0700908 CLK_DUMMY("iface_clk", TSIF_P_CLK, NULL, OFF),
Manu Gautam5143b252012-01-05 19:25:23 -0800909 CLK_DUMMY("iface_clk", USB_FS1_P_CLK, NULL, OFF),
910 CLK_DUMMY("iface_clk", USB_HS1_P_CLK, NULL, OFF),
911 CLK_DUMMY("iface_clk", USB_HS3_P_CLK, NULL, OFF),
912 CLK_DUMMY("iface_clk", USB_HS4_P_CLK, NULL, OFF),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700913 CLK_DUMMY("iface_clk", SDC1_P_CLK, NULL, OFF),
914 CLK_DUMMY("iface_clk", SDC2_P_CLK, NULL, OFF),
915 CLK_DUMMY("iface_clk", SDC3_P_CLK, NULL, OFF),
916 CLK_DUMMY("iface_clk", SDC4_P_CLK, NULL, OFF),
Jin Hong01f2dbb2011-11-03 22:13:51 -0700917 CLK_DUMMY("core_clk", ADM0_CLK, "msm_dmov", OFF),
918 CLK_DUMMY("iface_clk", ADM0_P_CLK, "msm_dmov", OFF),
Matt Wagantallb86ad262011-10-24 19:50:29 -0700919 CLK_DUMMY("iface_clk", PMIC_ARB0_P_CLK, NULL, OFF),
920 CLK_DUMMY("iface_clk", PMIC_ARB1_P_CLK, NULL, OFF),
921 CLK_DUMMY("core_clk", PMIC_SSBI2_CLK, NULL, OFF),
922 CLK_DUMMY("mem_clk", RPM_MSG_RAM_P_CLK, NULL, OFF),
923 CLK_DUMMY("core_clk", AMP_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700924 CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
925 CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
926 CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
927 CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL, OFF),
928 CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
929 CLK_DUMMY("csi_clk", CSI1_CLK, NULL, OFF),
930 CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
931 CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
932 CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL, OFF),
933 CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL, OFF),
934 CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL, OFF),
935 CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, NULL, OFF),
936 CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, NULL, OFF),
937 CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, NULL, OFF),
938 CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, NULL, OFF),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700939 CLK_DUMMY("core_clk", VCAP_CLK, NULL, OFF),
940 CLK_DUMMY("npl_clk", VCAP_NPL_CLK, NULL, OFF),
Pu Chen86b4be92011-11-03 17:27:57 -0700941 CLK_DUMMY("core_clk", GFX3D_CLK, "kgsl-3d0.0", OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700942 CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700943 CLK_DUMMY("mem_clk", IMEM_CLK, NULL, OFF),
Matt Wagantallb86ad262011-10-24 19:50:29 -0700944 CLK_DUMMY("core_clk", JPEGD_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700945 CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
946 CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
947 CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
Matt Wagantallbb90da92011-10-25 15:07:52 -0700948 CLK_DUMMY("core_clk", ROT_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700949 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
Matt Wagantallb86ad262011-10-24 19:50:29 -0700950 CLK_DUMMY("core_clk", VCODEC_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700951 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
Tianyi Gou86bb4722011-08-09 13:28:02 -0700952 CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF),
953 CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700954 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -0700955 CLK_DUMMY("core_clk", HDMI_APP_CLK, "hdmi_msm.1", OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700956 CLK_DUMMY("vpe_clk", VPE_CLK, NULL, OFF),
957 CLK_DUMMY("vfe_clk", VFE_CLK, NULL, OFF),
958 CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL, OFF),
959 CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
960 CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
961 CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
Matt Wagantallbb90da92011-10-25 15:07:52 -0700962 CLK_DUMMY("bus_clk", ROT_AXI_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700963 CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
964 CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
965 CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
966 CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL, OFF),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700967 CLK_DUMMY("bus_clk", GFX3D_AXI_CLK, NULL, OFF),
Tianyi Gou86bb4722011-08-09 13:28:02 -0700968 CLK_DUMMY("vcap_axi_clk", VCAP_AXI_CLK, NULL, OFF),
969 CLK_DUMMY("vcap_ahb_clk", VCAP_AHB_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700970 CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL, OFF),
971 CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL, OFF),
972 CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, NULL, OFF),
973 CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, NULL, OFF),
974 CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, NULL, OFF),
975 CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, NULL, OFF),
Tianyi Gou86bb4722011-08-09 13:28:02 -0700976 CLK_DUMMY("lvds_clk", LVDS_CLK, NULL, OFF),
977 CLK_DUMMY("mdp_p2clk", MDP_P2CLK, NULL, OFF),
978 CLK_DUMMY("dsi2_pixel_clk", DSI2_PIXEL_CLK, NULL, OFF),
979 CLK_DUMMY("lvds_ref_clk", LVDS_REF_CLK, NULL, OFF),
Pu Chen86b4be92011-11-03 17:27:57 -0700980 CLK_DUMMY("iface_clk", GFX3D_P_CLK, "kgsl-3d0.0", OFF),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -0700981 CLK_DUMMY("master_iface_clk", HDMI_M_P_CLK, "hdmi_msm.1", OFF),
982 CLK_DUMMY("slave_iface_clk", HDMI_S_P_CLK, "hdmi_msm.1", OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700983 CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL, OFF),
984 CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700985 CLK_DUMMY("mem_iface_clk", IMEM_P_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700986 CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
Matt Wagantalle604d712011-10-21 15:38:18 -0700987 CLK_DUMMY("iface_clk", SMMU_P_CLK, "msm_smmu", OFF),
Matt Wagantallbb90da92011-10-25 15:07:52 -0700988 CLK_DUMMY("iface_clk", ROT_P_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700989 CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
990 CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
991 CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF),
992 CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
993 CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
994 CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
995 CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
996 CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
997 CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
998 CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
999 CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
1000 CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
1001 CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
1002 CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
Tianyi Gou142b8db2011-09-21 18:01:54 -07001003 CLK_DUMMY("audio_slimbus_clk", AUDIO_SLIMBUS_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001004
1005 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
Manu Gautam5143b252012-01-05 19:25:23 -08001006 CLK_DUMMY("core_clk", DFAB_USB_HS_CLK, NULL, 0),
Matt Wagantall37ce3842011-08-17 16:00:36 -07001007 CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, NULL, 0),
1008 CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, NULL, 0),
1009 CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, NULL, 0),
1010 CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, NULL, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001011 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
1012 CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0),
Jin Hong01f2dbb2011-11-03 22:13:51 -07001013 CLK_DUMMY("mem_clk", EBI1_ADM_CLK, "msm_dmov", 0),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07001014 CLK_DUMMY("ce3_core_src_clk", CE3_SRC_CLK, "qce.0", OFF),
1015 CLK_DUMMY("ce3_core_src_clk", CE3_SRC_CLK, "qcrypto.0", OFF),
1016 CLK_DUMMY("core_clk", CE3_CORE_CLK, "qce.0", OFF),
1017 CLK_DUMMY("core_clk", CE3_CORE_CLK, "qcrypto.0", OFF),
1018 CLK_DUMMY("iface_clk", CE3_P_CLK, "qce0.0", OFF),
1019 CLK_DUMMY("iface_clk", CE3_P_CLK, "qcrypto.0", OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001020};
1021
Stephen Boydbb600ae2011-08-02 20:11:40 -07001022struct clock_init_data apq8064_dummy_clock_init_data __initdata = {
1023 .table = msm_clocks_8064_dummy,
1024 .size = ARRAY_SIZE(msm_clocks_8064_dummy),
1025};
Praveen Chidambaram78499012011-11-01 17:15:17 -06001026
1027struct msm_rpm_platform_data apq8064_rpm_data __initdata = {
1028 .reg_base_addrs = {
1029 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
1030 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
1031 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
1032 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
1033 },
1034 .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
1035 .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
1036 .ipc_rpm_val = 4,
1037 .target_id = {
1038 MSM_RPM_MAP(8064, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
1039 MSM_RPM_MAP(8064, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
1040 MSM_RPM_MAP(8064, INVALIDATE_0, INVALIDATE, 8),
1041 MSM_RPM_MAP(8064, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
1042 MSM_RPM_MAP(8064, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
1043 MSM_RPM_MAP(8064, RPM_CTL, RPM_CTL, 1),
1044 MSM_RPM_MAP(8064, CXO_CLK, CXO_CLK, 1),
1045 MSM_RPM_MAP(8064, PXO_CLK, PXO_CLK, 1),
1046 MSM_RPM_MAP(8064, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
1047 MSM_RPM_MAP(8064, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
1048 MSM_RPM_MAP(8064, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
1049 MSM_RPM_MAP(8064, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
1050 MSM_RPM_MAP(8064, SFPB_CLK, SFPB_CLK, 1),
1051 MSM_RPM_MAP(8064, CFPB_CLK, CFPB_CLK, 1),
1052 MSM_RPM_MAP(8064, MMFPB_CLK, MMFPB_CLK, 1),
1053 MSM_RPM_MAP(8064, EBI1_CLK, EBI1_CLK, 1),
1054 MSM_RPM_MAP(8064, APPS_FABRIC_CFG_HALT_0,
1055 APPS_FABRIC_CFG_HALT, 2),
1056 MSM_RPM_MAP(8064, APPS_FABRIC_CFG_CLKMOD_0,
1057 APPS_FABRIC_CFG_CLKMOD, 3),
1058 MSM_RPM_MAP(8064, APPS_FABRIC_CFG_IOCTL,
1059 APPS_FABRIC_CFG_IOCTL, 1),
1060 MSM_RPM_MAP(8064, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
1061 MSM_RPM_MAP(8064, SYS_FABRIC_CFG_HALT_0,
1062 SYS_FABRIC_CFG_HALT, 2),
1063 MSM_RPM_MAP(8064, SYS_FABRIC_CFG_CLKMOD_0,
1064 SYS_FABRIC_CFG_CLKMOD, 3),
1065 MSM_RPM_MAP(8064, SYS_FABRIC_CFG_IOCTL,
1066 SYS_FABRIC_CFG_IOCTL, 1),
1067 MSM_RPM_MAP(8064, SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 30),
1068 MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_HALT_0,
1069 MMSS_FABRIC_CFG_HALT, 2),
1070 MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_CLKMOD_0,
1071 MMSS_FABRIC_CFG_CLKMOD, 3),
1072 MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_IOCTL,
1073 MMSS_FABRIC_CFG_IOCTL, 1),
1074 MSM_RPM_MAP(8064, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 21),
1075 MSM_RPM_MAP(8064, PM8921_S1_0, PM8921_S1, 2),
1076 MSM_RPM_MAP(8064, PM8921_S2_0, PM8921_S2, 2),
1077 MSM_RPM_MAP(8064, PM8921_S3_0, PM8921_S3, 2),
1078 MSM_RPM_MAP(8064, PM8921_S4_0, PM8921_S4, 2),
1079 MSM_RPM_MAP(8064, PM8921_S5_0, PM8921_S5, 2),
1080 MSM_RPM_MAP(8064, PM8921_S6_0, PM8921_S6, 2),
1081 MSM_RPM_MAP(8064, PM8921_S7_0, PM8921_S7, 2),
1082 MSM_RPM_MAP(8064, PM8921_S8_0, PM8921_S8, 2),
1083 MSM_RPM_MAP(8064, PM8921_L1_0, PM8921_L1, 2),
1084 MSM_RPM_MAP(8064, PM8921_L2_0, PM8921_L2, 2),
1085 MSM_RPM_MAP(8064, PM8921_L3_0, PM8921_L3, 2),
1086 MSM_RPM_MAP(8064, PM8921_L4_0, PM8921_L4, 2),
1087 MSM_RPM_MAP(8064, PM8921_L5_0, PM8921_L5, 2),
1088 MSM_RPM_MAP(8064, PM8921_L6_0, PM8921_L6, 2),
1089 MSM_RPM_MAP(8064, PM8921_L7_0, PM8921_L7, 2),
1090 MSM_RPM_MAP(8064, PM8921_L8_0, PM8921_L8, 2),
1091 MSM_RPM_MAP(8064, PM8921_L9_0, PM8921_L9, 2),
1092 MSM_RPM_MAP(8064, PM8921_L10_0, PM8921_L10, 2),
1093 MSM_RPM_MAP(8064, PM8921_L11_0, PM8921_L11, 2),
1094 MSM_RPM_MAP(8064, PM8921_L12_0, PM8921_L12, 2),
1095 MSM_RPM_MAP(8064, PM8921_L13_0, PM8921_L13, 2),
1096 MSM_RPM_MAP(8064, PM8921_L14_0, PM8921_L14, 2),
1097 MSM_RPM_MAP(8064, PM8921_L15_0, PM8921_L15, 2),
1098 MSM_RPM_MAP(8064, PM8921_L16_0, PM8921_L16, 2),
1099 MSM_RPM_MAP(8064, PM8921_L17_0, PM8921_L17, 2),
1100 MSM_RPM_MAP(8064, PM8921_L18_0, PM8921_L18, 2),
1101 MSM_RPM_MAP(8064, PM8921_L19_0, PM8921_L19, 2),
1102 MSM_RPM_MAP(8064, PM8921_L20_0, PM8921_L20, 2),
1103 MSM_RPM_MAP(8064, PM8921_L21_0, PM8921_L21, 2),
1104 MSM_RPM_MAP(8064, PM8921_L22_0, PM8921_L22, 2),
1105 MSM_RPM_MAP(8064, PM8921_L23_0, PM8921_L23, 2),
1106 MSM_RPM_MAP(8064, PM8921_L24_0, PM8921_L24, 2),
1107 MSM_RPM_MAP(8064, PM8921_L25_0, PM8921_L25, 2),
1108 MSM_RPM_MAP(8064, PM8921_L26_0, PM8921_L26, 2),
1109 MSM_RPM_MAP(8064, PM8921_L27_0, PM8921_L27, 2),
1110 MSM_RPM_MAP(8064, PM8921_L28_0, PM8921_L28, 2),
1111 MSM_RPM_MAP(8064, PM8921_L29_0, PM8921_L29, 2),
1112 MSM_RPM_MAP(8064, PM8921_CLK1_0, PM8921_CLK1, 2),
1113 MSM_RPM_MAP(8064, PM8921_CLK2_0, PM8921_CLK2, 2),
1114 MSM_RPM_MAP(8064, PM8921_LVS1, PM8921_LVS1, 1),
1115 MSM_RPM_MAP(8064, PM8921_LVS2, PM8921_LVS2, 1),
1116 MSM_RPM_MAP(8064, PM8921_LVS3, PM8921_LVS3, 1),
1117 MSM_RPM_MAP(8064, PM8921_LVS4, PM8921_LVS4, 1),
1118 MSM_RPM_MAP(8064, PM8921_LVS5, PM8921_LVS5, 1),
1119 MSM_RPM_MAP(8064, PM8921_LVS6, PM8921_LVS6, 1),
1120 MSM_RPM_MAP(8064, PM8921_LVS7, PM8921_LVS7, 1),
1121 MSM_RPM_MAP(8064, PM8821_S1_0, PM8821_S1, 2),
1122 MSM_RPM_MAP(8064, PM8821_S2_0, PM8821_S2, 2),
1123 MSM_RPM_MAP(8064, PM8821_L1_0, PM8821_L1, 2),
1124 MSM_RPM_MAP(8064, NCP_0, NCP, 2),
1125 MSM_RPM_MAP(8064, CXO_BUFFERS, CXO_BUFFERS, 1),
1126 MSM_RPM_MAP(8064, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
1127 MSM_RPM_MAP(8064, HDMI_SWITCH, HDMI_SWITCH, 1),
1128 MSM_RPM_MAP(8064, DDR_DMM_0, DDR_DMM, 2),
1129 MSM_RPM_MAP(8064, QDSS_CLK, QDSS_CLK, 1),
1130 },
1131 .target_status = {
1132 MSM_RPM_STATUS_ID_MAP(8064, VERSION_MAJOR),
1133 MSM_RPM_STATUS_ID_MAP(8064, VERSION_MINOR),
1134 MSM_RPM_STATUS_ID_MAP(8064, VERSION_BUILD),
1135 MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_0),
1136 MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_1),
1137 MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_2),
1138 MSM_RPM_STATUS_ID_MAP(8064, RESERVED_SUPPORTED_RESOURCES_0),
1139 MSM_RPM_STATUS_ID_MAP(8064, SEQUENCE),
1140 MSM_RPM_STATUS_ID_MAP(8064, RPM_CTL),
1141 MSM_RPM_STATUS_ID_MAP(8064, CXO_CLK),
1142 MSM_RPM_STATUS_ID_MAP(8064, PXO_CLK),
1143 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CLK),
1144 MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_CLK),
1145 MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_CLK),
1146 MSM_RPM_STATUS_ID_MAP(8064, DAYTONA_FABRIC_CLK),
1147 MSM_RPM_STATUS_ID_MAP(8064, SFPB_CLK),
1148 MSM_RPM_STATUS_ID_MAP(8064, CFPB_CLK),
1149 MSM_RPM_STATUS_ID_MAP(8064, MMFPB_CLK),
1150 MSM_RPM_STATUS_ID_MAP(8064, EBI1_CLK),
1151 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_HALT),
1152 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_CLKMOD),
1153 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_IOCTL),
1154 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_ARB),
1155 MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_HALT),
1156 MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_CLKMOD),
1157 MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_IOCTL),
1158 MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_ARB),
1159 MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_HALT),
1160 MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_CLKMOD),
1161 MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_IOCTL),
1162 MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_ARB),
1163 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_0),
1164 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_1),
1165 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_0),
1166 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_1),
1167 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_0),
1168 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_1),
1169 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_0),
1170 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_1),
1171 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_0),
1172 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_1),
1173 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_0),
1174 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_1),
1175 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_0),
1176 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_1),
1177 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_0),
1178 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_1),
1179 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_0),
1180 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_1),
1181 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_0),
1182 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_1),
1183 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_0),
1184 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_1),
1185 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_0),
1186 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_1),
1187 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_0),
1188 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_1),
1189 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_0),
1190 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_1),
1191 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_0),
1192 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_1),
1193 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_0),
1194 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_1),
1195 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_0),
1196 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_1),
1197 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_0),
1198 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_1),
1199 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_0),
1200 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_1),
1201 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_0),
1202 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_1),
1203 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_0),
1204 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_1),
1205 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_0),
1206 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_1),
1207 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_0),
1208 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_1),
1209 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_0),
1210 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_1),
1211 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_0),
1212 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_1),
1213 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_0),
1214 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_1),
1215 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_0),
1216 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_1),
1217 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_0),
1218 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_1),
1219 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_0),
1220 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_1),
1221 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_0),
1222 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_1),
1223 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_0),
1224 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_1),
1225 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_0),
1226 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_1),
1227 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_0),
1228 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_1),
1229 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_0),
1230 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_1),
1231 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_0),
1232 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_1),
1233 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_0),
1234 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_1),
1235 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_0),
1236 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_1),
1237 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_0),
1238 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_1),
1239 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_0),
1240 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_1),
1241 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS1),
1242 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS2),
1243 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS3),
1244 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS4),
1245 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS5),
1246 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS6),
1247 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS7),
1248 MSM_RPM_STATUS_ID_MAP(8064, NCP_0),
1249 MSM_RPM_STATUS_ID_MAP(8064, NCP_1),
1250 MSM_RPM_STATUS_ID_MAP(8064, CXO_BUFFERS),
1251 MSM_RPM_STATUS_ID_MAP(8064, USB_OTG_SWITCH),
1252 MSM_RPM_STATUS_ID_MAP(8064, HDMI_SWITCH),
1253 MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_0),
1254 MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_1),
1255 MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH0_RANGE),
1256 MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH1_RANGE),
1257 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_0),
1258 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_1),
1259 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_0),
1260 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_1),
1261 MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_0),
1262 MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_1),
1263 },
1264 .target_ctrl_id = {
1265 MSM_RPM_CTRL_MAP(8064, VERSION_MAJOR),
1266 MSM_RPM_CTRL_MAP(8064, VERSION_MINOR),
1267 MSM_RPM_CTRL_MAP(8064, VERSION_BUILD),
1268 MSM_RPM_CTRL_MAP(8064, REQ_CTX_0),
1269 MSM_RPM_CTRL_MAP(8064, REQ_SEL_0),
1270 MSM_RPM_CTRL_MAP(8064, ACK_CTX_0),
1271 MSM_RPM_CTRL_MAP(8064, ACK_SEL_0),
1272 },
1273 .sel_invalidate = MSM_RPM_8064_SEL_INVALIDATE,
1274 .sel_notification = MSM_RPM_8064_SEL_NOTIFICATION,
1275 .sel_last = MSM_RPM_8064_SEL_LAST,
1276 .ver = {3, 0, 0},
1277};
1278
1279struct platform_device apq8064_rpm_device = {
1280 .name = "msm_rpm",
1281 .id = -1,
1282};
1283
1284static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
1285 .phys_addr_base = 0x0010D204,
1286 .phys_size = SZ_8K,
1287};
1288
1289struct platform_device apq8064_rpm_stat_device = {
1290 .name = "msm_rpm_stat",
1291 .id = -1,
1292 .dev = {
1293 .platform_data = &msm_rpm_stat_pdata,
1294 },
1295};
1296
1297static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
1298 .phys_addr_base = 0x0010C000,
1299 .reg_offsets = {
1300 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
1301 [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
1302 },
1303 .phys_size = SZ_8K,
1304 .log_len = 4096, /* log's buffer length in bytes */
1305 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
1306};
1307
1308struct platform_device apq8064_rpm_log_device = {
1309 .name = "msm_rpm_log",
1310 .id = -1,
1311 .dev = {
1312 .platform_data = &msm_rpm_log_pdata,
1313 },
1314};
1315
1316#ifdef CONFIG_MSM_MPM
1317static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
1318 [1] = MSM_GPIO_TO_INT(26),
1319 [2] = MSM_GPIO_TO_INT(88),
1320 [4] = MSM_GPIO_TO_INT(73),
1321 [5] = MSM_GPIO_TO_INT(74),
1322 [6] = MSM_GPIO_TO_INT(75),
1323 [7] = MSM_GPIO_TO_INT(76),
1324 [8] = MSM_GPIO_TO_INT(77),
1325 [9] = MSM_GPIO_TO_INT(36),
1326 [10] = MSM_GPIO_TO_INT(84),
1327 [11] = MSM_GPIO_TO_INT(7),
1328 [12] = MSM_GPIO_TO_INT(11),
1329 [13] = MSM_GPIO_TO_INT(52),
1330 [14] = MSM_GPIO_TO_INT(15),
1331 [15] = MSM_GPIO_TO_INT(83),
1332 [16] = USB3_HS_IRQ,
1333 [19] = MSM_GPIO_TO_INT(61),
1334 [20] = MSM_GPIO_TO_INT(58),
1335 [23] = MSM_GPIO_TO_INT(65),
1336 [24] = MSM_GPIO_TO_INT(63),
1337 [25] = USB1_HS_IRQ,
1338 [27] = HDMI_IRQ,
1339 [29] = MSM_GPIO_TO_INT(22),
1340 [30] = MSM_GPIO_TO_INT(72),
1341 [31] = USB4_HS_IRQ,
1342 [33] = MSM_GPIO_TO_INT(44),
1343 [34] = MSM_GPIO_TO_INT(39),
1344 [35] = MSM_GPIO_TO_INT(19),
1345 [36] = MSM_GPIO_TO_INT(23),
1346 [37] = MSM_GPIO_TO_INT(41),
1347 [38] = MSM_GPIO_TO_INT(30),
1348 [41] = MSM_GPIO_TO_INT(42),
1349 [42] = MSM_GPIO_TO_INT(56),
1350 [43] = MSM_GPIO_TO_INT(55),
1351 [44] = MSM_GPIO_TO_INT(50),
1352 [45] = MSM_GPIO_TO_INT(49),
1353 [46] = MSM_GPIO_TO_INT(47),
1354 [47] = MSM_GPIO_TO_INT(45),
1355 [48] = MSM_GPIO_TO_INT(38),
1356 [49] = MSM_GPIO_TO_INT(34),
1357 [50] = MSM_GPIO_TO_INT(32),
1358 [51] = MSM_GPIO_TO_INT(29),
1359 [52] = MSM_GPIO_TO_INT(18),
1360 [53] = MSM_GPIO_TO_INT(10),
1361 [54] = MSM_GPIO_TO_INT(81),
1362 [55] = MSM_GPIO_TO_INT(6),
1363};
1364
1365static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
1366 TLMM_MSM_SUMMARY_IRQ,
1367 RPM_APCC_CPU0_GP_HIGH_IRQ,
1368 RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1369 RPM_APCC_CPU0_GP_LOW_IRQ,
1370 RPM_APCC_CPU0_WAKE_UP_IRQ,
1371 RPM_APCC_CPU1_GP_HIGH_IRQ,
1372 RPM_APCC_CPU1_GP_MEDIUM_IRQ,
1373 RPM_APCC_CPU1_GP_LOW_IRQ,
1374 RPM_APCC_CPU1_WAKE_UP_IRQ,
1375 MSS_TO_APPS_IRQ_0,
1376 MSS_TO_APPS_IRQ_1,
1377 MSS_TO_APPS_IRQ_2,
1378 MSS_TO_APPS_IRQ_3,
1379 MSS_TO_APPS_IRQ_4,
1380 MSS_TO_APPS_IRQ_5,
1381 MSS_TO_APPS_IRQ_6,
1382 MSS_TO_APPS_IRQ_7,
1383 MSS_TO_APPS_IRQ_8,
1384 MSS_TO_APPS_IRQ_9,
1385 LPASS_SCSS_GP_LOW_IRQ,
1386 LPASS_SCSS_GP_MEDIUM_IRQ,
1387 LPASS_SCSS_GP_HIGH_IRQ,
1388 SPS_MTI_30,
1389 SPS_MTI_31,
1390 RIVA_APSS_SPARE_IRQ,
1391 RIVA_APPS_WLAN_SMSM_IRQ,
1392 RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
1393 RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
1394};
1395
1396struct msm_mpm_device_data apq8064_mpm_dev_data __initdata = {
1397 .irqs_m2a = msm_mpm_irqs_m2a,
1398 .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
1399 .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
1400 .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
1401 .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
1402 .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
1403 .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
1404 .mpm_apps_ipc_val = BIT(1),
1405 .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1406
1407};
1408#endif
Joel Kingdacbc822012-01-25 13:30:57 -08001409
1410#define MDM2AP_ERRFATAL 19
1411#define AP2MDM_ERRFATAL 18
1412#define MDM2AP_STATUS 49
1413#define AP2MDM_STATUS 48
1414#define AP2MDM_PMIC_RESET_N 27
1415
1416static struct resource mdm_resources[] = {
1417 {
1418 .start = MDM2AP_ERRFATAL,
1419 .end = MDM2AP_ERRFATAL,
1420 .name = "MDM2AP_ERRFATAL",
1421 .flags = IORESOURCE_IO,
1422 },
1423 {
1424 .start = AP2MDM_ERRFATAL,
1425 .end = AP2MDM_ERRFATAL,
1426 .name = "AP2MDM_ERRFATAL",
1427 .flags = IORESOURCE_IO,
1428 },
1429 {
1430 .start = MDM2AP_STATUS,
1431 .end = MDM2AP_STATUS,
1432 .name = "MDM2AP_STATUS",
1433 .flags = IORESOURCE_IO,
1434 },
1435 {
1436 .start = AP2MDM_STATUS,
1437 .end = AP2MDM_STATUS,
1438 .name = "AP2MDM_STATUS",
1439 .flags = IORESOURCE_IO,
1440 },
1441 {
1442 .start = AP2MDM_PMIC_RESET_N,
1443 .end = AP2MDM_PMIC_RESET_N,
1444 .name = "AP2MDM_PMIC_RESET_N",
1445 .flags = IORESOURCE_IO,
1446 },
1447};
1448
1449struct platform_device mdm_8064_device = {
1450 .name = "mdm2_modem",
1451 .id = -1,
1452 .num_resources = ARRAY_SIZE(mdm_resources),
1453 .resource = mdm_resources,
1454};
1455