blob: cb33a408e2b03d4146cfef8608704f3678fa674b [file] [log] [blame]
Mitchel Humpherys85d08692012-10-23 12:56:35 -07001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/include/ "skeleton.dtsi"
Mitchel Humpherys52ffaec2012-10-09 15:40:13 -070014/include/ "msm8226-ion.dtsi"
Patrick Dalye8977aa2012-11-06 15:25:58 -080015/include/ "msm-gdsc.dtsi"
Mitchel Humpherys85d08692012-10-23 12:56:35 -070016/include/ "msm8226-iommu.dtsi"
Praveen Chidambaramc8af25e2012-12-19 11:27:36 -070017/include/ "msm8226-pm.dtsi"
Eric Holmberg3d112ee2013-01-29 19:12:39 -070018/include/ "msm8226-smp2p.dtsi"
liu zhongf5c0edb2013-01-25 11:18:53 -070019/include/ "msm8226-gpu.dtsi"
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070020
21/ {
22 model = "Qualcomm MSM 8226";
23 compatible = "qcom,msm8226";
24 interrupt-parent = <&intc>;
25
26 intc: interrupt-controller@f9000000 {
27 compatible = "qcom,msm-qgic2";
28 interrupt-controller;
29 #interrupt-cells = <3>;
30 reg = <0xF9000000 0x1000>,
31 <0xF9002000 0x1000>;
32 };
33
34 msmgpio: gpio@fd510000 {
35 compatible = "qcom,msm-gpio";
36 interrupt-controller;
37 #interrupt-cells = <2>;
38 reg = <0xfd510000 0x4000>;
Syed Rameez Mustafa86cccfc2012-12-10 18:06:08 -080039 gpio-controller;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070040 #gpio-cells = <2>;
Rohit Vaswani341c2032012-11-08 18:49:29 -080041 ngpio = <117>;
Rohit Vaswanid2001522012-12-05 19:23:44 -080042 interrupts = <0 208 0>;
Rohit Vaswanied0a4ef2012-12-11 15:14:42 -080043 qcom,direct-connect-irqs = <8>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070044 };
45
46 timer {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -080047 compatible = "arm,armv7-timer";
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070048 interrupts = <1 2 0 1 3 0>;
49 clock-frequency = <19200000>;
50 };
51
52 serial@f991f000 {
53 compatible = "qcom,msm-lsuart-v14";
54 reg = <0xf991f000 0x1000>;
55 interrupts = <0 109 0>;
56 status = "disabled";
57 };
58
59 serial@f995e000 {
60 compatible = "qcom,msm-lsuart-v14";
61 reg = <0xf995e000 0x1000>;
62 interrupts = <0 114 0>;
63 status = "disabled";
64 };
65
Abhimanyu Kapur032b1f42013-01-18 00:10:50 -080066 qcom,msm-imem@fe805000 {
67 compatible = "qcom,msm-imem";
68 reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
69 };
70
Yan He7c06ce32012-12-03 17:12:31 -080071 qcom,sps@f9984000 {
72 compatible = "qcom,msm_sps";
73 reg = <0xf9984000 0x15000>,
74 <0xf9999000 0xb000>;
75 interrupts = <0 94 0>;
76 };
77
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070078 usb@f9a55000 {
79 compatible = "qcom,hsusb-otg";
80 reg = <0xf9a55000 0x400>;
Mayank Ranaac2a54f2013-01-17 10:14:35 +053081 interrupts = <0 134 0>, <0 140 0>;
82 interrupt-names = "core_irq", "async_irq";
83 HSUSB_VDDCX-supply = <&pm8026_s1>;
84 HSUSB_1p8-supply = <&pm8026_l10>;
85 HSUSB_3p3-supply = <&pm8026_l20>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070086
87 qcom,hsusb-otg-phy-type = <2>;
88 qcom,hsusb-otg-mode = <1>;
89 qcom,hsusb-otg-otg-control = <1>;
90 qcom,hsusb-otg-disable-reset;
91 };
92
Mayank Rana6bd9a272013-01-29 16:23:23 +053093 android_usb@fe8050c8 {
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070094 compatible = "qcom,android-usb";
Mayank Rana6bd9a272013-01-29 16:23:23 +053095 reg = <0xfe8050c8 0xc8>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070096 };
97
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -080098 wcd9xxx_intc: wcd9xxx-irq {
99 compatible = "qcom,wcd9xxx-irq";
100 interrupt-controller;
101 #interrupt-cells = <1>;
102 interrupt-parent = <&msmgpio>;
103 interrupts = <68 0>;
104 interrupt-names = "cdc-int";
105 };
106
Bhalchandra Gajarefb785972012-12-06 19:25:10 -0800107 slim@fe12f000 {
108 cell-index = <1>;
109 compatible = "qcom,slim-ngd";
110 reg = <0xfe12f000 0x35000>,
111 <0xfe104000 0x20000>;
112 reg-names = "slimbus_physical", "slimbus_bam_physical";
113 interrupts = <0 163 0>, <0 164 0>;
114 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800115
116 tapan_codec {
117 compatible = "qcom,tapan-slim-pgd";
118 elemental-addr = [00 01 E0 00 17 02];
119
120 interrupt-parent = <&wcd9xxx_intc>;
121 interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
122 17 18 19 20 21 22 23 24 25 26 27 28>;
123 qcom,cdc-reset-gpio = <&msmgpio 72 0>;
124
125 cdc-vdd-buck-supply = <&pm8026_s4>;
126 qcom,cdc-vdd-buck-voltage = <2100000 2100000>;
127 qcom,cdc-vdd-buck-current = <650000>;
128
129 cdc-vdd-h-supply = <&pm8026_l6>;
130 qcom,cdc-vdd-h-voltage = <1800000 1800000>;
131 qcom,cdc-vdd-h-current = <25000>;
132
133 cdc-vdd-px-supply = <&pm8026_l6>;
134 qcom,cdc-vdd-px-voltage = <1800000 1800000>;
135 qcom,cdc-vdd-px-current = <25000>;
136
137 cdc-vdd-a-1p2v-supply = <&pm8026_l4>;
138 qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
139 qcom,cdc-vdd-a-1p2v-current = <10000>;
140
141 cdc-vdd-cx-supply = <&pm8026_l4>;
142 qcom,cdc-vdd-cx-voltage = <1200000 1200000>;
143 qcom,cdc-vdd-cx-current = <10000>;
144
145 qcom,cdc-micbias-ldoh-v = <0x3>;
146 qcom,cdc-micbias-cfilt1-mv = <1800>;
147 qcom,cdc-micbias-cfilt2-mv = <1800>;
148 qcom,cdc-micbias-cfilt3-mv = <1800>;
149
150 qcom,cdc-micbias1-cfilt-sel = <0x0>;
151 qcom,cdc-micbias2-cfilt-sel = <0x1>;
152 qcom,cdc-micbias3-cfilt-sel = <0x2>;
153
154 qcom,cdc-mclk-clk-rate = <9600000>;
155 qcom,cdc-slim-ifd = "tapan-slim-ifd";
156 qcom,cdc-slim-ifd-elemental-addr = [00 00 E0 00 17 02];
157 };
Bhalchandra Gajarefb785972012-12-06 19:25:10 -0800158 };
159
Bhalchandra Gajaree1915b82012-12-12 17:28:39 -0800160 qcom,msm-adsp-loader {
161 compatible = "qcom,adsp-loader";
162 qcom,adsp-state = <0>;
163 };
164
Bhalchandra Gajare03a40ec2012-12-17 11:38:28 -0800165 sound {
166 compatible = "qcom,msm8226-audio-tapan";
167 qcom,model = "msm8226-tapan-snd-card";
168
169 qcom,audio-routing =
170 "RX_BIAS", "MCLK",
171 "LDO_H", "MCLK",
172 "AMIC1", "MIC BIAS1 Internal1",
173 "MIC BIAS1 Internal1", "Handset Mic",
174 "AMIC2", "MIC BIAS2 External",
175 "MIC BIAS2 External", "Headset Mic",
176 "AMIC3", "MIC BIAS2 External",
177 "MIC BIAS2 External", "ANCRight Headset Mic",
178 "AMIC4", "MIC BIAS2 External",
179 "MIC BIAS2 External", "ANCLeft Headset Mic",
180 "DMIC1", "MIC BIAS1 External",
181 "MIC BIAS1 External", "Digital Mic1",
182 "DMIC2", "MIC BIAS1 External",
183 "MIC BIAS1 External", "Digital Mic2",
184 "DMIC3", "MIC BIAS3 External",
185 "MIC BIAS3 External", "Digital Mic3",
186 "DMIC4", "MIC BIAS3 External",
187 "MIC BIAS3 External", "Digital Mic4",
188 "DMIC5", "MIC BIAS4 External",
189 "MIC BIAS4 External", "Digital Mic5",
190 "DMIC6", "MIC BIAS4 External",
191 "MIC BIAS4 External", "Digital Mic6";
192 qcom,tapan-mclk-clk-freq = <9600000>;
193 };
194
195 qcom,msm-pcm {
196 compatible = "qcom,msm-pcm-dsp";
197 };
198
199 qcom,msm-pcm-routing {
200 compatible = "qcom,msm-pcm-routing";
201 };
202
203 qcom,msm-pcm-lpa {
204 compatible = "qcom,msm-pcm-lpa";
205 };
206
207 qcom,msm-compr-dsp {
208 compatible = "qcom,msm-compr-dsp";
209 };
210
211 qcom,msm-voip-dsp {
212 compatible = "qcom,msm-voip-dsp";
213 };
214
215 qcom,msm-pcm-voice {
216 compatible = "qcom,msm-pcm-voice";
217 };
218
219 qcom,msm-stub-codec {
220 compatible = "qcom,msm-stub-codec";
221 };
222
223 qcom,msm-dai-fe {
224 compatible = "qcom,msm-dai-fe";
225 };
226
227 qcom,msm-pcm-afe {
228 compatible = "qcom,msm-pcm-afe";
229 };
230
231 qcom,msm-dai-q6-hdmi {
232 compatible = "qcom,msm-dai-q6-hdmi";
233 qcom,msm-dai-q6-dev-id = <8>;
234 };
235
236 qcom,msm-dai-q6 {
237 compatible = "qcom,msm-dai-q6";
238 qcom,msm-dai-q6-sb-0-rx {
239 compatible = "qcom,msm-dai-q6-dev";
240 qcom,msm-dai-q6-dev-id = <16384>;
241 };
242
243 qcom,msm-dai-q6-sb-0-tx {
244 compatible = "qcom,msm-dai-q6-dev";
245 qcom,msm-dai-q6-dev-id = <16385>;
246 };
247
248 qcom,msm-dai-q6-sb-1-rx {
249 compatible = "qcom,msm-dai-q6-dev";
250 qcom,msm-dai-q6-dev-id = <16386>;
251 };
252
253 qcom,msm-dai-q6-sb-1-tx {
254 compatible = "qcom,msm-dai-q6-dev";
255 qcom,msm-dai-q6-dev-id = <16387>;
256 };
257
258 qcom,msm-dai-q6-sb-3-rx {
259 compatible = "qcom,msm-dai-q6-dev";
260 qcom,msm-dai-q6-dev-id = <16390>;
261 };
262
263 qcom,msm-dai-q6-sb-3-tx {
264 compatible = "qcom,msm-dai-q6-dev";
265 qcom,msm-dai-q6-dev-id = <16391>;
266 };
267
268 qcom,msm-dai-q6-sb-4-rx {
269 compatible = "qcom,msm-dai-q6-dev";
270 qcom,msm-dai-q6-dev-id = <16392>;
271 };
272
273 qcom,msm-dai-q6-sb-4-tx {
274 compatible = "qcom,msm-dai-q6-dev";
275 qcom,msm-dai-q6-dev-id = <16393>;
276 };
277
278 qcom,msm-dai-q6-bt-sco-rx {
279 compatible = "qcom,msm-dai-q6-dev";
280 qcom,msm-dai-q6-dev-id = <12288>;
281 };
282
283 qcom,msm-dai-q6-bt-sco-tx {
284 compatible = "qcom,msm-dai-q6-dev";
285 qcom,msm-dai-q6-dev-id = <12289>;
286 };
287
288 qcom,msm-dai-q6-int-fm-rx {
289 compatible = "qcom,msm-dai-q6-dev";
290 qcom,msm-dai-q6-dev-id = <12292>;
291 };
292
293 qcom,msm-dai-q6-int-fm-tx {
294 compatible = "qcom,msm-dai-q6-dev";
295 qcom,msm-dai-q6-dev-id = <12293>;
296 };
297
298 qcom,msm-dai-q6-be-afe-pcm-rx {
299 compatible = "qcom,msm-dai-q6-dev";
300 qcom,msm-dai-q6-dev-id = <224>;
301 };
302
303 qcom,msm-dai-q6-be-afe-pcm-tx {
304 compatible = "qcom,msm-dai-q6-dev";
305 qcom,msm-dai-q6-dev-id = <225>;
306 };
307
308 qcom,msm-dai-q6-afe-proxy-rx {
309 compatible = "qcom,msm-dai-q6-dev";
310 qcom,msm-dai-q6-dev-id = <241>;
311 };
312
313 qcom,msm-dai-q6-afe-proxy-tx {
314 compatible = "qcom,msm-dai-q6-dev";
315 qcom,msm-dai-q6-dev-id = <240>;
316 };
317 };
318
319 qcom,msm-pcm-hostless {
320 compatible = "qcom,msm-pcm-hostless";
321 };
322
Mitchel Humpherys5fe1c9b2012-10-09 17:30:19 -0700323 qcom,wdt@f9017000 {
324 compatible = "qcom,msm-watchdog";
325 reg = <0xf9017000 0x1000>;
326 interrupts = <0 3 0>, <0 4 0>;
327 qcom,bark-time = <11000>;
328 qcom,pet-time = <10000>;
Mitchel Humpherys1be23802012-11-16 15:52:32 -0800329 qcom,ipi-ping;
Mitchel Humpherys5fe1c9b2012-10-09 17:30:19 -0700330 };
331
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600332 qcom,smem@fa00000 {
333 compatible = "qcom,smem";
334 reg = <0xfa00000 0x200000>,
335 <0xfa006000 0x1000>,
336 <0xfc428000 0x4000>;
337 reg-names = "smem", "irq-reg-base", "aux-mem1";
338
339 qcom,smd-modem {
340 compatible = "qcom,smd";
341 qcom,smd-edge = <0>;
342 qcom,smd-irq-offset = <0x8>;
343 qcom,smd-irq-bitmask = <0x1000>;
344 qcom,pil-string = "modem";
345 interrupts = <0 25 1>;
David Ngb715e322012-12-01 12:57:08 -0800346 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600347
348 qcom,smsm-modem {
349 compatible = "qcom,smsm";
350 qcom,smsm-edge = <0>;
351 qcom,smsm-irq-offset = <0x8>;
352 qcom,smsm-irq-bitmask = <0x2000>;
353 interrupts = <0 26 1>;
David Ngb715e322012-12-01 12:57:08 -0800354 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600355
356 qcom,smd-adsp {
357 compatible = "qcom,smd";
358 qcom,smd-edge = <1>;
359 qcom,smd-irq-offset = <0x8>;
360 qcom,smd-irq-bitmask = <0x100>;
361 qcom,pil-string = "adsp";
362 interrupts = <0 156 1>;
David Ngb715e322012-12-01 12:57:08 -0800363 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600364
365 qcom,smsm-adsp {
366 compatible = "qcom,smsm";
367 qcom,smsm-edge = <1>;
368 qcom,smsm-irq-offset = <0x8>;
369 qcom,smsm-irq-bitmask = <0x200>;
370 interrupts = <0 157 1>;
David Ngb715e322012-12-01 12:57:08 -0800371 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600372
373 qcom,smd-wcnss {
374 compatible = "qcom,smd";
375 qcom,smd-edge = <6>;
376 qcom,smd-irq-offset = <0x8>;
377 qcom,smd-irq-bitmask = <0x20000>;
378 qcom,pil-string = "wcnss";
379 interrupts = <0 142 1>;
David Ngb715e322012-12-01 12:57:08 -0800380 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600381
382 qcom,smsm-wcnss {
383 compatible = "qcom,smsm";
384 qcom,smsm-edge = <6>;
385 qcom,smsm-irq-offset = <0x8>;
386 qcom,smsm-irq-bitmask = <0x80000>;
387 interrupts = <0 144 1>;
David Ngb715e322012-12-01 12:57:08 -0800388 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600389
390 qcom,smd-rpm {
391 compatible = "qcom,smd";
392 qcom,smd-edge = <15>;
393 qcom,smd-irq-offset = <0x8>;
394 qcom,smd-irq-bitmask = <0x1>;
395 interrupts = <0 168 1>;
396 qcom,irq-no-suspend;
David Ngb715e322012-12-01 12:57:08 -0800397 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600398 };
399
Praveen Chidambaramc8af25e2012-12-19 11:27:36 -0700400 rpm_bus: qcom,rpm-smd {
401 compatible = "qcom,rpm-smd";
402 rpm-channel-name = "rpm_requests";
403 rpm-channel-type = <15>; /* SMD_APPS_RPM */
404 rpm-standalone;
405 };
406
Asutosh Das99912e62012-12-06 12:38:46 +0530407 sdcc1: qcom,sdcc@f9824000 {
408 cell-index = <1>; /* SDC1 eMMC slot */
409 compatible = "qcom,msm-sdcc";
410
Asutosh Das6b82fc52012-11-23 12:00:26 +0530411 reg = <0xf9824000 0x800>,
412 <0xf9824800 0x100>,
413 <0xf9804000 0x7000>;
414 reg-names = "core_mem", "dml_mem", "bam_mem";
415 interrupts = <0 123 0>, <0 137 0>;
416 interrupt-names = "core_irq", "bam_irq";
Asutosh Das99912e62012-12-06 12:38:46 +0530417
418 qcom,bus-width = <8>;
419 status = "disabled";
420 };
421
422 sdcc2: qcom,sdcc@f98a4000 {
423 cell-index = <2>; /* SDC2 SD card slot */
424 compatible = "qcom,msm-sdcc";
425
Asutosh Das6b82fc52012-11-23 12:00:26 +0530426 reg = <0xf98a4000 0x800>,
427 <0xf98a4800 0x100>,
428 <0xf9884000 0x7000>;
429 reg-names = "core_mem", "dml_mem", "bam_mem";
430 interrupts = <0 125 0>, <0 220 0>;
431 interrupt-names = "core_irq", "bam_irq";
Asutosh Das99912e62012-12-06 12:38:46 +0530432
433 qcom,bus-width = <4>;
434 status = "disabled";
435 };
Kenneth Heitkee5804002012-11-15 17:50:07 -0700436
437 spmi_bus: qcom,spmi@fc4c0000 {
438 cell-index = <0>;
439 compatible = "qcom,spmi-pmic-arb";
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700440 reg-names = "core", "intr", "cnfg";
Kenneth Heitkee5804002012-11-15 17:50:07 -0700441 reg = <0xfc4cf000 0x1000>,
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700442 <0Xfc4cb000 0x1000>,
443 <0Xfc4ca000 0x1000>;
Kenneth Heitkee5804002012-11-15 17:50:07 -0700444 /* 190,ee0_krait_hlos_spmi_periph_irq */
445 /* 187,channel_0_krait_hlos_trans_done_irq */
446 interrupts = <0 190 0>, <0 187 0>;
447 qcom,not-wakeup;
448 qcom,pmic-arb-ee = <0>;
449 qcom,pmic-arb-channel = <0>;
Kenneth Heitkee5804002012-11-15 17:50:07 -0700450 };
451
Gilad Avidov28e18eb2012-11-21 18:13:25 -0700452 i2c@f9926000 { /* BLSP-1 QUP-4 */
453 cell-index = <0>;
454 compatible = "qcom,i2c-qup";
455 reg = <0xf9926000 0x1000>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 reg-names = "qup_phys_addr";
459 interrupts = <0 98 0>;
460 interrupt-names = "qup_err_intr";
461 qcom,i2c-bus-freq = <100000>;
462 };
Patrick Daly99a52ca2012-10-23 12:00:45 -0700463
464 qcom,acpuclk@f9011050 {
465 compatible = "qcom,acpuclk-a7";
466 reg = <0xf9011050 0x8>;
467 reg-names = "rcg_base";
468 a7_cpu-supply = <&pm8026_s2>;
469 a7_mem-supply = <&pm8026_l3>;
470 };
Mitchel Humpherys00beacf2012-10-11 13:53:43 -0700471
472 qcom,ocmem@fdd00000 {
473 compatible = "qcom,msm-ocmem";
474 reg = <0xfdd00000 0x2000>,
475 <0xfdd02000 0x2000>,
476 <0xfe039000 0x400>,
477 <0xfec00000 0x180000>;
478 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
479 interrupts = <0 76 0 0 77 0>;
480 interrupt-names = "ocmem_irq", "dm_irq";
481 qcom,ocmem-num-regions = <0x1>;
482 qcom,ocmem-num-macros = <0x2>;
483 qcom,resource-type = <0x706d636f>;
484 #address-cells = <1>;
485 #size-cells = <1>;
486 ranges = <0x0 0xfec00000 0x180000>;
487
488 partition@0 {
489 reg = <0x0 0x100000>;
490 qcom,ocmem-part-name = "graphics";
491 qcom,ocmem-part-min = <0x80000>;
492 };
493 };
494
Patrick Dalyb83f0b02013-01-09 12:36:19 -0800495 qcom,venus@fdce0000 {
496 compatible = "qcom,pil-venus";
497 reg = <0xfdce0000 0x4000>,
498 <0xfdc80000 0x400>;
499 reg-names = "wrapper_base", "vbif_base";
500 vdd-supply = <&gdsc_venus>;
501
502 qcom,firmware-name = "venus";
503 };
Patrick Daly1e3bc6c2013-01-09 12:34:25 -0800504
505 qcom,pronto@fb21b000 {
506 compatible = "qcom,pil-pronto";
507 reg = <0xfb21b000 0x3000>,
508 <0xfc401700 0x4>,
509 <0xfd485300 0xc>;
510 reg-names = "pmu_base", "clk_base", "halt_base";
511 interrupts = <0 149 1>;
512 vdd_pronto_pll-supply = <&pm8026_l8>;
513
514 qcom,firmware-name = "wcnss";
515 };
Neeti Desai1f7ca2d2012-11-21 13:25:57 -0800516
Patrick Daly4df59842013-01-09 12:31:40 -0800517 qcom,lpass@fe200000 {
518 compatible = "qcom,pil-q6v5-lpass";
519 reg = <0xfe200000 0x00100>,
520 <0xfd485100 0x00010>;
521 reg-names = "qdsp6_base", "halt_base";
522 interrupts = <0 162 1>;
523
524 qcom,firmware-name = "adsp";
525 };
526
Neeti Desai1f7ca2d2012-11-21 13:25:57 -0800527 qcom,msm-mem-hole {
528 compatible = "qcom,msm-mem-hole";
529 qcom,memblock-remove = <0x8100000 0x7e00000>; /* Address and Size of Hole */
530 };
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700531};
David Collins37ddb972012-10-17 15:00:26 -0700532
Patrick Dalye8977aa2012-11-06 15:25:58 -0800533&gdsc_venus {
534 status = "ok";
535};
536
537&gdsc_mdss {
538 status = "ok";
539};
540
541&gdsc_jpeg {
542 status = "ok";
543};
544
545&gdsc_vfe {
546 status = "ok";
547};
548
549&gdsc_oxili_cx {
550 status = "ok";
551};
552
553&gdsc_usb_hsic {
554 status = "ok";
555};
556
David Collins37ddb972012-10-17 15:00:26 -0700557/include/ "msm8226-regulator.dtsi"
Kenneth Heitkebea6ca22013-02-07 17:23:21 -0700558/include/ "msm-pm8226.dtsi"