mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 1 | // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 | // All Rights Reserved. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 3 | // |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 4 | // Redistribution and use in source and binary forms, with or without |
| 5 | // modification, are permitted provided that the following conditions |
| 6 | // are met: |
| 7 | // |
| 8 | // - Redistributions of source code must retain the above copyright notice, |
| 9 | // this list of conditions and the following disclaimer. |
| 10 | // |
| 11 | // - Redistribution in binary form must reproduce the above copyright |
| 12 | // notice, this list of conditions and the following disclaimer in the |
| 13 | // documentation and/or other materials provided with the |
| 14 | // distribution. |
| 15 | // |
| 16 | // - Neither the name of Sun Microsystems or the names of contributors may |
| 17 | // be used to endorse or promote products derived from this software without |
| 18 | // specific prior written permission. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 19 | // |
| 20 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 21 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 22 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 23 | // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 24 | // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 26 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 27 | // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 28 | // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 29 | // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 30 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
| 31 | // OF THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 33 | // The original source code covered by the above license above has been |
| 34 | // modified significantly by Google Inc. |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 35 | // Copyright 2012 the V8 project authors. All rights reserved. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 36 | |
| 37 | #include "v8.h" |
| 38 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 39 | #if defined(V8_TARGET_ARCH_ARM) |
| 40 | |
ager@chromium.org | 3a37e9b | 2009-04-27 09:26:21 +0000 | [diff] [blame] | 41 | #include "arm/assembler-arm-inl.h" |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 42 | #include "serialize.h" |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 43 | |
kasperl@chromium.org | 71affb5 | 2009-05-26 05:44:31 +0000 | [diff] [blame] | 44 | namespace v8 { |
| 45 | namespace internal { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 46 | |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 47 | #ifdef DEBUG |
| 48 | bool CpuFeatures::initialized_ = false; |
| 49 | #endif |
| 50 | unsigned CpuFeatures::supported_ = 0; |
| 51 | unsigned CpuFeatures::found_by_runtime_probing_ = 0; |
| 52 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 53 | |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 54 | ExternalReference ExternalReference::cpu_features() { |
| 55 | ASSERT(CpuFeatures::initialized_); |
| 56 | return ExternalReference(&CpuFeatures::supported_); |
| 57 | } |
| 58 | |
fschneider@chromium.org | fb144a0 | 2011-05-04 12:43:48 +0000 | [diff] [blame] | 59 | // Get the CPU features enabled by the build. For cross compilation the |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 60 | // preprocessor symbols CAN_USE_ARMV7_INSTRUCTIONS and CAN_USE_VFP3_INSTRUCTIONS |
fschneider@chromium.org | fb144a0 | 2011-05-04 12:43:48 +0000 | [diff] [blame] | 61 | // can be defined to enable ARMv7 and VFPv3 instructions when building the |
| 62 | // snapshot. |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 63 | static unsigned CpuFeaturesImpliedByCompiler() { |
| 64 | unsigned answer = 0; |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 65 | #ifdef CAN_USE_ARMV7_INSTRUCTIONS |
| 66 | answer |= 1u << ARMv7; |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 67 | #endif // CAN_USE_ARMV7_INSTRUCTIONS |
| 68 | #ifdef CAN_USE_VFP3_INSTRUCTIONS |
| 69 | answer |= 1u << VFP3 | 1u << VFP2 | 1u << ARMv7; |
| 70 | #endif // CAN_USE_VFP3_INSTRUCTIONS |
| 71 | #ifdef CAN_USE_VFP2_INSTRUCTIONS |
| 72 | answer |= 1u << VFP2; |
| 73 | #endif // CAN_USE_VFP2_INSTRUCTIONS |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 74 | #ifdef CAN_USE_VFP32DREGS |
| 75 | answer |= 1u << VFP32DREGS; |
| 76 | #endif // CAN_USE_VFP32DREGS |
fschneider@chromium.org | fb144a0 | 2011-05-04 12:43:48 +0000 | [diff] [blame] | 77 | |
| 78 | #ifdef __arm__ |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 79 | // If the compiler is allowed to use VFP then we can use VFP too in our code |
svenpanne@chromium.org | 4efbdb1 | 2012-03-12 08:18:42 +0000 | [diff] [blame] | 80 | // generation even when generating snapshots. ARMv7 and hardware floating |
| 81 | // point support implies VFPv3, see ARM DDI 0406B, page A1-6. |
| 82 | #if defined(CAN_USE_ARMV7_INSTRUCTIONS) && defined(__VFP_FP__) \ |
| 83 | && !defined(__SOFTFP__) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 84 | answer |= 1u << VFP3 | 1u << ARMv7 | 1u << VFP2; |
svenpanne@chromium.org | 4efbdb1 | 2012-03-12 08:18:42 +0000 | [diff] [blame] | 85 | #endif // defined(CAN_USE_ARMV7_INSTRUCTIONS) && defined(__VFP_FP__) |
| 86 | // && !defined(__SOFTFP__) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 87 | #endif // _arm__ |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 88 | if (answer & (1u << ARMv7)) { |
| 89 | answer |= 1u << UNALIGNED_ACCESSES; |
| 90 | } |
fschneider@chromium.org | fb144a0 | 2011-05-04 12:43:48 +0000 | [diff] [blame] | 91 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 92 | return answer; |
| 93 | } |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 94 | |
| 95 | |
yangguo@chromium.org | a6bbcc8 | 2012-12-21 12:35:02 +0000 | [diff] [blame] | 96 | const char* DwVfpRegister::AllocationIndexToString(int index) { |
| 97 | if (CpuFeatures::IsSupported(VFP2)) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 98 | ASSERT(index >= 0 && index < NumAllocatableRegisters()); |
| 99 | ASSERT(kScratchDoubleReg.code() - kDoubleRegZero.code() == |
| 100 | kNumReservedRegisters - 1); |
| 101 | if (index >= kDoubleRegZero.code()) |
| 102 | index += kNumReservedRegisters; |
| 103 | |
mstarzinger@chromium.org | e3b8d0f | 2013-02-01 09:06:41 +0000 | [diff] [blame^] | 104 | return VFPRegisters::Name(index, true); |
yangguo@chromium.org | a6bbcc8 | 2012-12-21 12:35:02 +0000 | [diff] [blame] | 105 | } else { |
| 106 | ASSERT(index == 0); |
| 107 | return "sfpd0"; |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 112 | void CpuFeatures::Probe() { |
rossberg@chromium.org | 657d53b | 2012-07-12 11:06:03 +0000 | [diff] [blame] | 113 | unsigned standard_features = static_cast<unsigned>( |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 114 | OS::CpuFeaturesImpliedByPlatform()) | CpuFeaturesImpliedByCompiler(); |
erik.corry@gmail.com | c3b670f | 2011-10-05 21:44:48 +0000 | [diff] [blame] | 115 | ASSERT(supported_ == 0 || supported_ == standard_features); |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 116 | #ifdef DEBUG |
| 117 | initialized_ = true; |
| 118 | #endif |
fschneider@chromium.org | fb144a0 | 2011-05-04 12:43:48 +0000 | [diff] [blame] | 119 | |
| 120 | // Get the features implied by the OS and the compiler settings. This is the |
| 121 | // minimal set of features which is also alowed for generated code in the |
| 122 | // snapshot. |
erik.corry@gmail.com | c3b670f | 2011-10-05 21:44:48 +0000 | [diff] [blame] | 123 | supported_ |= standard_features; |
fschneider@chromium.org | fb144a0 | 2011-05-04 12:43:48 +0000 | [diff] [blame] | 124 | |
| 125 | if (Serializer::enabled()) { |
| 126 | // No probing for features if we might serialize (generate snapshot). |
| 127 | return; |
| 128 | } |
| 129 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 130 | #ifndef __arm__ |
ager@chromium.org | a9aa5fa | 2011-04-13 08:46:07 +0000 | [diff] [blame] | 131 | // For the simulator=arm build, use VFP when FLAG_enable_vfp3 is |
| 132 | // enabled. VFPv3 implies ARMv7, see ARM DDI 0406B, page A1-6. |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 133 | if (FLAG_enable_vfp3) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 134 | supported_ |= 1u << VFP3 | 1u << ARMv7 | 1u << VFP2; |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 135 | } |
| 136 | // For the simulator=arm build, use ARMv7 when FLAG_enable_armv7 is enabled |
| 137 | if (FLAG_enable_armv7) { |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 138 | supported_ |= 1u << ARMv7; |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 139 | } |
verwaest@chromium.org | 33e09c8 | 2012-10-10 17:07:22 +0000 | [diff] [blame] | 140 | |
| 141 | if (FLAG_enable_sudiv) { |
| 142 | supported_ |= 1u << SUDIV; |
| 143 | } |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 144 | |
| 145 | if (FLAG_enable_movw_movt) { |
| 146 | supported_ |= 1u << MOVW_MOVT_IMMEDIATE_LOADS; |
| 147 | } |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 148 | |
| 149 | if (FLAG_enable_32dregs) { |
| 150 | supported_ |= 1u << VFP32DREGS; |
| 151 | } |
| 152 | |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 153 | #else // __arm__ |
fschneider@chromium.org | fb144a0 | 2011-05-04 12:43:48 +0000 | [diff] [blame] | 154 | // Probe for additional features not already known to be available. |
| 155 | if (!IsSupported(VFP3) && OS::ArmCpuHasFeature(VFP3)) { |
ager@chromium.org | a9aa5fa | 2011-04-13 08:46:07 +0000 | [diff] [blame] | 156 | // This implementation also sets the VFP flags if runtime |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 157 | // detection of VFP returns true. VFPv3 implies ARMv7 and VFP2, see ARM DDI |
ager@chromium.org | a9aa5fa | 2011-04-13 08:46:07 +0000 | [diff] [blame] | 158 | // 0406B, page A1-6. |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 159 | found_by_runtime_probing_ |= 1u << VFP3 | 1u << ARMv7 | 1u << VFP2; |
| 160 | } else if (!IsSupported(VFP2) && OS::ArmCpuHasFeature(VFP2)) { |
| 161 | found_by_runtime_probing_ |= 1u << VFP2; |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 162 | } |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 163 | |
fschneider@chromium.org | fb144a0 | 2011-05-04 12:43:48 +0000 | [diff] [blame] | 164 | if (!IsSupported(ARMv7) && OS::ArmCpuHasFeature(ARMv7)) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 165 | found_by_runtime_probing_ |= 1u << ARMv7; |
| 166 | } |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 167 | |
verwaest@chromium.org | 33e09c8 | 2012-10-10 17:07:22 +0000 | [diff] [blame] | 168 | if (!IsSupported(SUDIV) && OS::ArmCpuHasFeature(SUDIV)) { |
| 169 | found_by_runtime_probing_ |= 1u << SUDIV; |
| 170 | } |
| 171 | |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 172 | if (!IsSupported(UNALIGNED_ACCESSES) && OS::ArmCpuHasFeature(ARMv7)) { |
| 173 | found_by_runtime_probing_ |= 1u << UNALIGNED_ACCESSES; |
| 174 | } |
| 175 | |
| 176 | if (OS::GetCpuImplementer() == QUALCOMM_IMPLEMENTER && |
| 177 | OS::ArmCpuHasFeature(ARMv7)) { |
| 178 | found_by_runtime_probing_ |= 1u << MOVW_MOVT_IMMEDIATE_LOADS; |
| 179 | } |
| 180 | |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 181 | if (!IsSupported(VFP32DREGS) && OS::ArmCpuHasFeature(VFP32DREGS)) { |
| 182 | found_by_runtime_probing_ |= 1u << VFP32DREGS; |
| 183 | } |
| 184 | |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 185 | supported_ |= found_by_runtime_probing_; |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 186 | #endif |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 187 | |
| 188 | // Assert that VFP3 implies VFP2 and ARMv7. |
| 189 | ASSERT(!IsSupported(VFP3) || (IsSupported(VFP2) && IsSupported(ARMv7))); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 193 | // ----------------------------------------------------------------------------- |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 194 | // Implementation of RelocInfo |
| 195 | |
| 196 | const int RelocInfo::kApplyMask = 0; |
| 197 | |
| 198 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 199 | bool RelocInfo::IsCodedSpecially() { |
| 200 | // The deserializer needs to know whether a pointer is specially coded. Being |
| 201 | // specially coded on ARM means that it is a movw/movt instruction. We don't |
| 202 | // generate those yet. |
| 203 | return false; |
| 204 | } |
| 205 | |
| 206 | |
iposva@chromium.org | 245aa85 | 2009-02-10 00:49:54 +0000 | [diff] [blame] | 207 | void RelocInfo::PatchCode(byte* instructions, int instruction_count) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 208 | // Patch the code at the current address with the supplied instructions. |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 209 | Instr* pc = reinterpret_cast<Instr*>(pc_); |
| 210 | Instr* instr = reinterpret_cast<Instr*>(instructions); |
| 211 | for (int i = 0; i < instruction_count; i++) { |
| 212 | *(pc + i) = *(instr + i); |
| 213 | } |
| 214 | |
| 215 | // Indicate that code has changed. |
| 216 | CPU::FlushICache(pc_, instruction_count * Assembler::kInstrSize); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | |
| 220 | // Patch the code at the current PC with a call to the target address. |
iposva@chromium.org | 245aa85 | 2009-02-10 00:49:54 +0000 | [diff] [blame] | 221 | // Additional guard instructions can be added if required. |
| 222 | void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 223 | // Patch the code at the current address with a call to the target. |
| 224 | UNIMPLEMENTED(); |
| 225 | } |
| 226 | |
| 227 | |
| 228 | // ----------------------------------------------------------------------------- |
| 229 | // Implementation of Operand and MemOperand |
| 230 | // See assembler-arm-inl.h for inlined constructors |
| 231 | |
| 232 | Operand::Operand(Handle<Object> handle) { |
| 233 | rm_ = no_reg; |
| 234 | // Verify all Objects referred by code are NOT in new space. |
| 235 | Object* obj = *handle; |
sgjesse@chromium.org | ea88ce9 | 2011-03-23 11:19:56 +0000 | [diff] [blame] | 236 | ASSERT(!HEAP->InNewSpace(obj)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 237 | if (obj->IsHeapObject()) { |
| 238 | imm32_ = reinterpret_cast<intptr_t>(handle.location()); |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 239 | rmode_ = RelocInfo::EMBEDDED_OBJECT; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 240 | } else { |
| 241 | // no relocation needed |
| 242 | imm32_ = reinterpret_cast<intptr_t>(obj); |
jkummerow@chromium.org | 59297c7 | 2013-01-09 16:32:23 +0000 | [diff] [blame] | 243 | rmode_ = RelocInfo::NONE32; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 244 | } |
| 245 | } |
| 246 | |
| 247 | |
| 248 | Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { |
| 249 | ASSERT(is_uint5(shift_imm)); |
| 250 | ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it |
| 251 | rm_ = rm; |
| 252 | rs_ = no_reg; |
| 253 | shift_op_ = shift_op; |
| 254 | shift_imm_ = shift_imm & 31; |
| 255 | if (shift_op == RRX) { |
| 256 | // encoded as ROR with shift_imm == 0 |
| 257 | ASSERT(shift_imm == 0); |
| 258 | shift_op_ = ROR; |
| 259 | shift_imm_ = 0; |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | |
| 264 | Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { |
| 265 | ASSERT(shift_op != RRX); |
| 266 | rm_ = rm; |
| 267 | rs_ = no_reg; |
| 268 | shift_op_ = shift_op; |
| 269 | rs_ = rs; |
| 270 | } |
| 271 | |
| 272 | |
| 273 | MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) { |
| 274 | rn_ = rn; |
| 275 | rm_ = no_reg; |
| 276 | offset_ = offset; |
| 277 | am_ = am; |
| 278 | } |
| 279 | |
| 280 | MemOperand::MemOperand(Register rn, Register rm, AddrMode am) { |
| 281 | rn_ = rn; |
| 282 | rm_ = rm; |
| 283 | shift_op_ = LSL; |
| 284 | shift_imm_ = 0; |
| 285 | am_ = am; |
| 286 | } |
| 287 | |
| 288 | |
| 289 | MemOperand::MemOperand(Register rn, Register rm, |
| 290 | ShiftOp shift_op, int shift_imm, AddrMode am) { |
| 291 | ASSERT(is_uint5(shift_imm)); |
| 292 | rn_ = rn; |
| 293 | rm_ = rm; |
| 294 | shift_op_ = shift_op; |
| 295 | shift_imm_ = shift_imm & 31; |
| 296 | am_ = am; |
| 297 | } |
| 298 | |
| 299 | |
| 300 | // ----------------------------------------------------------------------------- |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 301 | // Specific instructions, constants, and masks. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 302 | |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 303 | // add(sp, sp, 4) instruction (aka Pop()) |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 304 | const Instr kPopInstruction = |
jkummerow@chromium.org | 1456e70 | 2012-03-30 08:38:13 +0000 | [diff] [blame] | 305 | al | PostIndex | 4 | LeaveCC | I | kRegister_sp_Code * B16 | |
| 306 | kRegister_sp_Code * B12; |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 307 | // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) |
| 308 | // register r is not encoded. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 309 | const Instr kPushRegPattern = |
jkummerow@chromium.org | 1456e70 | 2012-03-30 08:38:13 +0000 | [diff] [blame] | 310 | al | B26 | 4 | NegPreIndex | kRegister_sp_Code * B16; |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 311 | // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) |
| 312 | // register r is not encoded. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 313 | const Instr kPopRegPattern = |
jkummerow@chromium.org | 1456e70 | 2012-03-30 08:38:13 +0000 | [diff] [blame] | 314 | al | B26 | L | 4 | PostIndex | kRegister_sp_Code * B16; |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 315 | // mov lr, pc |
jkummerow@chromium.org | 1456e70 | 2012-03-30 08:38:13 +0000 | [diff] [blame] | 316 | const Instr kMovLrPc = al | MOV | kRegister_pc_Code | kRegister_lr_Code * B12; |
whesse@chromium.org | cec079d | 2010-03-22 14:44:04 +0000 | [diff] [blame] | 317 | // ldr rd, [pc, #offset] |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 318 | const Instr kLdrPCMask = 15 * B24 | 7 * B20 | 15 * B16; |
| 319 | const Instr kLdrPCPattern = 5 * B24 | L | kRegister_pc_Code * B16; |
| 320 | // vldr dd, [pc, #offset] |
| 321 | const Instr kVldrDPCMask = 15 * B24 | 3 * B20 | 15 * B16 | 15 * B8; |
| 322 | const Instr kVldrDPCPattern = 13 * B24 | L | kRegister_pc_Code * B16 | 11 * B8; |
whesse@chromium.org | cec079d | 2010-03-22 14:44:04 +0000 | [diff] [blame] | 323 | // blxcc rm |
| 324 | const Instr kBlxRegMask = |
| 325 | 15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4; |
| 326 | const Instr kBlxRegPattern = |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 327 | B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX; |
danno@chromium.org | 88aa058 | 2012-03-23 15:11:57 +0000 | [diff] [blame] | 328 | const Instr kBlxIp = al | kBlxRegPattern | ip.code(); |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 329 | const Instr kMovMvnMask = 0x6d * B21 | 0xf * B16; |
| 330 | const Instr kMovMvnPattern = 0xd * B21; |
| 331 | const Instr kMovMvnFlip = B22; |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 332 | const Instr kMovLeaveCCMask = 0xdff * B16; |
| 333 | const Instr kMovLeaveCCPattern = 0x1a0 * B16; |
| 334 | const Instr kMovwMask = 0xff * B20; |
| 335 | const Instr kMovwPattern = 0x30 * B20; |
| 336 | const Instr kMovwLeaveCCFlip = 0x5 * B21; |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 337 | const Instr kCmpCmnMask = 0xdd * B20 | 0xf * B12; |
| 338 | const Instr kCmpCmnPattern = 0x15 * B20; |
| 339 | const Instr kCmpCmnFlip = B21; |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 340 | const Instr kAddSubFlip = 0x6 * B21; |
| 341 | const Instr kAndBicFlip = 0xe * B21; |
| 342 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 343 | // A mask for the Rd register for push, pop, ldr, str instructions. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 344 | const Instr kLdrRegFpOffsetPattern = |
jkummerow@chromium.org | 1456e70 | 2012-03-30 08:38:13 +0000 | [diff] [blame] | 345 | al | B26 | L | Offset | kRegister_fp_Code * B16; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 346 | const Instr kStrRegFpOffsetPattern = |
jkummerow@chromium.org | 1456e70 | 2012-03-30 08:38:13 +0000 | [diff] [blame] | 347 | al | B26 | Offset | kRegister_fp_Code * B16; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 348 | const Instr kLdrRegFpNegOffsetPattern = |
jkummerow@chromium.org | 1456e70 | 2012-03-30 08:38:13 +0000 | [diff] [blame] | 349 | al | B26 | L | NegOffset | kRegister_fp_Code * B16; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 350 | const Instr kStrRegFpNegOffsetPattern = |
jkummerow@chromium.org | 1456e70 | 2012-03-30 08:38:13 +0000 | [diff] [blame] | 351 | al | B26 | NegOffset | kRegister_fp_Code * B16; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 352 | const Instr kLdrStrInstrTypeMask = 0xffff0000; |
| 353 | const Instr kLdrStrInstrArgumentMask = 0x0000ffff; |
| 354 | const Instr kLdrStrOffsetMask = 0x00000fff; |
| 355 | |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 356 | |
ulan@chromium.org | 8e8d882 | 2012-11-23 14:36:46 +0000 | [diff] [blame] | 357 | Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size) |
| 358 | : AssemblerBase(isolate, buffer, buffer_size), |
mstarzinger@chromium.org | 471f2f1 | 2012-08-10 14:46:33 +0000 | [diff] [blame] | 359 | recorded_ast_id_(TypeFeedbackId::None()), |
mvstanton@chromium.org | e4ac3ef | 2012-11-12 14:53:34 +0000 | [diff] [blame] | 360 | positions_recorder_(this) { |
ulan@chromium.org | 8e8d882 | 2012-11-23 14:36:46 +0000 | [diff] [blame] | 361 | reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_); |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 362 | num_pending_reloc_info_ = 0; |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 363 | num_pending_64_bit_reloc_info_ = 0; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 364 | next_buffer_check_ = 0; |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 365 | const_pool_blocked_nesting_ = 0; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 366 | no_const_pool_before_ = 0; |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 367 | first_const_pool_use_ = -1; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 368 | last_bound_pos_ = 0; |
rossberg@chromium.org | 717967f | 2011-07-20 13:44:42 +0000 | [diff] [blame] | 369 | ClearRecordedAstId(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 370 | } |
| 371 | |
| 372 | |
| 373 | Assembler::~Assembler() { |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 374 | ASSERT(const_pool_blocked_nesting_ == 0); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | |
| 378 | void Assembler::GetCode(CodeDesc* desc) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 379 | // Emit constant pool if necessary. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 380 | CheckConstPool(true, false); |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 381 | ASSERT(num_pending_reloc_info_ == 0); |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 382 | ASSERT(num_pending_64_bit_reloc_info_ == 0); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 383 | |
erik.corry@gmail.com | f2038fb | 2012-01-16 11:42:08 +0000 | [diff] [blame] | 384 | // Set up code descriptor. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 385 | desc->buffer = buffer_; |
| 386 | desc->buffer_size = buffer_size_; |
| 387 | desc->instr_size = pc_offset(); |
| 388 | desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); |
| 389 | } |
| 390 | |
| 391 | |
| 392 | void Assembler::Align(int m) { |
| 393 | ASSERT(m >= 4 && IsPowerOf2(m)); |
| 394 | while ((pc_offset() & (m - 1)) != 0) { |
| 395 | nop(); |
| 396 | } |
| 397 | } |
| 398 | |
| 399 | |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 400 | void Assembler::CodeTargetAlign() { |
| 401 | // Preferred alignment of jump targets on some ARM chips. |
| 402 | Align(8); |
| 403 | } |
| 404 | |
| 405 | |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 406 | Condition Assembler::GetCondition(Instr instr) { |
| 407 | return Instruction::ConditionField(instr); |
| 408 | } |
| 409 | |
| 410 | |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 411 | bool Assembler::IsBranch(Instr instr) { |
| 412 | return (instr & (B27 | B25)) == (B27 | B25); |
| 413 | } |
| 414 | |
| 415 | |
| 416 | int Assembler::GetBranchOffset(Instr instr) { |
| 417 | ASSERT(IsBranch(instr)); |
| 418 | // Take the jump offset in the lower 24 bits, sign extend it and multiply it |
| 419 | // with 4 to get the offset in bytes. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 420 | return ((instr & kImm24Mask) << 8) >> 6; |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 421 | } |
| 422 | |
| 423 | |
| 424 | bool Assembler::IsLdrRegisterImmediate(Instr instr) { |
| 425 | return (instr & (B27 | B26 | B25 | B22 | B20)) == (B26 | B20); |
| 426 | } |
| 427 | |
| 428 | |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 429 | bool Assembler::IsVldrDRegisterImmediate(Instr instr) { |
| 430 | return (instr & (15 * B24 | 3 * B20 | 15 * B8)) == (13 * B24 | B20 | 11 * B8); |
| 431 | } |
| 432 | |
| 433 | |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 434 | int Assembler::GetLdrRegisterImmediateOffset(Instr instr) { |
| 435 | ASSERT(IsLdrRegisterImmediate(instr)); |
| 436 | bool positive = (instr & B23) == B23; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 437 | int offset = instr & kOff12Mask; // Zero extended offset. |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 438 | return positive ? offset : -offset; |
| 439 | } |
| 440 | |
| 441 | |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 442 | int Assembler::GetVldrDRegisterImmediateOffset(Instr instr) { |
| 443 | ASSERT(IsVldrDRegisterImmediate(instr)); |
| 444 | bool positive = (instr & B23) == B23; |
| 445 | int offset = instr & kOff8Mask; // Zero extended offset. |
| 446 | offset <<= 2; |
| 447 | return positive ? offset : -offset; |
| 448 | } |
| 449 | |
| 450 | |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 451 | Instr Assembler::SetLdrRegisterImmediateOffset(Instr instr, int offset) { |
| 452 | ASSERT(IsLdrRegisterImmediate(instr)); |
| 453 | bool positive = offset >= 0; |
| 454 | if (!positive) offset = -offset; |
| 455 | ASSERT(is_uint12(offset)); |
| 456 | // Set bit indicating whether the offset should be added. |
| 457 | instr = (instr & ~B23) | (positive ? B23 : 0); |
| 458 | // Set the actual offset. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 459 | return (instr & ~kOff12Mask) | offset; |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 460 | } |
| 461 | |
| 462 | |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 463 | Instr Assembler::SetVldrDRegisterImmediateOffset(Instr instr, int offset) { |
| 464 | ASSERT(IsVldrDRegisterImmediate(instr)); |
| 465 | ASSERT((offset & ~3) == offset); // Must be 64-bit aligned. |
| 466 | bool positive = offset >= 0; |
| 467 | if (!positive) offset = -offset; |
| 468 | ASSERT(is_uint10(offset)); |
| 469 | // Set bit indicating whether the offset should be added. |
| 470 | instr = (instr & ~B23) | (positive ? B23 : 0); |
| 471 | // Set the actual offset. Its bottom 2 bits are zero. |
| 472 | return (instr & ~kOff8Mask) | (offset >> 2); |
| 473 | } |
| 474 | |
| 475 | |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 476 | bool Assembler::IsStrRegisterImmediate(Instr instr) { |
| 477 | return (instr & (B27 | B26 | B25 | B22 | B20)) == B26; |
| 478 | } |
| 479 | |
| 480 | |
| 481 | Instr Assembler::SetStrRegisterImmediateOffset(Instr instr, int offset) { |
| 482 | ASSERT(IsStrRegisterImmediate(instr)); |
| 483 | bool positive = offset >= 0; |
| 484 | if (!positive) offset = -offset; |
| 485 | ASSERT(is_uint12(offset)); |
| 486 | // Set bit indicating whether the offset should be added. |
| 487 | instr = (instr & ~B23) | (positive ? B23 : 0); |
| 488 | // Set the actual offset. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 489 | return (instr & ~kOff12Mask) | offset; |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 490 | } |
| 491 | |
| 492 | |
| 493 | bool Assembler::IsAddRegisterImmediate(Instr instr) { |
| 494 | return (instr & (B27 | B26 | B25 | B24 | B23 | B22 | B21)) == (B25 | B23); |
| 495 | } |
| 496 | |
| 497 | |
| 498 | Instr Assembler::SetAddRegisterImmediateOffset(Instr instr, int offset) { |
| 499 | ASSERT(IsAddRegisterImmediate(instr)); |
| 500 | ASSERT(offset >= 0); |
| 501 | ASSERT(is_uint12(offset)); |
| 502 | // Set the offset. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 503 | return (instr & ~kOff12Mask) | offset; |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 507 | Register Assembler::GetRd(Instr instr) { |
| 508 | Register reg; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 509 | reg.code_ = Instruction::RdValue(instr); |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 510 | return reg; |
| 511 | } |
| 512 | |
| 513 | |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 514 | Register Assembler::GetRn(Instr instr) { |
| 515 | Register reg; |
| 516 | reg.code_ = Instruction::RnValue(instr); |
| 517 | return reg; |
| 518 | } |
| 519 | |
| 520 | |
| 521 | Register Assembler::GetRm(Instr instr) { |
| 522 | Register reg; |
| 523 | reg.code_ = Instruction::RmValue(instr); |
| 524 | return reg; |
| 525 | } |
| 526 | |
| 527 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 528 | bool Assembler::IsPush(Instr instr) { |
| 529 | return ((instr & ~kRdMask) == kPushRegPattern); |
| 530 | } |
| 531 | |
| 532 | |
| 533 | bool Assembler::IsPop(Instr instr) { |
| 534 | return ((instr & ~kRdMask) == kPopRegPattern); |
| 535 | } |
| 536 | |
| 537 | |
| 538 | bool Assembler::IsStrRegFpOffset(Instr instr) { |
| 539 | return ((instr & kLdrStrInstrTypeMask) == kStrRegFpOffsetPattern); |
| 540 | } |
| 541 | |
| 542 | |
| 543 | bool Assembler::IsLdrRegFpOffset(Instr instr) { |
| 544 | return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpOffsetPattern); |
| 545 | } |
| 546 | |
| 547 | |
| 548 | bool Assembler::IsStrRegFpNegOffset(Instr instr) { |
| 549 | return ((instr & kLdrStrInstrTypeMask) == kStrRegFpNegOffsetPattern); |
| 550 | } |
| 551 | |
| 552 | |
| 553 | bool Assembler::IsLdrRegFpNegOffset(Instr instr) { |
| 554 | return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpNegOffsetPattern); |
| 555 | } |
| 556 | |
| 557 | |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 558 | bool Assembler::IsLdrPcImmediateOffset(Instr instr) { |
| 559 | // Check the instruction is indeed a |
| 560 | // ldr<cond> <Rd>, [pc +/- offset_12]. |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 561 | return (instr & kLdrPCMask) == kLdrPCPattern; |
| 562 | } |
| 563 | |
| 564 | |
| 565 | bool Assembler::IsVldrDPcImmediateOffset(Instr instr) { |
| 566 | // Check the instruction is indeed a |
| 567 | // vldr<cond> <Dd>, [pc +/- offset_10]. |
| 568 | return (instr & kVldrDPCMask) == kVldrDPCPattern; |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 569 | } |
| 570 | |
| 571 | |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 572 | bool Assembler::IsTstImmediate(Instr instr) { |
| 573 | return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) == |
| 574 | (I | TST | S); |
| 575 | } |
| 576 | |
| 577 | |
| 578 | bool Assembler::IsCmpRegister(Instr instr) { |
| 579 | return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask | B4)) == |
| 580 | (CMP | S); |
| 581 | } |
| 582 | |
| 583 | |
| 584 | bool Assembler::IsCmpImmediate(Instr instr) { |
| 585 | return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) == |
| 586 | (I | CMP | S); |
| 587 | } |
| 588 | |
| 589 | |
| 590 | Register Assembler::GetCmpImmediateRegister(Instr instr) { |
| 591 | ASSERT(IsCmpImmediate(instr)); |
| 592 | return GetRn(instr); |
| 593 | } |
| 594 | |
| 595 | |
| 596 | int Assembler::GetCmpImmediateRawImmediate(Instr instr) { |
| 597 | ASSERT(IsCmpImmediate(instr)); |
| 598 | return instr & kOff12Mask; |
| 599 | } |
| 600 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 601 | // Labels refer to positions in the (to be) generated code. |
| 602 | // There are bound, linked, and unused labels. |
| 603 | // |
| 604 | // Bound labels refer to known positions in the already |
| 605 | // generated code. pos() is the position the label refers to. |
| 606 | // |
| 607 | // Linked labels refer to unknown positions in the code |
| 608 | // to be generated; pos() is the position of the last |
| 609 | // instruction using the label. |
| 610 | |
| 611 | |
| 612 | // The link chain is terminated by a negative code position (must be aligned) |
| 613 | const int kEndOfChain = -4; |
| 614 | |
| 615 | |
| 616 | int Assembler::target_at(int pos) { |
| 617 | Instr instr = instr_at(pos); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 618 | if ((instr & ~kImm24Mask) == 0) { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 619 | // Emitted label constant, not part of a branch. |
| 620 | return instr - (Code::kHeaderSize - kHeapObjectTag); |
| 621 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 622 | ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24 |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 623 | int imm26 = ((instr & kImm24Mask) << 8) >> 6; |
| 624 | if ((Instruction::ConditionField(instr) == kSpecialCondition) && |
| 625 | ((instr & B24) != 0)) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 626 | // blx uses bit 24 to encode bit 2 of imm26 |
| 627 | imm26 += 2; |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 628 | } |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 629 | return pos + kPcLoadDelta + imm26; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 630 | } |
| 631 | |
| 632 | |
| 633 | void Assembler::target_at_put(int pos, int target_pos) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 634 | Instr instr = instr_at(pos); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 635 | if ((instr & ~kImm24Mask) == 0) { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 636 | ASSERT(target_pos == kEndOfChain || target_pos >= 0); |
| 637 | // Emitted label constant, not part of a branch. |
| 638 | // Make label relative to Code* of generated Code object. |
| 639 | instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
| 640 | return; |
| 641 | } |
| 642 | int imm26 = target_pos - (pos + kPcLoadDelta); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 643 | ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24 |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 644 | if (Instruction::ConditionField(instr) == kSpecialCondition) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 645 | // blx uses bit 24 to encode bit 2 of imm26 |
| 646 | ASSERT((imm26 & 1) == 0); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 647 | instr = (instr & ~(B24 | kImm24Mask)) | ((imm26 & 2) >> 1)*B24; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 648 | } else { |
| 649 | ASSERT((imm26 & 3) == 0); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 650 | instr &= ~kImm24Mask; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 651 | } |
| 652 | int imm24 = imm26 >> 2; |
| 653 | ASSERT(is_int24(imm24)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 654 | instr_at_put(pos, instr | (imm24 & kImm24Mask)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 655 | } |
| 656 | |
| 657 | |
| 658 | void Assembler::print(Label* L) { |
| 659 | if (L->is_unused()) { |
| 660 | PrintF("unused label\n"); |
| 661 | } else if (L->is_bound()) { |
| 662 | PrintF("bound label to %d\n", L->pos()); |
| 663 | } else if (L->is_linked()) { |
| 664 | Label l = *L; |
| 665 | PrintF("unbound label"); |
| 666 | while (l.is_linked()) { |
| 667 | PrintF("@ %d ", l.pos()); |
| 668 | Instr instr = instr_at(l.pos()); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 669 | if ((instr & ~kImm24Mask) == 0) { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 670 | PrintF("value\n"); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 671 | } else { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 672 | ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 673 | Condition cond = Instruction::ConditionField(instr); |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 674 | const char* b; |
| 675 | const char* c; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 676 | if (cond == kSpecialCondition) { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 677 | b = "blx"; |
| 678 | c = ""; |
| 679 | } else { |
| 680 | if ((instr & B24) != 0) |
| 681 | b = "bl"; |
| 682 | else |
| 683 | b = "b"; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 684 | |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 685 | switch (cond) { |
| 686 | case eq: c = "eq"; break; |
| 687 | case ne: c = "ne"; break; |
| 688 | case hs: c = "hs"; break; |
| 689 | case lo: c = "lo"; break; |
| 690 | case mi: c = "mi"; break; |
| 691 | case pl: c = "pl"; break; |
| 692 | case vs: c = "vs"; break; |
| 693 | case vc: c = "vc"; break; |
| 694 | case hi: c = "hi"; break; |
| 695 | case ls: c = "ls"; break; |
| 696 | case ge: c = "ge"; break; |
| 697 | case lt: c = "lt"; break; |
| 698 | case gt: c = "gt"; break; |
| 699 | case le: c = "le"; break; |
| 700 | case al: c = ""; break; |
| 701 | default: |
| 702 | c = ""; |
| 703 | UNREACHABLE(); |
| 704 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 705 | } |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 706 | PrintF("%s%s\n", b, c); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 707 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 708 | next(&l); |
| 709 | } |
| 710 | } else { |
| 711 | PrintF("label in inconsistent state (pos = %d)\n", L->pos_); |
| 712 | } |
| 713 | } |
| 714 | |
| 715 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 716 | void Assembler::bind_to(Label* L, int pos) { |
| 717 | ASSERT(0 <= pos && pos <= pc_offset()); // must have a valid binding position |
| 718 | while (L->is_linked()) { |
| 719 | int fixup_pos = L->pos(); |
| 720 | next(L); // call next before overwriting link with target at fixup_pos |
| 721 | target_at_put(fixup_pos, pos); |
| 722 | } |
| 723 | L->bind_to(pos); |
| 724 | |
kasperl@chromium.org | 41044eb | 2008-10-06 08:24:46 +0000 | [diff] [blame] | 725 | // Keep track of the last bound label so we don't eliminate any instructions |
| 726 | // before a bound label. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 727 | if (pos > last_bound_pos_) |
| 728 | last_bound_pos_ = pos; |
| 729 | } |
| 730 | |
| 731 | |
| 732 | void Assembler::link_to(Label* L, Label* appendix) { |
| 733 | if (appendix->is_linked()) { |
| 734 | if (L->is_linked()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 735 | // Append appendix to L's list. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 736 | int fixup_pos; |
| 737 | int link = L->pos(); |
| 738 | do { |
| 739 | fixup_pos = link; |
| 740 | link = target_at(fixup_pos); |
| 741 | } while (link > 0); |
| 742 | ASSERT(link == kEndOfChain); |
| 743 | target_at_put(fixup_pos, appendix->pos()); |
| 744 | } else { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 745 | // L is empty, simply use appendix. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 746 | *L = *appendix; |
| 747 | } |
| 748 | } |
| 749 | appendix->Unuse(); // appendix should not be used anymore |
| 750 | } |
| 751 | |
| 752 | |
| 753 | void Assembler::bind(Label* L) { |
| 754 | ASSERT(!L->is_bound()); // label can only be bound once |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 755 | bind_to(L, pc_offset()); |
| 756 | } |
| 757 | |
| 758 | |
| 759 | void Assembler::next(Label* L) { |
| 760 | ASSERT(L->is_linked()); |
| 761 | int link = target_at(L->pos()); |
yangguo@chromium.org | 80c42ed | 2011-08-31 09:03:56 +0000 | [diff] [blame] | 762 | if (link == kEndOfChain) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 763 | L->Unuse(); |
yangguo@chromium.org | 80c42ed | 2011-08-31 09:03:56 +0000 | [diff] [blame] | 764 | } else { |
| 765 | ASSERT(link >= 0); |
| 766 | L->link_to(link); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 767 | } |
| 768 | } |
| 769 | |
| 770 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 771 | // Low-level code emission routines depending on the addressing mode. |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 772 | // If this returns true then you have to use the rotate_imm and immed_8 |
| 773 | // that it returns, because it may have already changed the instruction |
| 774 | // to match them! |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 775 | static bool fits_shifter(uint32_t imm32, |
| 776 | uint32_t* rotate_imm, |
| 777 | uint32_t* immed_8, |
| 778 | Instr* instr) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 779 | // imm32 must be unsigned. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 780 | for (int rot = 0; rot < 16; rot++) { |
| 781 | uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot)); |
| 782 | if ((imm8 <= 0xff)) { |
| 783 | *rotate_imm = rot; |
| 784 | *immed_8 = imm8; |
| 785 | return true; |
| 786 | } |
| 787 | } |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 788 | // If the opcode is one with a complementary version and the complementary |
| 789 | // immediate fits, change the opcode. |
| 790 | if (instr != NULL) { |
| 791 | if ((*instr & kMovMvnMask) == kMovMvnPattern) { |
| 792 | if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) { |
| 793 | *instr ^= kMovMvnFlip; |
| 794 | return true; |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 795 | } else if ((*instr & kMovLeaveCCMask) == kMovLeaveCCPattern) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 796 | if (CpuFeatures::IsSupported(ARMv7)) { |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 797 | if (imm32 < 0x10000) { |
| 798 | *instr ^= kMovwLeaveCCFlip; |
| 799 | *instr |= EncodeMovwImmediate(imm32); |
| 800 | *rotate_imm = *immed_8 = 0; // Not used for movw. |
| 801 | return true; |
| 802 | } |
| 803 | } |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 804 | } |
| 805 | } else if ((*instr & kCmpCmnMask) == kCmpCmnPattern) { |
rossberg@chromium.org | 657d53b | 2012-07-12 11:06:03 +0000 | [diff] [blame] | 806 | if (fits_shifter(-static_cast<int>(imm32), rotate_imm, immed_8, NULL)) { |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 807 | *instr ^= kCmpCmnFlip; |
| 808 | return true; |
| 809 | } |
| 810 | } else { |
| 811 | Instr alu_insn = (*instr & kALUMask); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 812 | if (alu_insn == ADD || |
| 813 | alu_insn == SUB) { |
rossberg@chromium.org | 657d53b | 2012-07-12 11:06:03 +0000 | [diff] [blame] | 814 | if (fits_shifter(-static_cast<int>(imm32), rotate_imm, immed_8, NULL)) { |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 815 | *instr ^= kAddSubFlip; |
| 816 | return true; |
| 817 | } |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 818 | } else if (alu_insn == AND || |
| 819 | alu_insn == BIC) { |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 820 | if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) { |
| 821 | *instr ^= kAndBicFlip; |
| 822 | return true; |
| 823 | } |
| 824 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 825 | } |
| 826 | } |
| 827 | return false; |
| 828 | } |
| 829 | |
| 830 | |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 831 | // We have to use the temporary register for things that can be relocated even |
| 832 | // if they can be encoded in the ARM's 12 bits of immediate-offset instruction |
| 833 | // space. There is no guarantee that the relocated location can be similarly |
| 834 | // encoded. |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 835 | bool Operand::must_output_reloc_info(const Assembler* assembler) const { |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 836 | if (rmode_ == RelocInfo::EXTERNAL_REFERENCE) { |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 837 | #ifdef DEBUG |
| 838 | if (!Serializer::enabled()) { |
| 839 | Serializer::TooLateToEnableNow(); |
| 840 | } |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 841 | #endif // def DEBUG |
mstarzinger@chromium.org | 471f2f1 | 2012-08-10 14:46:33 +0000 | [diff] [blame] | 842 | if (assembler != NULL && assembler->predictable_code_size()) return true; |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 843 | return Serializer::enabled(); |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 844 | } else if (RelocInfo::IsNone(rmode_)) { |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 845 | return false; |
| 846 | } |
| 847 | return true; |
| 848 | } |
| 849 | |
| 850 | |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 851 | static bool use_movw_movt(const Operand& x, const Assembler* assembler) { |
| 852 | if (Assembler::use_immediate_embedded_pointer_loads(assembler)) { |
| 853 | return true; |
| 854 | } |
| 855 | if (x.must_output_reloc_info(assembler)) { |
| 856 | return false; |
| 857 | } |
| 858 | return CpuFeatures::IsSupported(ARMv7); |
| 859 | } |
| 860 | |
| 861 | |
mstarzinger@chromium.org | 471f2f1 | 2012-08-10 14:46:33 +0000 | [diff] [blame] | 862 | bool Operand::is_single_instruction(const Assembler* assembler, |
| 863 | Instr instr) const { |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 864 | if (rm_.is_valid()) return true; |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 865 | uint32_t dummy1, dummy2; |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 866 | if (must_output_reloc_info(assembler) || |
whesse@chromium.org | b08986c | 2011-03-14 16:13:42 +0000 | [diff] [blame] | 867 | !fits_shifter(imm32_, &dummy1, &dummy2, &instr)) { |
| 868 | // The immediate operand cannot be encoded as a shifter operand, or use of |
| 869 | // constant pool is required. For a mov instruction not setting the |
| 870 | // condition code additional instruction conventions can be used. |
| 871 | if ((instr & ~kCondMask) == 13*B21) { // mov, S not set |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 872 | return !use_movw_movt(*this, assembler); |
whesse@chromium.org | b08986c | 2011-03-14 16:13:42 +0000 | [diff] [blame] | 873 | } else { |
| 874 | // If this is not a mov or mvn instruction there will always an additional |
| 875 | // instructions - either mov or ldr. The mov might actually be two |
| 876 | // instructions mov or movw followed by movt so including the actual |
| 877 | // instruction two or three instructions will be generated. |
| 878 | return false; |
| 879 | } |
| 880 | } else { |
| 881 | // No use of constant pool and the immediate operand can be encoded as a |
| 882 | // shifter operand. |
| 883 | return true; |
| 884 | } |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 885 | } |
| 886 | |
| 887 | |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 888 | void Assembler::move_32_bit_immediate(Condition cond, |
| 889 | Register rd, |
| 890 | SBit s, |
| 891 | const Operand& x) { |
| 892 | if (rd.code() != pc.code() && s == LeaveCC) { |
| 893 | if (use_movw_movt(x, this)) { |
| 894 | if (x.must_output_reloc_info(this)) { |
| 895 | RecordRelocInfo(x.rmode_, x.imm32_, DONT_USE_CONSTANT_POOL); |
| 896 | // Make sure the movw/movt doesn't get separated. |
| 897 | BlockConstPoolFor(2); |
| 898 | } |
| 899 | emit(cond | 0x30*B20 | rd.code()*B12 | |
| 900 | EncodeMovwImmediate(x.imm32_ & 0xffff)); |
| 901 | movt(rd, static_cast<uint32_t>(x.imm32_) >> 16, cond); |
| 902 | return; |
| 903 | } |
| 904 | } |
| 905 | |
| 906 | RecordRelocInfo(x.rmode_, x.imm32_, USE_CONSTANT_POOL); |
| 907 | ldr(rd, MemOperand(pc, 0), cond); |
| 908 | } |
| 909 | |
| 910 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 911 | void Assembler::addrmod1(Instr instr, |
| 912 | Register rn, |
| 913 | Register rd, |
| 914 | const Operand& x) { |
| 915 | CheckBuffer(); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 916 | ASSERT((instr & ~(kCondMask | kOpCodeMask | S)) == 0); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 917 | if (!x.rm_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 918 | // Immediate. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 919 | uint32_t rotate_imm; |
| 920 | uint32_t immed_8; |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 921 | if (x.must_output_reloc_info(this) || |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 922 | !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) { |
| 923 | // The immediate operand cannot be encoded as a shifter operand, so load |
| 924 | // it first to register ip and change the original instruction to use ip. |
| 925 | // However, if the original instruction is a 'mov rd, x' (not setting the |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 926 | // condition code), then replace it with a 'ldr rd, [pc]'. |
ager@chromium.org | a74f0da | 2008-12-03 16:05:52 +0000 | [diff] [blame] | 927 | CHECK(!rn.is(ip)); // rn should never be ip, or will be trashed |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 928 | Condition cond = Instruction::ConditionField(instr); |
| 929 | if ((instr & ~kCondMask) == 13*B21) { // mov, S not set |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 930 | move_32_bit_immediate(cond, rd, LeaveCC, x); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 931 | } else { |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 932 | if ((instr & kMovMvnMask) == kMovMvnPattern) { |
| 933 | // Moves need to use a constant pool entry. |
| 934 | RecordRelocInfo(x.rmode_, x.imm32_, USE_CONSTANT_POOL); |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 935 | ldr(ip, MemOperand(pc, 0), cond); |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 936 | } else if (x.must_output_reloc_info(this)) { |
| 937 | // Otherwise, use most efficient form of fetching from constant pool. |
| 938 | move_32_bit_immediate(cond, ip, LeaveCC, x); |
| 939 | } else { |
| 940 | // If this is not a mov or mvn instruction we may still be able to |
| 941 | // avoid a constant pool entry by using mvn or movw. |
| 942 | mov(ip, x, LeaveCC, cond); |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 943 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 944 | addrmod1(instr, rn, rd, Operand(ip)); |
| 945 | } |
| 946 | return; |
| 947 | } |
| 948 | instr |= I | rotate_imm*B8 | immed_8; |
| 949 | } else if (!x.rs_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 950 | // Immediate shift. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 951 | instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code(); |
| 952 | } else { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 953 | // Register shift. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 954 | ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc)); |
| 955 | instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code(); |
| 956 | } |
| 957 | emit(instr | rn.code()*B16 | rd.code()*B12); |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 958 | if (rn.is(pc) || x.rm_.is(pc)) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 959 | // Block constant pool emission for one instruction after reading pc. |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 960 | BlockConstPoolFor(1); |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 961 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 962 | } |
| 963 | |
| 964 | |
| 965 | void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 966 | ASSERT((instr & ~(kCondMask | B | L)) == B26); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 967 | int am = x.am_; |
| 968 | if (!x.rm_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 969 | // Immediate offset. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 970 | int offset_12 = x.offset_; |
| 971 | if (offset_12 < 0) { |
| 972 | offset_12 = -offset_12; |
| 973 | am ^= U; |
| 974 | } |
| 975 | if (!is_uint12(offset_12)) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 976 | // Immediate offset cannot be encoded, load it first to register ip |
| 977 | // rn (and rd in a load) should never be ip, or will be trashed. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 978 | ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 979 | mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 980 | addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_)); |
| 981 | return; |
| 982 | } |
| 983 | ASSERT(offset_12 >= 0); // no masking needed |
| 984 | instr |= offset_12; |
| 985 | } else { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 986 | // Register offset (shift_imm_ and shift_op_ are 0) or scaled |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 987 | // register offset the constructors make sure than both shift_imm_ |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 988 | // and shift_op_ are initialized. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 989 | ASSERT(!x.rm_.is(pc)); |
| 990 | instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code(); |
| 991 | } |
| 992 | ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback |
| 993 | emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); |
| 994 | } |
| 995 | |
| 996 | |
| 997 | void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 998 | ASSERT((instr & ~(kCondMask | L | S6 | H)) == (B4 | B7)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 999 | ASSERT(x.rn_.is_valid()); |
| 1000 | int am = x.am_; |
| 1001 | if (!x.rm_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1002 | // Immediate offset. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1003 | int offset_8 = x.offset_; |
| 1004 | if (offset_8 < 0) { |
| 1005 | offset_8 = -offset_8; |
| 1006 | am ^= U; |
| 1007 | } |
| 1008 | if (!is_uint8(offset_8)) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1009 | // Immediate offset cannot be encoded, load it first to register ip |
| 1010 | // rn (and rd in a load) should never be ip, or will be trashed. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1011 | ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1012 | mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1013 | addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_)); |
| 1014 | return; |
| 1015 | } |
| 1016 | ASSERT(offset_8 >= 0); // no masking needed |
| 1017 | instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf); |
| 1018 | } else if (x.shift_imm_ != 0) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1019 | // Scaled register offset not supported, load index first |
| 1020 | // rn (and rd in a load) should never be ip, or will be trashed. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1021 | ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); |
| 1022 | mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC, |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1023 | Instruction::ConditionField(instr)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1024 | addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_)); |
| 1025 | return; |
| 1026 | } else { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1027 | // Register offset. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1028 | ASSERT((am & (P|W)) == P || !x.rm_.is(pc)); // no pc index with writeback |
| 1029 | instr |= x.rm_.code(); |
| 1030 | } |
| 1031 | ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback |
| 1032 | emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); |
| 1033 | } |
| 1034 | |
| 1035 | |
| 1036 | void Assembler::addrmod4(Instr instr, Register rn, RegList rl) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1037 | ASSERT((instr & ~(kCondMask | P | U | W | L)) == B27); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1038 | ASSERT(rl != 0); |
| 1039 | ASSERT(!rn.is(pc)); |
| 1040 | emit(instr | rn.code()*B16 | rl); |
| 1041 | } |
| 1042 | |
| 1043 | |
| 1044 | void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1045 | // Unindexed addressing is not encoded by this function. |
kasperl@chromium.org | b3284ad | 2009-05-18 06:12:45 +0000 | [diff] [blame] | 1046 | ASSERT_EQ((B27 | B26), |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1047 | (instr & ~(kCondMask | kCoprocessorMask | P | U | N | W | L))); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1048 | ASSERT(x.rn_.is_valid() && !x.rm_.is_valid()); |
| 1049 | int am = x.am_; |
| 1050 | int offset_8 = x.offset_; |
| 1051 | ASSERT((offset_8 & 3) == 0); // offset must be an aligned word offset |
| 1052 | offset_8 >>= 2; |
| 1053 | if (offset_8 < 0) { |
| 1054 | offset_8 = -offset_8; |
| 1055 | am ^= U; |
| 1056 | } |
| 1057 | ASSERT(is_uint8(offset_8)); // unsigned word offset must fit in a byte |
| 1058 | ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback |
| 1059 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1060 | // Post-indexed addressing requires W == 1; different than in addrmod2/3. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1061 | if ((am & P) == 0) |
| 1062 | am |= W; |
| 1063 | |
| 1064 | ASSERT(offset_8 >= 0); // no masking needed |
| 1065 | emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8); |
| 1066 | } |
| 1067 | |
| 1068 | |
mads.s.ager@gmail.com | 769cc96 | 2008-08-06 10:02:49 +0000 | [diff] [blame] | 1069 | int Assembler::branch_offset(Label* L, bool jump_elimination_allowed) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1070 | int target_pos; |
| 1071 | if (L->is_bound()) { |
| 1072 | target_pos = L->pos(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1073 | } else { |
kasperl@chromium.org | 41044eb | 2008-10-06 08:24:46 +0000 | [diff] [blame] | 1074 | if (L->is_linked()) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1075 | target_pos = L->pos(); // L's link |
kasperl@chromium.org | 41044eb | 2008-10-06 08:24:46 +0000 | [diff] [blame] | 1076 | } else { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1077 | target_pos = kEndOfChain; |
kasperl@chromium.org | 41044eb | 2008-10-06 08:24:46 +0000 | [diff] [blame] | 1078 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1079 | L->link_to(pc_offset()); |
| 1080 | } |
| 1081 | |
| 1082 | // Block the emission of the constant pool, since the branch instruction must |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1083 | // be emitted at the pc offset recorded by the label. |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 1084 | BlockConstPoolFor(1); |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 1085 | return target_pos - (pc_offset() + kPcLoadDelta); |
| 1086 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1087 | |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 1088 | |
| 1089 | void Assembler::label_at_put(Label* L, int at_offset) { |
| 1090 | int target_pos; |
| 1091 | if (L->is_bound()) { |
| 1092 | target_pos = L->pos(); |
| 1093 | } else { |
| 1094 | if (L->is_linked()) { |
| 1095 | target_pos = L->pos(); // L's link |
| 1096 | } else { |
| 1097 | target_pos = kEndOfChain; |
| 1098 | } |
| 1099 | L->link_to(at_offset); |
| 1100 | instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
| 1101 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1102 | } |
| 1103 | |
| 1104 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1105 | // Branch instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1106 | void Assembler::b(int branch_offset, Condition cond) { |
| 1107 | ASSERT((branch_offset & 3) == 0); |
| 1108 | int imm24 = branch_offset >> 2; |
| 1109 | ASSERT(is_int24(imm24)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1110 | emit(cond | B27 | B25 | (imm24 & kImm24Mask)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1111 | |
lrn@chromium.org | c34f580 | 2010-04-28 12:53:43 +0000 | [diff] [blame] | 1112 | if (cond == al) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1113 | // Dead code is a good location to emit the constant pool. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1114 | CheckConstPool(false, false); |
lrn@chromium.org | c34f580 | 2010-04-28 12:53:43 +0000 | [diff] [blame] | 1115 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1116 | } |
| 1117 | |
| 1118 | |
| 1119 | void Assembler::bl(int branch_offset, Condition cond) { |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1120 | positions_recorder()->WriteRecordedPositions(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1121 | ASSERT((branch_offset & 3) == 0); |
| 1122 | int imm24 = branch_offset >> 2; |
| 1123 | ASSERT(is_int24(imm24)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1124 | emit(cond | B27 | B25 | B24 | (imm24 & kImm24Mask)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1125 | } |
| 1126 | |
| 1127 | |
| 1128 | void Assembler::blx(int branch_offset) { // v5 and above |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1129 | positions_recorder()->WriteRecordedPositions(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1130 | ASSERT((branch_offset & 1) == 0); |
| 1131 | int h = ((branch_offset & 2) >> 1)*B24; |
| 1132 | int imm24 = branch_offset >> 2; |
| 1133 | ASSERT(is_int24(imm24)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1134 | emit(kSpecialCondition | B27 | B25 | h | (imm24 & kImm24Mask)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1135 | } |
| 1136 | |
| 1137 | |
| 1138 | void Assembler::blx(Register target, Condition cond) { // v5 and above |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1139 | positions_recorder()->WriteRecordedPositions(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1140 | ASSERT(!target.is(pc)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1141 | emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BLX | target.code()); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1142 | } |
| 1143 | |
| 1144 | |
| 1145 | void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1146 | positions_recorder()->WriteRecordedPositions(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1147 | ASSERT(!target.is(pc)); // use of pc is actually allowed, but discouraged |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1148 | emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BX | target.code()); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1149 | } |
| 1150 | |
| 1151 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1152 | // Data-processing instructions. |
| 1153 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1154 | void Assembler::and_(Register dst, Register src1, const Operand& src2, |
| 1155 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1156 | addrmod1(cond | AND | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1157 | } |
| 1158 | |
| 1159 | |
| 1160 | void Assembler::eor(Register dst, Register src1, const Operand& src2, |
| 1161 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1162 | addrmod1(cond | EOR | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1163 | } |
| 1164 | |
| 1165 | |
| 1166 | void Assembler::sub(Register dst, Register src1, const Operand& src2, |
| 1167 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1168 | addrmod1(cond | SUB | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1169 | } |
| 1170 | |
| 1171 | |
| 1172 | void Assembler::rsb(Register dst, Register src1, const Operand& src2, |
| 1173 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1174 | addrmod1(cond | RSB | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1175 | } |
| 1176 | |
| 1177 | |
| 1178 | void Assembler::add(Register dst, Register src1, const Operand& src2, |
| 1179 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1180 | addrmod1(cond | ADD | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1181 | } |
| 1182 | |
| 1183 | |
| 1184 | void Assembler::adc(Register dst, Register src1, const Operand& src2, |
| 1185 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1186 | addrmod1(cond | ADC | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1187 | } |
| 1188 | |
| 1189 | |
| 1190 | void Assembler::sbc(Register dst, Register src1, const Operand& src2, |
| 1191 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1192 | addrmod1(cond | SBC | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1193 | } |
| 1194 | |
| 1195 | |
| 1196 | void Assembler::rsc(Register dst, Register src1, const Operand& src2, |
| 1197 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1198 | addrmod1(cond | RSC | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | |
| 1202 | void Assembler::tst(Register src1, const Operand& src2, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1203 | addrmod1(cond | TST | S, src1, r0, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1204 | } |
| 1205 | |
| 1206 | |
| 1207 | void Assembler::teq(Register src1, const Operand& src2, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1208 | addrmod1(cond | TEQ | S, src1, r0, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1209 | } |
| 1210 | |
| 1211 | |
| 1212 | void Assembler::cmp(Register src1, const Operand& src2, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1213 | addrmod1(cond | CMP | S, src1, r0, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1214 | } |
| 1215 | |
| 1216 | |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 1217 | void Assembler::cmp_raw_immediate( |
| 1218 | Register src, int raw_immediate, Condition cond) { |
| 1219 | ASSERT(is_uint12(raw_immediate)); |
| 1220 | emit(cond | I | CMP | S | src.code() << 16 | raw_immediate); |
| 1221 | } |
| 1222 | |
| 1223 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1224 | void Assembler::cmn(Register src1, const Operand& src2, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1225 | addrmod1(cond | CMN | S, src1, r0, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1226 | } |
| 1227 | |
| 1228 | |
| 1229 | void Assembler::orr(Register dst, Register src1, const Operand& src2, |
| 1230 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1231 | addrmod1(cond | ORR | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1232 | } |
| 1233 | |
| 1234 | |
| 1235 | void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) { |
kasperl@chromium.org | defbd10 | 2009-07-13 14:04:26 +0000 | [diff] [blame] | 1236 | if (dst.is(pc)) { |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1237 | positions_recorder()->WriteRecordedPositions(); |
kasperl@chromium.org | defbd10 | 2009-07-13 14:04:26 +0000 | [diff] [blame] | 1238 | } |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 1239 | // Don't allow nop instructions in the form mov rn, rn to be generated using |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 1240 | // the mov instruction. They must be generated using nop(int/NopMarkerTypes) |
| 1241 | // or MarkCode(int/NopMarkerTypes) pseudo instructions. |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 1242 | ASSERT(!(src.is_reg() && src.rm().is(dst) && s == LeaveCC && cond == al)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1243 | addrmod1(cond | MOV | s, r0, dst, src); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1244 | } |
| 1245 | |
| 1246 | |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 1247 | void Assembler::movw(Register reg, uint32_t immediate, Condition cond) { |
| 1248 | ASSERT(immediate < 0x10000); |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 1249 | // May use movw if supported, but on unsupported platforms will try to use |
| 1250 | // equivalent rotated immed_8 value and other tricks before falling back to a |
| 1251 | // constant pool load. |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 1252 | mov(reg, Operand(immediate), LeaveCC, cond); |
| 1253 | } |
| 1254 | |
| 1255 | |
| 1256 | void Assembler::movt(Register reg, uint32_t immediate, Condition cond) { |
| 1257 | emit(cond | 0x34*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate)); |
| 1258 | } |
| 1259 | |
| 1260 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1261 | void Assembler::bic(Register dst, Register src1, const Operand& src2, |
| 1262 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1263 | addrmod1(cond | BIC | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1264 | } |
| 1265 | |
| 1266 | |
| 1267 | void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1268 | addrmod1(cond | MVN | s, r0, dst, src); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1269 | } |
| 1270 | |
| 1271 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1272 | // Multiply instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1273 | void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, |
| 1274 | SBit s, Condition cond) { |
| 1275 | ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1276 | emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | |
| 1277 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1278 | } |
| 1279 | |
| 1280 | |
verwaest@chromium.org | 33e09c8 | 2012-10-10 17:07:22 +0000 | [diff] [blame] | 1281 | void Assembler::mls(Register dst, Register src1, Register src2, Register srcA, |
| 1282 | Condition cond) { |
| 1283 | ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
| 1284 | emit(cond | B22 | B21 | dst.code()*B16 | srcA.code()*B12 | |
| 1285 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1286 | } |
| 1287 | |
| 1288 | |
| 1289 | void Assembler::sdiv(Register dst, Register src1, Register src2, |
| 1290 | Condition cond) { |
| 1291 | ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
| 1292 | emit(cond | B26 | B25| B24 | B20 | dst.code()*B16 | 0xf * B12 | |
| 1293 | src2.code()*B8 | B4 | src1.code()); |
| 1294 | } |
| 1295 | |
| 1296 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1297 | void Assembler::mul(Register dst, Register src1, Register src2, |
| 1298 | SBit s, Condition cond) { |
| 1299 | ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 86f77b7 | 2009-07-06 08:21:57 +0000 | [diff] [blame] | 1300 | // dst goes in bits 16-19 for this instruction! |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1301 | emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1302 | } |
| 1303 | |
| 1304 | |
| 1305 | void Assembler::smlal(Register dstL, |
| 1306 | Register dstH, |
| 1307 | Register src1, |
| 1308 | Register src2, |
| 1309 | SBit s, |
| 1310 | Condition cond) { |
| 1311 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 1312 | ASSERT(!dstL.is(dstH)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1313 | emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1314 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1315 | } |
| 1316 | |
| 1317 | |
| 1318 | void Assembler::smull(Register dstL, |
| 1319 | Register dstH, |
| 1320 | Register src1, |
| 1321 | Register src2, |
| 1322 | SBit s, |
| 1323 | Condition cond) { |
| 1324 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 1325 | ASSERT(!dstL.is(dstH)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1326 | emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1327 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1328 | } |
| 1329 | |
| 1330 | |
| 1331 | void Assembler::umlal(Register dstL, |
| 1332 | Register dstH, |
| 1333 | Register src1, |
| 1334 | Register src2, |
| 1335 | SBit s, |
| 1336 | Condition cond) { |
| 1337 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 1338 | ASSERT(!dstL.is(dstH)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1339 | emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1340 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1341 | } |
| 1342 | |
| 1343 | |
| 1344 | void Assembler::umull(Register dstL, |
| 1345 | Register dstH, |
| 1346 | Register src1, |
| 1347 | Register src2, |
| 1348 | SBit s, |
| 1349 | Condition cond) { |
| 1350 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 1351 | ASSERT(!dstL.is(dstH)); |
kasperl@chromium.org | 86f77b7 | 2009-07-06 08:21:57 +0000 | [diff] [blame] | 1352 | emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1353 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1354 | } |
| 1355 | |
| 1356 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1357 | // Miscellaneous arithmetic instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1358 | void Assembler::clz(Register dst, Register src, Condition cond) { |
| 1359 | // v5 and above. |
| 1360 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1361 | emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 | |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1362 | 15*B8 | CLZ | src.code()); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1363 | } |
| 1364 | |
| 1365 | |
fschneider@chromium.org | ed78ffd | 2010-07-21 11:05:19 +0000 | [diff] [blame] | 1366 | // Saturating instructions. |
| 1367 | |
| 1368 | // Unsigned saturate. |
| 1369 | void Assembler::usat(Register dst, |
| 1370 | int satpos, |
| 1371 | const Operand& src, |
| 1372 | Condition cond) { |
| 1373 | // v6 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1374 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
fschneider@chromium.org | ed78ffd | 2010-07-21 11:05:19 +0000 | [diff] [blame] | 1375 | ASSERT(!dst.is(pc) && !src.rm_.is(pc)); |
| 1376 | ASSERT((satpos >= 0) && (satpos <= 31)); |
| 1377 | ASSERT((src.shift_op_ == ASR) || (src.shift_op_ == LSL)); |
| 1378 | ASSERT(src.rs_.is(no_reg)); |
| 1379 | |
| 1380 | int sh = 0; |
| 1381 | if (src.shift_op_ == ASR) { |
| 1382 | sh = 1; |
| 1383 | } |
| 1384 | |
| 1385 | emit(cond | 0x6*B24 | 0xe*B20 | satpos*B16 | dst.code()*B12 | |
| 1386 | src.shift_imm_*B7 | sh*B6 | 0x1*B4 | src.rm_.code()); |
| 1387 | } |
| 1388 | |
| 1389 | |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1390 | // Bitfield manipulation instructions. |
| 1391 | |
| 1392 | // Unsigned bit field extract. |
| 1393 | // Extracts #width adjacent bits from position #lsb in a register, and |
| 1394 | // writes them to the low bits of a destination register. |
| 1395 | // ubfx dst, src, #lsb, #width |
| 1396 | void Assembler::ubfx(Register dst, |
| 1397 | Register src, |
| 1398 | int lsb, |
| 1399 | int width, |
| 1400 | Condition cond) { |
| 1401 | // v7 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1402 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1403 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1404 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1405 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1406 | emit(cond | 0xf*B23 | B22 | B21 | (width - 1)*B16 | dst.code()*B12 | |
| 1407 | lsb*B7 | B6 | B4 | src.code()); |
| 1408 | } |
| 1409 | |
| 1410 | |
| 1411 | // Signed bit field extract. |
| 1412 | // Extracts #width adjacent bits from position #lsb in a register, and |
| 1413 | // writes them to the low bits of a destination register. The extracted |
| 1414 | // value is sign extended to fill the destination register. |
| 1415 | // sbfx dst, src, #lsb, #width |
| 1416 | void Assembler::sbfx(Register dst, |
| 1417 | Register src, |
| 1418 | int lsb, |
| 1419 | int width, |
| 1420 | Condition cond) { |
| 1421 | // v7 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1422 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1423 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1424 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1425 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1426 | emit(cond | 0xf*B23 | B21 | (width - 1)*B16 | dst.code()*B12 | |
| 1427 | lsb*B7 | B6 | B4 | src.code()); |
| 1428 | } |
| 1429 | |
| 1430 | |
| 1431 | // Bit field clear. |
| 1432 | // Sets #width adjacent bits at position #lsb in the destination register |
| 1433 | // to zero, preserving the value of the other bits. |
| 1434 | // bfc dst, #lsb, #width |
| 1435 | void Assembler::bfc(Register dst, int lsb, int width, Condition cond) { |
| 1436 | // v7 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1437 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1438 | ASSERT(!dst.is(pc)); |
| 1439 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1440 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1441 | int msb = lsb + width - 1; |
| 1442 | emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 | 0xf); |
| 1443 | } |
| 1444 | |
| 1445 | |
| 1446 | // Bit field insert. |
| 1447 | // Inserts #width adjacent bits from the low bits of the source register |
| 1448 | // into position #lsb of the destination register. |
| 1449 | // bfi dst, src, #lsb, #width |
| 1450 | void Assembler::bfi(Register dst, |
| 1451 | Register src, |
| 1452 | int lsb, |
| 1453 | int width, |
| 1454 | Condition cond) { |
| 1455 | // v7 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1456 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1457 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1458 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1459 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1460 | int msb = lsb + width - 1; |
| 1461 | emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 | |
| 1462 | src.code()); |
| 1463 | } |
| 1464 | |
| 1465 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1466 | // Status register access instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1467 | void Assembler::mrs(Register dst, SRegister s, Condition cond) { |
| 1468 | ASSERT(!dst.is(pc)); |
| 1469 | emit(cond | B24 | s | 15*B16 | dst.code()*B12); |
| 1470 | } |
| 1471 | |
| 1472 | |
| 1473 | void Assembler::msr(SRegisterFieldMask fields, const Operand& src, |
| 1474 | Condition cond) { |
| 1475 | ASSERT(fields >= B16 && fields < B20); // at least one field set |
| 1476 | Instr instr; |
| 1477 | if (!src.rm_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1478 | // Immediate. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1479 | uint32_t rotate_imm; |
| 1480 | uint32_t immed_8; |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 1481 | if (src.must_output_reloc_info(this) || |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1482 | !fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1483 | // Immediate operand cannot be encoded, load it first to register ip. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1484 | RecordRelocInfo(src.rmode_, src.imm32_); |
| 1485 | ldr(ip, MemOperand(pc, 0), cond); |
| 1486 | msr(fields, Operand(ip), cond); |
| 1487 | return; |
| 1488 | } |
| 1489 | instr = I | rotate_imm*B8 | immed_8; |
| 1490 | } else { |
| 1491 | ASSERT(!src.rs_.is_valid() && src.shift_imm_ == 0); // only rm allowed |
| 1492 | instr = src.rm_.code(); |
| 1493 | } |
| 1494 | emit(cond | instr | B24 | B21 | fields | 15*B12); |
| 1495 | } |
| 1496 | |
| 1497 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1498 | // Load/Store instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1499 | void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) { |
kasperl@chromium.org | defbd10 | 2009-07-13 14:04:26 +0000 | [diff] [blame] | 1500 | if (dst.is(pc)) { |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1501 | positions_recorder()->WriteRecordedPositions(); |
kasperl@chromium.org | defbd10 | 2009-07-13 14:04:26 +0000 | [diff] [blame] | 1502 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1503 | addrmod2(cond | B26 | L, dst, src); |
| 1504 | } |
| 1505 | |
| 1506 | |
| 1507 | void Assembler::str(Register src, const MemOperand& dst, Condition cond) { |
| 1508 | addrmod2(cond | B26, src, dst); |
| 1509 | } |
| 1510 | |
| 1511 | |
| 1512 | void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) { |
| 1513 | addrmod2(cond | B26 | B | L, dst, src); |
| 1514 | } |
| 1515 | |
| 1516 | |
| 1517 | void Assembler::strb(Register src, const MemOperand& dst, Condition cond) { |
| 1518 | addrmod2(cond | B26 | B, src, dst); |
| 1519 | } |
| 1520 | |
| 1521 | |
| 1522 | void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) { |
| 1523 | addrmod3(cond | L | B7 | H | B4, dst, src); |
| 1524 | } |
| 1525 | |
| 1526 | |
| 1527 | void Assembler::strh(Register src, const MemOperand& dst, Condition cond) { |
| 1528 | addrmod3(cond | B7 | H | B4, src, dst); |
| 1529 | } |
| 1530 | |
| 1531 | |
| 1532 | void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) { |
| 1533 | addrmod3(cond | L | B7 | S6 | B4, dst, src); |
| 1534 | } |
| 1535 | |
| 1536 | |
| 1537 | void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) { |
| 1538 | addrmod3(cond | L | B7 | S6 | H | B4, dst, src); |
| 1539 | } |
| 1540 | |
| 1541 | |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1542 | void Assembler::ldrd(Register dst1, Register dst2, |
| 1543 | const MemOperand& src, Condition cond) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1544 | ASSERT(CpuFeatures::IsEnabled(ARMv7)); |
sgjesse@chromium.org | 720dc0b | 2010-05-10 09:25:39 +0000 | [diff] [blame] | 1545 | ASSERT(src.rm().is(no_reg)); |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1546 | ASSERT(!dst1.is(lr)); // r14. |
| 1547 | ASSERT_EQ(0, dst1.code() % 2); |
| 1548 | ASSERT_EQ(dst1.code() + 1, dst2.code()); |
| 1549 | addrmod3(cond | B7 | B6 | B4, dst1, src); |
sgjesse@chromium.org | 720dc0b | 2010-05-10 09:25:39 +0000 | [diff] [blame] | 1550 | } |
| 1551 | |
| 1552 | |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1553 | void Assembler::strd(Register src1, Register src2, |
| 1554 | const MemOperand& dst, Condition cond) { |
sgjesse@chromium.org | 720dc0b | 2010-05-10 09:25:39 +0000 | [diff] [blame] | 1555 | ASSERT(dst.rm().is(no_reg)); |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1556 | ASSERT(!src1.is(lr)); // r14. |
| 1557 | ASSERT_EQ(0, src1.code() % 2); |
| 1558 | ASSERT_EQ(src1.code() + 1, src2.code()); |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1559 | ASSERT(CpuFeatures::IsEnabled(ARMv7)); |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1560 | addrmod3(cond | B7 | B6 | B5 | B4, src1, dst); |
sgjesse@chromium.org | 720dc0b | 2010-05-10 09:25:39 +0000 | [diff] [blame] | 1561 | } |
| 1562 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1563 | // Load/Store multiple instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1564 | void Assembler::ldm(BlockAddrMode am, |
| 1565 | Register base, |
| 1566 | RegList dst, |
| 1567 | Condition cond) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1568 | // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1569 | ASSERT(base.is(sp) || (dst & sp.bit()) == 0); |
| 1570 | |
| 1571 | addrmod4(cond | B27 | am | L, base, dst); |
| 1572 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1573 | // Emit the constant pool after a function return implemented by ldm ..{..pc}. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1574 | if (cond == al && (dst & pc.bit()) != 0) { |
| 1575 | // There is a slight chance that the ldm instruction was actually a call, |
| 1576 | // in which case it would be wrong to return into the constant pool; we |
| 1577 | // recognize this case by checking if the emission of the pool was blocked |
| 1578 | // at the pc of the ldm instruction by a mov lr, pc instruction; if this is |
| 1579 | // the case, we emit a jump over the pool. |
| 1580 | CheckConstPool(true, no_const_pool_before_ == pc_offset() - kInstrSize); |
| 1581 | } |
| 1582 | } |
| 1583 | |
| 1584 | |
| 1585 | void Assembler::stm(BlockAddrMode am, |
| 1586 | Register base, |
| 1587 | RegList src, |
| 1588 | Condition cond) { |
| 1589 | addrmod4(cond | B27 | am, base, src); |
| 1590 | } |
| 1591 | |
| 1592 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1593 | // Exception-generating instructions and debugging support. |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1594 | // Stops with a non-negative code less than kNumOfWatchedStops support |
| 1595 | // enabling/disabling and a counter feature. See simulator-arm.h . |
| 1596 | void Assembler::stop(const char* msg, Condition cond, int32_t code) { |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1597 | #ifndef __arm__ |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1598 | ASSERT(code >= kDefaultStopCode); |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 1599 | { |
| 1600 | // The Simulator will handle the stop instruction and get the message |
| 1601 | // address. It expects to find the address just after the svc instruction. |
| 1602 | BlockConstPoolScope block_const_pool(this); |
| 1603 | if (code >= 0) { |
| 1604 | svc(kStopCode + code, cond); |
| 1605 | } else { |
| 1606 | svc(kStopCode + kMaxStopCode, cond); |
| 1607 | } |
| 1608 | emit(reinterpret_cast<Instr>(msg)); |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1609 | } |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1610 | #else // def __arm__ |
| 1611 | #ifdef CAN_USE_ARMV5_INSTRUCTIONS |
vegorov@chromium.org | 0a4e901 | 2011-01-24 12:33:13 +0000 | [diff] [blame] | 1612 | if (cond != al) { |
| 1613 | Label skip; |
| 1614 | b(&skip, NegateCondition(cond)); |
| 1615 | bkpt(0); |
| 1616 | bind(&skip); |
| 1617 | } else { |
| 1618 | bkpt(0); |
| 1619 | } |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1620 | #else // ndef CAN_USE_ARMV5_INSTRUCTIONS |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1621 | svc(0x9f0001, cond); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1622 | #endif // ndef CAN_USE_ARMV5_INSTRUCTIONS |
| 1623 | #endif // def __arm__ |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1624 | } |
| 1625 | |
| 1626 | |
| 1627 | void Assembler::bkpt(uint32_t imm16) { // v5 and above |
| 1628 | ASSERT(is_uint16(imm16)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1629 | emit(al | B24 | B21 | (imm16 >> 4)*B8 | BKPT | (imm16 & 0xf)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1630 | } |
| 1631 | |
| 1632 | |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1633 | void Assembler::svc(uint32_t imm24, Condition cond) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1634 | ASSERT(is_uint24(imm24)); |
| 1635 | emit(cond | 15*B24 | imm24); |
| 1636 | } |
| 1637 | |
| 1638 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1639 | // Coprocessor instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1640 | void Assembler::cdp(Coprocessor coproc, |
| 1641 | int opcode_1, |
| 1642 | CRegister crd, |
| 1643 | CRegister crn, |
| 1644 | CRegister crm, |
| 1645 | int opcode_2, |
| 1646 | Condition cond) { |
| 1647 | ASSERT(is_uint4(opcode_1) && is_uint3(opcode_2)); |
| 1648 | emit(cond | B27 | B26 | B25 | (opcode_1 & 15)*B20 | crn.code()*B16 | |
| 1649 | crd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | crm.code()); |
| 1650 | } |
| 1651 | |
| 1652 | |
| 1653 | void Assembler::cdp2(Coprocessor coproc, |
| 1654 | int opcode_1, |
| 1655 | CRegister crd, |
| 1656 | CRegister crn, |
| 1657 | CRegister crm, |
| 1658 | int opcode_2) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1659 | cdp(coproc, opcode_1, crd, crn, crm, opcode_2, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1660 | } |
| 1661 | |
| 1662 | |
| 1663 | void Assembler::mcr(Coprocessor coproc, |
| 1664 | int opcode_1, |
| 1665 | Register rd, |
| 1666 | CRegister crn, |
| 1667 | CRegister crm, |
| 1668 | int opcode_2, |
| 1669 | Condition cond) { |
| 1670 | ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2)); |
| 1671 | emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | crn.code()*B16 | |
| 1672 | rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code()); |
| 1673 | } |
| 1674 | |
| 1675 | |
| 1676 | void Assembler::mcr2(Coprocessor coproc, |
| 1677 | int opcode_1, |
| 1678 | Register rd, |
| 1679 | CRegister crn, |
| 1680 | CRegister crm, |
| 1681 | int opcode_2) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1682 | mcr(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1683 | } |
| 1684 | |
| 1685 | |
| 1686 | void Assembler::mrc(Coprocessor coproc, |
| 1687 | int opcode_1, |
| 1688 | Register rd, |
| 1689 | CRegister crn, |
| 1690 | CRegister crm, |
| 1691 | int opcode_2, |
| 1692 | Condition cond) { |
| 1693 | ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2)); |
| 1694 | emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | L | crn.code()*B16 | |
| 1695 | rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code()); |
| 1696 | } |
| 1697 | |
| 1698 | |
| 1699 | void Assembler::mrc2(Coprocessor coproc, |
| 1700 | int opcode_1, |
| 1701 | Register rd, |
| 1702 | CRegister crn, |
| 1703 | CRegister crm, |
| 1704 | int opcode_2) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1705 | mrc(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1706 | } |
| 1707 | |
| 1708 | |
| 1709 | void Assembler::ldc(Coprocessor coproc, |
| 1710 | CRegister crd, |
| 1711 | const MemOperand& src, |
| 1712 | LFlag l, |
| 1713 | Condition cond) { |
| 1714 | addrmod5(cond | B27 | B26 | l | L | coproc*B8, crd, src); |
| 1715 | } |
| 1716 | |
| 1717 | |
| 1718 | void Assembler::ldc(Coprocessor coproc, |
| 1719 | CRegister crd, |
| 1720 | Register rn, |
| 1721 | int option, |
| 1722 | LFlag l, |
| 1723 | Condition cond) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1724 | // Unindexed addressing. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1725 | ASSERT(is_uint8(option)); |
| 1726 | emit(cond | B27 | B26 | U | l | L | rn.code()*B16 | crd.code()*B12 | |
| 1727 | coproc*B8 | (option & 255)); |
| 1728 | } |
| 1729 | |
| 1730 | |
| 1731 | void Assembler::ldc2(Coprocessor coproc, |
| 1732 | CRegister crd, |
| 1733 | const MemOperand& src, |
| 1734 | LFlag l) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1735 | ldc(coproc, crd, src, l, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1736 | } |
| 1737 | |
| 1738 | |
| 1739 | void Assembler::ldc2(Coprocessor coproc, |
| 1740 | CRegister crd, |
| 1741 | Register rn, |
| 1742 | int option, |
| 1743 | LFlag l) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1744 | ldc(coproc, crd, rn, option, l, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1745 | } |
| 1746 | |
| 1747 | |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 1748 | // Support for VFP. |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 1749 | |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1750 | void Assembler::vldr(const DwVfpRegister dst, |
| 1751 | const Register base, |
| 1752 | int offset, |
| 1753 | const Condition cond) { |
| 1754 | // Ddst = MEM(Rbase + offset). |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1755 | // Instruction details available in ARM DDI 0406C.b, A8-924. |
| 1756 | // cond(31-28) | 1101(27-24)| U(23) | D(22) | 01(21-20) | Rbase(19-16) | |
| 1757 | // Vd(15-12) | 1011(11-8) | offset |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 1758 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1759 | int u = 1; |
| 1760 | if (offset < 0) { |
| 1761 | offset = -offset; |
| 1762 | u = 0; |
| 1763 | } |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1764 | int vd, d; |
| 1765 | dst.split_code(&vd, &d); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1766 | |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 1767 | ASSERT(offset >= 0); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1768 | if ((offset % 4) == 0 && (offset / 4) < 256) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1769 | emit(cond | 0xD*B24 | u*B23 | d*B22 | B20 | base.code()*B16 | vd*B12 | |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1770 | 0xB*B8 | ((offset / 4) & 255)); |
| 1771 | } else { |
| 1772 | // Larger offsets must be handled by computing the correct address |
| 1773 | // in the ip register. |
| 1774 | ASSERT(!base.is(ip)); |
| 1775 | if (u == 1) { |
| 1776 | add(ip, base, Operand(offset)); |
| 1777 | } else { |
| 1778 | sub(ip, base, Operand(offset)); |
| 1779 | } |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1780 | emit(cond | 0xD*B24 | d*B22 | B20 | ip.code()*B16 | vd*B12 | 0xB*B8); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1781 | } |
| 1782 | } |
| 1783 | |
| 1784 | |
| 1785 | void Assembler::vldr(const DwVfpRegister dst, |
| 1786 | const MemOperand& operand, |
| 1787 | const Condition cond) { |
| 1788 | ASSERT(!operand.rm().is_valid()); |
| 1789 | ASSERT(operand.am_ == Offset); |
| 1790 | vldr(dst, operand.rn(), operand.offset(), cond); |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1791 | } |
| 1792 | |
| 1793 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1794 | void Assembler::vldr(const SwVfpRegister dst, |
| 1795 | const Register base, |
| 1796 | int offset, |
| 1797 | const Condition cond) { |
| 1798 | // Sdst = MEM(Rbase + offset). |
| 1799 | // Instruction details available in ARM DDI 0406A, A8-628. |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1800 | // cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1801 | // Vdst(15-12) | 1010(11-8) | offset |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 1802 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1803 | int u = 1; |
| 1804 | if (offset < 0) { |
| 1805 | offset = -offset; |
| 1806 | u = 0; |
| 1807 | } |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 1808 | int sd, d; |
| 1809 | dst.split_code(&sd, &d); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1810 | ASSERT(offset >= 0); |
| 1811 | |
| 1812 | if ((offset % 4) == 0 && (offset / 4) < 256) { |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1813 | emit(cond | u*B23 | d*B22 | 0xD1*B20 | base.code()*B16 | sd*B12 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1814 | 0xA*B8 | ((offset / 4) & 255)); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1815 | } else { |
| 1816 | // Larger offsets must be handled by computing the correct address |
| 1817 | // in the ip register. |
| 1818 | ASSERT(!base.is(ip)); |
| 1819 | if (u == 1) { |
| 1820 | add(ip, base, Operand(offset)); |
| 1821 | } else { |
| 1822 | sub(ip, base, Operand(offset)); |
| 1823 | } |
| 1824 | emit(cond | d*B22 | 0xD1*B20 | ip.code()*B16 | sd*B12 | 0xA*B8); |
| 1825 | } |
| 1826 | } |
| 1827 | |
| 1828 | |
| 1829 | void Assembler::vldr(const SwVfpRegister dst, |
| 1830 | const MemOperand& operand, |
| 1831 | const Condition cond) { |
| 1832 | ASSERT(!operand.rm().is_valid()); |
| 1833 | ASSERT(operand.am_ == Offset); |
| 1834 | vldr(dst, operand.rn(), operand.offset(), cond); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1835 | } |
| 1836 | |
| 1837 | |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1838 | void Assembler::vstr(const DwVfpRegister src, |
| 1839 | const Register base, |
| 1840 | int offset, |
| 1841 | const Condition cond) { |
| 1842 | // MEM(Rbase + offset) = Dsrc. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1843 | // Instruction details available in ARM DDI 0406C.b, A8-1082. |
| 1844 | // cond(31-28) | 1101(27-24)| U(23) | D(22) | 00(21-20) | Rbase(19-16) | |
| 1845 | // Vd(15-12) | 1011(11-8) | (offset/4) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 1846 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1847 | int u = 1; |
| 1848 | if (offset < 0) { |
| 1849 | offset = -offset; |
| 1850 | u = 0; |
| 1851 | } |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 1852 | ASSERT(offset >= 0); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1853 | int vd, d; |
| 1854 | src.split_code(&vd, &d); |
| 1855 | |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1856 | if ((offset % 4) == 0 && (offset / 4) < 256) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1857 | emit(cond | 0xD*B24 | u*B23 | d*B22 | base.code()*B16 | vd*B12 | 0xB*B8 | |
| 1858 | ((offset / 4) & 255)); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1859 | } else { |
| 1860 | // Larger offsets must be handled by computing the correct address |
| 1861 | // in the ip register. |
| 1862 | ASSERT(!base.is(ip)); |
| 1863 | if (u == 1) { |
| 1864 | add(ip, base, Operand(offset)); |
| 1865 | } else { |
| 1866 | sub(ip, base, Operand(offset)); |
| 1867 | } |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1868 | emit(cond | 0xD*B24 | d*B22 | ip.code()*B16 | vd*B12 | 0xB*B8); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1869 | } |
| 1870 | } |
| 1871 | |
| 1872 | |
| 1873 | void Assembler::vstr(const DwVfpRegister src, |
| 1874 | const MemOperand& operand, |
| 1875 | const Condition cond) { |
| 1876 | ASSERT(!operand.rm().is_valid()); |
| 1877 | ASSERT(operand.am_ == Offset); |
| 1878 | vstr(src, operand.rn(), operand.offset(), cond); |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1879 | } |
| 1880 | |
| 1881 | |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 1882 | void Assembler::vstr(const SwVfpRegister src, |
| 1883 | const Register base, |
| 1884 | int offset, |
| 1885 | const Condition cond) { |
| 1886 | // MEM(Rbase + offset) = SSrc. |
| 1887 | // Instruction details available in ARM DDI 0406A, A8-786. |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1888 | // cond(31-28) | 1101(27-24)| U000(23-20) | Rbase(19-16) | |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 1889 | // Vdst(15-12) | 1010(11-8) | (offset/4) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 1890 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1891 | int u = 1; |
| 1892 | if (offset < 0) { |
| 1893 | offset = -offset; |
| 1894 | u = 0; |
| 1895 | } |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 1896 | int sd, d; |
| 1897 | src.split_code(&sd, &d); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1898 | ASSERT(offset >= 0); |
| 1899 | if ((offset % 4) == 0 && (offset / 4) < 256) { |
| 1900 | emit(cond | u*B23 | d*B22 | 0xD0*B20 | base.code()*B16 | sd*B12 | |
| 1901 | 0xA*B8 | ((offset / 4) & 255)); |
| 1902 | } else { |
| 1903 | // Larger offsets must be handled by computing the correct address |
| 1904 | // in the ip register. |
| 1905 | ASSERT(!base.is(ip)); |
| 1906 | if (u == 1) { |
| 1907 | add(ip, base, Operand(offset)); |
| 1908 | } else { |
| 1909 | sub(ip, base, Operand(offset)); |
| 1910 | } |
| 1911 | emit(cond | d*B22 | 0xD0*B20 | ip.code()*B16 | sd*B12 | 0xA*B8); |
| 1912 | } |
| 1913 | } |
| 1914 | |
| 1915 | |
| 1916 | void Assembler::vstr(const SwVfpRegister src, |
| 1917 | const MemOperand& operand, |
| 1918 | const Condition cond) { |
| 1919 | ASSERT(!operand.rm().is_valid()); |
| 1920 | ASSERT(operand.am_ == Offset); |
svenpanne@chromium.org | c859c4f | 2012-10-15 11:51:39 +0000 | [diff] [blame] | 1921 | vstr(src, operand.rn(), operand.offset(), cond); |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 1922 | } |
| 1923 | |
| 1924 | |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame] | 1925 | void Assembler::vldm(BlockAddrMode am, |
| 1926 | Register base, |
| 1927 | DwVfpRegister first, |
| 1928 | DwVfpRegister last, |
| 1929 | Condition cond) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1930 | // Instruction details available in ARM DDI 0406C.b, A8-922. |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame] | 1931 | // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1932 | // first(15-12) | 1011(11-8) | (count * 2) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 1933 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame] | 1934 | ASSERT_LE(first.code(), last.code()); |
| 1935 | ASSERT(am == ia || am == ia_w || am == db_w); |
| 1936 | ASSERT(!base.is(pc)); |
| 1937 | |
| 1938 | int sd, d; |
| 1939 | first.split_code(&sd, &d); |
| 1940 | int count = last.code() - first.code() + 1; |
yangguo@chromium.org | 304cc33 | 2012-07-24 07:59:48 +0000 | [diff] [blame] | 1941 | ASSERT(count <= 16); |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame] | 1942 | emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 | |
| 1943 | 0xB*B8 | count*2); |
| 1944 | } |
| 1945 | |
| 1946 | |
| 1947 | void Assembler::vstm(BlockAddrMode am, |
| 1948 | Register base, |
| 1949 | DwVfpRegister first, |
| 1950 | DwVfpRegister last, |
| 1951 | Condition cond) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 1952 | // Instruction details available in ARM DDI 0406C.b, A8-1080. |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame] | 1953 | // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) | |
| 1954 | // first(15-12) | 1011(11-8) | (count * 2) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 1955 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame] | 1956 | ASSERT_LE(first.code(), last.code()); |
| 1957 | ASSERT(am == ia || am == ia_w || am == db_w); |
| 1958 | ASSERT(!base.is(pc)); |
| 1959 | |
| 1960 | int sd, d; |
| 1961 | first.split_code(&sd, &d); |
| 1962 | int count = last.code() - first.code() + 1; |
yangguo@chromium.org | 304cc33 | 2012-07-24 07:59:48 +0000 | [diff] [blame] | 1963 | ASSERT(count <= 16); |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame] | 1964 | emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 | |
| 1965 | 0xB*B8 | count*2); |
| 1966 | } |
| 1967 | |
| 1968 | void Assembler::vldm(BlockAddrMode am, |
| 1969 | Register base, |
| 1970 | SwVfpRegister first, |
| 1971 | SwVfpRegister last, |
| 1972 | Condition cond) { |
| 1973 | // Instruction details available in ARM DDI 0406A, A8-626. |
| 1974 | // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | |
| 1975 | // first(15-12) | 1010(11-8) | (count/2) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 1976 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame] | 1977 | ASSERT_LE(first.code(), last.code()); |
| 1978 | ASSERT(am == ia || am == ia_w || am == db_w); |
| 1979 | ASSERT(!base.is(pc)); |
| 1980 | |
| 1981 | int sd, d; |
| 1982 | first.split_code(&sd, &d); |
| 1983 | int count = last.code() - first.code() + 1; |
| 1984 | emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 | |
| 1985 | 0xA*B8 | count); |
| 1986 | } |
| 1987 | |
| 1988 | |
| 1989 | void Assembler::vstm(BlockAddrMode am, |
| 1990 | Register base, |
| 1991 | SwVfpRegister first, |
| 1992 | SwVfpRegister last, |
| 1993 | Condition cond) { |
| 1994 | // Instruction details available in ARM DDI 0406A, A8-784. |
| 1995 | // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) | |
| 1996 | // first(15-12) | 1011(11-8) | (count/2) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 1997 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame] | 1998 | ASSERT_LE(first.code(), last.code()); |
| 1999 | ASSERT(am == ia || am == ia_w || am == db_w); |
| 2000 | ASSERT(!base.is(pc)); |
| 2001 | |
| 2002 | int sd, d; |
| 2003 | first.split_code(&sd, &d); |
| 2004 | int count = last.code() - first.code() + 1; |
| 2005 | emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 | |
| 2006 | 0xA*B8 | count); |
| 2007 | } |
| 2008 | |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2009 | static void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) { |
| 2010 | uint64_t i; |
| 2011 | memcpy(&i, &d, 8); |
| 2012 | |
| 2013 | *lo = i & 0xffffffff; |
| 2014 | *hi = i >> 32; |
| 2015 | } |
| 2016 | |
| 2017 | // Only works for little endian floating point formats. |
| 2018 | // We don't support VFP on the mixed endian floating point platform. |
| 2019 | static bool FitsVMOVDoubleImmediate(double d, uint32_t *encoding) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2020 | ASSERT(CpuFeatures::IsSupported(VFP3)); |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2021 | |
| 2022 | // VMOV can accept an immediate of the form: |
| 2023 | // |
| 2024 | // +/- m * 2^(-n) where 16 <= m <= 31 and 0 <= n <= 7 |
| 2025 | // |
| 2026 | // The immediate is encoded using an 8-bit quantity, comprised of two |
| 2027 | // 4-bit fields. For an 8-bit immediate of the form: |
| 2028 | // |
| 2029 | // [abcdefgh] |
| 2030 | // |
| 2031 | // where a is the MSB and h is the LSB, an immediate 64-bit double can be |
| 2032 | // created of the form: |
| 2033 | // |
| 2034 | // [aBbbbbbb,bbcdefgh,00000000,00000000, |
| 2035 | // 00000000,00000000,00000000,00000000] |
| 2036 | // |
| 2037 | // where B = ~b. |
| 2038 | // |
| 2039 | |
| 2040 | uint32_t lo, hi; |
| 2041 | DoubleAsTwoUInt32(d, &lo, &hi); |
| 2042 | |
| 2043 | // The most obvious constraint is the long block of zeroes. |
| 2044 | if ((lo != 0) || ((hi & 0xffff) != 0)) { |
| 2045 | return false; |
| 2046 | } |
| 2047 | |
| 2048 | // Bits 62:55 must be all clear or all set. |
| 2049 | if (((hi & 0x3fc00000) != 0) && ((hi & 0x3fc00000) != 0x3fc00000)) { |
| 2050 | return false; |
| 2051 | } |
| 2052 | |
| 2053 | // Bit 63 must be NOT bit 62. |
| 2054 | if (((hi ^ (hi << 1)) & (0x40000000)) == 0) { |
| 2055 | return false; |
| 2056 | } |
| 2057 | |
| 2058 | // Create the encoded immediate in the form: |
| 2059 | // [00000000,0000abcd,00000000,0000efgh] |
| 2060 | *encoding = (hi >> 16) & 0xf; // Low nybble. |
| 2061 | *encoding |= (hi >> 4) & 0x70000; // Low three bits of the high nybble. |
| 2062 | *encoding |= (hi >> 12) & 0x80000; // Top bit of the high nybble. |
| 2063 | |
| 2064 | return true; |
| 2065 | } |
| 2066 | |
| 2067 | |
| 2068 | void Assembler::vmov(const DwVfpRegister dst, |
| 2069 | double imm, |
verwaest@chromium.org | 33e09c8 | 2012-10-10 17:07:22 +0000 | [diff] [blame] | 2070 | const Register scratch, |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2071 | const Condition cond) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2072 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2073 | |
| 2074 | uint32_t enc; |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2075 | if (CpuFeatures::IsSupported(VFP3) && FitsVMOVDoubleImmediate(imm, &enc)) { |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2076 | // The double can be encoded in the instruction. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2077 | // |
| 2078 | // Dd = immediate |
| 2079 | // Instruction details available in ARM DDI 0406C.b, A8-936. |
| 2080 | // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | imm4H(19-16) | |
| 2081 | // Vd(15-12) | 101(11-9) | sz=1(8) | imm4L(3-0) |
| 2082 | int vd, d; |
| 2083 | dst.split_code(&vd, &d); |
| 2084 | emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | vd*B12 | 0x5*B9 | B8 | enc); |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2085 | } else if (FLAG_enable_vldr_imm) { |
| 2086 | // TODO(jfb) Temporarily turned off until we have constant blinding or |
| 2087 | // some equivalent mitigation: an attacker can otherwise control |
| 2088 | // generated data which also happens to be executable, a Very Bad |
| 2089 | // Thing indeed. |
| 2090 | // Blinding gets tricky because we don't have xor, we probably |
| 2091 | // need to add/subtract without losing precision, which requires a |
| 2092 | // cookie value that Lithium is probably better positioned to |
| 2093 | // choose. |
| 2094 | // We could also add a few peepholes here like detecting 0.0 and |
| 2095 | // -0.0 and doing a vmov from the sequestered d14, forcing denorms |
| 2096 | // to zero (we set flush-to-zero), and normalizing NaN values. |
| 2097 | // We could also detect redundant values. |
| 2098 | // The code could also randomize the order of values, though |
| 2099 | // that's tricky because vldr has a limited reach. Furthermore |
| 2100 | // it breaks load locality. |
| 2101 | RecordRelocInfo(imm); |
| 2102 | vldr(dst, MemOperand(pc, 0), cond); |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2103 | } else { |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2104 | // Synthesise the double from ARM immediates. |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2105 | uint32_t lo, hi; |
| 2106 | DoubleAsTwoUInt32(imm, &lo, &hi); |
| 2107 | |
verwaest@chromium.org | 33e09c8 | 2012-10-10 17:07:22 +0000 | [diff] [blame] | 2108 | if (scratch.is(no_reg)) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2109 | if (dst.code() < 16) { |
| 2110 | // Move the low part of the double into the lower of the corresponsing S |
| 2111 | // registers of D register dst. |
| 2112 | mov(ip, Operand(lo)); |
| 2113 | vmov(dst.low(), ip, cond); |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2114 | |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2115 | // Move the high part of the double into the higher of the |
| 2116 | // corresponsing S registers of D register dst. |
| 2117 | mov(ip, Operand(hi)); |
| 2118 | vmov(dst.high(), ip, cond); |
| 2119 | } else { |
| 2120 | // D16-D31 does not have S registers, so move the low and high parts |
| 2121 | // directly to the D register using vmov.32. |
| 2122 | // Note: This may be slower, so we only do this when we have to. |
| 2123 | mov(ip, Operand(lo)); |
| 2124 | vmov(dst, 0, ip, cond); |
| 2125 | mov(ip, Operand(hi)); |
| 2126 | vmov(dst, 1, ip, cond); |
| 2127 | } |
verwaest@chromium.org | 33e09c8 | 2012-10-10 17:07:22 +0000 | [diff] [blame] | 2128 | } else { |
| 2129 | // Move the low and high parts of the double to a D register in one |
| 2130 | // instruction. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2131 | mov(ip, Operand(lo)); |
verwaest@chromium.org | 33e09c8 | 2012-10-10 17:07:22 +0000 | [diff] [blame] | 2132 | mov(scratch, Operand(hi)); |
| 2133 | vmov(dst, ip, scratch, cond); |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2134 | } |
| 2135 | } |
| 2136 | } |
| 2137 | |
| 2138 | |
| 2139 | void Assembler::vmov(const SwVfpRegister dst, |
| 2140 | const SwVfpRegister src, |
| 2141 | const Condition cond) { |
| 2142 | // Sd = Sm |
| 2143 | // Instruction details available in ARM DDI 0406B, A8-642. |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2144 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2145 | int sd, d, sm, m; |
| 2146 | dst.split_code(&sd, &d); |
| 2147 | src.split_code(&sm, &m); |
| 2148 | emit(cond | 0xE*B24 | d*B22 | 0xB*B20 | sd*B12 | 0xA*B8 | B6 | m*B5 | sm); |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2149 | } |
| 2150 | |
| 2151 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2152 | void Assembler::vmov(const DwVfpRegister dst, |
kmillikin@chromium.org | 69ea396 | 2010-07-05 11:01:40 +0000 | [diff] [blame] | 2153 | const DwVfpRegister src, |
| 2154 | const Condition cond) { |
| 2155 | // Dd = Dm |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2156 | // Instruction details available in ARM DDI 0406C.b, A8-938. |
| 2157 | // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0000(19-16) | Vd(15-12) | |
| 2158 | // 101(11-9) | sz=1(8) | 0(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2159 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2160 | int vd, d; |
| 2161 | dst.split_code(&vd, &d); |
| 2162 | int vm, m; |
| 2163 | src.split_code(&vm, &m); |
| 2164 | emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | vd*B12 | 0x5*B9 | B8 | B6 | m*B5 | |
| 2165 | vm); |
| 2166 | } |
| 2167 | |
| 2168 | |
| 2169 | void Assembler::vmov(const DwVfpRegister dst, |
| 2170 | int index, |
| 2171 | const Register src, |
| 2172 | const Condition cond) { |
| 2173 | // Dd[index] = Rt |
| 2174 | // Instruction details available in ARM DDI 0406C.b, A8-940. |
| 2175 | // cond(31-28) | 1110(27-24) | 0(23) | opc1=0index(22-21) | 0(20) | |
| 2176 | // Vd(19-16) | Rt(15-12) | 1011(11-8) | D(7) | opc2=00(6-5) | 1(4) | 0000(3-0) |
| 2177 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
| 2178 | ASSERT(index == 0 || index == 1); |
| 2179 | int vd, d; |
| 2180 | dst.split_code(&vd, &d); |
| 2181 | emit(cond | 0xE*B24 | index*B21 | vd*B16 | src.code()*B12 | 0xB*B8 | d*B7 | |
| 2182 | B4); |
kmillikin@chromium.org | 69ea396 | 2010-07-05 11:01:40 +0000 | [diff] [blame] | 2183 | } |
| 2184 | |
| 2185 | |
| 2186 | void Assembler::vmov(const DwVfpRegister dst, |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2187 | const Register src1, |
| 2188 | const Register src2, |
| 2189 | const Condition cond) { |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2190 | // Dm = <Rt,Rt2>. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2191 | // Instruction details available in ARM DDI 0406C.b, A8-948. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2192 | // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) | |
| 2193 | // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2194 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2195 | ASSERT(!src1.is(pc) && !src2.is(pc)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2196 | int vm, m; |
| 2197 | dst.split_code(&vm, &m); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2198 | emit(cond | 0xC*B24 | B22 | src2.code()*B16 | |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2199 | src1.code()*B12 | 0xB*B8 | m*B5 | B4 | vm); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2200 | } |
| 2201 | |
| 2202 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2203 | void Assembler::vmov(const Register dst1, |
| 2204 | const Register dst2, |
| 2205 | const DwVfpRegister src, |
| 2206 | const Condition cond) { |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2207 | // <Rt,Rt2> = Dm. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2208 | // Instruction details available in ARM DDI 0406C.b, A8-948. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2209 | // cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) | |
| 2210 | // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2211 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2212 | ASSERT(!dst1.is(pc) && !dst2.is(pc)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2213 | int vm, m; |
| 2214 | src.split_code(&vm, &m); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2215 | emit(cond | 0xC*B24 | B22 | B20 | dst2.code()*B16 | |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2216 | dst1.code()*B12 | 0xB*B8 | m*B5 | B4 | vm); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2217 | } |
| 2218 | |
| 2219 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2220 | void Assembler::vmov(const SwVfpRegister dst, |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2221 | const Register src, |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2222 | const Condition cond) { |
| 2223 | // Sn = Rt. |
| 2224 | // Instruction details available in ARM DDI 0406A, A8-642. |
| 2225 | // cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) | |
| 2226 | // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2227 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2228 | ASSERT(!src.is(pc)); |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2229 | int sn, n; |
| 2230 | dst.split_code(&sn, &n); |
| 2231 | emit(cond | 0xE*B24 | sn*B16 | src.code()*B12 | 0xA*B8 | n*B7 | B4); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2232 | } |
| 2233 | |
| 2234 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2235 | void Assembler::vmov(const Register dst, |
| 2236 | const SwVfpRegister src, |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2237 | const Condition cond) { |
| 2238 | // Rt = Sn. |
| 2239 | // Instruction details available in ARM DDI 0406A, A8-642. |
| 2240 | // cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) | |
| 2241 | // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2242 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2243 | ASSERT(!dst.is(pc)); |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2244 | int sn, n; |
| 2245 | src.split_code(&sn, &n); |
| 2246 | emit(cond | 0xE*B24 | B20 | sn*B16 | dst.code()*B12 | 0xA*B8 | n*B7 | B4); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2247 | } |
| 2248 | |
| 2249 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2250 | // Type of data to read from or write to VFP register. |
| 2251 | // Used as specifier in generic vcvt instruction. |
| 2252 | enum VFPType { S32, U32, F32, F64 }; |
| 2253 | |
| 2254 | |
| 2255 | static bool IsSignedVFPType(VFPType type) { |
| 2256 | switch (type) { |
| 2257 | case S32: |
| 2258 | return true; |
| 2259 | case U32: |
| 2260 | return false; |
| 2261 | default: |
| 2262 | UNREACHABLE(); |
| 2263 | return false; |
| 2264 | } |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2265 | } |
| 2266 | |
| 2267 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2268 | static bool IsIntegerVFPType(VFPType type) { |
| 2269 | switch (type) { |
| 2270 | case S32: |
| 2271 | case U32: |
| 2272 | return true; |
| 2273 | case F32: |
| 2274 | case F64: |
| 2275 | return false; |
| 2276 | default: |
| 2277 | UNREACHABLE(); |
| 2278 | return false; |
| 2279 | } |
| 2280 | } |
| 2281 | |
| 2282 | |
| 2283 | static bool IsDoubleVFPType(VFPType type) { |
| 2284 | switch (type) { |
| 2285 | case F32: |
| 2286 | return false; |
| 2287 | case F64: |
| 2288 | return true; |
| 2289 | default: |
| 2290 | UNREACHABLE(); |
| 2291 | return false; |
| 2292 | } |
| 2293 | } |
| 2294 | |
| 2295 | |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2296 | // Split five bit reg_code based on size of reg_type. |
| 2297 | // 32-bit register codes are Vm:M |
| 2298 | // 64-bit register codes are M:Vm |
| 2299 | // where Vm is four bits, and M is a single bit. |
| 2300 | static void SplitRegCode(VFPType reg_type, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2301 | int reg_code, |
| 2302 | int* vm, |
| 2303 | int* m) { |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2304 | ASSERT((reg_code >= 0) && (reg_code <= 31)); |
| 2305 | if (IsIntegerVFPType(reg_type) || !IsDoubleVFPType(reg_type)) { |
| 2306 | // 32 bit type. |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2307 | *m = reg_code & 0x1; |
| 2308 | *vm = reg_code >> 1; |
| 2309 | } else { |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2310 | // 64 bit type. |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2311 | *m = (reg_code & 0x10) >> 4; |
| 2312 | *vm = reg_code & 0x0F; |
| 2313 | } |
| 2314 | } |
| 2315 | |
| 2316 | |
| 2317 | // Encode vcvt.src_type.dst_type instruction. |
| 2318 | static Instr EncodeVCVT(const VFPType dst_type, |
| 2319 | const int dst_code, |
| 2320 | const VFPType src_type, |
| 2321 | const int src_code, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2322 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2323 | const Condition cond) { |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2324 | ASSERT(src_type != dst_type); |
| 2325 | int D, Vd, M, Vm; |
| 2326 | SplitRegCode(src_type, src_code, &Vm, &M); |
| 2327 | SplitRegCode(dst_type, dst_code, &Vd, &D); |
| 2328 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2329 | if (IsIntegerVFPType(dst_type) || IsIntegerVFPType(src_type)) { |
| 2330 | // Conversion between IEEE floating point and 32-bit integer. |
| 2331 | // Instruction details available in ARM DDI 0406B, A8.6.295. |
| 2332 | // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 1(19) | opc2(18-16) | |
| 2333 | // Vd(15-12) | 101(11-9) | sz(8) | op(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
| 2334 | ASSERT(!IsIntegerVFPType(dst_type) || !IsIntegerVFPType(src_type)); |
| 2335 | |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2336 | int sz, opc2, op; |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2337 | |
| 2338 | if (IsIntegerVFPType(dst_type)) { |
| 2339 | opc2 = IsSignedVFPType(dst_type) ? 0x5 : 0x4; |
| 2340 | sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0; |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2341 | op = mode; |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2342 | } else { |
| 2343 | ASSERT(IsIntegerVFPType(src_type)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2344 | opc2 = 0x0; |
| 2345 | sz = IsDoubleVFPType(dst_type) ? 0x1 : 0x0; |
| 2346 | op = IsSignedVFPType(src_type) ? 0x1 : 0x0; |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2347 | } |
| 2348 | |
| 2349 | return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | B19 | opc2*B16 | |
| 2350 | Vd*B12 | 0x5*B9 | sz*B8 | op*B7 | B6 | M*B5 | Vm); |
| 2351 | } else { |
| 2352 | // Conversion between IEEE double and single precision. |
| 2353 | // Instruction details available in ARM DDI 0406B, A8.6.298. |
| 2354 | // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0111(19-16) | |
| 2355 | // Vd(15-12) | 101(11-9) | sz(8) | 1(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2356 | int sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0; |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2357 | return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | 0x7*B16 | |
| 2358 | Vd*B12 | 0x5*B9 | sz*B8 | B7 | B6 | M*B5 | Vm); |
| 2359 | } |
| 2360 | } |
| 2361 | |
| 2362 | |
| 2363 | void Assembler::vcvt_f64_s32(const DwVfpRegister dst, |
| 2364 | const SwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2365 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2366 | const Condition cond) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2367 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2368 | emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2369 | } |
| 2370 | |
| 2371 | |
| 2372 | void Assembler::vcvt_f32_s32(const SwVfpRegister dst, |
| 2373 | const SwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2374 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2375 | const Condition cond) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2376 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2377 | emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2378 | } |
| 2379 | |
| 2380 | |
| 2381 | void Assembler::vcvt_f64_u32(const DwVfpRegister dst, |
| 2382 | const SwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2383 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2384 | const Condition cond) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2385 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2386 | emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2387 | } |
| 2388 | |
| 2389 | |
| 2390 | void Assembler::vcvt_s32_f64(const SwVfpRegister dst, |
| 2391 | const DwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2392 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2393 | const Condition cond) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2394 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2395 | emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2396 | } |
| 2397 | |
| 2398 | |
| 2399 | void Assembler::vcvt_u32_f64(const SwVfpRegister dst, |
| 2400 | const DwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2401 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2402 | const Condition cond) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2403 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2404 | emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2405 | } |
| 2406 | |
| 2407 | |
| 2408 | void Assembler::vcvt_f64_f32(const DwVfpRegister dst, |
| 2409 | const SwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2410 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2411 | const Condition cond) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2412 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2413 | emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2414 | } |
| 2415 | |
| 2416 | |
| 2417 | void Assembler::vcvt_f32_f64(const SwVfpRegister dst, |
| 2418 | const DwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2419 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2420 | const Condition cond) { |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2421 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2422 | emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2423 | } |
| 2424 | |
| 2425 | |
ricow@chromium.org | badaffc | 2011-03-17 12:15:27 +0000 | [diff] [blame] | 2426 | void Assembler::vneg(const DwVfpRegister dst, |
| 2427 | const DwVfpRegister src, |
| 2428 | const Condition cond) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2429 | // Instruction details available in ARM DDI 0406C.b, A8-968. |
| 2430 | // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) | |
| 2431 | // 101(11-9) | sz=1(8) | 0(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2432 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2433 | int vd, d; |
| 2434 | dst.split_code(&vd, &d); |
| 2435 | int vm, m; |
| 2436 | src.split_code(&vm, &m); |
| 2437 | |
| 2438 | emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | B16 | vd*B12 | 0x5*B9 | B8 | B6 | |
| 2439 | m*B5 | vm); |
ricow@chromium.org | badaffc | 2011-03-17 12:15:27 +0000 | [diff] [blame] | 2440 | } |
| 2441 | |
| 2442 | |
whesse@chromium.org | 7a392b3 | 2011-01-31 11:30:36 +0000 | [diff] [blame] | 2443 | void Assembler::vabs(const DwVfpRegister dst, |
| 2444 | const DwVfpRegister src, |
| 2445 | const Condition cond) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2446 | // Instruction details available in ARM DDI 0406C.b, A8-524. |
| 2447 | // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0000(19-16) | Vd(15-12) | |
| 2448 | // 101(11-9) | sz=1(8) | 1(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2449 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2450 | int vd, d; |
| 2451 | dst.split_code(&vd, &d); |
| 2452 | int vm, m; |
| 2453 | src.split_code(&vm, &m); |
| 2454 | emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | vd*B12 | 0x5*B9 | B8 | B7 | B6 | |
| 2455 | m*B5 | vm); |
whesse@chromium.org | 7a392b3 | 2011-01-31 11:30:36 +0000 | [diff] [blame] | 2456 | } |
| 2457 | |
| 2458 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2459 | void Assembler::vadd(const DwVfpRegister dst, |
| 2460 | const DwVfpRegister src1, |
| 2461 | const DwVfpRegister src2, |
| 2462 | const Condition cond) { |
| 2463 | // Dd = vadd(Dn, Dm) double precision floating point addition. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2464 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2465 | // Instruction details available in ARM DDI 0406C.b, A8-830. |
| 2466 | // cond(31-28) | 11100(27-23)| D(22) | 11(21-20) | Vn(19-16) | |
| 2467 | // Vd(15-12) | 101(11-9) | sz=1(8) | N(7) | 0(6) | M(5) | 0(4) | Vm(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2468 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2469 | int vd, d; |
| 2470 | dst.split_code(&vd, &d); |
| 2471 | int vn, n; |
| 2472 | src1.split_code(&vn, &n); |
| 2473 | int vm, m; |
| 2474 | src2.split_code(&vm, &m); |
| 2475 | emit(cond | 0x1C*B23 | d*B22 | 0x3*B20 | vn*B16 | vd*B12 | 0x5*B9 | B8 | |
| 2476 | n*B7 | m*B5 | vm); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2477 | } |
| 2478 | |
| 2479 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2480 | void Assembler::vsub(const DwVfpRegister dst, |
| 2481 | const DwVfpRegister src1, |
| 2482 | const DwVfpRegister src2, |
| 2483 | const Condition cond) { |
| 2484 | // Dd = vsub(Dn, Dm) double precision floating point subtraction. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2485 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2486 | // Instruction details available in ARM DDI 0406C.b, A8-1086. |
| 2487 | // cond(31-28) | 11100(27-23)| D(22) | 11(21-20) | Vn(19-16) | |
| 2488 | // Vd(15-12) | 101(11-9) | sz=1(8) | N(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2489 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2490 | int vd, d; |
| 2491 | dst.split_code(&vd, &d); |
| 2492 | int vn, n; |
| 2493 | src1.split_code(&vn, &n); |
| 2494 | int vm, m; |
| 2495 | src2.split_code(&vm, &m); |
| 2496 | emit(cond | 0x1C*B23 | d*B22 | 0x3*B20 | vn*B16 | vd*B12 | 0x5*B9 | B8 | |
| 2497 | n*B7 | B6 | m*B5 | vm); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2498 | } |
| 2499 | |
| 2500 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2501 | void Assembler::vmul(const DwVfpRegister dst, |
| 2502 | const DwVfpRegister src1, |
| 2503 | const DwVfpRegister src2, |
| 2504 | const Condition cond) { |
| 2505 | // Dd = vmul(Dn, Dm) double precision floating point multiplication. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2506 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2507 | // Instruction details available in ARM DDI 0406C.b, A8-960. |
| 2508 | // cond(31-28) | 11100(27-23)| D(22) | 10(21-20) | Vn(19-16) | |
| 2509 | // Vd(15-12) | 101(11-9) | sz=1(8) | N(7) | 0(6) | M(5) | 0(4) | Vm(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2510 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2511 | int vd, d; |
| 2512 | dst.split_code(&vd, &d); |
| 2513 | int vn, n; |
| 2514 | src1.split_code(&vn, &n); |
| 2515 | int vm, m; |
| 2516 | src2.split_code(&vm, &m); |
| 2517 | emit(cond | 0x1C*B23 | d*B22 | 0x2*B20 | vn*B16 | vd*B12 | 0x5*B9 | B8 | |
| 2518 | n*B7 | m*B5 | vm); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2519 | } |
| 2520 | |
| 2521 | |
yangguo@chromium.org | fb37721 | 2012-11-16 14:43:43 +0000 | [diff] [blame] | 2522 | void Assembler::vmla(const DwVfpRegister dst, |
| 2523 | const DwVfpRegister src1, |
| 2524 | const DwVfpRegister src2, |
| 2525 | const Condition cond) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2526 | // Instruction details available in ARM DDI 0406C.b, A8-932. |
| 2527 | // cond(31-28) | 11100(27-23) | D(22) | 00(21-20) | Vn(19-16) | |
| 2528 | // Vd(15-12) | 101(11-9) | sz=1(8) | N(7) | op=0(6) | M(5) | 0(4) | Vm(3-0) |
| 2529 | int vd, d; |
| 2530 | dst.split_code(&vd, &d); |
| 2531 | int vn, n; |
| 2532 | src1.split_code(&vn, &n); |
| 2533 | int vm, m; |
| 2534 | src2.split_code(&vm, &m); |
| 2535 | emit(cond | 0x1C*B23 | d*B22 | vn*B16 | vd*B12 | 0x5*B9 | B8 | n*B7 | m*B5 | |
| 2536 | vm); |
yangguo@chromium.org | fb37721 | 2012-11-16 14:43:43 +0000 | [diff] [blame] | 2537 | } |
| 2538 | |
| 2539 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2540 | void Assembler::vdiv(const DwVfpRegister dst, |
| 2541 | const DwVfpRegister src1, |
| 2542 | const DwVfpRegister src2, |
| 2543 | const Condition cond) { |
| 2544 | // Dd = vdiv(Dn, Dm) double precision floating point division. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2545 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2546 | // Instruction details available in ARM DDI 0406C.b, A8-882. |
| 2547 | // cond(31-28) | 11101(27-23)| D(22) | 00(21-20) | Vn(19-16) | |
| 2548 | // Vd(15-12) | 101(11-9) | sz=1(8) | N(7) | 0(6) | M(5) | 0(4) | Vm(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2549 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2550 | int vd, d; |
| 2551 | dst.split_code(&vd, &d); |
| 2552 | int vn, n; |
| 2553 | src1.split_code(&vn, &n); |
| 2554 | int vm, m; |
| 2555 | src2.split_code(&vm, &m); |
| 2556 | emit(cond | 0x1D*B23 | d*B22 | vn*B16 | vd*B12 | 0x5*B9 | B8 | n*B7 | m*B5 | |
| 2557 | vm); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2558 | } |
| 2559 | |
| 2560 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2561 | void Assembler::vcmp(const DwVfpRegister src1, |
| 2562 | const DwVfpRegister src2, |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2563 | const Condition cond) { |
| 2564 | // vcmp(Dd, Dm) double precision floating point comparison. |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2565 | // Instruction details available in ARM DDI 0406C.b, A8-864. |
| 2566 | // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0100(19-16) | |
| 2567 | // Vd(15-12) | 101(11-9) | sz=1(8) | E=0(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2568 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2569 | int vd, d; |
| 2570 | src1.split_code(&vd, &d); |
| 2571 | int vm, m; |
| 2572 | src2.split_code(&vm, &m); |
| 2573 | emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | 0x4*B16 | vd*B12 | 0x5*B9 | B8 | B6 | |
| 2574 | m*B5 | vm); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2575 | } |
| 2576 | |
| 2577 | |
ager@chromium.org | ea4f62e | 2010-08-16 16:28:43 +0000 | [diff] [blame] | 2578 | void Assembler::vcmp(const DwVfpRegister src1, |
| 2579 | const double src2, |
ager@chromium.org | ea4f62e | 2010-08-16 16:28:43 +0000 | [diff] [blame] | 2580 | const Condition cond) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2581 | // vcmp(Dd, #0.0) double precision floating point comparison. |
| 2582 | // Instruction details available in ARM DDI 0406C.b, A8-864. |
| 2583 | // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0101(19-16) | |
| 2584 | // Vd(15-12) | 101(11-9) | sz=1(8) | E=0(7) | 1(6) | 0(5) | 0(4) | 0000(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2585 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | ea4f62e | 2010-08-16 16:28:43 +0000 | [diff] [blame] | 2586 | ASSERT(src2 == 0.0); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2587 | int vd, d; |
| 2588 | src1.split_code(&vd, &d); |
| 2589 | emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | 0x5*B16 | vd*B12 | 0x5*B9 | B8 | B6); |
ager@chromium.org | ea4f62e | 2010-08-16 16:28:43 +0000 | [diff] [blame] | 2590 | } |
| 2591 | |
| 2592 | |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2593 | void Assembler::vmsr(Register dst, Condition cond) { |
| 2594 | // Instruction details available in ARM DDI 0406A, A8-652. |
| 2595 | // cond(31-28) | 1110 (27-24) | 1110(23-20)| 0001 (19-16) | |
| 2596 | // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2597 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2598 | emit(cond | 0xE*B24 | 0xE*B20 | B16 | |
| 2599 | dst.code()*B12 | 0xA*B8 | B4); |
| 2600 | } |
| 2601 | |
| 2602 | |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2603 | void Assembler::vmrs(Register dst, Condition cond) { |
| 2604 | // Instruction details available in ARM DDI 0406A, A8-652. |
| 2605 | // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) | |
| 2606 | // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2607 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2608 | emit(cond | 0xE*B24 | 0xF*B20 | B16 | |
| 2609 | dst.code()*B12 | 0xA*B8 | B4); |
| 2610 | } |
| 2611 | |
| 2612 | |
lrn@chromium.org | 32d961d | 2010-06-30 09:09:34 +0000 | [diff] [blame] | 2613 | void Assembler::vsqrt(const DwVfpRegister dst, |
| 2614 | const DwVfpRegister src, |
| 2615 | const Condition cond) { |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2616 | // Instruction details available in ARM DDI 0406C.b, A8-1058. |
| 2617 | // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0001(19-16) | |
| 2618 | // Vd(15-12) | 101(11-9) | sz=1(8) | 11(7-6) | M(5) | 0(4) | Vm(3-0) |
verwaest@chromium.org | b6d052d | 2012-07-27 08:03:27 +0000 | [diff] [blame] | 2619 | ASSERT(CpuFeatures::IsEnabled(VFP2)); |
yangguo@chromium.org | 003650e | 2013-01-24 16:31:08 +0000 | [diff] [blame] | 2620 | int vd, d; |
| 2621 | dst.split_code(&vd, &d); |
| 2622 | int vm, m; |
| 2623 | src.split_code(&vm, &m); |
| 2624 | emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | B16 | vd*B12 | 0x5*B9 | B8 | 0x3*B6 | |
| 2625 | m*B5 | vm); |
lrn@chromium.org | 32d961d | 2010-06-30 09:09:34 +0000 | [diff] [blame] | 2626 | } |
| 2627 | |
| 2628 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2629 | // Pseudo instructions. |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 2630 | void Assembler::nop(int type) { |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 2631 | // ARMv6{K/T2} and v7 have an actual NOP instruction but it serializes |
| 2632 | // some of the CPU's pipeline and has to issue. Older ARM chips simply used |
| 2633 | // MOV Rx, Rx as NOP and it performs better even in newer CPUs. |
| 2634 | // We therefore use MOV Rx, Rx, even on newer CPUs, and use Rx to encode |
| 2635 | // a type. |
| 2636 | ASSERT(0 <= type && type <= 14); // mov pc, pc isn't a nop. |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 2637 | emit(al | 13*B21 | type*B12 | type); |
| 2638 | } |
| 2639 | |
| 2640 | |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 2641 | bool Assembler::IsMovT(Instr instr) { |
| 2642 | instr &= ~(((kNumberOfConditions - 1) << 28) | // Mask off conditions |
| 2643 | ((kNumRegisters-1)*B12) | // mask out register |
| 2644 | EncodeMovwImmediate(0xFFFF)); // mask out immediate value |
| 2645 | return instr == 0x34*B20; |
| 2646 | } |
| 2647 | |
| 2648 | |
| 2649 | bool Assembler::IsMovW(Instr instr) { |
| 2650 | instr &= ~(((kNumberOfConditions - 1) << 28) | // Mask off conditions |
| 2651 | ((kNumRegisters-1)*B12) | // mask out destination |
| 2652 | EncodeMovwImmediate(0xFFFF)); // mask out immediate value |
| 2653 | return instr == 0x30*B20; |
| 2654 | } |
| 2655 | |
| 2656 | |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 2657 | bool Assembler::IsNop(Instr instr, int type) { |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 2658 | ASSERT(0 <= type && type <= 14); // mov pc, pc isn't a nop. |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 2659 | // Check for mov rx, rx where x = type. |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 2660 | return instr == (al | 13*B21 | type*B12 | type); |
| 2661 | } |
| 2662 | |
| 2663 | |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2664 | bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) { |
| 2665 | uint32_t dummy1; |
| 2666 | uint32_t dummy2; |
| 2667 | return fits_shifter(imm32, &dummy1, &dummy2, NULL); |
| 2668 | } |
| 2669 | |
| 2670 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2671 | // Debugging. |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 2672 | void Assembler::RecordJSReturn() { |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 2673 | positions_recorder()->WriteRecordedPositions(); |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 2674 | CheckBuffer(); |
| 2675 | RecordRelocInfo(RelocInfo::JS_RETURN); |
| 2676 | } |
| 2677 | |
| 2678 | |
vegorov@chromium.org | 2356e6f | 2010-06-09 09:38:56 +0000 | [diff] [blame] | 2679 | void Assembler::RecordDebugBreakSlot() { |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 2680 | positions_recorder()->WriteRecordedPositions(); |
vegorov@chromium.org | 2356e6f | 2010-06-09 09:38:56 +0000 | [diff] [blame] | 2681 | CheckBuffer(); |
| 2682 | RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT); |
| 2683 | } |
| 2684 | |
| 2685 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2686 | void Assembler::RecordComment(const char* msg) { |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2687 | if (FLAG_code_comments) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2688 | CheckBuffer(); |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 2689 | RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2690 | } |
| 2691 | } |
| 2692 | |
| 2693 | |
yangguo@chromium.org | 5a11aaf | 2012-06-20 11:29:00 +0000 | [diff] [blame] | 2694 | void Assembler::RecordConstPool(int size) { |
| 2695 | // We only need this for debugger support, to correctly compute offsets in the |
| 2696 | // code. |
| 2697 | #ifdef ENABLE_DEBUGGER_SUPPORT |
| 2698 | RecordRelocInfo(RelocInfo::CONST_POOL, static_cast<intptr_t>(size)); |
| 2699 | #endif |
| 2700 | } |
| 2701 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2702 | void Assembler::GrowBuffer() { |
| 2703 | if (!own_buffer_) FATAL("external code buffer is too small"); |
| 2704 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2705 | // Compute new buffer size. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2706 | CodeDesc desc; // the new buffer |
| 2707 | if (buffer_size_ < 4*KB) { |
| 2708 | desc.buffer_size = 4*KB; |
| 2709 | } else if (buffer_size_ < 1*MB) { |
| 2710 | desc.buffer_size = 2*buffer_size_; |
| 2711 | } else { |
| 2712 | desc.buffer_size = buffer_size_ + 1*MB; |
| 2713 | } |
| 2714 | CHECK_GT(desc.buffer_size, 0); // no overflow |
| 2715 | |
erik.corry@gmail.com | f2038fb | 2012-01-16 11:42:08 +0000 | [diff] [blame] | 2716 | // Set up new buffer. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2717 | desc.buffer = NewArray<byte>(desc.buffer_size); |
| 2718 | |
| 2719 | desc.instr_size = pc_offset(); |
| 2720 | desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); |
| 2721 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2722 | // Copy the data. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2723 | int pc_delta = desc.buffer - buffer_; |
| 2724 | int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_); |
| 2725 | memmove(desc.buffer, buffer_, desc.instr_size); |
| 2726 | memmove(reloc_info_writer.pos() + rc_delta, |
| 2727 | reloc_info_writer.pos(), desc.reloc_size); |
| 2728 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2729 | // Switch buffers. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2730 | DeleteArray(buffer_); |
| 2731 | buffer_ = desc.buffer; |
| 2732 | buffer_size_ = desc.buffer_size; |
| 2733 | pc_ += pc_delta; |
| 2734 | reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta, |
| 2735 | reloc_info_writer.last_pc() + pc_delta); |
| 2736 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2737 | // None of our relocation types are pc relative pointing outside the code |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2738 | // buffer nor pc absolute pointing inside the code buffer, so there is no need |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2739 | // to relocate any emitted relocation entries. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2740 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2741 | // Relocate pending relocation entries. |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2742 | for (int i = 0; i < num_pending_reloc_info_; i++) { |
| 2743 | RelocInfo& rinfo = pending_reloc_info_[i]; |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 2744 | ASSERT(rinfo.rmode() != RelocInfo::COMMENT && |
| 2745 | rinfo.rmode() != RelocInfo::POSITION); |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 2746 | if (rinfo.rmode() != RelocInfo::JS_RETURN) { |
| 2747 | rinfo.set_pc(rinfo.pc() + pc_delta); |
| 2748 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2749 | } |
| 2750 | } |
| 2751 | |
| 2752 | |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2753 | void Assembler::db(uint8_t data) { |
erik.corry@gmail.com | 0511e24 | 2011-01-19 11:11:08 +0000 | [diff] [blame] | 2754 | // No relocation info should be pending while using db. db is used |
| 2755 | // to write pure data with no pointers and the constant pool should |
| 2756 | // be emitted before using db. |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2757 | ASSERT(num_pending_reloc_info_ == 0); |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2758 | ASSERT(num_pending_64_bit_reloc_info_ == 0); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2759 | CheckBuffer(); |
| 2760 | *reinterpret_cast<uint8_t*>(pc_) = data; |
| 2761 | pc_ += sizeof(uint8_t); |
| 2762 | } |
| 2763 | |
| 2764 | |
| 2765 | void Assembler::dd(uint32_t data) { |
erik.corry@gmail.com | 0511e24 | 2011-01-19 11:11:08 +0000 | [diff] [blame] | 2766 | // No relocation info should be pending while using dd. dd is used |
| 2767 | // to write pure data with no pointers and the constant pool should |
| 2768 | // be emitted before using dd. |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2769 | ASSERT(num_pending_reloc_info_ == 0); |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2770 | ASSERT(num_pending_64_bit_reloc_info_ == 0); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2771 | CheckBuffer(); |
| 2772 | *reinterpret_cast<uint32_t*>(pc_) = data; |
| 2773 | pc_ += sizeof(uint32_t); |
| 2774 | } |
| 2775 | |
| 2776 | |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 2777 | void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data, |
| 2778 | UseConstantPoolMode mode) { |
erik.corry@gmail.com | c3b670f | 2011-10-05 21:44:48 +0000 | [diff] [blame] | 2779 | // We do not try to reuse pool constants. |
| 2780 | RelocInfo rinfo(pc_, rmode, data, NULL); |
yangguo@chromium.org | 5a11aaf | 2012-06-20 11:29:00 +0000 | [diff] [blame] | 2781 | if (((rmode >= RelocInfo::JS_RETURN) && |
| 2782 | (rmode <= RelocInfo::DEBUG_BREAK_SLOT)) || |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 2783 | (rmode == RelocInfo::CONST_POOL) || |
| 2784 | mode == DONT_USE_CONSTANT_POOL) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2785 | // Adjust code for new modes. |
vegorov@chromium.org | 2356e6f | 2010-06-09 09:38:56 +0000 | [diff] [blame] | 2786 | ASSERT(RelocInfo::IsDebugBreakSlot(rmode) |
| 2787 | || RelocInfo::IsJSReturn(rmode) |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 2788 | || RelocInfo::IsComment(rmode) |
yangguo@chromium.org | 5a11aaf | 2012-06-20 11:29:00 +0000 | [diff] [blame] | 2789 | || RelocInfo::IsPosition(rmode) |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 2790 | || RelocInfo::IsConstPool(rmode) |
| 2791 | || mode == DONT_USE_CONSTANT_POOL); |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2792 | // These modes do not need an entry in the constant pool. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2793 | } else { |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2794 | RecordRelocInfoConstantPoolEntryHelper(rinfo); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2795 | } |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2796 | if (!RelocInfo::IsNone(rinfo.rmode())) { |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 2797 | // Don't record external references unless the heap will be serialized. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2798 | if (rmode == RelocInfo::EXTERNAL_REFERENCE) { |
| 2799 | #ifdef DEBUG |
| 2800 | if (!Serializer::enabled()) { |
| 2801 | Serializer::TooLateToEnableNow(); |
| 2802 | } |
| 2803 | #endif |
ricow@chromium.org | badaffc | 2011-03-17 12:15:27 +0000 | [diff] [blame] | 2804 | if (!Serializer::enabled() && !emit_debug_code()) { |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2805 | return; |
| 2806 | } |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 2807 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2808 | ASSERT(buffer_space() >= kMaxRelocSize); // too late to grow buffer here |
sgjesse@chromium.org | 8e8294a | 2011-05-02 14:30:53 +0000 | [diff] [blame] | 2809 | if (rmode == RelocInfo::CODE_TARGET_WITH_ID) { |
mstarzinger@chromium.org | 471f2f1 | 2012-08-10 14:46:33 +0000 | [diff] [blame] | 2810 | RelocInfo reloc_info_with_ast_id(pc_, |
| 2811 | rmode, |
| 2812 | RecordedAstId().ToInt(), |
| 2813 | NULL); |
rossberg@chromium.org | 717967f | 2011-07-20 13:44:42 +0000 | [diff] [blame] | 2814 | ClearRecordedAstId(); |
sgjesse@chromium.org | 8e8294a | 2011-05-02 14:30:53 +0000 | [diff] [blame] | 2815 | reloc_info_writer.Write(&reloc_info_with_ast_id); |
| 2816 | } else { |
| 2817 | reloc_info_writer.Write(&rinfo); |
| 2818 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2819 | } |
| 2820 | } |
| 2821 | |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2822 | void Assembler::RecordRelocInfo(double data) { |
| 2823 | // We do not try to reuse pool constants. |
| 2824 | RelocInfo rinfo(pc_, data); |
| 2825 | RecordRelocInfoConstantPoolEntryHelper(rinfo); |
| 2826 | } |
| 2827 | |
| 2828 | |
| 2829 | void Assembler::RecordRelocInfoConstantPoolEntryHelper(const RelocInfo& rinfo) { |
| 2830 | ASSERT(num_pending_reloc_info_ < kMaxNumPendingRelocInfo); |
| 2831 | if (num_pending_reloc_info_ == 0) { |
| 2832 | first_const_pool_use_ = pc_offset(); |
| 2833 | } |
| 2834 | pending_reloc_info_[num_pending_reloc_info_++] = rinfo; |
| 2835 | if (rinfo.rmode() == RelocInfo::NONE64) { |
| 2836 | ++num_pending_64_bit_reloc_info_; |
| 2837 | } |
| 2838 | ASSERT(num_pending_64_bit_reloc_info_ <= num_pending_reloc_info_); |
| 2839 | // Make sure the constant pool is not emitted in place of the next |
| 2840 | // instruction for which we just recorded relocation info. |
| 2841 | BlockConstPoolFor(1); |
| 2842 | } |
| 2843 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2844 | |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2845 | void Assembler::BlockConstPoolFor(int instructions) { |
| 2846 | int pc_limit = pc_offset() + instructions * kInstrSize; |
| 2847 | if (no_const_pool_before_ < pc_limit) { |
| 2848 | // If there are some pending entries, the constant pool cannot be blocked |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2849 | // further than constant pool instruction's reach. |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2850 | ASSERT((num_pending_reloc_info_ == 0) || |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2851 | (pc_limit - first_const_pool_use_ < kMaxDistToIntPool)); |
| 2852 | // TODO(jfb) Also check 64-bit entries are in range (requires splitting |
| 2853 | // them up from 32-bit entries). |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2854 | no_const_pool_before_ = pc_limit; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2855 | } |
| 2856 | |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2857 | if (next_buffer_check_ < no_const_pool_before_) { |
| 2858 | next_buffer_check_ = no_const_pool_before_; |
| 2859 | } |
| 2860 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2861 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2862 | |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2863 | void Assembler::CheckConstPool(bool force_emit, bool require_jump) { |
| 2864 | // Some short sequence of instruction mustn't be broken up by constant pool |
| 2865 | // emission, such sequences are protected by calls to BlockConstPoolFor and |
| 2866 | // BlockConstPoolScope. |
| 2867 | if (is_const_pool_blocked()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2868 | // Something is wrong if emission is forced and blocked at the same time. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2869 | ASSERT(!force_emit); |
| 2870 | return; |
| 2871 | } |
| 2872 | |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2873 | // There is nothing to do if there are no pending constant pool entries. |
| 2874 | if (num_pending_reloc_info_ == 0) { |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2875 | ASSERT(num_pending_64_bit_reloc_info_ == 0); |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2876 | // Calculate the offset of the next check. |
| 2877 | next_buffer_check_ = pc_offset() + kCheckPoolInterval; |
| 2878 | return; |
| 2879 | } |
| 2880 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2881 | // Check that the code buffer is large enough before emitting the constant |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2882 | // pool (include the jump over the pool and the constant pool marker and |
| 2883 | // the gap to the relocation information). |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2884 | // Note 64-bit values are wider, and the first one needs to be 64-bit aligned. |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2885 | int jump_instr = require_jump ? kInstrSize : 0; |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2886 | int size_up_to_marker = jump_instr + kInstrSize; |
| 2887 | int size_after_marker = num_pending_reloc_info_ * kPointerSize; |
| 2888 | bool has_fp_values = (num_pending_64_bit_reloc_info_ > 0); |
| 2889 | // 64-bit values must be 64-bit aligned. |
| 2890 | // We'll start emitting at PC: branch+marker, then 32-bit values, then |
| 2891 | // 64-bit values which might need to be aligned. |
| 2892 | bool require_64_bit_align = has_fp_values && |
| 2893 | (((uintptr_t)pc_ + size_up_to_marker + size_after_marker) & 0x3); |
| 2894 | if (require_64_bit_align) { |
| 2895 | size_after_marker += kInstrSize; |
| 2896 | } |
| 2897 | // num_pending_reloc_info_ also contains 64-bit entries, the above code |
| 2898 | // therefore already counted half of the size for 64-bit entries. Add the |
| 2899 | // remaining size. |
| 2900 | STATIC_ASSERT(kPointerSize == kDoubleSize / 2); |
| 2901 | size_after_marker += num_pending_64_bit_reloc_info_ * (kDoubleSize / 2); |
| 2902 | |
| 2903 | int size = size_up_to_marker + size_after_marker; |
| 2904 | |
| 2905 | // We emit a constant pool when: |
| 2906 | // * requested to do so by parameter force_emit (e.g. after each function). |
| 2907 | // * the distance from the first instruction accessing the constant pool to |
| 2908 | // any of the constant pool entries will exceed its limit the next |
| 2909 | // time the pool is checked. This is overly restrictive, but we don't emit |
| 2910 | // constant pool entries in-order so it's conservatively correct. |
| 2911 | // * the instruction doesn't require a jump after itself to jump over the |
| 2912 | // constant pool, and we're getting close to running out of range. |
| 2913 | if (!force_emit) { |
| 2914 | ASSERT((first_const_pool_use_ >= 0) && (num_pending_reloc_info_ > 0)); |
| 2915 | int dist = pc_offset() + size - first_const_pool_use_; |
| 2916 | if (has_fp_values) { |
| 2917 | if ((dist < kMaxDistToFPPool - kCheckPoolInterval) && |
| 2918 | (require_jump || (dist < kMaxDistToFPPool / 2))) { |
| 2919 | return; |
| 2920 | } |
| 2921 | } else { |
| 2922 | if ((dist < kMaxDistToIntPool - kCheckPoolInterval) && |
| 2923 | (require_jump || (dist < kMaxDistToIntPool / 2))) { |
| 2924 | return; |
| 2925 | } |
| 2926 | } |
| 2927 | } |
| 2928 | |
yangguo@chromium.org | 5a11aaf | 2012-06-20 11:29:00 +0000 | [diff] [blame] | 2929 | int needed_space = size + kGap; |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2930 | while (buffer_space() <= needed_space) GrowBuffer(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2931 | |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2932 | { |
| 2933 | // Block recursive calls to CheckConstPool. |
| 2934 | BlockConstPoolScope block_const_pool(this); |
yangguo@chromium.org | 5a11aaf | 2012-06-20 11:29:00 +0000 | [diff] [blame] | 2935 | RecordComment("[ Constant Pool"); |
| 2936 | RecordConstPool(size); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2937 | |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2938 | // Emit jump over constant pool if necessary. |
| 2939 | Label after_pool; |
| 2940 | if (require_jump) { |
| 2941 | b(&after_pool); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2942 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2943 | |
danno@chromium.org | 72204d5 | 2012-10-31 10:02:10 +0000 | [diff] [blame] | 2944 | // Put down constant pool marker "Undefined instruction". |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2945 | // The data size helps disassembly know what to print. |
| 2946 | emit(kConstantPoolMarker | EncodeConstantPoolLength(size_after_marker)); |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2947 | |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2948 | if (require_64_bit_align) { |
| 2949 | emit(kConstantPoolMarker); |
| 2950 | } |
| 2951 | |
| 2952 | // Emit 64-bit constant pool entries first: their range is smaller than |
| 2953 | // 32-bit entries. |
| 2954 | for (int i = 0; i < num_pending_reloc_info_; i++) { |
| 2955 | RelocInfo& rinfo = pending_reloc_info_[i]; |
| 2956 | |
| 2957 | if (rinfo.rmode() != RelocInfo::NONE64) { |
| 2958 | // 32-bit values emitted later. |
| 2959 | continue; |
| 2960 | } |
| 2961 | |
| 2962 | ASSERT(!((uintptr_t)pc_ & 0x3)); // Check 64-bit alignment. |
| 2963 | |
| 2964 | Instr instr = instr_at(rinfo.pc()); |
| 2965 | // Instruction to patch must be 'vldr rd, [pc, #offset]' with offset == 0. |
| 2966 | ASSERT((IsVldrDPcImmediateOffset(instr) && |
| 2967 | GetVldrDRegisterImmediateOffset(instr) == 0)); |
| 2968 | |
| 2969 | int delta = pc_ - rinfo.pc() - kPcLoadDelta; |
| 2970 | ASSERT(is_uint10(delta)); |
| 2971 | |
| 2972 | instr_at_put(rinfo.pc(), SetVldrDRegisterImmediateOffset(instr, delta)); |
| 2973 | |
| 2974 | const double double_data = rinfo.data64(); |
| 2975 | uint64_t uint_data = 0; |
| 2976 | memcpy(&uint_data, &double_data, sizeof(double_data)); |
| 2977 | emit(uint_data & 0xFFFFFFFF); |
| 2978 | emit(uint_data >> 32); |
| 2979 | } |
| 2980 | |
| 2981 | // Emit 32-bit constant pool entries. |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2982 | for (int i = 0; i < num_pending_reloc_info_; i++) { |
| 2983 | RelocInfo& rinfo = pending_reloc_info_[i]; |
| 2984 | ASSERT(rinfo.rmode() != RelocInfo::COMMENT && |
| 2985 | rinfo.rmode() != RelocInfo::POSITION && |
yangguo@chromium.org | 5a11aaf | 2012-06-20 11:29:00 +0000 | [diff] [blame] | 2986 | rinfo.rmode() != RelocInfo::STATEMENT_POSITION && |
| 2987 | rinfo.rmode() != RelocInfo::CONST_POOL); |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2988 | |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2989 | if (rinfo.rmode() == RelocInfo::NONE64) { |
| 2990 | // 64-bit values emitted earlier. |
| 2991 | continue; |
| 2992 | } |
| 2993 | |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 2994 | Instr instr = instr_at(rinfo.pc()); |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 2995 | |
| 2996 | // 64-bit loads shouldn't get here. |
| 2997 | ASSERT(!IsVldrDPcImmediateOffset(instr)); |
| 2998 | |
| 2999 | int delta = pc_ - rinfo.pc() - kPcLoadDelta; |
| 3000 | // 0 is the smallest delta: |
| 3001 | // ldr rd, [pc, #0] |
| 3002 | // constant pool marker |
| 3003 | // data |
| 3004 | |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 3005 | if (IsLdrPcImmediateOffset(instr) && |
| 3006 | GetLdrRegisterImmediateOffset(instr) == 0) { |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 3007 | ASSERT(is_uint12(delta)); |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 3008 | instr_at_put(rinfo.pc(), SetLdrRegisterImmediateOffset(instr, delta)); |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 3009 | emit(rinfo.data()); |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 3010 | } else { |
| 3011 | ASSERT(IsMovW(instr)); |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 3012 | emit(rinfo.data()); |
rossberg@chromium.org | 89e18f5 | 2012-10-22 13:09:53 +0000 | [diff] [blame] | 3013 | } |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 3014 | } |
| 3015 | |
| 3016 | num_pending_reloc_info_ = 0; |
yangguo@chromium.org | 4cd70b4 | 2013-01-04 08:57:54 +0000 | [diff] [blame] | 3017 | num_pending_64_bit_reloc_info_ = 0; |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 3018 | first_const_pool_use_ = -1; |
| 3019 | |
| 3020 | RecordComment("]"); |
| 3021 | |
| 3022 | if (after_pool.is_linked()) { |
| 3023 | bind(&after_pool); |
| 3024 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 3025 | } |
| 3026 | |
| 3027 | // Since a constant pool was just emitted, move the check offset forward by |
| 3028 | // the standard interval. |
whesse@chromium.org | 7b26015 | 2011-06-20 15:33:18 +0000 | [diff] [blame] | 3029 | next_buffer_check_ = pc_offset() + kCheckPoolInterval; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 3030 | } |
| 3031 | |
| 3032 | |
| 3033 | } } // namespace v8::internal |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 3034 | |
| 3035 | #endif // V8_TARGET_ARCH_ARM |