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Chris Lattnerd32b2362005-08-18 18:45:24 +00001//===-- ScheduleDAG.cpp - Implement a trivial DAG scheduler ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
Jim Laskey5a608dd2005-10-31 12:49:09 +00005// This file was developed by James M. Laskey and is distributed under the
Chris Lattnerd32b2362005-08-18 18:45:24 +00006// University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Jim Laskeye6b90fb2005-09-26 21:57:04 +000010// This implements a simple two pass scheduler. The first pass attempts to push
11// backward any lengthy instructions and critical paths. The second pass packs
12// instructions into semi-optimal time slots.
Chris Lattnerd32b2362005-08-18 18:45:24 +000013//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "sched"
Chris Lattner5839bf22005-08-26 17:15:30 +000017#include "llvm/CodeGen/MachineConstantPool.h"
Chris Lattner4ccd4062005-08-19 20:45:43 +000018#include "llvm/CodeGen/MachineFunction.h"
Chris Lattnerd32b2362005-08-18 18:45:24 +000019#include "llvm/CodeGen/SelectionDAGISel.h"
Chris Lattner2d973e42005-08-18 20:07:59 +000020#include "llvm/CodeGen/SelectionDAG.h"
Chris Lattner4ccd4062005-08-19 20:45:43 +000021#include "llvm/CodeGen/SSARegMap.h"
Chris Lattner2d973e42005-08-18 20:07:59 +000022#include "llvm/Target/TargetMachine.h"
23#include "llvm/Target/TargetInstrInfo.h"
Jim Laskey7d090f32005-11-04 04:05:35 +000024#include "llvm/Target/TargetInstrItineraries.h"
Chris Lattner025c39b2005-08-26 20:54:47 +000025#include "llvm/Target/TargetLowering.h"
Chris Lattner068ca152005-08-18 20:11:49 +000026#include "llvm/Support/CommandLine.h"
Jim Laskeye6b90fb2005-09-26 21:57:04 +000027#include "llvm/Support/Debug.h"
28#include <iostream>
Chris Lattnerd32b2362005-08-18 18:45:24 +000029using namespace llvm;
30
Jim Laskeye6b90fb2005-09-26 21:57:04 +000031namespace {
32 // Style of scheduling to use.
33 enum ScheduleChoices {
34 noScheduling,
35 simpleScheduling,
Jim Laskey7d090f32005-11-04 04:05:35 +000036 simpleNoItinScheduling
Jim Laskeye6b90fb2005-09-26 21:57:04 +000037 };
38} // namespace
39
40cl::opt<ScheduleChoices> ScheduleStyle("sched",
41 cl::desc("Choose scheduling style"),
42 cl::init(noScheduling),
43 cl::values(
44 clEnumValN(noScheduling, "none",
45 "Trivial emission with no analysis"),
46 clEnumValN(simpleScheduling, "simple",
47 "Minimize critical path and maximize processor utilization"),
Jim Laskey7d090f32005-11-04 04:05:35 +000048 clEnumValN(simpleNoItinScheduling, "simple-noitin",
49 "Same as simple except using generic latency"),
Jim Laskeye6b90fb2005-09-26 21:57:04 +000050 clEnumValEnd));
51
52
Chris Lattnerda8abb02005-09-01 18:44:10 +000053#ifndef NDEBUG
Chris Lattner068ca152005-08-18 20:11:49 +000054static cl::opt<bool>
55ViewDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
57#else
Chris Lattnera639a432005-09-02 07:09:28 +000058static const bool ViewDAGs = 0;
Chris Lattner068ca152005-08-18 20:11:49 +000059#endif
60
Chris Lattner2d973e42005-08-18 20:07:59 +000061namespace {
Jim Laskeye6b90fb2005-09-26 21:57:04 +000062//===----------------------------------------------------------------------===//
63///
64/// BitsIterator - Provides iteration through individual bits in a bit vector.
65///
66template<class T>
67class BitsIterator {
68private:
69 T Bits; // Bits left to iterate through
70
71public:
72 /// Ctor.
73 BitsIterator(T Initial) : Bits(Initial) {}
74
75 /// Next - Returns the next bit set or zero if exhausted.
76 inline T Next() {
77 // Get the rightmost bit set
78 T Result = Bits & -Bits;
79 // Remove from rest
80 Bits &= ~Result;
81 // Return single bit or zero
82 return Result;
83 }
84};
85
86//===----------------------------------------------------------------------===//
87
88
89//===----------------------------------------------------------------------===//
90///
91/// ResourceTally - Manages the use of resources over time intervals. Each
92/// item (slot) in the tally vector represents the resources used at a given
93/// moment. A bit set to 1 indicates that a resource is in use, otherwise
94/// available. An assumption is made that the tally is large enough to schedule
95/// all current instructions (asserts otherwise.)
96///
97template<class T>
98class ResourceTally {
99private:
100 std::vector<T> Tally; // Resources used per slot
101 typedef typename std::vector<T>::iterator Iter;
102 // Tally iterator
103
Jim Laskeya5e5bff2005-11-05 00:01:25 +0000104 /// SlotsAvailable - Returns true if all units are available.
105 ///
106 bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
Jim Laskey7d090f32005-11-04 04:05:35 +0000107 unsigned &Resource) {
108 assert(N && "Must check availability with N != 0");
109 // Determine end of interval
110 Iter End = Begin + N;
Jim Laskey7d090f32005-11-04 04:05:35 +0000111 assert(End <= Tally.end() && "Tally is not large enough for schedule");
112
113 // Iterate thru each resource
114 BitsIterator<T> Resources(ResourceSet & ~*Begin);
115 while (unsigned Res = Resources.Next()) {
116 // Check if resource is available for next N slots
117 Iter Interval = End;
118 do {
119 Interval--;
120 if (*Interval & Res) break;
121 } while (Interval != Begin);
122
123 // If available for N
124 if (Interval == Begin) {
125 // Success
126 Resource = Res;
Jim Laskeya5e5bff2005-11-05 00:01:25 +0000127 return true;
Jim Laskey7d090f32005-11-04 04:05:35 +0000128 }
Jim Laskey7d090f32005-11-04 04:05:35 +0000129 }
130
131 // No luck
Jim Laskey54f997d2005-11-04 18:26:02 +0000132 Resource = 0;
Jim Laskeya5e5bff2005-11-05 00:01:25 +0000133 return false;
Jim Laskey7d090f32005-11-04 04:05:35 +0000134 }
Jim Laskeya5e5bff2005-11-05 00:01:25 +0000135
136 /// RetrySlot - Finds a good candidate slot to retry search.
137 Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
138 assert(N && "Must check availability with N != 0");
139 // Determine end of interval
140 Iter End = Begin + N;
141 assert(End <= Tally.end() && "Tally is not large enough for schedule");
142
143 while (Begin != End--) {
144 // Clear units in use
145 ResourceSet &= ~*End;
146 // If no units left then we should go no further
147 if (!ResourceSet) return End + 1;
148 }
149 // Made it all the way through
150 return Begin;
151 }
Jim Laskey7d090f32005-11-04 04:05:35 +0000152
153 /// FindAndReserveStages - Return true if the stages can be completed. If
154 /// so mark as busy.
155 bool FindAndReserveStages(Iter Begin,
156 InstrStage *Stage, InstrStage *StageEnd) {
157 // If at last stage then we're done
158 if (Stage == StageEnd) return true;
159 // Get number of cycles for current stage
160 unsigned N = Stage->Cycles;
161 // Check to see if N slots are available, if not fail
162 unsigned Resource;
Jim Laskeya5e5bff2005-11-05 00:01:25 +0000163 if (!SlotsAvailable(Begin, N, Stage->Units, Resource)) return false;
Jim Laskey7d090f32005-11-04 04:05:35 +0000164 // Check to see if remaining stages are available, if not fail
165 if (!FindAndReserveStages(Begin + N, Stage + 1, StageEnd)) return false;
166 // Reserve resource
167 Reserve(Begin, N, Resource);
168 // Success
169 return true;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000170 }
171
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000172 /// Reserve - Mark busy (set) the specified N slots.
173 void Reserve(Iter Begin, unsigned N, unsigned Resource) {
174 // Determine end of interval
175 Iter End = Begin + N;
176 assert(End <= Tally.end() && "Tally is not large enough for schedule");
177
178 // Set resource bit in each slot
179 for (; Begin < End; Begin++)
180 *Begin |= Resource;
181 }
182
Jim Laskey7d090f32005-11-04 04:05:35 +0000183 /// FindSlots - Starting from Begin, locate consecutive slots where all stages
184 /// can be completed. Returns the address of first slot.
185 Iter FindSlots(Iter Begin, InstrStage *StageBegin, InstrStage *StageEnd) {
186 // Track position
187 Iter Cursor = Begin;
188
189 // Try all possible slots forward
190 while (true) {
191 // Try at cursor, if successful return position.
192 if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor;
193 // Locate a better position
Jim Laskeya5e5bff2005-11-05 00:01:25 +0000194 Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units);
Jim Laskey7d090f32005-11-04 04:05:35 +0000195 }
196 }
197
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000198public:
199 /// Initialize - Resize and zero the tally to the specified number of time
200 /// slots.
201 inline void Initialize(unsigned N) {
202 Tally.assign(N, 0); // Initialize tally to all zeros.
203 }
Jim Laskey7d090f32005-11-04 04:05:35 +0000204
205 // FindAndReserve - Locate an ideal slot for the specified stages and mark
206 // as busy.
207 unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
208 InstrStage *StageEnd) {
Jim Laskeya5e5bff2005-11-05 00:01:25 +0000209 // Where to begin
210 Iter Begin = Tally.begin() + Slot;
211 // Find a free slot
212 Iter Where = FindSlots(Begin, StageBegin, StageEnd);
213 // Distance is slot number
214 unsigned Final = Where - Tally.begin();
215 return Final;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000216 }
217
218};
219//===----------------------------------------------------------------------===//
220
Jim Laskeyfab66f62005-10-12 18:29:35 +0000221// Forward
222class NodeInfo;
Jim Laskey5a608dd2005-10-31 12:49:09 +0000223typedef NodeInfo *NodeInfoPtr;
224typedef std::vector<NodeInfoPtr> NIVector;
225typedef std::vector<NodeInfoPtr>::iterator NIIterator;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000226
227//===----------------------------------------------------------------------===//
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000228///
229/// Node group - This struct is used to manage flagged node groups.
230///
Jim Laskey5a608dd2005-10-31 12:49:09 +0000231class NodeGroup {
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000232private:
Jim Laskey5a608dd2005-10-31 12:49:09 +0000233 NIVector Members; // Group member nodes
Jim Laskey7d090f32005-11-04 04:05:35 +0000234 NodeInfo *Dominator; // Node with highest latency
235 unsigned Latency; // Total latency of the group
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000236 int Pending; // Number of visits pending before
237 // adding to order
238
239public:
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000240 // Ctor.
Jim Laskey7d090f32005-11-04 04:05:35 +0000241 NodeGroup() : Dominator(NULL), Pending(0) {}
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000242
243 // Accessors
Jim Laskey7d090f32005-11-04 04:05:35 +0000244 inline void setDominator(NodeInfo *D) { Dominator = D; }
245 inline NodeInfo *getDominator() { return Dominator; }
246 inline void setLatency(unsigned L) { Latency = L; }
247 inline unsigned getLatency() { return Latency; }
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000248 inline int getPending() const { return Pending; }
249 inline void setPending(int P) { Pending = P; }
250 inline int addPending(int I) { return Pending += I; }
Jim Laskey5a608dd2005-10-31 12:49:09 +0000251
252 // Pass thru
253 inline bool group_empty() { return Members.empty(); }
254 inline NIIterator group_begin() { return Members.begin(); }
255 inline NIIterator group_end() { return Members.end(); }
256 inline void group_push_back(const NodeInfoPtr &NI) { Members.push_back(NI); }
257 inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr &NI) {
258 return Members.insert(Pos, NI);
259 }
260 inline void group_insert(NIIterator Pos, NIIterator First, NIIterator Last) {
261 Members.insert(Pos, First, Last);
262 }
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000263
264 static void Add(NodeInfo *D, NodeInfo *U);
265 static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U);
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000266};
267//===----------------------------------------------------------------------===//
268
269
270//===----------------------------------------------------------------------===//
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000271///
272/// NodeInfo - This struct tracks information used to schedule the a node.
273///
274class NodeInfo {
275private:
276 int Pending; // Number of visits pending before
277 // adding to order
278public:
279 SDNode *Node; // DAG node
Jim Laskey7d090f32005-11-04 04:05:35 +0000280 InstrStage *StageBegin; // First stage in itinerary
281 InstrStage *StageEnd; // Last+1 stage in itinerary
282 unsigned Latency; // Total cycles to complete instruction
Jim Laskey53c523c2005-10-13 16:44:00 +0000283 bool IsCall; // Is function call
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000284 unsigned Slot; // Node's time slot
285 NodeGroup *Group; // Grouping information
286 unsigned VRBase; // Virtual register base
Jim Laskeyfab66f62005-10-12 18:29:35 +0000287#ifndef NDEBUG
288 unsigned Preorder; // Index before scheduling
289#endif
290
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000291 // Ctor.
292 NodeInfo(SDNode *N = NULL)
293 : Pending(0)
294 , Node(N)
Jim Laskey7d090f32005-11-04 04:05:35 +0000295 , StageBegin(NULL)
296 , StageEnd(NULL)
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000297 , Latency(0)
Jim Laskey53c523c2005-10-13 16:44:00 +0000298 , IsCall(false)
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000299 , Slot(0)
300 , Group(NULL)
301 , VRBase(0)
Jim Laskey53c523c2005-10-13 16:44:00 +0000302#ifndef NDEBUG
303 , Preorder(0)
304#endif
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000305 {}
306
307 // Accessors
308 inline bool isInGroup() const {
Jim Laskey5a608dd2005-10-31 12:49:09 +0000309 assert(!Group || !Group->group_empty() && "Group with no members");
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000310 return Group != NULL;
311 }
Jim Laskey7d090f32005-11-04 04:05:35 +0000312 inline bool isGroupDominator() const {
313 return isInGroup() && Group->getDominator() == this;
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000314 }
315 inline int getPending() const {
316 return Group ? Group->getPending() : Pending;
317 }
318 inline void setPending(int P) {
319 if (Group) Group->setPending(P);
320 else Pending = P;
321 }
322 inline int addPending(int I) {
323 if (Group) return Group->addPending(I);
324 else return Pending += I;
325 }
326};
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000327//===----------------------------------------------------------------------===//
328
329
330//===----------------------------------------------------------------------===//
331///
332/// NodeGroupIterator - Iterates over all the nodes indicated by the node info.
333/// If the node is in a group then iterate over the members of the group,
334/// otherwise just the node info.
335///
336class NodeGroupIterator {
337private:
338 NodeInfo *NI; // Node info
339 NIIterator NGI; // Node group iterator
340 NIIterator NGE; // Node group iterator end
341
342public:
343 // Ctor.
344 NodeGroupIterator(NodeInfo *N) : NI(N) {
345 // If the node is in a group then set up the group iterator. Otherwise
346 // the group iterators will trip first time out.
347 if (N->isInGroup()) {
348 // get Group
349 NodeGroup *Group = NI->Group;
Jim Laskey5a608dd2005-10-31 12:49:09 +0000350 NGI = Group->group_begin();
351 NGE = Group->group_end();
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000352 // Prevent this node from being used (will be in members list
353 NI = NULL;
354 }
355 }
356
357 /// next - Return the next node info, otherwise NULL.
358 ///
359 NodeInfo *next() {
360 // If members list
361 if (NGI != NGE) return *NGI++;
362 // Use node as the result (may be NULL)
363 NodeInfo *Result = NI;
364 // Only use once
365 NI = NULL;
366 // Return node or NULL
367 return Result;
368 }
369};
370//===----------------------------------------------------------------------===//
371
372
373//===----------------------------------------------------------------------===//
374///
375/// NodeGroupOpIterator - Iterates over all the operands of a node. If the node
376/// is a member of a group, this iterates over all the operands of all the
377/// members of the group.
378///
379class NodeGroupOpIterator {
380private:
381 NodeInfo *NI; // Node containing operands
382 NodeGroupIterator GI; // Node group iterator
383 SDNode::op_iterator OI; // Operand iterator
384 SDNode::op_iterator OE; // Operand iterator end
385
386 /// CheckNode - Test if node has more operands. If not get the next node
387 /// skipping over nodes that have no operands.
388 void CheckNode() {
389 // Only if operands are exhausted first
390 while (OI == OE) {
391 // Get next node info
392 NodeInfo *NI = GI.next();
393 // Exit if nodes are exhausted
394 if (!NI) return;
395 // Get node itself
396 SDNode *Node = NI->Node;
397 // Set up the operand iterators
398 OI = Node->op_begin();
399 OE = Node->op_end();
400 }
401 }
402
403public:
404 // Ctor.
Chris Lattner4012eb22005-11-08 21:54:57 +0000405 NodeGroupOpIterator(NodeInfo *N)
406 : NI(N), GI(N), OI(SDNode::op_iterator()), OE(SDNode::op_iterator()) {}
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000407
408 /// isEnd - Returns true when not more operands are available.
409 ///
410 inline bool isEnd() { CheckNode(); return OI == OE; }
411
412 /// next - Returns the next available operand.
413 ///
414 inline SDOperand next() {
415 assert(OI != OE && "Not checking for end of NodeGroupOpIterator correctly");
416 return *OI++;
417 }
418};
419//===----------------------------------------------------------------------===//
420
421
422//===----------------------------------------------------------------------===//
423///
424/// SimpleSched - Simple two pass scheduler.
425///
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000426class SimpleSched {
427private:
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000428 MachineBasicBlock *BB; // Current basic block
429 SelectionDAG &DAG; // DAG of the current basic block
430 const TargetMachine &TM; // Target processor
431 const TargetInstrInfo &TII; // Target instruction information
432 const MRegisterInfo &MRI; // Target processor register information
433 SSARegMap *RegMap; // Virtual/real register map
434 MachineConstantPool *ConstPool; // Target constant pool
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000435 unsigned NodeCount; // Number of nodes in DAG
Jim Laskey7d090f32005-11-04 04:05:35 +0000436 bool HasGroups; // True if there are any groups
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000437 NodeInfo *Info; // Info for nodes being scheduled
438 std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
Jim Laskeyfab66f62005-10-12 18:29:35 +0000439 NIVector Ordering; // Emit ordering of nodes
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000440 ResourceTally<unsigned> Tally; // Resource usage tally
441 unsigned NSlots; // Total latency
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000442 static const unsigned NotFound = ~0U; // Search marker
443
444public:
445
446 // Ctor.
447 SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
448 : BB(bb), DAG(D), TM(D.getTarget()), TII(*TM.getInstrInfo()),
449 MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()),
450 ConstPool(BB->getParent()->getConstantPool()),
Jim Laskey7d090f32005-11-04 04:05:35 +0000451 NodeCount(0), HasGroups(false), Info(NULL), Map(), Tally(), NSlots(0) {
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000452 assert(&TII && "Target doesn't provide instr info?");
453 assert(&MRI && "Target doesn't provide register info?");
454 }
455
456 // Run - perform scheduling.
457 MachineBasicBlock *Run() {
458 Schedule();
459 return BB;
460 }
461
462private:
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000463 /// getNI - Returns the node info for the specified node.
464 ///
465 inline NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
466
467 /// getVR - Returns the virtual register number of the node.
468 ///
469 inline unsigned getVR(SDOperand Op) {
470 NodeInfo *NI = getNI(Op.Val);
471 assert(NI->VRBase != 0 && "Node emitted out of order - late");
472 return NI->VRBase + Op.ResNo;
473 }
474
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000475 static bool isFlagDefiner(SDNode *A);
476 static bool isFlagUser(SDNode *A);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000477 static bool isDefiner(NodeInfo *A, NodeInfo *B);
478 static bool isPassiveNode(SDNode *Node);
479 void IncludeNode(NodeInfo *NI);
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000480 void VisitAll();
481 void Schedule();
Jim Laskeyfab66f62005-10-12 18:29:35 +0000482 void IdentifyGroups();
483 void GatherSchedulingInfo();
Jim Laskey7d090f32005-11-04 04:05:35 +0000484 void FakeGroupDominators();
Jim Laskeyfab66f62005-10-12 18:29:35 +0000485 void PrepareNodeInfo();
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000486 bool isStrongDependency(NodeInfo *A, NodeInfo *B);
487 bool isWeakDependency(NodeInfo *A, NodeInfo *B);
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000488 void ScheduleBackward();
489 void ScheduleForward();
490 void EmitAll();
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000491 void EmitNode(NodeInfo *NI);
492 static unsigned CountResults(SDNode *Node);
493 static unsigned CountOperands(SDNode *Node);
494 unsigned CreateVirtualRegisters(MachineInstr *MI,
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000495 unsigned NumResults,
496 const TargetInstrDescriptor &II);
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000497
Jim Laskeyfab66f62005-10-12 18:29:35 +0000498 void printChanges(unsigned Index);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000499 void printSI(std::ostream &O, NodeInfo *NI) const;
500 void print(std::ostream &O) const;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000501 inline void dump(const char *tag) const { std::cerr << tag; dump(); }
502 void dump() const;
503};
Jim Laskey7d090f32005-11-04 04:05:35 +0000504
505
506//===----------------------------------------------------------------------===//
507/// Special case itineraries.
508///
509enum {
510 CallLatency = 40, // To push calls back in time
511
512 RSInteger = 0xC0000000, // Two integer units
513 RSFloat = 0x30000000, // Two float units
514 RSLoadStore = 0x0C000000, // Two load store units
515 RSBranch = 0x02000000 // One branch unit
516};
517static InstrStage CallStage = { CallLatency, RSBranch };
518static InstrStage LoadStage = { 5, RSLoadStore };
519static InstrStage StoreStage = { 2, RSLoadStore };
520static InstrStage IntStage = { 2, RSInteger };
521static InstrStage FloatStage = { 3, RSFloat };
522//===----------------------------------------------------------------------===//
523
524
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000525//===----------------------------------------------------------------------===//
526
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000527} // namespace
Jim Laskey41755e22005-10-01 00:03:07 +0000528
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000529//===----------------------------------------------------------------------===//
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000530
531
532//===----------------------------------------------------------------------===//
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000533/// Add - Adds a definer and user pair to a node group.
534///
535void NodeGroup::Add(NodeInfo *D, NodeInfo *U) {
536 // Get current groups
537 NodeGroup *DGroup = D->Group;
538 NodeGroup *UGroup = U->Group;
539 // If both are members of groups
540 if (DGroup && UGroup) {
541 // There may have been another edge connecting
542 if (DGroup == UGroup) return;
543 // Add the pending users count
544 DGroup->addPending(UGroup->getPending());
545 // For each member of the users group
546 NodeGroupIterator UNGI(U);
547 while (NodeInfo *UNI = UNGI.next() ) {
548 // Change the group
549 UNI->Group = DGroup;
550 // For each member of the definers group
551 NodeGroupIterator DNGI(D);
552 while (NodeInfo *DNI = DNGI.next() ) {
553 // Remove internal edges
554 DGroup->addPending(-CountInternalUses(DNI, UNI));
555 }
556 }
557 // Merge the two lists
Jim Laskey5a608dd2005-10-31 12:49:09 +0000558 DGroup->group_insert(DGroup->group_end(),
559 UGroup->group_begin(), UGroup->group_end());
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000560 } else if (DGroup) {
561 // Make user member of definers group
562 U->Group = DGroup;
563 // Add users uses to definers group pending
564 DGroup->addPending(U->Node->use_size());
565 // For each member of the definers group
566 NodeGroupIterator DNGI(D);
567 while (NodeInfo *DNI = DNGI.next() ) {
568 // Remove internal edges
569 DGroup->addPending(-CountInternalUses(DNI, U));
570 }
Jim Laskey5a608dd2005-10-31 12:49:09 +0000571 DGroup->group_push_back(U);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000572 } else if (UGroup) {
573 // Make definer member of users group
574 D->Group = UGroup;
575 // Add definers uses to users group pending
576 UGroup->addPending(D->Node->use_size());
577 // For each member of the users group
578 NodeGroupIterator UNGI(U);
579 while (NodeInfo *UNI = UNGI.next() ) {
580 // Remove internal edges
581 UGroup->addPending(-CountInternalUses(D, UNI));
582 }
Jim Laskey5a608dd2005-10-31 12:49:09 +0000583 UGroup->group_insert(UGroup->group_begin(), D);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000584 } else {
585 D->Group = U->Group = DGroup = new NodeGroup();
586 DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
587 CountInternalUses(D, U));
Jim Laskey5a608dd2005-10-31 12:49:09 +0000588 DGroup->group_push_back(D);
589 DGroup->group_push_back(U);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000590 }
591}
592
593/// CountInternalUses - Returns the number of edges between the two nodes.
594///
595unsigned NodeGroup::CountInternalUses(NodeInfo *D, NodeInfo *U) {
596 unsigned N = 0;
Jim Laskey5a608dd2005-10-31 12:49:09 +0000597 for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
598 SDOperand Op = U->Node->getOperand(M);
599 if (Op.Val == D->Node) N++;
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000600 }
Jim Laskey5a608dd2005-10-31 12:49:09 +0000601
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000602 return N;
603}
604//===----------------------------------------------------------------------===//
605
606
607//===----------------------------------------------------------------------===//
608/// isFlagDefiner - Returns true if the node defines a flag result.
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000609bool SimpleSched::isFlagDefiner(SDNode *A) {
610 unsigned N = A->getNumValues();
611 return N && A->getValueType(N - 1) == MVT::Flag;
Chris Lattner2d973e42005-08-18 20:07:59 +0000612}
613
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000614/// isFlagUser - Returns true if the node uses a flag result.
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000615///
616bool SimpleSched::isFlagUser(SDNode *A) {
617 unsigned N = A->getNumOperands();
618 return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
619}
620
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000621/// isDefiner - Return true if node A is a definer for B.
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000622///
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000623bool SimpleSched::isDefiner(NodeInfo *A, NodeInfo *B) {
624 // While there are A nodes
625 NodeGroupIterator NII(A);
626 while (NodeInfo *NI = NII.next()) {
627 // Extract node
628 SDNode *Node = NI->Node;
629 // While there operands in nodes of B
630 NodeGroupOpIterator NGOI(B);
631 while (!NGOI.isEnd()) {
632 SDOperand Op = NGOI.next();
633 // If node from A defines a node in B
634 if (Node == Op.Val) return true;
635 }
Chris Lattner2d973e42005-08-18 20:07:59 +0000636 }
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000637 return false;
638}
639
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000640/// isPassiveNode - Return true if the node is a non-scheduled leaf.
641///
642bool SimpleSched::isPassiveNode(SDNode *Node) {
643 if (isa<ConstantSDNode>(Node)) return true;
644 if (isa<RegisterSDNode>(Node)) return true;
645 if (isa<GlobalAddressSDNode>(Node)) return true;
646 if (isa<BasicBlockSDNode>(Node)) return true;
647 if (isa<FrameIndexSDNode>(Node)) return true;
648 if (isa<ConstantPoolSDNode>(Node)) return true;
649 if (isa<ExternalSymbolSDNode>(Node)) return true;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000650 return false;
651}
652
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000653/// IncludeNode - Add node to NodeInfo vector.
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000654///
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000655void SimpleSched::IncludeNode(NodeInfo *NI) {
Jim Laskey9022ed92005-12-18 03:59:21 +0000656 // Get node
657 SDNode *Node = NI->Node;
658 // Ignore entry node
659 if (Node->getOpcode() == ISD::EntryToken) return;
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000660 // Check current count for node
661 int Count = NI->getPending();
662 // If the node is already in list
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000663 if (Count < 0) return;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000664 // Decrement count to indicate a visit
665 Count--;
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000666 // If count has gone to zero then add node to list
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000667 if (!Count) {
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000668 // Add node
669 if (NI->isInGroup()) {
Jim Laskey7d090f32005-11-04 04:05:35 +0000670 Ordering.push_back(NI->Group->getDominator());
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000671 } else {
672 Ordering.push_back(NI);
673 }
674 // indicate node has been added
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000675 Count--;
676 }
677 // Mark as visited with new count
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000678 NI->setPending(Count);
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000679}
680
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000681/// VisitAll - Visit each node breadth-wise to produce an initial ordering.
682/// Note that the ordering in the Nodes vector is reversed.
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000683void SimpleSched::VisitAll() {
684 // Add first element to list
Jim Laskeybd2b6212005-12-18 04:40:52 +0000685 NodeInfo *NI = getNI(DAG.getRoot().Val);
686 if (NI->isInGroup()) {
687 Ordering.push_back(NI->Group->getDominator());
688 } else {
689 Ordering.push_back(NI);
690 }
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000691
692 // Iterate through all nodes that have been added
693 for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
694 // Visit all operands
695 NodeGroupOpIterator NGI(Ordering[i]);
696 while (!NGI.isEnd()) {
697 // Get next operand
698 SDOperand Op = NGI.next();
699 // Get node
700 SDNode *Node = Op.Val;
701 // Ignore passive nodes
702 if (isPassiveNode(Node)) continue;
703 // Check out node
704 IncludeNode(getNI(Node));
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000705 }
706 }
707
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000708 // Add entry node last (IncludeNode filters entry nodes)
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000709 if (DAG.getEntryNode().Val != DAG.getRoot().Val)
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000710 Ordering.push_back(getNI(DAG.getEntryNode().Val));
711
Chris Lattnera5282d82005-12-18 01:03:46 +0000712 // Reverse the order
713 std::reverse(Ordering.begin(), Ordering.end());
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000714}
715
Jim Laskeyfab66f62005-10-12 18:29:35 +0000716/// IdentifyGroups - Put flagged nodes into groups.
717///
718void SimpleSched::IdentifyGroups() {
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000719 for (unsigned i = 0, N = NodeCount; i < N; i++) {
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000720 NodeInfo* NI = &Info[i];
Jim Laskeyfab66f62005-10-12 18:29:35 +0000721 SDNode *Node = NI->Node;
722
723 // For each operand (in reverse to only look at flags)
724 for (unsigned N = Node->getNumOperands(); 0 < N--;) {
725 // Get operand
726 SDOperand Op = Node->getOperand(N);
727 // No more flags to walk
728 if (Op.getValueType() != MVT::Flag) break;
729 // Add to node group
730 NodeGroup::Add(getNI(Op.Val), NI);
Jim Laskey7d090f32005-11-04 04:05:35 +0000731 // Let evryone else know
732 HasGroups = true;
Jim Laskeyfab66f62005-10-12 18:29:35 +0000733 }
734 }
735}
736
737/// GatherSchedulingInfo - Get latency and resource information about each node.
738///
739void SimpleSched::GatherSchedulingInfo() {
Jim Laskeya5e5bff2005-11-05 00:01:25 +0000740 // Get instruction itineraries for the target
Jim Laskey7d090f32005-11-04 04:05:35 +0000741 const InstrItineraryData InstrItins = TM.getInstrItineraryData();
Jim Laskey53c523c2005-10-13 16:44:00 +0000742
743 // For each node
Jim Laskeyfab66f62005-10-12 18:29:35 +0000744 for (unsigned i = 0, N = NodeCount; i < N; i++) {
Jim Laskey53c523c2005-10-13 16:44:00 +0000745 // Get node info
Jim Laskeyfab66f62005-10-12 18:29:35 +0000746 NodeInfo* NI = &Info[i];
747 SDNode *Node = NI->Node;
Jim Laskey53c523c2005-10-13 16:44:00 +0000748
Jim Laskey7d090f32005-11-04 04:05:35 +0000749 // If there are itineraries and it is a machine instruction
750 if (InstrItins.isEmpty() || ScheduleStyle == simpleNoItinScheduling) {
751 // If machine opcode
752 if (Node->isTargetOpcode()) {
753 // Get return type to guess which processing unit
754 MVT::ValueType VT = Node->getValueType(0);
755 // Get machine opcode
756 MachineOpCode TOpc = Node->getTargetOpcode();
757 NI->IsCall = TII.isCall(TOpc);
Jim Laskeyfab66f62005-10-12 18:29:35 +0000758
Jim Laskey7d090f32005-11-04 04:05:35 +0000759 if (TII.isLoad(TOpc)) NI->StageBegin = &LoadStage;
760 else if (TII.isStore(TOpc)) NI->StageBegin = &StoreStage;
761 else if (MVT::isInteger(VT)) NI->StageBegin = &IntStage;
762 else if (MVT::isFloatingPoint(VT)) NI->StageBegin = &FloatStage;
763 if (NI->StageBegin) NI->StageEnd = NI->StageBegin + 1;
764 }
765 } else if (Node->isTargetOpcode()) {
766 // get machine opcode
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000767 MachineOpCode TOpc = Node->getTargetOpcode();
Jim Laskey7d090f32005-11-04 04:05:35 +0000768 // Check to see if it is a call
769 NI->IsCall = TII.isCall(TOpc);
770 // Get itinerary stages for instruction
771 unsigned II = TII.getSchedClass(TOpc);
772 NI->StageBegin = InstrItins.begin(II);
773 NI->StageEnd = InstrItins.end(II);
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000774 }
775
Jim Laskey7d090f32005-11-04 04:05:35 +0000776 // One slot for the instruction itself
777 NI->Latency = 1;
778
779 // Add long latency for a call to push it back in time
780 if (NI->IsCall) NI->Latency += CallLatency;
781
782 // Sum up all the latencies
783 for (InstrStage *Stage = NI->StageBegin, *E = NI->StageEnd;
784 Stage != E; Stage++) {
785 NI->Latency += Stage->Cycles;
786 }
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000787
788 // Sum up all the latencies for max tally size
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000789 NSlots += NI->Latency;
790 }
Jim Laskey53c523c2005-10-13 16:44:00 +0000791
792 // Unify metrics if in a group
Jim Laskey7d090f32005-11-04 04:05:35 +0000793 if (HasGroups) {
Jim Laskey53c523c2005-10-13 16:44:00 +0000794 for (unsigned i = 0, N = NodeCount; i < N; i++) {
795 NodeInfo* NI = &Info[i];
796
Jim Laskey7d090f32005-11-04 04:05:35 +0000797 if (NI->isInGroup()) {
Jim Laskey53c523c2005-10-13 16:44:00 +0000798 NodeGroup *Group = NI->Group;
Jim Laskey53c523c2005-10-13 16:44:00 +0000799
Jim Laskey7d090f32005-11-04 04:05:35 +0000800 if (!Group->getDominator()) {
801 NIIterator NGI = Group->group_begin(), NGE = Group->group_end();
802 NodeInfo *Dominator = *NGI;
Jim Laskeya5e5bff2005-11-05 00:01:25 +0000803 unsigned Latency = 0;
Jim Laskey53c523c2005-10-13 16:44:00 +0000804
Jim Laskey7d090f32005-11-04 04:05:35 +0000805 for (NGI++; NGI != NGE; NGI++) {
806 NodeInfo* NGNI = *NGI;
807 Latency += NGNI->Latency;
808 if (Dominator->Latency < NGNI->Latency) Dominator = NGNI;
Jim Laskey53c523c2005-10-13 16:44:00 +0000809 }
810
Jim Laskey7d090f32005-11-04 04:05:35 +0000811 Dominator->Latency = Latency;
812 Group->setDominator(Dominator);
Jim Laskey53c523c2005-10-13 16:44:00 +0000813 }
Jim Laskey7d090f32005-11-04 04:05:35 +0000814 }
815 }
816 }
817}
818
819/// FakeGroupDominators - Set dominators for non-scheduling.
820///
821void SimpleSched::FakeGroupDominators() {
822 for (unsigned i = 0, N = NodeCount; i < N; i++) {
823 NodeInfo* NI = &Info[i];
824
825 if (NI->isInGroup()) {
826 NodeGroup *Group = NI->Group;
827
828 if (!Group->getDominator()) {
829 Group->setDominator(NI);
Jim Laskey53c523c2005-10-13 16:44:00 +0000830 }
831 }
832 }
Jim Laskeyfab66f62005-10-12 18:29:35 +0000833}
Jim Laskey41755e22005-10-01 00:03:07 +0000834
Jim Laskeyfab66f62005-10-12 18:29:35 +0000835/// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
836///
837void SimpleSched::PrepareNodeInfo() {
838 // Allocate node information
839 Info = new NodeInfo[NodeCount];
Chris Lattnerde202b32005-11-09 23:47:37 +0000840
841 unsigned i = 0;
842 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
843 E = DAG.allnodes_end(); I != E; ++I, ++i) {
Jim Laskeyfab66f62005-10-12 18:29:35 +0000844 // Fast reference to node schedule info
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000845 NodeInfo* NI = &Info[i];
Jim Laskeyfab66f62005-10-12 18:29:35 +0000846 // Set up map
Chris Lattnerde202b32005-11-09 23:47:37 +0000847 Map[I] = NI;
Jim Laskeyfab66f62005-10-12 18:29:35 +0000848 // Set node
Chris Lattnerde202b32005-11-09 23:47:37 +0000849 NI->Node = I;
Jim Laskeyfab66f62005-10-12 18:29:35 +0000850 // Set pending visit count
Chris Lattnerde202b32005-11-09 23:47:37 +0000851 NI->setPending(I->use_size());
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000852 }
853}
854
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000855/// isStrongDependency - Return true if node A has results used by node B.
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000856/// I.E., B must wait for latency of A.
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000857bool SimpleSched::isStrongDependency(NodeInfo *A, NodeInfo *B) {
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000858 // If A defines for B then it's a strong dependency
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000859 return isDefiner(A, B);
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000860}
861
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000862/// isWeakDependency Return true if node A produces a result that will
Jim Laskey5a608dd2005-10-31 12:49:09 +0000863/// conflict with operands of B. It is assumed that we have called
864/// isStrongDependency prior.
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000865bool SimpleSched::isWeakDependency(NodeInfo *A, NodeInfo *B) {
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000866 // TODO check for conflicting real registers and aliases
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000867#if 0 // FIXME - Since we are in SSA form and not checking register aliasing
868 return A->Node->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
Jim Laskey5324fec2005-09-27 17:32:45 +0000869#else
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000870 return A->Node->getOpcode() == ISD::EntryToken;
Jim Laskey5324fec2005-09-27 17:32:45 +0000871#endif
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000872}
873
874/// ScheduleBackward - Schedule instructions so that any long latency
875/// instructions and the critical path get pushed back in time. Time is run in
876/// reverse to allow code reuse of the Tally and eliminate the overhead of
877/// biasing every slot indices against NSlots.
878void SimpleSched::ScheduleBackward() {
879 // Size and clear the resource tally
880 Tally.Initialize(NSlots);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000881 // Get number of nodes to schedule
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000882 unsigned N = Ordering.size();
883
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000884 // For each node being scheduled
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000885 for (unsigned i = N; 0 < i--;) {
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000886 NodeInfo *NI = Ordering[i];
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000887 // Track insertion
888 unsigned Slot = NotFound;
889
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000890 // Compare against those previously scheduled nodes
Jeff Cohenfef80f42005-09-29 01:59:49 +0000891 unsigned j = i + 1;
892 for (; j < N; j++) {
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000893 // Get following instruction
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000894 NodeInfo *Other = Ordering[j];
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000895
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000896 // Check dependency against previously inserted nodes
897 if (isStrongDependency(NI, Other)) {
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000898 Slot = Other->Slot + Other->Latency;
899 break;
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000900 } else if (isWeakDependency(NI, Other)) {
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000901 Slot = Other->Slot;
902 break;
903 }
904 }
905
906 // If independent of others (or first entry)
907 if (Slot == NotFound) Slot = 0;
908
Jim Laskey26b91eb2005-11-07 19:08:53 +0000909#if 0 // FIXME - measure later
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000910 // Find a slot where the needed resources are available
Jim Laskey7d090f32005-11-04 04:05:35 +0000911 if (NI->StageBegin != NI->StageEnd)
912 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
Jim Laskey26b91eb2005-11-07 19:08:53 +0000913#endif
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000914
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000915 // Set node slot
916 NI->Slot = Slot;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000917
918 // Insert sort based on slot
Jeff Cohenfef80f42005-09-29 01:59:49 +0000919 j = i + 1;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000920 for (; j < N; j++) {
921 // Get following instruction
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000922 NodeInfo *Other = Ordering[j];
Jim Laskeyfab66f62005-10-12 18:29:35 +0000923 // Should we look further (remember slots are in reverse time)
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000924 if (Slot >= Other->Slot) break;
925 // Shuffle other into ordering
926 Ordering[j - 1] = Other;
927 }
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000928 // Insert node in proper slot
929 if (j != i + 1) Ordering[j - 1] = NI;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000930 }
931}
932
933/// ScheduleForward - Schedule instructions to maximize packing.
934///
935void SimpleSched::ScheduleForward() {
936 // Size and clear the resource tally
937 Tally.Initialize(NSlots);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000938 // Get number of nodes to schedule
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000939 unsigned N = Ordering.size();
940
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000941 // For each node being scheduled
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000942 for (unsigned i = 0; i < N; i++) {
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000943 NodeInfo *NI = Ordering[i];
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000944 // Track insertion
945 unsigned Slot = NotFound;
946
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000947 // Compare against those previously scheduled nodes
Jeff Cohenfef80f42005-09-29 01:59:49 +0000948 unsigned j = i;
949 for (; 0 < j--;) {
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000950 // Get following instruction
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000951 NodeInfo *Other = Ordering[j];
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000952
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000953 // Check dependency against previously inserted nodes
954 if (isStrongDependency(Other, NI)) {
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000955 Slot = Other->Slot + Other->Latency;
956 break;
Jim Laskey53c523c2005-10-13 16:44:00 +0000957 } else if (Other->IsCall || isWeakDependency(Other, NI)) {
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000958 Slot = Other->Slot;
959 break;
960 }
961 }
962
963 // If independent of others (or first entry)
964 if (Slot == NotFound) Slot = 0;
965
966 // Find a slot where the needed resources are available
Jim Laskey7d090f32005-11-04 04:05:35 +0000967 if (NI->StageBegin != NI->StageEnd)
968 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000969
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000970 // Set node slot
971 NI->Slot = Slot;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000972
973 // Insert sort based on slot
Jeff Cohenfef80f42005-09-29 01:59:49 +0000974 j = i;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000975 for (; 0 < j--;) {
Jim Laskeyfab66f62005-10-12 18:29:35 +0000976 // Get prior instruction
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000977 NodeInfo *Other = Ordering[j];
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000978 // Should we look further
979 if (Slot >= Other->Slot) break;
980 // Shuffle other into ordering
981 Ordering[j + 1] = Other;
982 }
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000983 // Insert node in proper slot
984 if (j != i) Ordering[j + 1] = NI;
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000985 }
986}
987
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000988/// EmitAll - Emit all nodes in schedule sorted order.
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000989///
990void SimpleSched::EmitAll() {
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000991 // For each node in the ordering
Jim Laskeye6b90fb2005-09-26 21:57:04 +0000992 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
993 // Get the scheduling info
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000994 NodeInfo *NI = Ordering[i];
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000995 if (NI->isInGroup()) {
Jim Laskey9022ed92005-12-18 03:59:21 +0000996 NodeGroupIterator NGI(Ordering[i]);
997 while (NodeInfo *NI = NGI.next()) EmitNode(NI);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +0000998 } else {
999 EmitNode(NI);
1000 }
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001001 }
1002}
1003
1004/// CountResults - The results of target nodes have register or immediate
1005/// operands first, then an optional chain, and optional flag operands (which do
1006/// not go into the machine instrs.)
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001007unsigned SimpleSched::CountResults(SDNode *Node) {
1008 unsigned N = Node->getNumValues();
1009 while (N && Node->getValueType(N - 1) == MVT::Flag)
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001010 --N;
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001011 if (N && Node->getValueType(N - 1) == MVT::Other)
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001012 --N; // Skip over chain result.
1013 return N;
1014}
1015
1016/// CountOperands The inputs to target nodes have any actual inputs first,
1017/// followed by an optional chain operand, then flag operands. Compute the
1018/// number of actual operands that will go into the machine instr.
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001019unsigned SimpleSched::CountOperands(SDNode *Node) {
1020 unsigned N = Node->getNumOperands();
1021 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001022 --N;
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001023 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001024 --N; // Ignore chain if it exists.
1025 return N;
1026}
1027
1028/// CreateVirtualRegisters - Add result register values for things that are
1029/// defined by this instruction.
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001030unsigned SimpleSched::CreateVirtualRegisters(MachineInstr *MI,
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001031 unsigned NumResults,
1032 const TargetInstrDescriptor &II) {
1033 // Create the result registers for this node and add the result regs to
1034 // the machine instruction.
1035 const TargetOperandInfo *OpInfo = II.OpInfo;
1036 unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
1037 MI->addRegOperand(ResultReg, MachineOperand::Def);
1038 for (unsigned i = 1; i != NumResults; ++i) {
1039 assert(OpInfo[i].RegClass && "Isn't a register operand!");
Chris Lattner505277a2005-10-01 07:45:09 +00001040 MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001041 MachineOperand::Def);
1042 }
1043 return ResultReg;
1044}
1045
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001046/// EmitNode - Generate machine code for an node and needed dependencies.
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001047///
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001048void SimpleSched::EmitNode(NodeInfo *NI) {
1049 unsigned VRBase = 0; // First virtual register for node
1050 SDNode *Node = NI->Node;
Chris Lattner2d973e42005-08-18 20:07:59 +00001051
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001052 // If machine instruction
1053 if (Node->isTargetOpcode()) {
1054 unsigned Opc = Node->getTargetOpcode();
Chris Lattner2d973e42005-08-18 20:07:59 +00001055 const TargetInstrDescriptor &II = TII.get(Opc);
1056
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001057 unsigned NumResults = CountResults(Node);
1058 unsigned NodeOperands = CountOperands(Node);
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001059 unsigned NumMIOperands = NodeOperands + NumResults;
Chris Lattnerda8abb02005-09-01 18:44:10 +00001060#ifndef NDEBUG
Chris Lattner14b392a2005-08-24 22:02:41 +00001061 assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
Chris Lattner2d973e42005-08-18 20:07:59 +00001062 "#operands for dag node doesn't match .td file!");
Chris Lattnerca6aa2f2005-08-19 01:01:34 +00001063#endif
Chris Lattner2d973e42005-08-18 20:07:59 +00001064
1065 // Create the new machine instruction.
Chris Lattner14b392a2005-08-24 22:02:41 +00001066 MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
Chris Lattner2d973e42005-08-18 20:07:59 +00001067
1068 // Add result register values for things that are defined by this
1069 // instruction.
Chris Lattnera4176522005-10-30 18:54:27 +00001070
1071 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
1072 // the CopyToReg'd destination register instead of creating a new vreg.
1073 if (NumResults == 1) {
1074 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
1075 UI != E; ++UI) {
1076 SDNode *Use = *UI;
1077 if (Use->getOpcode() == ISD::CopyToReg &&
1078 Use->getOperand(2).Val == Node) {
1079 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
1080 if (MRegisterInfo::isVirtualRegister(Reg)) {
1081 VRBase = Reg;
1082 MI->addRegOperand(Reg, MachineOperand::Def);
1083 break;
1084 }
1085 }
1086 }
1087 }
1088
1089 // Otherwise, create new virtual registers.
1090 if (NumResults && VRBase == 0)
1091 VRBase = CreateVirtualRegisters(MI, NumResults, II);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001092
1093 // Emit all of the actual operands of this instruction, adding them to the
1094 // instruction as appropriate.
1095 for (unsigned i = 0; i != NodeOperands; ++i) {
1096 if (Node->getOperand(i).isTargetOpcode()) {
1097 // Note that this case is redundant with the final else block, but we
1098 // include it because it is the most common and it makes the logic
1099 // simpler here.
1100 assert(Node->getOperand(i).getValueType() != MVT::Other &&
1101 Node->getOperand(i).getValueType() != MVT::Flag &&
1102 "Chain and flag operands should occur at end of operand list!");
Chris Lattner505277a2005-10-01 07:45:09 +00001103
1104 // Get/emit the operand.
1105 unsigned VReg = getVR(Node->getOperand(i));
1106 MI->addRegOperand(VReg, MachineOperand::Use);
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001107
Chris Lattner505277a2005-10-01 07:45:09 +00001108 // Verify that it is right.
1109 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
1110 assert(II.OpInfo[i+NumResults].RegClass &&
1111 "Don't have operand info for this instruction!");
1112 assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
1113 "Register class of operand and regclass of use don't agree!");
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001114 } else if (ConstantSDNode *C =
1115 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1116 MI->addZeroExtImm64Operand(C->getValue());
1117 } else if (RegisterSDNode*R =
1118 dyn_cast<RegisterSDNode>(Node->getOperand(i))) {
1119 MI->addRegOperand(R->getReg(), MachineOperand::Use);
1120 } else if (GlobalAddressSDNode *TGA =
1121 dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
Evan Cheng61ca74b2005-11-30 02:04:11 +00001122 MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001123 } else if (BasicBlockSDNode *BB =
1124 dyn_cast<BasicBlockSDNode>(Node->getOperand(i))) {
1125 MI->addMachineBasicBlockOperand(BB->getBasicBlock());
1126 } else if (FrameIndexSDNode *FI =
1127 dyn_cast<FrameIndexSDNode>(Node->getOperand(i))) {
1128 MI->addFrameIndexOperand(FI->getIndex());
1129 } else if (ConstantPoolSDNode *CP =
1130 dyn_cast<ConstantPoolSDNode>(Node->getOperand(i))) {
1131 unsigned Idx = ConstPool->getConstantPoolIndex(CP->get());
1132 MI->addConstantPoolIndexOperand(Idx);
1133 } else if (ExternalSymbolSDNode *ES =
1134 dyn_cast<ExternalSymbolSDNode>(Node->getOperand(i))) {
1135 MI->addExternalSymbolOperand(ES->getSymbol(), false);
1136 } else {
1137 assert(Node->getOperand(i).getValueType() != MVT::Other &&
1138 Node->getOperand(i).getValueType() != MVT::Flag &&
1139 "Chain and flag operands should occur at end of operand list!");
Chris Lattner505277a2005-10-01 07:45:09 +00001140 unsigned VReg = getVR(Node->getOperand(i));
1141 MI->addRegOperand(VReg, MachineOperand::Use);
1142
1143 // Verify that it is right.
1144 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
1145 assert(II.OpInfo[i+NumResults].RegClass &&
1146 "Don't have operand info for this instruction!");
1147 assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
1148 "Register class of operand and regclass of use don't agree!");
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001149 }
1150 }
1151
1152 // Now that we have emitted all operands, emit this instruction itself.
1153 if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
1154 BB->insert(BB->end(), MI);
1155 } else {
1156 // Insert this instruction into the end of the basic block, potentially
1157 // taking some custom action.
1158 BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
1159 }
1160 } else {
1161 switch (Node->getOpcode()) {
1162 default:
1163 Node->dump();
1164 assert(0 && "This target-independent node should have been selected!");
1165 case ISD::EntryToken: // fall thru
1166 case ISD::TokenFactor:
1167 break;
1168 case ISD::CopyToReg: {
Chris Lattnera4176522005-10-30 18:54:27 +00001169 unsigned InReg = getVR(Node->getOperand(2));
1170 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1171 if (InReg != DestReg) // Coallesced away the copy?
1172 MRI.copyRegToReg(*BB, BB->end(), DestReg, InReg,
1173 RegMap->getRegClass(InReg));
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001174 break;
1175 }
1176 case ISD::CopyFromReg: {
1177 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
Chris Lattner089c25c2005-10-09 05:58:56 +00001178 if (MRegisterInfo::isVirtualRegister(SrcReg)) {
1179 VRBase = SrcReg; // Just use the input register directly!
1180 break;
1181 }
1182
Chris Lattnera4176522005-10-30 18:54:27 +00001183 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
1184 // the CopyToReg'd destination register instead of creating a new vreg.
1185 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
1186 UI != E; ++UI) {
1187 SDNode *Use = *UI;
1188 if (Use->getOpcode() == ISD::CopyToReg &&
1189 Use->getOperand(2).Val == Node) {
1190 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
1191 if (MRegisterInfo::isVirtualRegister(DestReg)) {
1192 VRBase = DestReg;
1193 break;
1194 }
1195 }
1196 }
1197
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001198 // Figure out the register class to create for the destreg.
1199 const TargetRegisterClass *TRC = 0;
Chris Lattnera4176522005-10-30 18:54:27 +00001200 if (VRBase) {
1201 TRC = RegMap->getRegClass(VRBase);
1202 } else {
Chris Lattner089c25c2005-10-09 05:58:56 +00001203
Chris Lattnera4176522005-10-30 18:54:27 +00001204 // Pick the register class of the right type that contains this physreg.
1205 for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
1206 E = MRI.regclass_end(); I != E; ++I)
Nate Begeman6510b222005-12-01 04:51:06 +00001207 if ((*I)->hasType(Node->getValueType(0)) &&
Chris Lattnera4176522005-10-30 18:54:27 +00001208 (*I)->contains(SrcReg)) {
1209 TRC = *I;
1210 break;
1211 }
1212 assert(TRC && "Couldn't find register class for reg copy!");
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001213
Chris Lattnera4176522005-10-30 18:54:27 +00001214 // Create the reg, emit the copy.
1215 VRBase = RegMap->createVirtualRegister(TRC);
1216 }
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001217 MRI.copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
1218 break;
1219 }
1220 }
1221 }
1222
1223 assert(NI->VRBase == 0 && "Node emitted out of order - early");
1224 NI->VRBase = VRBase;
1225}
1226
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001227/// Schedule - Order nodes according to selected style.
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001228///
1229void SimpleSched::Schedule() {
Jim Laskeyfab66f62005-10-12 18:29:35 +00001230 // Number the nodes
Chris Lattnerde202b32005-11-09 23:47:37 +00001231 NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
Jim Laskey7d090f32005-11-04 04:05:35 +00001232 // Test to see if scheduling should occur
1233 bool ShouldSchedule = NodeCount > 3 && ScheduleStyle != noScheduling;
1234 // Set up minimum info for scheduling
Jim Laskeyfab66f62005-10-12 18:29:35 +00001235 PrepareNodeInfo();
1236 // Construct node groups for flagged nodes
1237 IdentifyGroups();
Jim Laskey7d090f32005-11-04 04:05:35 +00001238
1239 // Don't waste time if is only entry and return
1240 if (ShouldSchedule) {
1241 // Get latency and resource requirements
1242 GatherSchedulingInfo();
1243 } else if (HasGroups) {
1244 // Make sure all the groups have dominators
1245 FakeGroupDominators();
1246 }
1247
Jim Laskeyfab66f62005-10-12 18:29:35 +00001248 // Breadth first walk of DAG
1249 VisitAll();
1250
1251#ifndef NDEBUG
1252 static unsigned Count = 0;
1253 Count++;
1254 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
1255 NodeInfo *NI = Ordering[i];
1256 NI->Preorder = i;
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001257 }
Jim Laskeyfab66f62005-10-12 18:29:35 +00001258#endif
1259
1260 // Don't waste time if is only entry and return
Jim Laskey7d090f32005-11-04 04:05:35 +00001261 if (ShouldSchedule) {
Jim Laskeyfab66f62005-10-12 18:29:35 +00001262 // Push back long instructions and critical path
1263 ScheduleBackward();
1264
1265 // Pack instructions to maximize resource utilization
1266 ScheduleForward();
1267 }
1268
1269 DEBUG(printChanges(Count));
1270
1271 // Emit in scheduled order
1272 EmitAll();
1273}
1274
1275/// printChanges - Hilight changes in order caused by scheduling.
1276///
1277void SimpleSched::printChanges(unsigned Index) {
1278#ifndef NDEBUG
1279 // Get the ordered node count
1280 unsigned N = Ordering.size();
1281 // Determine if any changes
1282 unsigned i = 0;
1283 for (; i < N; i++) {
1284 NodeInfo *NI = Ordering[i];
1285 if (NI->Preorder != i) break;
1286 }
1287
1288 if (i < N) {
1289 std::cerr << Index << ". New Ordering\n";
1290
1291 for (i = 0; i < N; i++) {
1292 NodeInfo *NI = Ordering[i];
1293 std::cerr << " " << NI->Preorder << ". ";
1294 printSI(std::cerr, NI);
1295 std::cerr << "\n";
Jim Laskey7d090f32005-11-04 04:05:35 +00001296 if (NI->isGroupDominator()) {
Jim Laskeyfab66f62005-10-12 18:29:35 +00001297 NodeGroup *Group = NI->Group;
Jim Laskey5a608dd2005-10-31 12:49:09 +00001298 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
Jim Laskeyfab66f62005-10-12 18:29:35 +00001299 NII != E; NII++) {
Jim Laskey53c523c2005-10-13 16:44:00 +00001300 std::cerr << " ";
Jim Laskeyfab66f62005-10-12 18:29:35 +00001301 printSI(std::cerr, *NII);
1302 std::cerr << "\n";
1303 }
1304 }
1305 }
1306 } else {
1307 std::cerr << Index << ". No Changes\n";
1308 }
1309#endif
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001310}
Chris Lattner2d973e42005-08-18 20:07:59 +00001311
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001312/// printSI - Print schedule info.
1313///
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001314void SimpleSched::printSI(std::ostream &O, NodeInfo *NI) const {
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001315#ifndef NDEBUG
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001316 SDNode *Node = NI->Node;
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001317 O << " "
Jim Laskeyfab66f62005-10-12 18:29:35 +00001318 << std::hex << Node << std::dec
Jim Laskeyb6d4c2c2005-09-30 19:15:27 +00001319 << ", Lat=" << NI->Latency
1320 << ", Slot=" << NI->Slot
1321 << ", ARITY=(" << Node->getNumOperands() << ","
1322 << Node->getNumValues() << ")"
1323 << " " << Node->getOperationName(&DAG);
1324 if (isFlagDefiner(Node)) O << "<#";
1325 if (isFlagUser(Node)) O << ">#";
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001326#endif
1327}
1328
1329/// print - Print ordering to specified output stream.
1330///
1331void SimpleSched::print(std::ostream &O) const {
1332#ifndef NDEBUG
1333 using namespace std;
1334 O << "Ordering\n";
1335 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
Jim Laskey41755e22005-10-01 00:03:07 +00001336 NodeInfo *NI = Ordering[i];
1337 printSI(O, NI);
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001338 O << "\n";
Jim Laskey7d090f32005-11-04 04:05:35 +00001339 if (NI->isGroupDominator()) {
Jim Laskey41755e22005-10-01 00:03:07 +00001340 NodeGroup *Group = NI->Group;
Jim Laskey5a608dd2005-10-31 12:49:09 +00001341 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
Jim Laskey41755e22005-10-01 00:03:07 +00001342 NII != E; NII++) {
1343 O << " ";
1344 printSI(O, *NII);
1345 O << "\n";
1346 }
1347 }
Jim Laskeye6b90fb2005-09-26 21:57:04 +00001348 }
1349#endif
1350}
1351
1352/// dump - Print ordering to std::cerr.
1353///
1354void SimpleSched::dump() const {
1355 print(std::cerr);
1356}
1357//===----------------------------------------------------------------------===//
1358
1359
1360//===----------------------------------------------------------------------===//
1361/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
1362/// target node in the graph.
Chris Lattnerd32b2362005-08-18 18:45:24 +00001363void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
Chris Lattner068ca152005-08-18 20:11:49 +00001364 if (ViewDAGs) SD.viewGraph();
Chris Lattner620c93c2005-08-27 00:58:02 +00001365 BB = SimpleSched(SD, BB).Run();
Chris Lattnerd32b2362005-08-18 18:45:24 +00001366}