Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1 | //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by Chris Lattner and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the interfaces that X86 uses to lower LLVM code into a |
| 11 | // selection DAG. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #include "X86.h" |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 16 | #include "X86InstrBuilder.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 17 | #include "X86ISelLowering.h" |
| 18 | #include "X86TargetMachine.h" |
| 19 | #include "llvm/CallingConv.h" |
| 20 | #include "llvm/Function.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 21 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineFunction.h" |
| 23 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/SelectionDAG.h" |
| 25 | #include "llvm/CodeGen/SSARegMap.h" |
| 26 | #include "llvm/Target/TargetOptions.h" |
| 27 | using namespace llvm; |
| 28 | |
| 29 | // FIXME: temporary. |
| 30 | #include "llvm/Support/CommandLine.h" |
| 31 | static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, |
| 32 | cl::desc("Enable fastcc on X86")); |
| 33 | |
| 34 | X86TargetLowering::X86TargetLowering(TargetMachine &TM) |
| 35 | : TargetLowering(TM) { |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 36 | // Set up the TargetLowering object. |
| 37 | |
| 38 | // X86 is weird, it always uses i8 for shift amounts and setcc results. |
| 39 | setShiftAmountType(MVT::i8); |
| 40 | setSetCCResultType(MVT::i8); |
| 41 | setSetCCResultContents(ZeroOrOneSetCCResult); |
| 42 | setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 |
Chris Lattner | 9edba76 | 2006-01-13 18:00:54 +0000 | [diff] [blame] | 43 | setStackPointerRegisterToSaveRestore(X86::ESP); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 44 | |
| 45 | // Set up the register classes. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 46 | addRegisterClass(MVT::i8, X86::R8RegisterClass); |
| 47 | addRegisterClass(MVT::i16, X86::R16RegisterClass); |
| 48 | addRegisterClass(MVT::i32, X86::R32RegisterClass); |
| 49 | |
| 50 | // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this |
| 51 | // operation. |
| 52 | setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); |
| 53 | setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); |
| 54 | setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); |
| 55 | setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); |
| 56 | |
| 57 | // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have |
| 58 | // this operation. |
| 59 | setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); |
| 60 | setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); |
| 61 | |
| 62 | if (!X86ScalarSSE) { |
| 63 | // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64 |
| 64 | // isn't legal. |
| 65 | setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); |
| 66 | setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); |
| 67 | setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); |
| 68 | setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); |
| 69 | } |
| 70 | |
| 71 | // Handle FP_TO_UINT by promoting the destination to a larger signed |
| 72 | // conversion. |
| 73 | setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); |
| 74 | setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); |
| 75 | setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); |
| 76 | |
| 77 | if (!X86ScalarSSE) |
| 78 | setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); |
| 79 | |
| 80 | // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have |
| 81 | // this operation. |
| 82 | setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); |
| 83 | setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); |
| 84 | setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); |
| 85 | |
Chris Lattner | 21f6685 | 2005-12-23 05:15:23 +0000 | [diff] [blame] | 86 | setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); |
| 87 | setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); |
| 88 | |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 89 | if (X86DAGIsel) { |
| 90 | setOperationAction(ISD::BRCOND , MVT::Other, Custom); |
| 91 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 92 | setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); |
| 93 | setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); |
| 94 | setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); |
| 95 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); |
Chris Lattner | e80242a | 2005-12-07 17:59:14 +0000 | [diff] [blame] | 96 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 97 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); |
| 98 | setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); |
| 99 | setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); |
| 100 | setOperationAction(ISD::FREM , MVT::f64 , Expand); |
| 101 | setOperationAction(ISD::CTPOP , MVT::i8 , Expand); |
| 102 | setOperationAction(ISD::CTTZ , MVT::i8 , Expand); |
| 103 | setOperationAction(ISD::CTLZ , MVT::i8 , Expand); |
| 104 | setOperationAction(ISD::CTPOP , MVT::i16 , Expand); |
| 105 | setOperationAction(ISD::CTTZ , MVT::i16 , Expand); |
| 106 | setOperationAction(ISD::CTLZ , MVT::i16 , Expand); |
| 107 | setOperationAction(ISD::CTPOP , MVT::i32 , Expand); |
| 108 | setOperationAction(ISD::CTTZ , MVT::i32 , Expand); |
| 109 | setOperationAction(ISD::CTLZ , MVT::i32 , Expand); |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 110 | setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 111 | |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 112 | if (!X86DAGIsel) { |
Nate Begeman | d88fc03 | 2006-01-14 03:14:10 +0000 | [diff] [blame] | 113 | setOperationAction(ISD::BSWAP , MVT::i32 , Expand); |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 114 | setOperationAction(ISD::ROTL , MVT::i8 , Expand); |
| 115 | setOperationAction(ISD::ROTR , MVT::i8 , Expand); |
| 116 | setOperationAction(ISD::ROTL , MVT::i16 , Expand); |
| 117 | setOperationAction(ISD::ROTR , MVT::i16 , Expand); |
| 118 | setOperationAction(ISD::ROTL , MVT::i32 , Expand); |
| 119 | setOperationAction(ISD::ROTR , MVT::i32 , Expand); |
| 120 | } |
Nate Begeman | d88fc03 | 2006-01-14 03:14:10 +0000 | [diff] [blame] | 121 | setOperationAction(ISD::BSWAP , MVT::i16 , Expand); |
Nate Begeman | 35ef913 | 2006-01-11 21:21:00 +0000 | [diff] [blame] | 122 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 123 | setOperationAction(ISD::READIO , MVT::i1 , Expand); |
| 124 | setOperationAction(ISD::READIO , MVT::i8 , Expand); |
| 125 | setOperationAction(ISD::READIO , MVT::i16 , Expand); |
| 126 | setOperationAction(ISD::READIO , MVT::i32 , Expand); |
| 127 | setOperationAction(ISD::WRITEIO , MVT::i1 , Expand); |
| 128 | setOperationAction(ISD::WRITEIO , MVT::i8 , Expand); |
| 129 | setOperationAction(ISD::WRITEIO , MVT::i16 , Expand); |
| 130 | setOperationAction(ISD::WRITEIO , MVT::i32 , Expand); |
| 131 | |
| 132 | // These should be promoted to a larger select which is supported. |
| 133 | setOperationAction(ISD::SELECT , MVT::i1 , Promote); |
| 134 | setOperationAction(ISD::SELECT , MVT::i8 , Promote); |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 135 | if (X86DAGIsel) { |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 136 | // X86 wants to expand cmov itself. |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 137 | setOperationAction(ISD::SELECT , MVT::i16 , Custom); |
| 138 | setOperationAction(ISD::SELECT , MVT::i32 , Custom); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 139 | setOperationAction(ISD::SELECT , MVT::f32 , Custom); |
| 140 | setOperationAction(ISD::SELECT , MVT::f64 , Custom); |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 141 | setOperationAction(ISD::SETCC , MVT::i8 , Custom); |
| 142 | setOperationAction(ISD::SETCC , MVT::i16 , Custom); |
| 143 | setOperationAction(ISD::SETCC , MVT::i32 , Custom); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 144 | setOperationAction(ISD::SETCC , MVT::f32 , Custom); |
| 145 | setOperationAction(ISD::SETCC , MVT::f64 , Custom); |
| 146 | // X86 ret instruction may pop stack. |
| 147 | setOperationAction(ISD::RET , MVT::Other, Custom); |
| 148 | // Darwin ABI issue. |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 149 | setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 150 | // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) |
| 151 | setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom); |
| 152 | setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom); |
| 153 | setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); |
| 154 | setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); |
| 155 | setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 156 | // X86 wants to expand memset / memcpy itself. |
| 157 | setOperationAction(ISD::MEMSET , MVT::Other, Custom); |
| 158 | setOperationAction(ISD::MEMCPY , MVT::Other, Custom); |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 159 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 160 | |
Chris Lattner | f73bae1 | 2005-11-29 06:16:21 +0000 | [diff] [blame] | 161 | // We don't have line number support yet. |
| 162 | setOperationAction(ISD::LOCATION, MVT::Other, Expand); |
Jim Laskey | e0bce71 | 2006-01-05 01:47:43 +0000 | [diff] [blame] | 163 | setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); |
| 164 | setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); |
Chris Lattner | f73bae1 | 2005-11-29 06:16:21 +0000 | [diff] [blame] | 165 | |
Chris Lattner | e112552 | 2006-01-15 09:00:21 +0000 | [diff] [blame] | 166 | // Expand to the default code. |
| 167 | setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); |
| 168 | setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); |
| 169 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); |
Chris Lattner | b99329e | 2006-01-13 02:42:53 +0000 | [diff] [blame] | 170 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 171 | if (X86ScalarSSE) { |
| 172 | // Set up the FP register classes. |
Evan Cheng | 5ee4ccc | 2006-01-12 08:27:59 +0000 | [diff] [blame] | 173 | addRegisterClass(MVT::f32, X86::FR32RegisterClass); |
| 174 | addRegisterClass(MVT::f64, X86::FR64RegisterClass); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 175 | |
| 176 | // SSE has no load+extend ops |
| 177 | setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); |
| 178 | setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); |
| 179 | |
| 180 | // SSE has no i16 to fp conversion, only i32 |
| 181 | setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); |
| 182 | setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); |
| 183 | |
| 184 | // Expand FP_TO_UINT into a select. |
| 185 | // FIXME: We would like to use a Custom expander here eventually to do |
| 186 | // the optimal thing for SSE vs. the default expansion in the legalizer. |
| 187 | setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); |
| 188 | |
| 189 | // We don't support sin/cos/sqrt/fmod |
| 190 | setOperationAction(ISD::FSIN , MVT::f64, Expand); |
| 191 | setOperationAction(ISD::FCOS , MVT::f64, Expand); |
| 192 | setOperationAction(ISD::FABS , MVT::f64, Expand); |
| 193 | setOperationAction(ISD::FNEG , MVT::f64, Expand); |
| 194 | setOperationAction(ISD::FREM , MVT::f64, Expand); |
| 195 | setOperationAction(ISD::FSIN , MVT::f32, Expand); |
| 196 | setOperationAction(ISD::FCOS , MVT::f32, Expand); |
| 197 | setOperationAction(ISD::FABS , MVT::f32, Expand); |
| 198 | setOperationAction(ISD::FNEG , MVT::f32, Expand); |
| 199 | setOperationAction(ISD::FREM , MVT::f32, Expand); |
| 200 | |
| 201 | addLegalFPImmediate(+0.0); // xorps / xorpd |
| 202 | } else { |
| 203 | // Set up the FP register classes. |
| 204 | addRegisterClass(MVT::f64, X86::RFPRegisterClass); |
| 205 | |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 206 | if (X86DAGIsel) { |
| 207 | setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom); |
| 208 | setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); |
| 209 | } |
| 210 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 211 | if (!UnsafeFPMath) { |
| 212 | setOperationAction(ISD::FSIN , MVT::f64 , Expand); |
| 213 | setOperationAction(ISD::FCOS , MVT::f64 , Expand); |
| 214 | } |
| 215 | |
| 216 | addLegalFPImmediate(+0.0); // FLD0 |
| 217 | addLegalFPImmediate(+1.0); // FLD1 |
| 218 | addLegalFPImmediate(-0.0); // FLD0/FCHS |
| 219 | addLegalFPImmediate(-1.0); // FLD1/FCHS |
| 220 | } |
| 221 | computeRegisterProperties(); |
| 222 | |
| 223 | maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores |
| 224 | maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores |
| 225 | maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores |
| 226 | allowUnalignedMemoryAccesses = true; // x86 supports it! |
| 227 | } |
| 228 | |
| 229 | std::vector<SDOperand> |
| 230 | X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { |
| 231 | if (F.getCallingConv() == CallingConv::Fast && EnableFastCC) |
| 232 | return LowerFastCCArguments(F, DAG); |
| 233 | return LowerCCCArguments(F, DAG); |
| 234 | } |
| 235 | |
| 236 | std::pair<SDOperand, SDOperand> |
| 237 | X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, |
| 238 | bool isVarArg, unsigned CallingConv, |
| 239 | bool isTailCall, |
| 240 | SDOperand Callee, ArgListTy &Args, |
| 241 | SelectionDAG &DAG) { |
| 242 | assert((!isVarArg || CallingConv == CallingConv::C) && |
| 243 | "Only C takes varargs!"); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 244 | |
| 245 | // If the callee is a GlobalAddress node (quite common, every direct call is) |
| 246 | // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. |
| 247 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) |
| 248 | Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 249 | else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) |
| 250 | Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 251 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 252 | if (CallingConv == CallingConv::Fast && EnableFastCC) |
| 253 | return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG); |
| 254 | return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG); |
| 255 | } |
| 256 | |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 257 | SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, |
| 258 | SelectionDAG &DAG) { |
| 259 | if (!X86DAGIsel) |
| 260 | return DAG.getNode(ISD::RET, MVT::Other, Chain, Op); |
| 261 | |
| 262 | SDOperand Copy; |
| 263 | MVT::ValueType OpVT = Op.getValueType(); |
| 264 | switch (OpVT) { |
| 265 | default: assert(0 && "Unknown type to return!"); |
| 266 | case MVT::i32: |
| 267 | Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand()); |
| 268 | break; |
| 269 | case MVT::i64: { |
| 270 | SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, |
| 271 | DAG.getConstant(1, MVT::i32)); |
| 272 | SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, |
| 273 | DAG.getConstant(0, MVT::i32)); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 274 | Copy = DAG.getCopyToReg(Chain, X86::EDX, Hi, SDOperand()); |
| 275 | Copy = DAG.getCopyToReg(Copy, X86::EAX, Lo, Copy.getValue(1)); |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 276 | break; |
| 277 | } |
| 278 | case MVT::f32: |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 279 | case MVT::f64: |
| 280 | if (!X86ScalarSSE) { |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 281 | if (OpVT == MVT::f32) |
| 282 | Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op); |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 283 | std::vector<MVT::ValueType> Tys; |
| 284 | Tys.push_back(MVT::Other); |
| 285 | Tys.push_back(MVT::Flag); |
| 286 | std::vector<SDOperand> Ops; |
| 287 | Ops.push_back(Chain); |
| 288 | Ops.push_back(Op); |
| 289 | Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops); |
| 290 | } else { |
| 291 | // Spill the value to memory and reload it into top of stack. |
| 292 | unsigned Size = MVT::getSizeInBits(OpVT)/8; |
| 293 | MachineFunction &MF = DAG.getMachineFunction(); |
| 294 | int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); |
| 295 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 296 | Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op, |
| 297 | StackSlot, DAG.getSrcValue(NULL)); |
| 298 | std::vector<MVT::ValueType> Tys; |
| 299 | Tys.push_back(MVT::f64); |
| 300 | Tys.push_back(MVT::Other); |
| 301 | std::vector<SDOperand> Ops; |
| 302 | Ops.push_back(Chain); |
| 303 | Ops.push_back(StackSlot); |
| 304 | Ops.push_back(DAG.getValueType(OpVT)); |
| 305 | Copy = DAG.getNode(X86ISD::FLD, Tys, Ops); |
| 306 | Tys.clear(); |
| 307 | Tys.push_back(MVT::Other); |
| 308 | Tys.push_back(MVT::Flag); |
| 309 | Ops.clear(); |
| 310 | Ops.push_back(Copy.getValue(1)); |
| 311 | Ops.push_back(Copy); |
| 312 | Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops); |
| 313 | } |
| 314 | break; |
| 315 | } |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 316 | |
| 317 | return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, |
| 318 | Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16), |
| 319 | Copy.getValue(1)); |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 320 | } |
| 321 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 322 | //===----------------------------------------------------------------------===// |
| 323 | // C Calling Convention implementation |
| 324 | //===----------------------------------------------------------------------===// |
| 325 | |
| 326 | std::vector<SDOperand> |
| 327 | X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) { |
| 328 | std::vector<SDOperand> ArgValues; |
| 329 | |
| 330 | MachineFunction &MF = DAG.getMachineFunction(); |
| 331 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 332 | |
| 333 | // Add DAG nodes to load the arguments... On entry to a function on the X86, |
| 334 | // the stack frame looks like this: |
| 335 | // |
| 336 | // [ESP] -- return address |
| 337 | // [ESP + 4] -- first argument (leftmost lexically) |
| 338 | // [ESP + 8] -- second argument, if first argument is four bytes in size |
| 339 | // ... |
| 340 | // |
| 341 | unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot |
| 342 | for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { |
| 343 | MVT::ValueType ObjectVT = getValueType(I->getType()); |
| 344 | unsigned ArgIncrement = 4; |
| 345 | unsigned ObjSize; |
| 346 | switch (ObjectVT) { |
| 347 | default: assert(0 && "Unhandled argument type!"); |
| 348 | case MVT::i1: |
| 349 | case MVT::i8: ObjSize = 1; break; |
| 350 | case MVT::i16: ObjSize = 2; break; |
| 351 | case MVT::i32: ObjSize = 4; break; |
| 352 | case MVT::i64: ObjSize = ArgIncrement = 8; break; |
| 353 | case MVT::f32: ObjSize = 4; break; |
| 354 | case MVT::f64: ObjSize = ArgIncrement = 8; break; |
| 355 | } |
| 356 | // Create the frame index object for this incoming parameter... |
| 357 | int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); |
| 358 | |
| 359 | // Create the SelectionDAG nodes corresponding to a load from this parameter |
| 360 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 361 | |
| 362 | // Don't codegen dead arguments. FIXME: remove this check when we can nuke |
| 363 | // dead loads. |
| 364 | SDOperand ArgValue; |
| 365 | if (!I->use_empty()) |
| 366 | ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, |
| 367 | DAG.getSrcValue(NULL)); |
| 368 | else { |
| 369 | if (MVT::isInteger(ObjectVT)) |
| 370 | ArgValue = DAG.getConstant(0, ObjectVT); |
| 371 | else |
| 372 | ArgValue = DAG.getConstantFP(0, ObjectVT); |
| 373 | } |
| 374 | ArgValues.push_back(ArgValue); |
| 375 | |
| 376 | ArgOffset += ArgIncrement; // Move on to the next argument... |
| 377 | } |
| 378 | |
| 379 | // If the function takes variable number of arguments, make a frame index for |
| 380 | // the start of the first vararg value... for expansion of llvm.va_start. |
| 381 | if (F.isVarArg()) |
| 382 | VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); |
| 383 | ReturnAddrIndex = 0; // No return address slot generated yet. |
| 384 | BytesToPopOnReturn = 0; // Callee pops nothing. |
| 385 | BytesCallerReserves = ArgOffset; |
| 386 | |
| 387 | // Finally, inform the code generator which regs we return values in. |
| 388 | switch (getValueType(F.getReturnType())) { |
| 389 | default: assert(0 && "Unknown type!"); |
| 390 | case MVT::isVoid: break; |
| 391 | case MVT::i1: |
| 392 | case MVT::i8: |
| 393 | case MVT::i16: |
| 394 | case MVT::i32: |
| 395 | MF.addLiveOut(X86::EAX); |
| 396 | break; |
| 397 | case MVT::i64: |
| 398 | MF.addLiveOut(X86::EAX); |
| 399 | MF.addLiveOut(X86::EDX); |
| 400 | break; |
| 401 | case MVT::f32: |
| 402 | case MVT::f64: |
| 403 | MF.addLiveOut(X86::ST0); |
| 404 | break; |
| 405 | } |
| 406 | return ArgValues; |
| 407 | } |
| 408 | |
| 409 | std::pair<SDOperand, SDOperand> |
| 410 | X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy, |
| 411 | bool isVarArg, bool isTailCall, |
| 412 | SDOperand Callee, ArgListTy &Args, |
| 413 | SelectionDAG &DAG) { |
| 414 | // Count how many bytes are to be pushed on the stack. |
| 415 | unsigned NumBytes = 0; |
| 416 | |
| 417 | if (Args.empty()) { |
| 418 | // Save zero bytes. |
| 419 | Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, |
| 420 | DAG.getConstant(0, getPointerTy())); |
| 421 | } else { |
| 422 | for (unsigned i = 0, e = Args.size(); i != e; ++i) |
| 423 | switch (getValueType(Args[i].second)) { |
| 424 | default: assert(0 && "Unknown value type!"); |
| 425 | case MVT::i1: |
| 426 | case MVT::i8: |
| 427 | case MVT::i16: |
| 428 | case MVT::i32: |
| 429 | case MVT::f32: |
| 430 | NumBytes += 4; |
| 431 | break; |
| 432 | case MVT::i64: |
| 433 | case MVT::f64: |
| 434 | NumBytes += 8; |
| 435 | break; |
| 436 | } |
| 437 | |
| 438 | Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, |
| 439 | DAG.getConstant(NumBytes, getPointerTy())); |
| 440 | |
| 441 | // Arguments go on the stack in reverse order, as specified by the ABI. |
| 442 | unsigned ArgOffset = 0; |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 443 | SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 444 | std::vector<SDOperand> Stores; |
| 445 | |
| 446 | for (unsigned i = 0, e = Args.size(); i != e; ++i) { |
| 447 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 448 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 449 | |
| 450 | switch (getValueType(Args[i].second)) { |
| 451 | default: assert(0 && "Unexpected ValueType for argument!"); |
| 452 | case MVT::i1: |
| 453 | case MVT::i8: |
| 454 | case MVT::i16: |
| 455 | // Promote the integer to 32 bits. If the input type is signed use a |
| 456 | // sign extend, otherwise use a zero extend. |
| 457 | if (Args[i].second->isSigned()) |
| 458 | Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); |
| 459 | else |
| 460 | Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); |
| 461 | |
| 462 | // FALL THROUGH |
| 463 | case MVT::i32: |
| 464 | case MVT::f32: |
| 465 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 466 | Args[i].first, PtrOff, |
| 467 | DAG.getSrcValue(NULL))); |
| 468 | ArgOffset += 4; |
| 469 | break; |
| 470 | case MVT::i64: |
| 471 | case MVT::f64: |
| 472 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 473 | Args[i].first, PtrOff, |
| 474 | DAG.getSrcValue(NULL))); |
| 475 | ArgOffset += 8; |
| 476 | break; |
| 477 | } |
| 478 | } |
| 479 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); |
| 480 | } |
| 481 | |
| 482 | std::vector<MVT::ValueType> RetVals; |
| 483 | MVT::ValueType RetTyVT = getValueType(RetTy); |
| 484 | RetVals.push_back(MVT::Other); |
| 485 | |
| 486 | // The result values produced have to be legal. Promote the result. |
| 487 | switch (RetTyVT) { |
| 488 | case MVT::isVoid: break; |
| 489 | default: |
| 490 | RetVals.push_back(RetTyVT); |
| 491 | break; |
| 492 | case MVT::i1: |
| 493 | case MVT::i8: |
| 494 | case MVT::i16: |
| 495 | RetVals.push_back(MVT::i32); |
| 496 | break; |
| 497 | case MVT::f32: |
| 498 | if (X86ScalarSSE) |
| 499 | RetVals.push_back(MVT::f32); |
| 500 | else |
| 501 | RetVals.push_back(MVT::f64); |
| 502 | break; |
| 503 | case MVT::i64: |
| 504 | RetVals.push_back(MVT::i32); |
| 505 | RetVals.push_back(MVT::i32); |
| 506 | break; |
| 507 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 508 | |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 509 | if (X86DAGIsel) { |
| 510 | std::vector<MVT::ValueType> NodeTys; |
| 511 | NodeTys.push_back(MVT::Other); // Returns a chain |
| 512 | NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 513 | std::vector<SDOperand> Ops; |
| 514 | Ops.push_back(Chain); |
| 515 | Ops.push_back(Callee); |
| 516 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 517 | // FIXME: Do not generate X86ISD::TAILCALL for now. |
| 518 | Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 519 | SDOperand InFlag = Chain.getValue(1); |
| 520 | |
| 521 | SDOperand RetVal; |
| 522 | if (RetTyVT != MVT::isVoid) { |
| 523 | switch (RetTyVT) { |
| 524 | default: assert(0 && "Unknown value type to return!"); |
| 525 | case MVT::i1: |
| 526 | case MVT::i8: |
| 527 | RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag); |
| 528 | Chain = RetVal.getValue(1); |
| 529 | break; |
| 530 | case MVT::i16: |
| 531 | RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag); |
| 532 | Chain = RetVal.getValue(1); |
| 533 | break; |
| 534 | case MVT::i32: |
| 535 | RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); |
| 536 | Chain = RetVal.getValue(1); |
| 537 | break; |
| 538 | case MVT::i64: { |
| 539 | SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); |
| 540 | SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32, |
| 541 | Lo.getValue(2)); |
| 542 | RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); |
| 543 | Chain = Hi.getValue(1); |
| 544 | break; |
| 545 | } |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 546 | case MVT::f64: { |
| 547 | std::vector<MVT::ValueType> Tys; |
| 548 | Tys.push_back(MVT::f64); |
| 549 | Tys.push_back(MVT::Other); |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 550 | Tys.push_back(MVT::Flag); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 551 | std::vector<SDOperand> Ops; |
| 552 | Ops.push_back(Chain); |
| 553 | Ops.push_back(InFlag); |
| 554 | RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops); |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 555 | Chain = RetVal.getValue(1); |
| 556 | InFlag = RetVal.getValue(2); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 557 | if (X86ScalarSSE) { |
Evan Cheng | 2059f88 | 2006-01-17 00:37:42 +0000 | [diff] [blame^] | 558 | // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This |
| 559 | // shouldn't be necessary except for RFP cannot be live across |
| 560 | // multiple blocks. When stackifier is fixed, they can be uncoupled. |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 561 | unsigned Size = MVT::getSizeInBits(MVT::f64)/8; |
| 562 | MachineFunction &MF = DAG.getMachineFunction(); |
| 563 | int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); |
| 564 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 565 | Tys.clear(); |
| 566 | Tys.push_back(MVT::Other); |
| 567 | Ops.clear(); |
| 568 | Ops.push_back(Chain); |
| 569 | Ops.push_back(RetVal); |
| 570 | Ops.push_back(StackSlot); |
| 571 | Ops.push_back(DAG.getValueType(RetTyVT)); |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 572 | Ops.push_back(InFlag); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 573 | Chain = DAG.getNode(X86ISD::FST, Tys, Ops); |
| 574 | RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot, |
| 575 | DAG.getSrcValue(NULL)); |
| 576 | Chain = RetVal.getValue(1); |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 577 | } |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 578 | break; |
| 579 | } |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, |
| 584 | DAG.getConstant(NumBytes, getPointerTy()), |
| 585 | DAG.getConstant(0, getPointerTy())); |
| 586 | return std::make_pair(RetVal, Chain); |
| 587 | } else { |
| 588 | std::vector<SDOperand> Ops; |
| 589 | Ops.push_back(Chain); |
| 590 | Ops.push_back(Callee); |
| 591 | Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); |
| 592 | Ops.push_back(DAG.getConstant(0, getPointerTy())); |
| 593 | |
| 594 | SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, |
| 595 | RetVals, Ops); |
| 596 | |
| 597 | SDOperand ResultVal; |
| 598 | switch (RetTyVT) { |
| 599 | case MVT::isVoid: break; |
| 600 | default: |
| 601 | ResultVal = TheCall.getValue(1); |
| 602 | break; |
| 603 | case MVT::i1: |
| 604 | case MVT::i8: |
| 605 | case MVT::i16: |
| 606 | ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); |
| 607 | break; |
| 608 | case MVT::f32: |
| 609 | // FIXME: we would really like to remember that this FP_ROUND operation is |
| 610 | // okay to eliminate if we allow excess FP precision. |
| 611 | ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); |
| 612 | break; |
| 613 | case MVT::i64: |
| 614 | ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), |
| 615 | TheCall.getValue(2)); |
| 616 | break; |
| 617 | } |
| 618 | |
| 619 | Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); |
| 620 | return std::make_pair(ResultVal, Chain); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 621 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 622 | } |
| 623 | |
| 624 | SDOperand |
| 625 | X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP, |
| 626 | Value *VAListV, SelectionDAG &DAG) { |
| 627 | // vastart just stores the address of the VarArgsFrameIndex slot. |
| 628 | SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); |
| 629 | return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, |
| 630 | DAG.getSrcValue(VAListV)); |
| 631 | } |
| 632 | |
| 633 | |
| 634 | std::pair<SDOperand,SDOperand> |
| 635 | X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, |
| 636 | Value *VAListV, const Type *ArgTy, |
| 637 | SelectionDAG &DAG) { |
| 638 | MVT::ValueType ArgVT = getValueType(ArgTy); |
| 639 | SDOperand Val = DAG.getLoad(MVT::i32, Chain, |
| 640 | VAListP, DAG.getSrcValue(VAListV)); |
| 641 | SDOperand Result = DAG.getLoad(ArgVT, Chain, Val, |
| 642 | DAG.getSrcValue(NULL)); |
| 643 | unsigned Amt; |
| 644 | if (ArgVT == MVT::i32) |
| 645 | Amt = 4; |
| 646 | else { |
| 647 | assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) && |
| 648 | "Other types should have been promoted for varargs!"); |
| 649 | Amt = 8; |
| 650 | } |
| 651 | Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val, |
| 652 | DAG.getConstant(Amt, Val.getValueType())); |
| 653 | Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 654 | Val, VAListP, DAG.getSrcValue(VAListV)); |
| 655 | return std::make_pair(Result, Chain); |
| 656 | } |
| 657 | |
| 658 | //===----------------------------------------------------------------------===// |
| 659 | // Fast Calling Convention implementation |
| 660 | //===----------------------------------------------------------------------===// |
| 661 | // |
| 662 | // The X86 'fast' calling convention passes up to two integer arguments in |
| 663 | // registers (an appropriate portion of EAX/EDX), passes arguments in C order, |
| 664 | // and requires that the callee pop its arguments off the stack (allowing proper |
| 665 | // tail calls), and has the same return value conventions as C calling convs. |
| 666 | // |
| 667 | // This calling convention always arranges for the callee pop value to be 8n+4 |
| 668 | // bytes, which is needed for tail recursion elimination and stack alignment |
| 669 | // reasons. |
| 670 | // |
| 671 | // Note that this can be enhanced in the future to pass fp vals in registers |
| 672 | // (when we have a global fp allocator) and do other tricks. |
| 673 | // |
| 674 | |
| 675 | /// AddLiveIn - This helper function adds the specified physical register to the |
| 676 | /// MachineFunction as a live in value. It also creates a corresponding virtual |
| 677 | /// register for it. |
| 678 | static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, |
| 679 | TargetRegisterClass *RC) { |
| 680 | assert(RC->contains(PReg) && "Not the correct regclass!"); |
| 681 | unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); |
| 682 | MF.addLiveIn(PReg, VReg); |
| 683 | return VReg; |
| 684 | } |
| 685 | |
| 686 | |
| 687 | std::vector<SDOperand> |
| 688 | X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) { |
| 689 | std::vector<SDOperand> ArgValues; |
| 690 | |
| 691 | MachineFunction &MF = DAG.getMachineFunction(); |
| 692 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 693 | |
| 694 | // Add DAG nodes to load the arguments... On entry to a function the stack |
| 695 | // frame looks like this: |
| 696 | // |
| 697 | // [ESP] -- return address |
| 698 | // [ESP + 4] -- first nonreg argument (leftmost lexically) |
| 699 | // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size |
| 700 | // ... |
| 701 | unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot |
| 702 | |
| 703 | // Keep track of the number of integer regs passed so far. This can be either |
| 704 | // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both |
| 705 | // used). |
| 706 | unsigned NumIntRegs = 0; |
| 707 | |
| 708 | for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { |
| 709 | MVT::ValueType ObjectVT = getValueType(I->getType()); |
| 710 | unsigned ArgIncrement = 4; |
| 711 | unsigned ObjSize = 0; |
| 712 | SDOperand ArgValue; |
| 713 | |
| 714 | switch (ObjectVT) { |
| 715 | default: assert(0 && "Unhandled argument type!"); |
| 716 | case MVT::i1: |
| 717 | case MVT::i8: |
| 718 | if (NumIntRegs < 2) { |
| 719 | if (!I->use_empty()) { |
| 720 | unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL, |
| 721 | X86::R8RegisterClass); |
| 722 | ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8); |
| 723 | DAG.setRoot(ArgValue.getValue(1)); |
Chris Lattner | f31d193 | 2005-12-27 03:02:18 +0000 | [diff] [blame] | 724 | if (ObjectVT == MVT::i1) |
| 725 | // FIXME: Should insert a assertzext here. |
| 726 | ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 727 | } |
| 728 | ++NumIntRegs; |
| 729 | break; |
| 730 | } |
| 731 | |
| 732 | ObjSize = 1; |
| 733 | break; |
| 734 | case MVT::i16: |
| 735 | if (NumIntRegs < 2) { |
| 736 | if (!I->use_empty()) { |
| 737 | unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX, |
| 738 | X86::R16RegisterClass); |
| 739 | ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16); |
| 740 | DAG.setRoot(ArgValue.getValue(1)); |
| 741 | } |
| 742 | ++NumIntRegs; |
| 743 | break; |
| 744 | } |
| 745 | ObjSize = 2; |
| 746 | break; |
| 747 | case MVT::i32: |
| 748 | if (NumIntRegs < 2) { |
| 749 | if (!I->use_empty()) { |
| 750 | unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX, |
| 751 | X86::R32RegisterClass); |
| 752 | ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); |
| 753 | DAG.setRoot(ArgValue.getValue(1)); |
| 754 | } |
| 755 | ++NumIntRegs; |
| 756 | break; |
| 757 | } |
| 758 | ObjSize = 4; |
| 759 | break; |
| 760 | case MVT::i64: |
| 761 | if (NumIntRegs == 0) { |
| 762 | if (!I->use_empty()) { |
| 763 | unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass); |
| 764 | unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); |
| 765 | |
| 766 | SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); |
| 767 | SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32); |
| 768 | DAG.setRoot(Hi.getValue(1)); |
| 769 | |
| 770 | ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); |
| 771 | } |
| 772 | NumIntRegs = 2; |
| 773 | break; |
| 774 | } else if (NumIntRegs == 1) { |
| 775 | if (!I->use_empty()) { |
| 776 | unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); |
| 777 | SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); |
| 778 | DAG.setRoot(Low.getValue(1)); |
| 779 | |
| 780 | // Load the high part from memory. |
| 781 | // Create the frame index object for this incoming parameter... |
| 782 | int FI = MFI->CreateFixedObject(4, ArgOffset); |
| 783 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 784 | SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, |
| 785 | DAG.getSrcValue(NULL)); |
| 786 | ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); |
| 787 | } |
| 788 | ArgOffset += 4; |
| 789 | NumIntRegs = 2; |
| 790 | break; |
| 791 | } |
| 792 | ObjSize = ArgIncrement = 8; |
| 793 | break; |
| 794 | case MVT::f32: ObjSize = 4; break; |
| 795 | case MVT::f64: ObjSize = ArgIncrement = 8; break; |
| 796 | } |
| 797 | |
| 798 | // Don't codegen dead arguments. FIXME: remove this check when we can nuke |
| 799 | // dead loads. |
| 800 | if (ObjSize && !I->use_empty()) { |
| 801 | // Create the frame index object for this incoming parameter... |
| 802 | int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); |
| 803 | |
| 804 | // Create the SelectionDAG nodes corresponding to a load from this |
| 805 | // parameter. |
| 806 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 807 | |
| 808 | ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, |
| 809 | DAG.getSrcValue(NULL)); |
| 810 | } else if (ArgValue.Val == 0) { |
| 811 | if (MVT::isInteger(ObjectVT)) |
| 812 | ArgValue = DAG.getConstant(0, ObjectVT); |
| 813 | else |
| 814 | ArgValue = DAG.getConstantFP(0, ObjectVT); |
| 815 | } |
| 816 | ArgValues.push_back(ArgValue); |
| 817 | |
| 818 | if (ObjSize) |
| 819 | ArgOffset += ArgIncrement; // Move on to the next argument. |
| 820 | } |
| 821 | |
| 822 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 823 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 824 | if ((ArgOffset & 7) == 0) |
| 825 | ArgOffset += 4; |
| 826 | |
| 827 | VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. |
| 828 | ReturnAddrIndex = 0; // No return address slot generated yet. |
| 829 | BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments. |
| 830 | BytesCallerReserves = 0; |
| 831 | |
| 832 | // Finally, inform the code generator which regs we return values in. |
| 833 | switch (getValueType(F.getReturnType())) { |
| 834 | default: assert(0 && "Unknown type!"); |
| 835 | case MVT::isVoid: break; |
| 836 | case MVT::i1: |
| 837 | case MVT::i8: |
| 838 | case MVT::i16: |
| 839 | case MVT::i32: |
| 840 | MF.addLiveOut(X86::EAX); |
| 841 | break; |
| 842 | case MVT::i64: |
| 843 | MF.addLiveOut(X86::EAX); |
| 844 | MF.addLiveOut(X86::EDX); |
| 845 | break; |
| 846 | case MVT::f32: |
| 847 | case MVT::f64: |
| 848 | MF.addLiveOut(X86::ST0); |
| 849 | break; |
| 850 | } |
| 851 | return ArgValues; |
| 852 | } |
| 853 | |
| 854 | std::pair<SDOperand, SDOperand> |
| 855 | X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, |
| 856 | bool isTailCall, SDOperand Callee, |
| 857 | ArgListTy &Args, SelectionDAG &DAG) { |
| 858 | // Count how many bytes are to be pushed on the stack. |
| 859 | unsigned NumBytes = 0; |
| 860 | |
| 861 | // Keep track of the number of integer regs passed so far. This can be either |
| 862 | // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both |
| 863 | // used). |
| 864 | unsigned NumIntRegs = 0; |
| 865 | |
| 866 | for (unsigned i = 0, e = Args.size(); i != e; ++i) |
| 867 | switch (getValueType(Args[i].second)) { |
| 868 | default: assert(0 && "Unknown value type!"); |
| 869 | case MVT::i1: |
| 870 | case MVT::i8: |
| 871 | case MVT::i16: |
| 872 | case MVT::i32: |
| 873 | if (NumIntRegs < 2) { |
| 874 | ++NumIntRegs; |
| 875 | break; |
| 876 | } |
| 877 | // fall through |
| 878 | case MVT::f32: |
| 879 | NumBytes += 4; |
| 880 | break; |
| 881 | case MVT::i64: |
| 882 | if (NumIntRegs == 0) { |
| 883 | NumIntRegs = 2; |
| 884 | break; |
| 885 | } else if (NumIntRegs == 1) { |
| 886 | NumIntRegs = 2; |
| 887 | NumBytes += 4; |
| 888 | break; |
| 889 | } |
| 890 | |
| 891 | // fall through |
| 892 | case MVT::f64: |
| 893 | NumBytes += 8; |
| 894 | break; |
| 895 | } |
| 896 | |
| 897 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 898 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 899 | if ((NumBytes & 7) == 0) |
| 900 | NumBytes += 4; |
| 901 | |
| 902 | Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, |
| 903 | DAG.getConstant(NumBytes, getPointerTy())); |
| 904 | |
| 905 | // Arguments go on the stack in reverse order, as specified by the ABI. |
| 906 | unsigned ArgOffset = 0; |
| 907 | SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), |
| 908 | X86::ESP, MVT::i32); |
| 909 | NumIntRegs = 0; |
| 910 | std::vector<SDOperand> Stores; |
| 911 | std::vector<SDOperand> RegValuesToPass; |
| 912 | for (unsigned i = 0, e = Args.size(); i != e; ++i) { |
| 913 | switch (getValueType(Args[i].second)) { |
| 914 | default: assert(0 && "Unexpected ValueType for argument!"); |
| 915 | case MVT::i1: |
Chris Lattner | f31d193 | 2005-12-27 03:02:18 +0000 | [diff] [blame] | 916 | Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first); |
| 917 | // Fall through. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 918 | case MVT::i8: |
| 919 | case MVT::i16: |
| 920 | case MVT::i32: |
| 921 | if (NumIntRegs < 2) { |
| 922 | RegValuesToPass.push_back(Args[i].first); |
| 923 | ++NumIntRegs; |
| 924 | break; |
| 925 | } |
| 926 | // Fall through |
| 927 | case MVT::f32: { |
| 928 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 929 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 930 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 931 | Args[i].first, PtrOff, |
| 932 | DAG.getSrcValue(NULL))); |
| 933 | ArgOffset += 4; |
| 934 | break; |
| 935 | } |
| 936 | case MVT::i64: |
| 937 | if (NumIntRegs < 2) { // Can pass part of it in regs? |
| 938 | SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, |
| 939 | Args[i].first, DAG.getConstant(1, MVT::i32)); |
| 940 | SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, |
| 941 | Args[i].first, DAG.getConstant(0, MVT::i32)); |
| 942 | RegValuesToPass.push_back(Lo); |
| 943 | ++NumIntRegs; |
| 944 | if (NumIntRegs < 2) { // Pass both parts in regs? |
| 945 | RegValuesToPass.push_back(Hi); |
| 946 | ++NumIntRegs; |
| 947 | } else { |
| 948 | // Pass the high part in memory. |
| 949 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 950 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 951 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 952 | Hi, PtrOff, DAG.getSrcValue(NULL))); |
| 953 | ArgOffset += 4; |
| 954 | } |
| 955 | break; |
| 956 | } |
| 957 | // Fall through |
| 958 | case MVT::f64: |
| 959 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 960 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 961 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 962 | Args[i].first, PtrOff, |
| 963 | DAG.getSrcValue(NULL))); |
| 964 | ArgOffset += 8; |
| 965 | break; |
| 966 | } |
| 967 | } |
| 968 | if (!Stores.empty()) |
| 969 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); |
| 970 | |
| 971 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 972 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 973 | if ((ArgOffset & 7) == 0) |
| 974 | ArgOffset += 4; |
| 975 | |
| 976 | std::vector<MVT::ValueType> RetVals; |
| 977 | MVT::ValueType RetTyVT = getValueType(RetTy); |
| 978 | |
| 979 | RetVals.push_back(MVT::Other); |
| 980 | |
| 981 | // The result values produced have to be legal. Promote the result. |
| 982 | switch (RetTyVT) { |
| 983 | case MVT::isVoid: break; |
| 984 | default: |
| 985 | RetVals.push_back(RetTyVT); |
| 986 | break; |
| 987 | case MVT::i1: |
| 988 | case MVT::i8: |
| 989 | case MVT::i16: |
| 990 | RetVals.push_back(MVT::i32); |
| 991 | break; |
| 992 | case MVT::f32: |
| 993 | if (X86ScalarSSE) |
| 994 | RetVals.push_back(MVT::f32); |
| 995 | else |
| 996 | RetVals.push_back(MVT::f64); |
| 997 | break; |
| 998 | case MVT::i64: |
| 999 | RetVals.push_back(MVT::i32); |
| 1000 | RetVals.push_back(MVT::i32); |
| 1001 | break; |
| 1002 | } |
| 1003 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1004 | if (X86DAGIsel) { |
| 1005 | // Build a sequence of copy-to-reg nodes chained together with token chain |
| 1006 | // and flag operands which copy the outgoing args into registers. |
| 1007 | SDOperand InFlag; |
| 1008 | for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { |
| 1009 | unsigned CCReg; |
| 1010 | SDOperand RegToPass = RegValuesToPass[i]; |
| 1011 | switch (RegToPass.getValueType()) { |
| 1012 | default: assert(0 && "Bad thing to pass in regs"); |
| 1013 | case MVT::i8: |
| 1014 | CCReg = (i == 0) ? X86::AL : X86::DL; |
| 1015 | break; |
| 1016 | case MVT::i16: |
| 1017 | CCReg = (i == 0) ? X86::AX : X86::DX; |
| 1018 | break; |
| 1019 | case MVT::i32: |
| 1020 | CCReg = (i == 0) ? X86::EAX : X86::EDX; |
| 1021 | break; |
| 1022 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1023 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1024 | Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag); |
| 1025 | InFlag = Chain.getValue(1); |
| 1026 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1027 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1028 | std::vector<MVT::ValueType> NodeTys; |
| 1029 | NodeTys.push_back(MVT::Other); // Returns a chain |
| 1030 | NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1031 | std::vector<SDOperand> Ops; |
| 1032 | Ops.push_back(Chain); |
| 1033 | Ops.push_back(Callee); |
| 1034 | if (InFlag.Val) |
| 1035 | Ops.push_back(InFlag); |
| 1036 | |
| 1037 | // FIXME: Do not generate X86ISD::TAILCALL for now. |
| 1038 | Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops); |
| 1039 | InFlag = Chain.getValue(1); |
| 1040 | |
| 1041 | SDOperand RetVal; |
| 1042 | if (RetTyVT != MVT::isVoid) { |
| 1043 | switch (RetTyVT) { |
| 1044 | default: assert(0 && "Unknown value type to return!"); |
| 1045 | case MVT::i1: |
| 1046 | case MVT::i8: |
| 1047 | RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag); |
| 1048 | Chain = RetVal.getValue(1); |
| 1049 | break; |
| 1050 | case MVT::i16: |
| 1051 | RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag); |
| 1052 | Chain = RetVal.getValue(1); |
| 1053 | break; |
| 1054 | case MVT::i32: |
| 1055 | RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); |
| 1056 | Chain = RetVal.getValue(1); |
| 1057 | break; |
| 1058 | case MVT::i64: { |
| 1059 | SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); |
| 1060 | SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32, |
| 1061 | Lo.getValue(2)); |
| 1062 | RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); |
| 1063 | Chain = Hi.getValue(1); |
| 1064 | break; |
| 1065 | } |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1066 | case MVT::f64: { |
| 1067 | std::vector<MVT::ValueType> Tys; |
| 1068 | Tys.push_back(MVT::f64); |
| 1069 | Tys.push_back(MVT::Other); |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 1070 | Tys.push_back(MVT::Flag); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1071 | std::vector<SDOperand> Ops; |
| 1072 | Ops.push_back(Chain); |
| 1073 | Ops.push_back(InFlag); |
| 1074 | RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops); |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 1075 | Chain = RetVal.getValue(1); |
| 1076 | InFlag = RetVal.getValue(2); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1077 | if (X86ScalarSSE) { |
Evan Cheng | 2059f88 | 2006-01-17 00:37:42 +0000 | [diff] [blame^] | 1078 | // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This |
| 1079 | // shouldn't be necessary except for RFP cannot be live across |
| 1080 | // multiple blocks. When stackifier is fixed, they can be uncoupled. |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1081 | unsigned Size = MVT::getSizeInBits(MVT::f64)/8; |
| 1082 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1083 | int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); |
| 1084 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 1085 | Tys.clear(); |
| 1086 | Tys.push_back(MVT::Other); |
| 1087 | Ops.clear(); |
| 1088 | Ops.push_back(Chain); |
| 1089 | Ops.push_back(RetVal); |
| 1090 | Ops.push_back(StackSlot); |
| 1091 | Ops.push_back(DAG.getValueType(RetTyVT)); |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 1092 | Ops.push_back(InFlag); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1093 | Chain = DAG.getNode(X86ISD::FST, Tys, Ops); |
| 1094 | RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot, |
| 1095 | DAG.getSrcValue(NULL)); |
| 1096 | Chain = RetVal.getValue(1); |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 1097 | } |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1098 | break; |
| 1099 | } |
| 1100 | } |
| 1101 | } |
| 1102 | |
| 1103 | Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, |
| 1104 | DAG.getConstant(ArgOffset, getPointerTy()), |
| 1105 | DAG.getConstant(ArgOffset, getPointerTy())); |
| 1106 | return std::make_pair(RetVal, Chain); |
| 1107 | } else { |
| 1108 | std::vector<SDOperand> Ops; |
| 1109 | Ops.push_back(Chain); |
| 1110 | Ops.push_back(Callee); |
| 1111 | Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); |
| 1112 | // Callee pops all arg values on the stack. |
| 1113 | Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); |
| 1114 | |
| 1115 | // Pass register arguments as needed. |
| 1116 | Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end()); |
| 1117 | |
| 1118 | SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, |
| 1119 | RetVals, Ops); |
| 1120 | Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); |
| 1121 | |
| 1122 | SDOperand ResultVal; |
| 1123 | switch (RetTyVT) { |
| 1124 | case MVT::isVoid: break; |
| 1125 | default: |
| 1126 | ResultVal = TheCall.getValue(1); |
| 1127 | break; |
| 1128 | case MVT::i1: |
| 1129 | case MVT::i8: |
| 1130 | case MVT::i16: |
| 1131 | ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); |
| 1132 | break; |
| 1133 | case MVT::f32: |
| 1134 | // FIXME: we would really like to remember that this FP_ROUND operation is |
| 1135 | // okay to eliminate if we allow excess FP precision. |
| 1136 | ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); |
| 1137 | break; |
| 1138 | case MVT::i64: |
| 1139 | ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), |
| 1140 | TheCall.getValue(2)); |
| 1141 | break; |
| 1142 | } |
| 1143 | |
| 1144 | return std::make_pair(ResultVal, Chain); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1145 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1146 | } |
| 1147 | |
| 1148 | SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { |
| 1149 | if (ReturnAddrIndex == 0) { |
| 1150 | // Set up a frame object for the return address. |
| 1151 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1152 | ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); |
| 1153 | } |
| 1154 | |
| 1155 | return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32); |
| 1156 | } |
| 1157 | |
| 1158 | |
| 1159 | |
| 1160 | std::pair<SDOperand, SDOperand> X86TargetLowering:: |
| 1161 | LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, |
| 1162 | SelectionDAG &DAG) { |
| 1163 | SDOperand Result; |
| 1164 | if (Depth) // Depths > 0 not supported yet! |
| 1165 | Result = DAG.getConstant(0, getPointerTy()); |
| 1166 | else { |
| 1167 | SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); |
| 1168 | if (!isFrameAddress) |
| 1169 | // Just load the return address |
| 1170 | Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI, |
| 1171 | DAG.getSrcValue(NULL)); |
| 1172 | else |
| 1173 | Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI, |
| 1174 | DAG.getConstant(4, MVT::i32)); |
| 1175 | } |
| 1176 | return std::make_pair(Result, Chain); |
| 1177 | } |
| 1178 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1179 | /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode |
| 1180 | /// which corresponds to the condition code. |
| 1181 | static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) { |
| 1182 | switch (X86CC) { |
| 1183 | default: assert(0 && "Unknown X86 conditional code!"); |
| 1184 | case X86ISD::COND_A: return X86::JA; |
| 1185 | case X86ISD::COND_AE: return X86::JAE; |
| 1186 | case X86ISD::COND_B: return X86::JB; |
| 1187 | case X86ISD::COND_BE: return X86::JBE; |
| 1188 | case X86ISD::COND_E: return X86::JE; |
| 1189 | case X86ISD::COND_G: return X86::JG; |
| 1190 | case X86ISD::COND_GE: return X86::JGE; |
| 1191 | case X86ISD::COND_L: return X86::JL; |
| 1192 | case X86ISD::COND_LE: return X86::JLE; |
| 1193 | case X86ISD::COND_NE: return X86::JNE; |
| 1194 | case X86ISD::COND_NO: return X86::JNO; |
| 1195 | case X86ISD::COND_NP: return X86::JNP; |
| 1196 | case X86ISD::COND_NS: return X86::JNS; |
| 1197 | case X86ISD::COND_O: return X86::JO; |
| 1198 | case X86ISD::COND_P: return X86::JP; |
| 1199 | case X86ISD::COND_S: return X86::JS; |
| 1200 | } |
| 1201 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1202 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1203 | /// getX86CC - do a one to one translation of a ISD::CondCode to the X86 |
| 1204 | /// specific condition code. It returns a X86ISD::COND_INVALID if it cannot |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1205 | /// do a direct translation. |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1206 | static unsigned getX86CC(SDOperand CC, bool isFP) { |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1207 | ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); |
| 1208 | unsigned X86CC = X86ISD::COND_INVALID; |
| 1209 | if (!isFP) { |
| 1210 | switch (SetCCOpcode) { |
| 1211 | default: break; |
| 1212 | case ISD::SETEQ: X86CC = X86ISD::COND_E; break; |
| 1213 | case ISD::SETGT: X86CC = X86ISD::COND_G; break; |
| 1214 | case ISD::SETGE: X86CC = X86ISD::COND_GE; break; |
| 1215 | case ISD::SETLT: X86CC = X86ISD::COND_L; break; |
| 1216 | case ISD::SETLE: X86CC = X86ISD::COND_LE; break; |
| 1217 | case ISD::SETNE: X86CC = X86ISD::COND_NE; break; |
| 1218 | case ISD::SETULT: X86CC = X86ISD::COND_B; break; |
| 1219 | case ISD::SETUGT: X86CC = X86ISD::COND_A; break; |
| 1220 | case ISD::SETULE: X86CC = X86ISD::COND_BE; break; |
| 1221 | case ISD::SETUGE: X86CC = X86ISD::COND_AE; break; |
| 1222 | } |
| 1223 | } else { |
| 1224 | // On a floating point condition, the flags are set as follows: |
| 1225 | // ZF PF CF op |
| 1226 | // 0 | 0 | 0 | X > Y |
| 1227 | // 0 | 0 | 1 | X < Y |
| 1228 | // 1 | 0 | 0 | X == Y |
| 1229 | // 1 | 1 | 1 | unordered |
| 1230 | switch (SetCCOpcode) { |
| 1231 | default: break; |
| 1232 | case ISD::SETUEQ: |
| 1233 | case ISD::SETEQ: X86CC = X86ISD::COND_E; break; |
| 1234 | case ISD::SETOGT: |
| 1235 | case ISD::SETGT: X86CC = X86ISD::COND_A; break; |
| 1236 | case ISD::SETOGE: |
| 1237 | case ISD::SETGE: X86CC = X86ISD::COND_AE; break; |
| 1238 | case ISD::SETULT: |
| 1239 | case ISD::SETLT: X86CC = X86ISD::COND_B; break; |
| 1240 | case ISD::SETULE: |
| 1241 | case ISD::SETLE: X86CC = X86ISD::COND_BE; break; |
| 1242 | case ISD::SETONE: |
| 1243 | case ISD::SETNE: X86CC = X86ISD::COND_NE; break; |
| 1244 | case ISD::SETUO: X86CC = X86ISD::COND_P; break; |
| 1245 | case ISD::SETO: X86CC = X86ISD::COND_NP; break; |
| 1246 | } |
| 1247 | } |
| 1248 | return X86CC; |
| 1249 | } |
| 1250 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1251 | /// hasFPCMov - is there a floating point cmov for the specific X86 condition |
| 1252 | /// code. Current x86 isa includes the following FP cmov instructions: |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1253 | /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1254 | static bool hasFPCMov(unsigned X86CC) { |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1255 | switch (X86CC) { |
| 1256 | default: |
| 1257 | return false; |
| 1258 | case X86ISD::COND_B: |
| 1259 | case X86ISD::COND_BE: |
| 1260 | case X86ISD::COND_E: |
| 1261 | case X86ISD::COND_P: |
| 1262 | case X86ISD::COND_A: |
| 1263 | case X86ISD::COND_AE: |
| 1264 | case X86ISD::COND_NE: |
| 1265 | case X86ISD::COND_NP: |
| 1266 | return true; |
| 1267 | } |
| 1268 | } |
| 1269 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1270 | MachineBasicBlock * |
| 1271 | X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, |
| 1272 | MachineBasicBlock *BB) { |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 1273 | switch (MI->getOpcode()) { |
| 1274 | default: assert(false && "Unexpected instr type to insert"); |
| 1275 | case X86::CMOV_FR32: |
| 1276 | case X86::CMOV_FR64: { |
| 1277 | // To "insert" a SELECT_CC instruction, we actually have to insert the diamond |
| 1278 | // control-flow pattern. The incoming instruction knows the destination vreg |
| 1279 | // to set, the condition code register to branch on, the true/false values to |
| 1280 | // select between, and a branch opcode to use. |
| 1281 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
| 1282 | ilist<MachineBasicBlock>::iterator It = BB; |
| 1283 | ++It; |
| 1284 | |
| 1285 | // thisMBB: |
| 1286 | // ... |
| 1287 | // TrueVal = ... |
| 1288 | // cmpTY ccX, r1, r2 |
| 1289 | // bCC copy1MBB |
| 1290 | // fallthrough --> copy0MBB |
| 1291 | MachineBasicBlock *thisMBB = BB; |
| 1292 | MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); |
| 1293 | MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); |
| 1294 | unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue()); |
| 1295 | BuildMI(BB, Opc, 1).addMBB(sinkMBB); |
| 1296 | MachineFunction *F = BB->getParent(); |
| 1297 | F->getBasicBlockList().insert(It, copy0MBB); |
| 1298 | F->getBasicBlockList().insert(It, sinkMBB); |
| 1299 | // Update machine-CFG edges |
| 1300 | BB->addSuccessor(copy0MBB); |
| 1301 | BB->addSuccessor(sinkMBB); |
| 1302 | |
| 1303 | // copy0MBB: |
| 1304 | // %FalseValue = ... |
| 1305 | // # fallthrough to sinkMBB |
| 1306 | BB = copy0MBB; |
| 1307 | |
| 1308 | // Update machine-CFG edges |
| 1309 | BB->addSuccessor(sinkMBB); |
| 1310 | |
| 1311 | // sinkMBB: |
| 1312 | // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] |
| 1313 | // ... |
| 1314 | BB = sinkMBB; |
| 1315 | BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg()) |
| 1316 | .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) |
| 1317 | .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1318 | |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 1319 | delete MI; // The pseudo instruction is gone now. |
| 1320 | return BB; |
| 1321 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1322 | |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 1323 | case X86::FP_TO_INT16_IN_MEM: |
| 1324 | case X86::FP_TO_INT32_IN_MEM: |
| 1325 | case X86::FP_TO_INT64_IN_MEM: { |
| 1326 | // Change the floating point control register to use "round towards zero" |
| 1327 | // mode when truncating to an integer value. |
| 1328 | MachineFunction *F = BB->getParent(); |
| 1329 | int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); |
| 1330 | addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); |
| 1331 | |
| 1332 | // Load the old value of the high byte of the control word... |
| 1333 | unsigned OldCW = |
| 1334 | F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass); |
| 1335 | addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx); |
| 1336 | |
| 1337 | // Set the high part to be round to zero... |
| 1338 | addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F); |
| 1339 | |
| 1340 | // Reload the modified control word now... |
| 1341 | addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); |
| 1342 | |
| 1343 | // Restore the memory image of control word to original value |
| 1344 | addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW); |
| 1345 | |
| 1346 | // Get the X86 opcode to use. |
| 1347 | unsigned Opc; |
| 1348 | switch (MI->getOpcode()) { |
| 1349 | case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break; |
| 1350 | case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break; |
| 1351 | case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break; |
| 1352 | } |
| 1353 | |
| 1354 | X86AddressMode AM; |
| 1355 | MachineOperand &Op = MI->getOperand(0); |
| 1356 | if (Op.isRegister()) { |
| 1357 | AM.BaseType = X86AddressMode::RegBase; |
| 1358 | AM.Base.Reg = Op.getReg(); |
| 1359 | } else { |
| 1360 | AM.BaseType = X86AddressMode::FrameIndexBase; |
| 1361 | AM.Base.FrameIndex = Op.getFrameIndex(); |
| 1362 | } |
| 1363 | Op = MI->getOperand(1); |
| 1364 | if (Op.isImmediate()) |
| 1365 | AM.Scale = Op.getImmedValue(); |
| 1366 | Op = MI->getOperand(2); |
| 1367 | if (Op.isImmediate()) |
| 1368 | AM.IndexReg = Op.getImmedValue(); |
| 1369 | Op = MI->getOperand(3); |
| 1370 | if (Op.isGlobalAddress()) { |
| 1371 | AM.GV = Op.getGlobal(); |
| 1372 | } else { |
| 1373 | AM.Disp = Op.getImmedValue(); |
| 1374 | } |
| 1375 | addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg()); |
| 1376 | |
| 1377 | // Reload the original control word now. |
| 1378 | addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); |
| 1379 | |
| 1380 | delete MI; // The pseudo instruction is gone now. |
| 1381 | return BB; |
| 1382 | } |
| 1383 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1384 | } |
| 1385 | |
| 1386 | |
| 1387 | //===----------------------------------------------------------------------===// |
| 1388 | // X86 Custom Lowering Hooks |
| 1389 | //===----------------------------------------------------------------------===// |
| 1390 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1391 | /// LowerOperation - Provide custom lowering hooks for some operations. |
| 1392 | /// |
| 1393 | SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { |
| 1394 | switch (Op.getOpcode()) { |
| 1395 | default: assert(0 && "Should not custom lower this!"); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1396 | case ISD::ADD_PARTS: |
| 1397 | case ISD::SUB_PARTS: { |
| 1398 | assert(Op.getNumOperands() == 4 && Op.getValueType() == MVT::i32 && |
| 1399 | "Not an i64 add/sub!"); |
| 1400 | bool isAdd = Op.getOpcode() == ISD::ADD_PARTS; |
| 1401 | std::vector<MVT::ValueType> Tys; |
| 1402 | Tys.push_back(MVT::i32); |
| 1403 | Tys.push_back(MVT::Flag); |
| 1404 | std::vector<SDOperand> Ops; |
| 1405 | Ops.push_back(Op.getOperand(0)); |
| 1406 | Ops.push_back(Op.getOperand(2)); |
| 1407 | SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG, |
| 1408 | Tys, Ops); |
| 1409 | SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32, |
| 1410 | Op.getOperand(1), Op.getOperand(3), |
| 1411 | Lo.getValue(1)); |
| 1412 | Tys.clear(); |
| 1413 | Tys.push_back(MVT::i32); |
| 1414 | Tys.push_back(MVT::i32); |
| 1415 | Ops.clear(); |
| 1416 | Ops.push_back(Lo); |
| 1417 | Ops.push_back(Hi); |
| 1418 | return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); |
| 1419 | } |
| 1420 | case ISD::SHL_PARTS: |
| 1421 | case ISD::SRA_PARTS: |
| 1422 | case ISD::SRL_PARTS: { |
| 1423 | assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && |
| 1424 | "Not an i64 shift!"); |
| 1425 | bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; |
| 1426 | SDOperand ShOpLo = Op.getOperand(0); |
| 1427 | SDOperand ShOpHi = Op.getOperand(1); |
| 1428 | SDOperand ShAmt = Op.getOperand(2); |
| 1429 | SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, |
Evan Cheng | 910cd3c | 2006-01-09 22:29:54 +0000 | [diff] [blame] | 1430 | DAG.getConstant(31, MVT::i32)) |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1431 | : DAG.getConstant(0, MVT::i32); |
| 1432 | |
| 1433 | SDOperand Tmp2, Tmp3; |
| 1434 | if (Op.getOpcode() == ISD::SHL_PARTS) { |
| 1435 | Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt); |
| 1436 | Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt); |
| 1437 | } else { |
| 1438 | Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt); |
| 1439 | Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SHL, MVT::i32, ShOpHi, ShAmt); |
| 1440 | } |
| 1441 | |
| 1442 | SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag, |
| 1443 | ShAmt, DAG.getConstant(32, MVT::i8)); |
| 1444 | |
| 1445 | SDOperand Hi, Lo; |
Evan Cheng | 82a24b9 | 2006-01-09 20:49:21 +0000 | [diff] [blame] | 1446 | SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1447 | |
| 1448 | std::vector<MVT::ValueType> Tys; |
| 1449 | Tys.push_back(MVT::i32); |
| 1450 | Tys.push_back(MVT::Flag); |
| 1451 | std::vector<SDOperand> Ops; |
| 1452 | if (Op.getOpcode() == ISD::SHL_PARTS) { |
| 1453 | Ops.push_back(Tmp2); |
| 1454 | Ops.push_back(Tmp3); |
| 1455 | Ops.push_back(CC); |
| 1456 | Ops.push_back(InFlag); |
| 1457 | Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops); |
| 1458 | InFlag = Hi.getValue(1); |
| 1459 | |
| 1460 | Ops.clear(); |
| 1461 | Ops.push_back(Tmp3); |
| 1462 | Ops.push_back(Tmp1); |
| 1463 | Ops.push_back(CC); |
| 1464 | Ops.push_back(InFlag); |
| 1465 | Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops); |
| 1466 | } else { |
| 1467 | Ops.push_back(Tmp2); |
| 1468 | Ops.push_back(Tmp3); |
| 1469 | Ops.push_back(CC); |
Evan Cheng | 910cd3c | 2006-01-09 22:29:54 +0000 | [diff] [blame] | 1470 | Ops.push_back(InFlag); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1471 | Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops); |
| 1472 | InFlag = Lo.getValue(1); |
| 1473 | |
| 1474 | Ops.clear(); |
| 1475 | Ops.push_back(Tmp3); |
| 1476 | Ops.push_back(Tmp1); |
| 1477 | Ops.push_back(CC); |
| 1478 | Ops.push_back(InFlag); |
| 1479 | Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops); |
| 1480 | } |
| 1481 | |
| 1482 | Tys.clear(); |
| 1483 | Tys.push_back(MVT::i32); |
| 1484 | Tys.push_back(MVT::i32); |
| 1485 | Ops.clear(); |
| 1486 | Ops.push_back(Lo); |
| 1487 | Ops.push_back(Hi); |
| 1488 | return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); |
| 1489 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1490 | case ISD::SINT_TO_FP: { |
| 1491 | assert(Op.getValueType() == MVT::f64 && |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1492 | Op.getOperand(0).getValueType() <= MVT::i64 && |
| 1493 | Op.getOperand(0).getValueType() >= MVT::i16 && |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1494 | "Unknown SINT_TO_FP to lower!"); |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1495 | |
| 1496 | SDOperand Result; |
| 1497 | MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); |
| 1498 | unsigned Size = MVT::getSizeInBits(SrcVT)/8; |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1499 | MachineFunction &MF = DAG.getMachineFunction(); |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1500 | int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1501 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1502 | SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other, |
| 1503 | DAG.getEntryNode(), Op.getOperand(0), |
| 1504 | StackSlot, DAG.getSrcValue(NULL)); |
| 1505 | |
| 1506 | // Build the FILD |
| 1507 | std::vector<MVT::ValueType> Tys; |
| 1508 | Tys.push_back(MVT::f64); |
| 1509 | Tys.push_back(MVT::Flag); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1510 | std::vector<SDOperand> Ops; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1511 | Ops.push_back(Chain); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1512 | Ops.push_back(StackSlot); |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1513 | Ops.push_back(DAG.getValueType(SrcVT)); |
| 1514 | Result = DAG.getNode(X86ISD::FILD, Tys, Ops); |
| 1515 | return Result; |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1516 | } |
| 1517 | case ISD::FP_TO_SINT: { |
| 1518 | assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && |
| 1519 | Op.getOperand(0).getValueType() == MVT::f64 && |
| 1520 | "Unknown FP_TO_SINT to lower!"); |
| 1521 | // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary |
| 1522 | // stack slot. |
| 1523 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1524 | unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; |
| 1525 | int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); |
| 1526 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 1527 | |
| 1528 | unsigned Opc; |
| 1529 | switch (Op.getValueType()) { |
| 1530 | default: assert(0 && "Invalid FP_TO_SINT to lower!"); |
| 1531 | case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; |
| 1532 | case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; |
| 1533 | case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; |
| 1534 | } |
| 1535 | |
| 1536 | // Build the FP_TO_INT*_IN_MEM |
| 1537 | std::vector<SDOperand> Ops; |
| 1538 | Ops.push_back(DAG.getEntryNode()); |
| 1539 | Ops.push_back(Op.getOperand(0)); |
| 1540 | Ops.push_back(StackSlot); |
| 1541 | SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops); |
| 1542 | |
| 1543 | // Load the result. |
| 1544 | return DAG.getLoad(Op.getValueType(), FIST, StackSlot, |
| 1545 | DAG.getSrcValue(NULL)); |
| 1546 | } |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 1547 | case ISD::READCYCLECOUNTER: { |
Chris Lattner | 81363c3 | 2005-11-20 22:01:40 +0000 | [diff] [blame] | 1548 | std::vector<MVT::ValueType> Tys; |
| 1549 | Tys.push_back(MVT::Other); |
| 1550 | Tys.push_back(MVT::Flag); |
| 1551 | std::vector<SDOperand> Ops; |
| 1552 | Ops.push_back(Op.getOperand(0)); |
| 1553 | SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops); |
Chris Lattner | 81f803d | 2005-11-20 22:57:19 +0000 | [diff] [blame] | 1554 | Ops.clear(); |
| 1555 | Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1))); |
| 1556 | Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX, |
| 1557 | MVT::i32, Ops[0].getValue(2))); |
| 1558 | Ops.push_back(Ops[1].getValue(1)); |
| 1559 | Tys[0] = Tys[1] = MVT::i32; |
| 1560 | Tys.push_back(MVT::Other); |
| 1561 | return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 1562 | } |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1563 | case ISD::SETCC: { |
| 1564 | assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); |
| 1565 | SDOperand CC = Op.getOperand(2); |
| 1566 | SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
| 1567 | Op.getOperand(0), Op.getOperand(1)); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1568 | ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); |
| 1569 | bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1570 | unsigned X86CC = getX86CC(CC, isFP); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1571 | if (X86CC != X86ISD::COND_INVALID) { |
| 1572 | return DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1573 | DAG.getConstant(X86CC, MVT::i8), Cond); |
| 1574 | } else { |
| 1575 | assert(isFP && "Illegal integer SetCC!"); |
| 1576 | |
| 1577 | std::vector<MVT::ValueType> Tys; |
| 1578 | std::vector<SDOperand> Ops; |
| 1579 | switch (SetCCOpcode) { |
| 1580 | default: assert(false && "Illegal floating point SetCC!"); |
| 1581 | case ISD::SETOEQ: { // !PF & ZF |
| 1582 | Tys.push_back(MVT::i8); |
| 1583 | Tys.push_back(MVT::Flag); |
| 1584 | Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8)); |
| 1585 | Ops.push_back(Cond); |
| 1586 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1587 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1588 | DAG.getConstant(X86ISD::COND_E, MVT::i8), |
| 1589 | Tmp1.getValue(1)); |
| 1590 | return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); |
| 1591 | } |
| 1592 | case ISD::SETOLT: { // !PF & CF |
| 1593 | Tys.push_back(MVT::i8); |
| 1594 | Tys.push_back(MVT::Flag); |
| 1595 | Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8)); |
| 1596 | Ops.push_back(Cond); |
| 1597 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1598 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1599 | DAG.getConstant(X86ISD::COND_B, MVT::i8), |
| 1600 | Tmp1.getValue(1)); |
| 1601 | return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); |
| 1602 | } |
| 1603 | case ISD::SETOLE: { // !PF & (CF || ZF) |
| 1604 | Tys.push_back(MVT::i8); |
| 1605 | Tys.push_back(MVT::Flag); |
| 1606 | Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8)); |
| 1607 | Ops.push_back(Cond); |
| 1608 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1609 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1610 | DAG.getConstant(X86ISD::COND_BE, MVT::i8), |
| 1611 | Tmp1.getValue(1)); |
| 1612 | return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); |
| 1613 | } |
| 1614 | case ISD::SETUGT: { // PF | (!ZF & !CF) |
| 1615 | Tys.push_back(MVT::i8); |
| 1616 | Tys.push_back(MVT::Flag); |
| 1617 | Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8)); |
| 1618 | Ops.push_back(Cond); |
| 1619 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1620 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1621 | DAG.getConstant(X86ISD::COND_A, MVT::i8), |
| 1622 | Tmp1.getValue(1)); |
| 1623 | return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); |
| 1624 | } |
| 1625 | case ISD::SETUGE: { // PF | !CF |
| 1626 | Tys.push_back(MVT::i8); |
| 1627 | Tys.push_back(MVT::Flag); |
| 1628 | Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8)); |
| 1629 | Ops.push_back(Cond); |
| 1630 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1631 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1632 | DAG.getConstant(X86ISD::COND_AE, MVT::i8), |
| 1633 | Tmp1.getValue(1)); |
| 1634 | return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); |
| 1635 | } |
| 1636 | case ISD::SETUNE: { // PF | !ZF |
| 1637 | Tys.push_back(MVT::i8); |
| 1638 | Tys.push_back(MVT::Flag); |
| 1639 | Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8)); |
| 1640 | Ops.push_back(Cond); |
| 1641 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1642 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1643 | DAG.getConstant(X86ISD::COND_NE, MVT::i8), |
| 1644 | Tmp1.getValue(1)); |
| 1645 | return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); |
| 1646 | } |
| 1647 | } |
| 1648 | } |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1649 | } |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 1650 | case ISD::SELECT: { |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1651 | MVT::ValueType VT = Op.getValueType(); |
| 1652 | bool isFP = MVT::isFloatingPoint(VT); |
| 1653 | bool isFPStack = isFP && (X86Vector < SSE2); |
| 1654 | bool isFPSSE = isFP && (X86Vector >= SSE2); |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1655 | bool addTest = false; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1656 | SDOperand Op0 = Op.getOperand(0); |
| 1657 | SDOperand Cond, CC; |
| 1658 | if (Op0.getOpcode() == X86ISD::SETCC) { |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1659 | // If condition flag is set by a X86ISD::CMP, then make a copy of it |
| 1660 | // (since flag operand cannot be shared). If the X86ISD::SETCC does not |
| 1661 | // have another use it will be eliminated. |
| 1662 | // If the X86ISD::SETCC has more than one use, then it's probably better |
| 1663 | // to use a test instead of duplicating the X86ISD::CMP (for register |
| 1664 | // pressure reason). |
Evan Cheng | 80ebe38 | 2006-01-13 01:17:24 +0000 | [diff] [blame] | 1665 | if (Op0.hasOneUse() && Op0.getOperand(1).getOpcode() == X86ISD::CMP) { |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1666 | CC = Op0.getOperand(0); |
| 1667 | Cond = Op0.getOperand(1); |
| 1668 | addTest = |
Evan Cheng | 80ebe38 | 2006-01-13 01:17:24 +0000 | [diff] [blame] | 1669 | isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1670 | } else |
| 1671 | addTest = true; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1672 | } else if (Op0.getOpcode() == ISD::SETCC) { |
| 1673 | CC = Op0.getOperand(2); |
| 1674 | bool isFP = MVT::isFloatingPoint(Op0.getOperand(1).getValueType()); |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1675 | unsigned X86CC = getX86CC(CC, isFP); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1676 | CC = DAG.getConstant(X86CC, MVT::i8); |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 1677 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1678 | Op0.getOperand(0), Op0.getOperand(1)); |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1679 | addTest = true; |
| 1680 | } else |
| 1681 | addTest = true; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1682 | |
Evan Cheng | 189d01e | 2006-01-13 01:06:49 +0000 | [diff] [blame] | 1683 | if (addTest) { |
Evan Cheng | e90da97 | 2006-01-13 19:51:46 +0000 | [diff] [blame] | 1684 | CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1685 | Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0); |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 1686 | } |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1687 | |
| 1688 | std::vector<MVT::ValueType> Tys; |
| 1689 | Tys.push_back(Op.getValueType()); |
| 1690 | Tys.push_back(MVT::Flag); |
| 1691 | std::vector<SDOperand> Ops; |
Evan Cheng | e90da97 | 2006-01-13 19:51:46 +0000 | [diff] [blame] | 1692 | // X86ISD::CMOV means set the result (which is operand 1) to the RHS if |
| 1693 | // condition is true. |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1694 | Ops.push_back(Op.getOperand(2)); |
Evan Cheng | e90da97 | 2006-01-13 19:51:46 +0000 | [diff] [blame] | 1695 | Ops.push_back(Op.getOperand(1)); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1696 | Ops.push_back(CC); |
| 1697 | Ops.push_back(Cond); |
| 1698 | return DAG.getNode(X86ISD::CMOV, Tys, Ops); |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 1699 | } |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 1700 | case ISD::BRCOND: { |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1701 | bool addTest = false; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 1702 | SDOperand Cond = Op.getOperand(1); |
| 1703 | SDOperand Dest = Op.getOperand(2); |
| 1704 | SDOperand CC; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1705 | if (Cond.getOpcode() == X86ISD::SETCC) { |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1706 | // If condition flag is set by a X86ISD::CMP, then make a copy of it |
| 1707 | // (since flag operand cannot be shared). If the X86ISD::SETCC does not |
| 1708 | // have another use it will be eliminated. |
| 1709 | // If the X86ISD::SETCC has more than one use, then it's probably better |
| 1710 | // to use a test instead of duplicating the X86ISD::CMP (for register |
| 1711 | // pressure reason). |
| 1712 | if (Cond.hasOneUse() && Cond.getOperand(1).getOpcode() == X86ISD::CMP) { |
| 1713 | CC = Cond.getOperand(0); |
| 1714 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
| 1715 | Cond.getOperand(1).getOperand(0), |
| 1716 | Cond.getOperand(1).getOperand(1)); |
| 1717 | } else |
| 1718 | addTest = true; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1719 | } else if (Cond.getOpcode() == ISD::SETCC) { |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 1720 | CC = Cond.getOperand(2); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1721 | bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType()); |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1722 | unsigned X86CC = getX86CC(CC, isFP); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1723 | CC = DAG.getConstant(X86CC, MVT::i8); |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 1724 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
| 1725 | Cond.getOperand(0), Cond.getOperand(1)); |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1726 | } else |
| 1727 | addTest = true; |
| 1728 | |
| 1729 | if (addTest) { |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1730 | CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 1731 | Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond); |
| 1732 | } |
| 1733 | return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), |
| 1734 | Op.getOperand(0), Op.getOperand(2), CC, Cond); |
| 1735 | } |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1736 | case ISD::RET: { |
| 1737 | // Can only be return void. |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1738 | return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1739 | DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); |
| 1740 | } |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1741 | case ISD::MEMSET: { |
| 1742 | SDOperand InFlag; |
| 1743 | SDOperand Chain = Op.getOperand(0); |
| 1744 | unsigned Align = |
| 1745 | (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); |
| 1746 | if (Align == 0) Align = 1; |
| 1747 | |
| 1748 | MVT::ValueType AVT; |
| 1749 | SDOperand Count; |
| 1750 | if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) { |
| 1751 | unsigned ValReg; |
| 1752 | unsigned Val = ValC->getValue() & 255; |
| 1753 | |
| 1754 | // If the value is a constant, then we can potentially use larger sets. |
| 1755 | switch (Align & 3) { |
| 1756 | case 2: // WORD aligned |
| 1757 | AVT = MVT::i16; |
| 1758 | if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3))) |
| 1759 | Count = DAG.getConstant(I->getValue() / 2, MVT::i32); |
| 1760 | else |
| 1761 | Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), |
| 1762 | DAG.getConstant(1, MVT::i8)); |
| 1763 | Val = (Val << 8) | Val; |
| 1764 | ValReg = X86::AX; |
| 1765 | break; |
| 1766 | case 0: // DWORD aligned |
| 1767 | AVT = MVT::i32; |
| 1768 | if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3))) |
| 1769 | Count = DAG.getConstant(I->getValue() / 4, MVT::i32); |
| 1770 | else |
| 1771 | Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), |
| 1772 | DAG.getConstant(2, MVT::i8)); |
| 1773 | Val = (Val << 8) | Val; |
| 1774 | Val = (Val << 16) | Val; |
| 1775 | ValReg = X86::EAX; |
| 1776 | break; |
| 1777 | default: // Byte aligned |
| 1778 | AVT = MVT::i8; |
| 1779 | Count = Op.getOperand(3); |
| 1780 | ValReg = X86::AL; |
| 1781 | break; |
| 1782 | } |
| 1783 | |
| 1784 | Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), |
| 1785 | InFlag); |
| 1786 | InFlag = Chain.getValue(1); |
| 1787 | } else { |
| 1788 | AVT = MVT::i8; |
| 1789 | Count = Op.getOperand(3); |
| 1790 | Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag); |
| 1791 | InFlag = Chain.getValue(1); |
| 1792 | } |
| 1793 | |
| 1794 | Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag); |
| 1795 | InFlag = Chain.getValue(1); |
| 1796 | Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag); |
| 1797 | InFlag = Chain.getValue(1); |
| 1798 | |
| 1799 | return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain, |
| 1800 | DAG.getValueType(AVT), InFlag); |
| 1801 | } |
| 1802 | case ISD::MEMCPY: { |
| 1803 | SDOperand Chain = Op.getOperand(0); |
| 1804 | unsigned Align = |
| 1805 | (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); |
| 1806 | if (Align == 0) Align = 1; |
| 1807 | |
| 1808 | MVT::ValueType AVT; |
| 1809 | SDOperand Count; |
| 1810 | switch (Align & 3) { |
| 1811 | case 2: // WORD aligned |
| 1812 | AVT = MVT::i16; |
| 1813 | if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3))) |
| 1814 | Count = DAG.getConstant(I->getValue() / 2, MVT::i32); |
| 1815 | else |
| 1816 | Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), |
| 1817 | DAG.getConstant(1, MVT::i8)); |
| 1818 | break; |
| 1819 | case 0: // DWORD aligned |
| 1820 | AVT = MVT::i32; |
| 1821 | if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3))) |
| 1822 | Count = DAG.getConstant(I->getValue() / 4, MVT::i32); |
| 1823 | else |
| 1824 | Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), |
| 1825 | DAG.getConstant(2, MVT::i8)); |
| 1826 | break; |
| 1827 | default: // Byte aligned |
| 1828 | AVT = MVT::i8; |
| 1829 | Count = Op.getOperand(3); |
| 1830 | break; |
| 1831 | } |
| 1832 | |
| 1833 | SDOperand InFlag; |
| 1834 | Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag); |
| 1835 | InFlag = Chain.getValue(1); |
| 1836 | Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag); |
| 1837 | InFlag = Chain.getValue(1); |
| 1838 | Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag); |
| 1839 | InFlag = Chain.getValue(1); |
| 1840 | |
| 1841 | return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain, |
| 1842 | DAG.getValueType(AVT), InFlag); |
| 1843 | } |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 1844 | case ISD::GlobalAddress: { |
Evan Cheng | 002fe9b | 2006-01-12 07:56:47 +0000 | [diff] [blame] | 1845 | SDOperand Result; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 1846 | GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); |
| 1847 | // For Darwin, external and weak symbols are indirect, so we want to load |
| 1848 | // the value at address GV, not the value of GV itself. This means that |
| 1849 | // the GlobalAddress must be in the base or index register of the address, |
| 1850 | // not the GV offset field. |
| 1851 | if (getTargetMachine(). |
| 1852 | getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() && |
| 1853 | (GV->hasWeakLinkage() || GV->isExternal())) |
Evan Cheng | 002fe9b | 2006-01-12 07:56:47 +0000 | [diff] [blame] | 1854 | Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), |
| 1855 | DAG.getTargetGlobalAddress(GV, getPointerTy()), |
| 1856 | DAG.getSrcValue(NULL)); |
| 1857 | return Result; |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1858 | } |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 1859 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1860 | } |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 1861 | |
| 1862 | const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { |
| 1863 | switch (Opcode) { |
| 1864 | default: return NULL; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1865 | case X86ISD::ADD_FLAG: return "X86ISD::ADD_FLAG"; |
| 1866 | case X86ISD::SUB_FLAG: return "X86ISD::SUB_FLAG"; |
| 1867 | case X86ISD::ADC: return "X86ISD::ADC"; |
| 1868 | case X86ISD::SBB: return "X86ISD::SBB"; |
| 1869 | case X86ISD::SHLD: return "X86ISD::SHLD"; |
| 1870 | case X86ISD::SHRD: return "X86ISD::SHRD"; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1871 | case X86ISD::FILD: return "X86ISD::FILD"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 1872 | case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; |
| 1873 | case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; |
| 1874 | case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 1875 | case X86ISD::FLD: return "X86ISD::FLD"; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 1876 | case X86ISD::FST: return "X86ISD::FST"; |
| 1877 | case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT"; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 1878 | case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 1879 | case X86ISD::CALL: return "X86ISD::CALL"; |
| 1880 | case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; |
| 1881 | case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; |
| 1882 | case X86ISD::CMP: return "X86ISD::CMP"; |
| 1883 | case X86ISD::TEST: return "X86ISD::TEST"; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1884 | case X86ISD::SETCC: return "X86ISD::SETCC"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 1885 | case X86ISD::CMOV: return "X86ISD::CMOV"; |
| 1886 | case X86ISD::BRCOND: return "X86ISD::BRCOND"; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 1887 | case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1888 | case X86ISD::REP_STOS: return "X86ISD::RET_STOS"; |
| 1889 | case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 1890 | } |
| 1891 | } |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 1892 | |
| 1893 | bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op, |
| 1894 | uint64_t Mask) const { |
| 1895 | |
| 1896 | unsigned Opc = Op.getOpcode(); |
| 1897 | |
| 1898 | switch (Opc) { |
| 1899 | default: |
| 1900 | assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node"); |
| 1901 | break; |
| 1902 | case X86ISD::SETCC: return (Mask & 1) == 0; |
| 1903 | } |
| 1904 | |
| 1905 | return false; |
| 1906 | } |