Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1 | //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 2 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 7 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 10 | // This file contains the PowerPC implementation of the TargetRegisterInfo |
| 11 | // class. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #define DEBUG_TYPE "reginfo" |
Chris Lattner | 2668959 | 2005-10-14 23:51:18 +0000 | [diff] [blame] | 16 | #include "PPC.h" |
Chris Lattner | 26bd0d4 | 2005-10-14 23:45:43 +0000 | [diff] [blame] | 17 | #include "PPCInstrBuilder.h" |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 18 | #include "PPCMachineFunctionInfo.h" |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 19 | #include "PPCRegisterInfo.h" |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 20 | #include "PPCFrameLowering.h" |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 21 | #include "PPCSubtarget.h" |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 22 | #include "llvm/CallingConv.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 23 | #include "llvm/Constants.h" |
Dale Johannesen | 1532f3d | 2008-04-02 00:25:04 +0000 | [diff] [blame] | 24 | #include "llvm/Function.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 25 | #include "llvm/Type.h" |
| 26 | #include "llvm/CodeGen/ValueTypes.h" |
| 27 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 28 | #include "llvm/CodeGen/MachineModuleInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 29 | #include "llvm/CodeGen/MachineFunction.h" |
| 30 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 31 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 32 | #include "llvm/CodeGen/RegisterScavenging.h" |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 33 | #include "llvm/Target/TargetFrameLowering.h" |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 34 | #include "llvm/Target/TargetInstrInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 35 | #include "llvm/Target/TargetMachine.h" |
| 36 | #include "llvm/Target/TargetOptions.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 37 | #include "llvm/Support/CommandLine.h" |
| 38 | #include "llvm/Support/Debug.h" |
Torok Edwin | dac237e | 2009-07-08 20:53:28 +0000 | [diff] [blame] | 39 | #include "llvm/Support/ErrorHandling.h" |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 40 | #include "llvm/Support/MathExtras.h" |
Torok Edwin | dac237e | 2009-07-08 20:53:28 +0000 | [diff] [blame] | 41 | #include "llvm/Support/raw_ostream.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 42 | #include "llvm/ADT/BitVector.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 43 | #include "llvm/ADT/STLExtras.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 44 | #include <cstdlib> |
Evan Cheng | 73f50d9 | 2011-06-27 18:32:37 +0000 | [diff] [blame] | 45 | |
Evan Cheng | 73f50d9 | 2011-06-27 18:32:37 +0000 | [diff] [blame] | 46 | #define GET_REGINFO_TARGET_DESC |
Evan Cheng | a347f85 | 2011-06-24 01:44:41 +0000 | [diff] [blame] | 47 | #include "PPCGenRegisterInfo.inc" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 48 | |
Dan Gohman | 82bcd23 | 2010-04-15 17:20:57 +0000 | [diff] [blame] | 49 | namespace llvm { |
Hal Finkel | 3fd0018 | 2011-12-05 17:55:17 +0000 | [diff] [blame] | 50 | cl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger", |
Dan Gohman | b357983 | 2010-04-15 17:08:50 +0000 | [diff] [blame] | 51 | cl::init(false), |
Hal Finkel | 3fd0018 | 2011-12-05 17:55:17 +0000 | [diff] [blame] | 52 | cl::desc("Disable PPC32 register scavenger"), |
Dan Gohman | b357983 | 2010-04-15 17:08:50 +0000 | [diff] [blame] | 53 | cl::Hidden); |
Hal Finkel | 3fd0018 | 2011-12-05 17:55:17 +0000 | [diff] [blame] | 54 | cl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger", |
Dan Gohman | b357983 | 2010-04-15 17:08:50 +0000 | [diff] [blame] | 55 | cl::init(false), |
Hal Finkel | 3fd0018 | 2011-12-05 17:55:17 +0000 | [diff] [blame] | 56 | cl::desc("Disable PPC64 register scavenger"), |
Dan Gohman | b357983 | 2010-04-15 17:08:50 +0000 | [diff] [blame] | 57 | cl::Hidden); |
Dan Gohman | 82bcd23 | 2010-04-15 17:20:57 +0000 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | using namespace llvm; |
| 61 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 62 | // FIXME (64-bit): Should be inlined. |
| 63 | bool |
| 64 | PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { |
Hal Finkel | 3fd0018 | 2011-12-05 17:55:17 +0000 | [diff] [blame] | 65 | return ((!DisablePPC32RS && !Subtarget.isPPC64()) || |
| 66 | (!DisablePPC64RS && Subtarget.isPPC64())); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 67 | } |
| 68 | |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 69 | PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, |
| 70 | const TargetInstrInfo &tii) |
Evan Cheng | 0e6a052 | 2011-07-18 20:57:22 +0000 | [diff] [blame] | 71 | : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, |
| 72 | ST.isPPC64() ? 0 : 1, |
| 73 | ST.isPPC64() ? 0 : 1), |
| 74 | Subtarget(ST), TII(tii) { |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 75 | ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 76 | ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; |
| 77 | ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; |
| 78 | ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; |
| 79 | ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; |
| 80 | ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; |
| 81 | ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 82 | ImmToIdxMap[PPC::ADDI] = PPC::ADD4; |
Bill Wendling | 82d2514 | 2007-09-07 22:01:02 +0000 | [diff] [blame] | 83 | |
| 84 | // 64-bit |
| 85 | ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; |
| 86 | ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; |
| 87 | ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; |
| 88 | ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; |
| 89 | ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 90 | } |
| 91 | |
Evan Cheng | 770bcc7 | 2009-02-06 17:43:24 +0000 | [diff] [blame] | 92 | /// getPointerRegClass - Return the register class to use to hold pointers. |
| 93 | /// This is used for addressing modes. |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 94 | const TargetRegisterClass * |
| 95 | PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { |
Evan Cheng | 770bcc7 | 2009-02-06 17:43:24 +0000 | [diff] [blame] | 96 | if (Subtarget.isPPC64()) |
| 97 | return &PPC::G8RCRegClass; |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 98 | return &PPC::GPRCRegClass; |
Evan Cheng | 770bcc7 | 2009-02-06 17:43:24 +0000 | [diff] [blame] | 99 | } |
| 100 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 101 | const unsigned* |
| 102 | PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 103 | // 32-bit Darwin calling convention. |
Tilmann Scheller | 2a9ddfb | 2009-07-03 06:47:08 +0000 | [diff] [blame] | 104 | static const unsigned Darwin32_CalleeSavedRegs[] = { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 105 | PPC::R13, PPC::R14, PPC::R15, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 106 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, |
| 107 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, |
| 108 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, |
| 109 | PPC::R28, PPC::R29, PPC::R30, PPC::R31, |
| 110 | |
| 111 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 112 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 113 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 114 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 115 | PPC::F30, PPC::F31, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 116 | |
| 117 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 118 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 119 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 120 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 121 | |
| 122 | PPC::LR, 0 |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 123 | }; |
Tilmann Scheller | 6b16eff | 2009-08-15 11:54:46 +0000 | [diff] [blame] | 124 | |
| 125 | // 32-bit SVR4 calling convention. |
Tilmann Scheller | 2a9ddfb | 2009-07-03 06:47:08 +0000 | [diff] [blame] | 126 | static const unsigned SVR4_CalleeSavedRegs[] = { |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame] | 127 | PPC::R14, PPC::R15, |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 128 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, |
| 129 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, |
| 130 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, |
| 131 | PPC::R28, PPC::R29, PPC::R30, PPC::R31, |
| 132 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 133 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 134 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 135 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 136 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 137 | PPC::F30, PPC::F31, |
| 138 | |
| 139 | PPC::CR2, PPC::CR3, PPC::CR4, |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame] | 140 | |
| 141 | PPC::VRSAVE, |
| 142 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 143 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 144 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 145 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 146 | |
Tilmann Scheller | 6b16eff | 2009-08-15 11:54:46 +0000 | [diff] [blame] | 147 | 0 |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 148 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 149 | // 64-bit Darwin calling convention. |
Tilmann Scheller | 2a9ddfb | 2009-07-03 06:47:08 +0000 | [diff] [blame] | 150 | static const unsigned Darwin64_CalleeSavedRegs[] = { |
Chris Lattner | bdc571b | 2006-11-20 19:33:51 +0000 | [diff] [blame] | 151 | PPC::X14, PPC::X15, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 152 | PPC::X16, PPC::X17, PPC::X18, PPC::X19, |
| 153 | PPC::X20, PPC::X21, PPC::X22, PPC::X23, |
| 154 | PPC::X24, PPC::X25, PPC::X26, PPC::X27, |
| 155 | PPC::X28, PPC::X29, PPC::X30, PPC::X31, |
| 156 | |
| 157 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 158 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 159 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 160 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 161 | PPC::F30, PPC::F31, |
| 162 | |
| 163 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 164 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 165 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 166 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 167 | |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 168 | PPC::LR8, 0 |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 169 | }; |
Tilmann Scheller | 6b16eff | 2009-08-15 11:54:46 +0000 | [diff] [blame] | 170 | |
| 171 | // 64-bit SVR4 calling convention. |
| 172 | static const unsigned SVR4_64_CalleeSavedRegs[] = { |
| 173 | PPC::X14, PPC::X15, |
| 174 | PPC::X16, PPC::X17, PPC::X18, PPC::X19, |
| 175 | PPC::X20, PPC::X21, PPC::X22, PPC::X23, |
| 176 | PPC::X24, PPC::X25, PPC::X26, PPC::X27, |
| 177 | PPC::X28, PPC::X29, PPC::X30, PPC::X31, |
| 178 | |
| 179 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 180 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 181 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 182 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 183 | PPC::F30, PPC::F31, |
| 184 | |
| 185 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 186 | |
| 187 | PPC::VRSAVE, |
| 188 | |
| 189 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 190 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 191 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 192 | |
Tilmann Scheller | 6b16eff | 2009-08-15 11:54:46 +0000 | [diff] [blame] | 193 | 0 |
| 194 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 195 | |
Tilmann Scheller | 2a9ddfb | 2009-07-03 06:47:08 +0000 | [diff] [blame] | 196 | if (Subtarget.isDarwinABI()) |
| 197 | return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : |
| 198 | Darwin32_CalleeSavedRegs; |
Tilmann Scheller | 6b16eff | 2009-08-15 11:54:46 +0000 | [diff] [blame] | 199 | |
| 200 | return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 201 | } |
| 202 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 203 | BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 204 | BitVector Reserved(getNumRegs()); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 205 | const PPCFrameLowering *PPCFI = |
| 206 | static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 207 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 208 | Reserved.set(PPC::R0); |
| 209 | Reserved.set(PPC::R1); |
| 210 | Reserved.set(PPC::LR); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 211 | Reserved.set(PPC::LR8); |
Dale Johannesen | b384ab9 | 2008-10-29 18:26:45 +0000 | [diff] [blame] | 212 | Reserved.set(PPC::RM); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 213 | |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame] | 214 | // The SVR4 ABI reserves r2 and r13 |
Tilmann Scheller | 2a9ddfb | 2009-07-03 06:47:08 +0000 | [diff] [blame] | 215 | if (Subtarget.isSVR4ABI()) { |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame] | 216 | Reserved.set(PPC::R2); // System-reserved register |
| 217 | Reserved.set(PPC::R13); // Small Data Area pointer register |
| 218 | } |
Dale Johannesen | ee25bc2 | 2010-02-12 22:00:40 +0000 | [diff] [blame] | 219 | // Reserve R2 on Darwin to hack around the problem of save/restore of CR |
| 220 | // when the stack frame is too big to address directly; we need two regs. |
| 221 | // This is a hack. |
| 222 | if (Subtarget.isDarwinABI()) { |
| 223 | Reserved.set(PPC::R2); |
| 224 | } |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame] | 225 | |
Tilmann Scheller | 6b16eff | 2009-08-15 11:54:46 +0000 | [diff] [blame] | 226 | // On PPC64, r13 is the thread pointer. Never allocate this register. |
| 227 | // Note that this is over conservative, as it also prevents allocation of R31 |
| 228 | // when the FP is not needed. |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 229 | if (Subtarget.isPPC64()) { |
| 230 | Reserved.set(PPC::R13); |
| 231 | Reserved.set(PPC::R31); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 232 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 233 | Reserved.set(PPC::X0); |
| 234 | Reserved.set(PPC::X1); |
| 235 | Reserved.set(PPC::X13); |
| 236 | Reserved.set(PPC::X31); |
Tilmann Scheller | 6b16eff | 2009-08-15 11:54:46 +0000 | [diff] [blame] | 237 | |
| 238 | // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. |
| 239 | if (Subtarget.isSVR4ABI()) { |
| 240 | Reserved.set(PPC::X2); |
| 241 | } |
Hal Finkel | 6d0e014 | 2011-12-07 06:34:02 +0000 | [diff] [blame] | 242 | // Reserve X2 on Darwin to hack around the problem of save/restore of CR |
Dale Johannesen | ee25bc2 | 2010-02-12 22:00:40 +0000 | [diff] [blame] | 243 | // when the stack frame is too big to address directly; we need two regs. |
| 244 | // This is a hack. |
| 245 | if (Subtarget.isDarwinABI()) { |
| 246 | Reserved.set(PPC::X2); |
| 247 | } |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 248 | } |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 249 | |
Anton Korobeynikov | c8bd78c | 2010-12-18 19:53:14 +0000 | [diff] [blame] | 250 | if (PPCFI->needsFP(MF)) |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 251 | Reserved.set(PPC::R31); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 252 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 253 | return Reserved; |
| 254 | } |
| 255 | |
Hal Finkel | 768c65f | 2011-11-22 16:21:04 +0000 | [diff] [blame] | 256 | unsigned |
| 257 | PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, |
| 258 | MachineFunction &MF) const { |
| 259 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
| 260 | const unsigned DefaultSafety = 1; |
| 261 | |
| 262 | switch (RC->getID()) { |
| 263 | default: |
| 264 | return 0; |
| 265 | case PPC::G8RCRegClassID: |
| 266 | case PPC::GPRCRegClassID: { |
| 267 | unsigned FP = TFI->hasFP(MF) ? 1 : 0; |
| 268 | return 32 - FP - DefaultSafety; |
| 269 | } |
| 270 | case PPC::F8RCRegClassID: |
| 271 | case PPC::F4RCRegClassID: |
| 272 | case PPC::VRRCRegClassID: |
| 273 | return 32 - DefaultSafety; |
Hal Finkel | 2e313ca | 2011-12-05 17:54:17 +0000 | [diff] [blame] | 274 | case PPC::CRRCRegClassID: |
| 275 | return 8 - DefaultSafety; |
Hal Finkel | 768c65f | 2011-11-22 16:21:04 +0000 | [diff] [blame] | 276 | } |
| 277 | } |
| 278 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 279 | //===----------------------------------------------------------------------===// |
| 280 | // Stack Frame Processing methods |
| 281 | //===----------------------------------------------------------------------===// |
| 282 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 283 | void PPCRegisterInfo:: |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 284 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 285 | MachineBasicBlock::iterator I) const { |
Nick Lewycky | 8a8d479 | 2011-12-02 22:16:29 +0000 | [diff] [blame] | 286 | if (MF.getTarget().Options.GuaranteedTailCallOpt && |
| 287 | I->getOpcode() == PPC::ADJCALLSTACKUP) { |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 288 | // Add (actually subtract) back the amount the callee popped on return. |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 289 | if (int CalleeAmt = I->getOperand(1).getImm()) { |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 290 | bool is64Bit = Subtarget.isPPC64(); |
| 291 | CalleeAmt *= -1; |
| 292 | unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; |
| 293 | unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; |
| 294 | unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; |
| 295 | unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; |
| 296 | unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; |
| 297 | unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 298 | MachineInstr *MI = I; |
| 299 | DebugLoc dl = MI->getDebugLoc(); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 300 | |
Benjamin Kramer | 34247a0 | 2010-03-29 21:13:41 +0000 | [diff] [blame] | 301 | if (isInt<16>(CalleeAmt)) { |
Hal Finkel | 2e95afa | 2011-12-30 00:34:00 +0000 | [diff] [blame^] | 302 | BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) |
| 303 | .addReg(StackReg, RegState::Kill) |
| 304 | .addImm(CalleeAmt); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 305 | } else { |
| 306 | MachineBasicBlock::iterator MBBI = I; |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 307 | BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 308 | .addImm(CalleeAmt >> 16); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 309 | BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 310 | .addReg(TmpReg, RegState::Kill) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 311 | .addImm(CalleeAmt & 0xFFFF); |
Hal Finkel | 2e95afa | 2011-12-30 00:34:00 +0000 | [diff] [blame^] | 312 | BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) |
| 313 | .addReg(StackReg, RegState::Kill) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 314 | .addReg(TmpReg); |
| 315 | } |
| 316 | } |
| 317 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 318 | // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 319 | MBB.erase(I); |
| 320 | } |
| 321 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 322 | /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered |
| 323 | /// register first and then a spilled callee-saved register if that fails. |
| 324 | static |
| 325 | unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, |
| 326 | const TargetRegisterClass *RC, int SPAdj) { |
| 327 | assert(RS && "Register scavenging must be on"); |
Jakob Stoklund Olesen | c0823fe | 2009-08-18 21:14:54 +0000 | [diff] [blame] | 328 | unsigned Reg = RS->FindUnusedReg(RC); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 329 | // FIXME: move ARM callee-saved reg scan to target independent code, then |
| 330 | // search for already spilled CS register here. |
| 331 | if (Reg == 0) |
| 332 | Reg = RS->scavengeRegister(RC, II, SPAdj); |
| 333 | return Reg; |
| 334 | } |
| 335 | |
| 336 | /// lowerDynamicAlloc - Generate the code for allocating an object in the |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 337 | /// current frame. The sequence of code with be in the general form |
| 338 | /// |
Dan Gohman | 0f8b53f | 2009-03-03 02:55:14 +0000 | [diff] [blame] | 339 | /// addi R0, SP, \#frameSize ; get the address of the previous frame |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 340 | /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size |
Dan Gohman | 0f8b53f | 2009-03-03 02:55:14 +0000 | [diff] [blame] | 341 | /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 342 | /// |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 343 | void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, |
| 344 | int SPAdj, RegScavenger *RS) const { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 345 | // Get the instruction. |
| 346 | MachineInstr &MI = *II; |
| 347 | // Get the instruction's basic block. |
| 348 | MachineBasicBlock &MBB = *MI.getParent(); |
| 349 | // Get the basic block's function. |
| 350 | MachineFunction &MF = *MBB.getParent(); |
| 351 | // Get the frame info. |
| 352 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 353 | // Determine whether 64-bit pointers are used. |
| 354 | bool LP64 = Subtarget.isPPC64(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 355 | DebugLoc dl = MI.getDebugLoc(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 356 | |
Evan Cheng | fab0439 | 2007-01-25 22:48:25 +0000 | [diff] [blame] | 357 | // Get the maximum call stack size. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 358 | unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 359 | // Get the total frame size. |
| 360 | unsigned FrameSize = MFI->getStackSize(); |
| 361 | |
| 362 | // Get stack alignments. |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 363 | unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 364 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Dale Johannesen | 38cb138 | 2010-07-30 21:09:48 +0000 | [diff] [blame] | 365 | if (MaxAlign > TargetAlign) |
| 366 | report_fatal_error("Dynamic alloca with large aligns not supported"); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 367 | |
| 368 | // Determine the previous frame's address. If FrameSize can't be |
| 369 | // represented as 16 bits or we need special alignment, then we load the |
| 370 | // previous frame's address from 0(SP). Why not do an addis of the hi? |
| 371 | // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. |
| 372 | // Constructing the constant and adding would take 3 instructions. |
| 373 | // Fortunately, a frame greater than 32K is rare. |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 374 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
| 375 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
| 376 | const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; |
| 377 | |
| 378 | // FIXME (64-bit): Use "findScratchRegister" |
| 379 | unsigned Reg; |
Anton Korobeynikov | 94c5ae0 | 2010-11-27 23:05:25 +0000 | [diff] [blame] | 380 | if (requiresRegisterScavenging(MF)) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 381 | Reg = findScratchRegister(II, RS, RC, SPAdj); |
| 382 | else |
| 383 | Reg = PPC::R0; |
| 384 | |
Benjamin Kramer | 34247a0 | 2010-03-29 21:13:41 +0000 | [diff] [blame] | 385 | if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 386 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 387 | .addReg(PPC::R31) |
| 388 | .addImm(FrameSize); |
| 389 | } else if (LP64) { |
Anton Korobeynikov | 94c5ae0 | 2010-11-27 23:05:25 +0000 | [diff] [blame] | 390 | if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 391 | BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 392 | .addImm(0) |
| 393 | .addReg(PPC::X1); |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 394 | else |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 395 | BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 396 | .addImm(0) |
| 397 | .addReg(PPC::X1); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 398 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 399 | BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 400 | .addImm(0) |
| 401 | .addReg(PPC::R1); |
| 402 | } |
| 403 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 404 | // Grow the stack and update the stack pointer link, then determine the |
| 405 | // address of new allocated space. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 406 | if (LP64) { |
Anton Korobeynikov | 94c5ae0 | 2010-11-27 23:05:25 +0000 | [diff] [blame] | 407 | if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 408 | BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 409 | .addReg(Reg, RegState::Kill) |
Hal Finkel | 2e95afa | 2011-12-30 00:34:00 +0000 | [diff] [blame^] | 410 | .addReg(PPC::X1, RegState::Define) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 411 | .addReg(MI.getOperand(1).getReg()); |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 412 | else |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 413 | BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 414 | .addReg(PPC::X0, RegState::Kill) |
Hal Finkel | 2e95afa | 2011-12-30 00:34:00 +0000 | [diff] [blame^] | 415 | .addReg(PPC::X1, RegState::Define) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 416 | .addReg(MI.getOperand(1).getReg()); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 417 | |
| 418 | if (!MI.getOperand(1).isKill()) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 419 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 420 | .addReg(PPC::X1) |
| 421 | .addImm(maxCallFrameSize); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 422 | else |
| 423 | // Implicitly kill the register. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 424 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 425 | .addReg(PPC::X1) |
| 426 | .addImm(maxCallFrameSize) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 427 | .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 428 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 429 | BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 430 | .addReg(Reg, RegState::Kill) |
Hal Finkel | 2e95afa | 2011-12-30 00:34:00 +0000 | [diff] [blame^] | 431 | .addReg(PPC::R1, RegState::Define) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 432 | .addReg(MI.getOperand(1).getReg()); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 433 | |
| 434 | if (!MI.getOperand(1).isKill()) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 435 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 436 | .addReg(PPC::R1) |
| 437 | .addImm(maxCallFrameSize); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 438 | else |
| 439 | // Implicitly kill the register. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 440 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 441 | .addReg(PPC::R1) |
| 442 | .addImm(maxCallFrameSize) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 443 | .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 444 | } |
| 445 | |
| 446 | // Discard the DYNALLOC instruction. |
| 447 | MBB.erase(II); |
| 448 | } |
| 449 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 450 | /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of |
| 451 | /// reserving a whole register (R0), we scrounge for one here. This generates |
| 452 | /// code like this: |
| 453 | /// |
| 454 | /// mfcr rA ; Move the conditional register into GPR rA. |
| 455 | /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. |
| 456 | /// stw rA, FI ; Store rA to the frame. |
| 457 | /// |
| 458 | void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, |
| 459 | unsigned FrameIndex, int SPAdj, |
| 460 | RegScavenger *RS) const { |
| 461 | // Get the instruction. |
Hal Finkel | d21e930 | 2011-12-06 20:55:36 +0000 | [diff] [blame] | 462 | MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 463 | // Get the instruction's basic block. |
| 464 | MachineBasicBlock &MBB = *MI.getParent(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 465 | DebugLoc dl = MI.getDebugLoc(); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 466 | |
Hal Finkel | fed4d19 | 2011-12-10 04:50:53 +0000 | [diff] [blame] | 467 | // FIXME: Once LLVM supports creating virtual registers here, or the register |
| 468 | // scavenger can return multiple registers, stop using reserved registers |
| 469 | // here. |
| 470 | (void) SPAdj; |
| 471 | (void) RS; |
| 472 | |
Roman Divacky | 951cd02 | 2011-06-17 15:21:10 +0000 | [diff] [blame] | 473 | bool LP64 = Subtarget.isPPC64(); |
Hal Finkel | fed4d19 | 2011-12-10 04:50:53 +0000 | [diff] [blame] | 474 | unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : |
| 475 | (LP64 ? PPC::X0 : PPC::R0); |
| 476 | unsigned SrcReg = MI.getOperand(0).getReg(); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 477 | |
Bill Wendling | 2b5fab6 | 2008-03-04 23:27:33 +0000 | [diff] [blame] | 478 | // We need to store the CR in the low 4-bits of the saved value. First, issue |
Dale Johannesen | 5f07d52 | 2010-05-20 17:48:26 +0000 | [diff] [blame] | 479 | // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. |
Hal Finkel | 234bb38 | 2011-12-07 06:34:06 +0000 | [diff] [blame] | 480 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) |
Dale Johannesen | 5f07d52 | 2010-05-20 17:48:26 +0000 | [diff] [blame] | 481 | .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); |
Bill Wendling | 2b5fab6 | 2008-03-04 23:27:33 +0000 | [diff] [blame] | 482 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 483 | // If the saved register wasn't CR0, shift the bits left so that they are in |
| 484 | // CR0's slot. |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 485 | if (SrcReg != PPC::CR0) |
| 486 | // rlwinm rA, rA, ShiftBits, 0, 31. |
Hal Finkel | 234bb38 | 2011-12-07 06:34:06 +0000 | [diff] [blame] | 487 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 488 | .addReg(Reg, RegState::Kill) |
Evan Cheng | 966aeb5 | 2011-07-25 19:53:23 +0000 | [diff] [blame] | 489 | .addImm(getPPCRegisterNumbering(SrcReg) * 4) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 490 | .addImm(0) |
| 491 | .addImm(31); |
| 492 | |
Roman Divacky | 951cd02 | 2011-06-17 15:21:10 +0000 | [diff] [blame] | 493 | addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 494 | .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 495 | FrameIndex); |
| 496 | |
| 497 | // Discard the pseudo instruction. |
| 498 | MBB.erase(II); |
| 499 | } |
| 500 | |
Hal Finkel | d21e930 | 2011-12-06 20:55:36 +0000 | [diff] [blame] | 501 | void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, |
| 502 | unsigned FrameIndex, int SPAdj, |
| 503 | RegScavenger *RS) const { |
| 504 | // Get the instruction. |
| 505 | MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> |
| 506 | // Get the instruction's basic block. |
| 507 | MachineBasicBlock &MBB = *MI.getParent(); |
| 508 | DebugLoc dl = MI.getDebugLoc(); |
| 509 | |
Hal Finkel | fed4d19 | 2011-12-10 04:50:53 +0000 | [diff] [blame] | 510 | // FIXME: Once LLVM supports creating virtual registers here, or the register |
| 511 | // scavenger can return multiple registers, stop using reserved registers |
| 512 | // here. |
| 513 | (void) SPAdj; |
| 514 | (void) RS; |
| 515 | |
| 516 | bool LP64 = Subtarget.isPPC64(); |
| 517 | unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : |
| 518 | (LP64 ? PPC::X0 : PPC::R0); |
Hal Finkel | d21e930 | 2011-12-06 20:55:36 +0000 | [diff] [blame] | 519 | unsigned DestReg = MI.getOperand(0).getReg(); |
| 520 | assert(MI.definesRegister(DestReg) && |
| 521 | "RESTORE_CR does not define its destination"); |
Hal Finkel | d21e930 | 2011-12-06 20:55:36 +0000 | [diff] [blame] | 522 | |
| 523 | addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), |
| 524 | Reg), FrameIndex); |
| 525 | |
| 526 | // If the reloaded register isn't CR0, shift the bits right so that they are |
| 527 | // in the right CR's slot. |
| 528 | if (DestReg != PPC::CR0) { |
| 529 | unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; |
| 530 | // rlwinm r11, r11, 32-ShiftBits, 0, 31. |
| 531 | BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) |
| 532 | .addReg(Reg).addImm(32-ShiftBits).addImm(0) |
| 533 | .addImm(31); |
| 534 | } |
| 535 | |
Hal Finkel | 234bb38 | 2011-12-07 06:34:06 +0000 | [diff] [blame] | 536 | BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) |
Hal Finkel | d21e930 | 2011-12-06 20:55:36 +0000 | [diff] [blame] | 537 | .addReg(Reg); |
| 538 | |
| 539 | // Discard the pseudo instruction. |
| 540 | MBB.erase(II); |
| 541 | } |
| 542 | |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 543 | void |
Jim Grosbach | b58f498 | 2009-10-07 17:12:56 +0000 | [diff] [blame] | 544 | PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 545 | int SPAdj, RegScavenger *RS) const { |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 546 | assert(SPAdj == 0 && "Unexpected"); |
| 547 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 548 | // Get the instruction. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 549 | MachineInstr &MI = *II; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 550 | // Get the instruction's basic block. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 551 | MachineBasicBlock &MBB = *MI.getParent(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 552 | // Get the basic block's function. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 553 | MachineFunction &MF = *MBB.getParent(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 554 | // Get the frame info. |
| 555 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 556 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 557 | DebugLoc dl = MI.getDebugLoc(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 558 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 559 | // Find out which operand is the frame index. |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 560 | unsigned FIOperandNo = 0; |
Dan Gohman | d735b80 | 2008-10-03 15:45:36 +0000 | [diff] [blame] | 561 | while (!MI.getOperand(FIOperandNo).isFI()) { |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 562 | ++FIOperandNo; |
| 563 | assert(FIOperandNo != MI.getNumOperands() && |
| 564 | "Instr doesn't have FrameIndex operand!"); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 565 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 566 | // Take into account whether it's an add or mem instruction |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 567 | unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; |
Chris Lattner | 518bb53 | 2010-02-09 19:54:29 +0000 | [diff] [blame] | 568 | if (MI.isInlineAsm()) |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 569 | OffsetOperandNo = FIOperandNo-1; |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 570 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 571 | // Get the frame index. |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 572 | int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 573 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 574 | // Get the frame pointer save index. Users of this index are primarily |
| 575 | // DYNALLOC instructions. |
| 576 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 577 | int FPSI = FI->getFramePointerSaveIndex(); |
| 578 | // Get the instruction opcode. |
| 579 | unsigned OpC = MI.getOpcode(); |
| 580 | |
| 581 | // Special case for dynamic alloca. |
| 582 | if (FPSI && FrameIndex == FPSI && |
| 583 | (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 584 | lowerDynamicAlloc(II, SPAdj, RS); |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 585 | return; |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 586 | } |
| 587 | |
Hal Finkel | d21e930 | 2011-12-06 20:55:36 +0000 | [diff] [blame] | 588 | // Special case for pseudo-ops SPILL_CR and RESTORE_CR. |
| 589 | if (requiresRegisterScavenging(MF)) { |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 590 | if (OpC == PPC::SPILL_CR) { |
| 591 | lowerCRSpilling(II, FrameIndex, SPAdj, RS); |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 592 | return; |
Hal Finkel | d21e930 | 2011-12-06 20:55:36 +0000 | [diff] [blame] | 593 | } else if (OpC == PPC::RESTORE_CR) { |
| 594 | lowerCRRestore(II, FrameIndex, SPAdj, RS); |
| 595 | return; |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 596 | } |
Hal Finkel | d21e930 | 2011-12-06 20:55:36 +0000 | [diff] [blame] | 597 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 598 | |
| 599 | // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). |
Hal Finkel | 6d0e014 | 2011-12-07 06:34:02 +0000 | [diff] [blame] | 600 | |
| 601 | bool is64Bit = Subtarget.isPPC64(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 602 | MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? |
Hal Finkel | 6d0e014 | 2011-12-07 06:34:02 +0000 | [diff] [blame] | 603 | (is64Bit ? PPC::X31 : PPC::R31) : |
| 604 | (is64Bit ? PPC::X1 : PPC::R1), |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 605 | false); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 606 | |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 607 | // Figure out if the offset in the instruction is shifted right two bits. This |
| 608 | // is true for instructions like "STD", which the machine implicitly adds two |
| 609 | // low zeros to. |
| 610 | bool isIXAddr = false; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 611 | switch (OpC) { |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 612 | case PPC::LWA: |
| 613 | case PPC::LD: |
| 614 | case PPC::STD: |
| 615 | case PPC::STD_32: |
| 616 | isIXAddr = true; |
| 617 | break; |
| 618 | } |
| 619 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 620 | // Now add the frame object offset to the offset from r1. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 621 | int Offset = MFI->getObjectOffset(FrameIndex); |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 622 | if (!isIXAddr) |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 623 | Offset += MI.getOperand(OffsetOperandNo).getImm(); |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 624 | else |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 625 | Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 626 | |
| 627 | // If we're not using a Frame Pointer that has been set to the value of the |
| 628 | // SP before having the stack size subtracted from it, then add the stack size |
| 629 | // to Offset to get the correct offset. |
Dale Johannesen | 8c5358c | 2010-04-29 19:32:19 +0000 | [diff] [blame] | 630 | // Naked functions have stack size 0, although getStackSize may not reflect that |
| 631 | // because we didn't call all the pieces that compute it for naked functions. |
| 632 | if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) |
| 633 | Offset += MFI->getStackSize(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 634 | |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 635 | // If we can, encode the offset directly into the instruction. If this is a |
| 636 | // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If |
| 637 | // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits |
| 638 | // clear can be encoded. This is extremely uncommon, because normally you |
| 639 | // only "std" to a stack slot that is at least 4-byte aligned, but it can |
| 640 | // happen in invalid code. |
Benjamin Kramer | 34247a0 | 2010-03-29 21:13:41 +0000 | [diff] [blame] | 641 | if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 642 | if (isIXAddr) |
Chris Lattner | 841d12d | 2005-10-18 16:51:22 +0000 | [diff] [blame] | 643 | Offset >>= 2; // The actual encoded value has the low two bits zero. |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 644 | MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 645 | return; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 646 | } |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 647 | |
| 648 | // The offset doesn't fit into a single register, scavenge one to build the |
| 649 | // offset in. |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 650 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 651 | unsigned SReg; |
Hal Finkel | 6d0e014 | 2011-12-07 06:34:02 +0000 | [diff] [blame] | 652 | if (requiresRegisterScavenging(MF)) { |
| 653 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
| 654 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
| 655 | SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj); |
| 656 | } else |
| 657 | SReg = is64Bit ? PPC::X0 : PPC::R0; |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 658 | |
| 659 | // Insert a set of rA with the full offset value before the ld, st, or add |
Hal Finkel | 6d0e014 | 2011-12-07 06:34:02 +0000 | [diff] [blame] | 660 | BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 661 | .addImm(Offset >> 16); |
Hal Finkel | 6d0e014 | 2011-12-07 06:34:02 +0000 | [diff] [blame] | 662 | BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 663 | .addReg(SReg, RegState::Kill) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 664 | .addImm(Offset); |
| 665 | |
| 666 | // Convert into indexed form of the instruction: |
| 667 | // |
| 668 | // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 |
| 669 | // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 670 | unsigned OperandBase; |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 671 | |
Chris Lattner | 518bb53 | 2010-02-09 19:54:29 +0000 | [diff] [blame] | 672 | if (OpC != TargetOpcode::INLINEASM) { |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 673 | assert(ImmToIdxMap.count(OpC) && |
| 674 | "No indexed form of load or store available!"); |
| 675 | unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; |
Chris Lattner | 5080f4d | 2008-01-11 18:10:50 +0000 | [diff] [blame] | 676 | MI.setDesc(TII.get(NewOpcode)); |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 677 | OperandBase = 1; |
| 678 | } else { |
| 679 | OperandBase = OffsetOperandNo; |
| 680 | } |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 681 | |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 682 | unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); |
| 683 | MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); |
Hal Finkel | 2e95afa | 2011-12-30 00:34:00 +0000 | [diff] [blame^] | 684 | MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 685 | } |
| 686 | |
David Greene | 3f2bf85 | 2009-11-12 20:49:22 +0000 | [diff] [blame] | 687 | unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 688 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 689 | |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 690 | if (!Subtarget.isPPC64()) |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 691 | return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 692 | else |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 693 | return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 694 | } |
| 695 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 696 | unsigned PPCRegisterInfo::getEHExceptionRegister() const { |
| 697 | return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; |
| 698 | } |
| 699 | |
| 700 | unsigned PPCRegisterInfo::getEHHandlerRegister() const { |
| 701 | return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; |
| 702 | } |