Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1 | //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 2 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 7 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 10 | // This file contains the PowerPC implementation of the TargetRegisterInfo |
| 11 | // class. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #define DEBUG_TYPE "reginfo" |
Chris Lattner | 2668959 | 2005-10-14 23:51:18 +0000 | [diff] [blame] | 16 | #include "PPC.h" |
Chris Lattner | 26bd0d4 | 2005-10-14 23:45:43 +0000 | [diff] [blame] | 17 | #include "PPCInstrBuilder.h" |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 18 | #include "PPCMachineFunctionInfo.h" |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 19 | #include "PPCRegisterInfo.h" |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 20 | #include "PPCFrameInfo.h" |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 21 | #include "PPCSubtarget.h" |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 22 | #include "llvm/CallingConv.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 23 | #include "llvm/Constants.h" |
Dale Johannesen | 1532f3d | 2008-04-02 00:25:04 +0000 | [diff] [blame] | 24 | #include "llvm/Function.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 25 | #include "llvm/Type.h" |
| 26 | #include "llvm/CodeGen/ValueTypes.h" |
| 27 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 28 | #include "llvm/CodeGen/MachineModuleInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 29 | #include "llvm/CodeGen/MachineFunction.h" |
| 30 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 31 | #include "llvm/CodeGen/MachineLocation.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 32 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 33 | #include "llvm/CodeGen/RegisterScavenging.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 34 | #include "llvm/Target/TargetFrameInfo.h" |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 35 | #include "llvm/Target/TargetInstrInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 36 | #include "llvm/Target/TargetMachine.h" |
| 37 | #include "llvm/Target/TargetOptions.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 38 | #include "llvm/Support/CommandLine.h" |
| 39 | #include "llvm/Support/Debug.h" |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 40 | #include "llvm/Support/MathExtras.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 41 | #include "llvm/ADT/BitVector.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 42 | #include "llvm/ADT/STLExtras.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 43 | #include <cstdlib> |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 44 | using namespace llvm; |
| 45 | |
Dale Johannesen | 82e4289 | 2008-03-10 22:59:46 +0000 | [diff] [blame] | 46 | // FIXME This disables some code that aligns the stack to a boundary |
| 47 | // bigger than the default (16 bytes on Darwin) when there is a stack local |
| 48 | // of greater alignment. This does not currently work, because the delta |
| 49 | // between old and new stack pointers is added to offsets that reference |
| 50 | // incoming parameters after the prolog is generated, and the code that |
| 51 | // does that doesn't handle a variable delta. You don't want to do that |
| 52 | // anyway; a better approach is to reserve another register that retains |
| 53 | // to the incoming stack pointer, and reference parameters relative to that. |
| 54 | #define ALIGN_STACK 0 |
| 55 | |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 56 | // FIXME (64-bit): Eventually enable by default. |
Bill Wendling | 4a66e9a | 2008-03-10 22:49:16 +0000 | [diff] [blame] | 57 | cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", |
| 58 | cl::init(false), |
| 59 | cl::desc("Enable PPC32 register scavenger"), |
| 60 | cl::Hidden); |
| 61 | cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", |
| 62 | cl::init(false), |
| 63 | cl::desc("Enable PPC64 register scavenger"), |
| 64 | cl::Hidden); |
| 65 | #define EnableRegisterScavenging \ |
| 66 | ((EnablePPC32RS && !Subtarget.isPPC64()) || \ |
| 67 | (EnablePPC64RS && Subtarget.isPPC64())) |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 68 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 69 | // FIXME (64-bit): Should be inlined. |
| 70 | bool |
| 71 | PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { |
Bill Wendling | 4a66e9a | 2008-03-10 22:49:16 +0000 | [diff] [blame] | 72 | return EnableRegisterScavenging; |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 73 | } |
| 74 | |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 75 | /// getRegisterNumbering - Given the enum value for some register, e.g. |
| 76 | /// PPC::F14, return the number that it corresponds to (e.g. 14). |
| 77 | unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 78 | using namespace PPC; |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 79 | switch (RegEnum) { |
Chris Lattner | a1998d1 | 2008-02-13 17:24:14 +0000 | [diff] [blame] | 80 | case 0: return 0; |
Nicolas Geoffray | 0404cd9 | 2008-03-10 14:12:10 +0000 | [diff] [blame] | 81 | case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; |
| 82 | case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; |
| 83 | case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; |
| 84 | case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; |
| 85 | case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; |
| 86 | case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; |
| 87 | case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; |
| 88 | case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; |
| 89 | case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; |
| 90 | case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; |
| 91 | case R10: case X10: case F10: case V10: case CR2EQ: return 10; |
| 92 | case R11: case X11: case F11: case V11: case CR2UN: return 11; |
| 93 | case R12: case X12: case F12: case V12: case CR3LT: return 12; |
| 94 | case R13: case X13: case F13: case V13: case CR3GT: return 13; |
| 95 | case R14: case X14: case F14: case V14: case CR3EQ: return 14; |
| 96 | case R15: case X15: case F15: case V15: case CR3UN: return 15; |
| 97 | case R16: case X16: case F16: case V16: case CR4LT: return 16; |
| 98 | case R17: case X17: case F17: case V17: case CR4GT: return 17; |
| 99 | case R18: case X18: case F18: case V18: case CR4EQ: return 18; |
| 100 | case R19: case X19: case F19: case V19: case CR4UN: return 19; |
| 101 | case R20: case X20: case F20: case V20: case CR5LT: return 20; |
| 102 | case R21: case X21: case F21: case V21: case CR5GT: return 21; |
| 103 | case R22: case X22: case F22: case V22: case CR5EQ: return 22; |
| 104 | case R23: case X23: case F23: case V23: case CR5UN: return 23; |
| 105 | case R24: case X24: case F24: case V24: case CR6LT: return 24; |
| 106 | case R25: case X25: case F25: case V25: case CR6GT: return 25; |
| 107 | case R26: case X26: case F26: case V26: case CR6EQ: return 26; |
| 108 | case R27: case X27: case F27: case V27: case CR6UN: return 27; |
| 109 | case R28: case X28: case F28: case V28: case CR7LT: return 28; |
| 110 | case R29: case X29: case F29: case V29: case CR7GT: return 29; |
| 111 | case R30: case X30: case F30: case V30: case CR7EQ: return 30; |
| 112 | case R31: case X31: case F31: case V31: case CR7UN: return 31; |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 113 | default: |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 114 | cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 115 | abort(); |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 116 | } |
| 117 | } |
| 118 | |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 119 | PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, |
| 120 | const TargetInstrInfo &tii) |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 121 | : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 122 | Subtarget(ST), TII(tii) { |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 123 | ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 124 | ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; |
| 125 | ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; |
| 126 | ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; |
| 127 | ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; |
| 128 | ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; |
| 129 | ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 130 | ImmToIdxMap[PPC::ADDI] = PPC::ADD4; |
Bill Wendling | 82d2514 | 2007-09-07 22:01:02 +0000 | [diff] [blame] | 131 | |
| 132 | // 64-bit |
| 133 | ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; |
| 134 | ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; |
| 135 | ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; |
| 136 | ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; |
| 137 | ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 138 | } |
| 139 | |
Evan Cheng | 770bcc7 | 2009-02-06 17:43:24 +0000 | [diff] [blame] | 140 | /// getPointerRegClass - Return the register class to use to hold pointers. |
| 141 | /// This is used for addressing modes. |
| 142 | const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const { |
| 143 | if (Subtarget.isPPC64()) |
| 144 | return &PPC::G8RCRegClass; |
| 145 | else |
| 146 | return &PPC::GPRCRegClass; |
| 147 | } |
| 148 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 149 | const unsigned* |
| 150 | PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 151 | // 32-bit Darwin calling convention. |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 152 | static const unsigned Macho32_CalleeSavedRegs[] = { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 153 | PPC::R13, PPC::R14, PPC::R15, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 154 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, |
| 155 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, |
| 156 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, |
| 157 | PPC::R28, PPC::R29, PPC::R30, PPC::R31, |
| 158 | |
| 159 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 160 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 161 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 162 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 163 | PPC::F30, PPC::F31, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 164 | |
| 165 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 166 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 167 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 168 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 169 | |
Nicolas Geoffray | 0404cd9 | 2008-03-10 14:12:10 +0000 | [diff] [blame] | 170 | PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, |
| 171 | PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, |
| 172 | PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, |
| 173 | |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 174 | PPC::LR, 0 |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 175 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 176 | |
| 177 | static const unsigned ELF32_CalleeSavedRegs[] = { |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 178 | PPC::R14, PPC::R15, |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 179 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, |
| 180 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, |
| 181 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, |
| 182 | PPC::R28, PPC::R29, PPC::R30, PPC::R31, |
| 183 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 184 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 185 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 186 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 187 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 188 | PPC::F30, PPC::F31, |
| 189 | |
| 190 | PPC::CR2, PPC::CR3, PPC::CR4, |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 191 | |
| 192 | PPC::VRSAVE, |
| 193 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 194 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 195 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 196 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 197 | |
Nicolas Geoffray | 0404cd9 | 2008-03-10 14:12:10 +0000 | [diff] [blame] | 198 | PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, |
| 199 | PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, |
| 200 | PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, |
| 201 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 202 | PPC::LR, 0 |
| 203 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 204 | // 64-bit Darwin calling convention. |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 205 | static const unsigned Macho64_CalleeSavedRegs[] = { |
Chris Lattner | bdc571b | 2006-11-20 19:33:51 +0000 | [diff] [blame] | 206 | PPC::X14, PPC::X15, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 207 | PPC::X16, PPC::X17, PPC::X18, PPC::X19, |
| 208 | PPC::X20, PPC::X21, PPC::X22, PPC::X23, |
| 209 | PPC::X24, PPC::X25, PPC::X26, PPC::X27, |
| 210 | PPC::X28, PPC::X29, PPC::X30, PPC::X31, |
| 211 | |
| 212 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 213 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 214 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 215 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 216 | PPC::F30, PPC::F31, |
| 217 | |
| 218 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 219 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 220 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 221 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 222 | |
Nicolas Geoffray | 0404cd9 | 2008-03-10 14:12:10 +0000 | [diff] [blame] | 223 | PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, |
| 224 | PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, |
| 225 | PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, |
| 226 | |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 227 | PPC::LR8, 0 |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 228 | }; |
| 229 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 230 | if (Subtarget.isMachoABI()) |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 231 | return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : |
| 232 | Macho32_CalleeSavedRegs; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 233 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 234 | // ELF 32. |
| 235 | return ELF32_CalleeSavedRegs; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | const TargetRegisterClass* const* |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 239 | PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 240 | // 32-bit Macho calling convention. |
| 241 | static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 242 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 243 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 244 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 245 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 246 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 247 | |
| 248 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 249 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 250 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 251 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 252 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 253 | |
| 254 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 255 | |
| 256 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 257 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 258 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 259 | |
Nicolas Geoffray | 0404cd9 | 2008-03-10 14:12:10 +0000 | [diff] [blame] | 260 | &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, |
| 261 | &PPC::CRBITRCRegClass, |
| 262 | &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, |
| 263 | &PPC::CRBITRCRegClass, |
| 264 | &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, |
| 265 | &PPC::CRBITRCRegClass, |
| 266 | |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 267 | &PPC::GPRCRegClass, 0 |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 268 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 269 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 270 | static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 271 | &PPC::GPRCRegClass,&PPC::GPRCRegClass, |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 272 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 273 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 274 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 275 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 276 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 277 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 278 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 279 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 280 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 281 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 282 | |
| 283 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 284 | |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 285 | &PPC::VRSAVERCRegClass, |
| 286 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 287 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 288 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 289 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 290 | |
Nicolas Geoffray | 0404cd9 | 2008-03-10 14:12:10 +0000 | [diff] [blame] | 291 | &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, |
| 292 | &PPC::CRBITRCRegClass, |
| 293 | &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, |
| 294 | &PPC::CRBITRCRegClass, |
| 295 | &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, |
| 296 | &PPC::CRBITRCRegClass, |
| 297 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 298 | &PPC::GPRCRegClass, 0 |
| 299 | }; |
| 300 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 301 | // 64-bit Macho calling convention. |
| 302 | static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { |
Chris Lattner | bdc571b | 2006-11-20 19:33:51 +0000 | [diff] [blame] | 303 | &PPC::G8RCRegClass,&PPC::G8RCRegClass, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 304 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 305 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 306 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 307 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 308 | |
| 309 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 310 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 311 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 312 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 313 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 314 | |
| 315 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 316 | |
| 317 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 318 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 319 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 320 | |
Nicolas Geoffray | 0404cd9 | 2008-03-10 14:12:10 +0000 | [diff] [blame] | 321 | &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, |
| 322 | &PPC::CRBITRCRegClass, |
| 323 | &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, |
| 324 | &PPC::CRBITRCRegClass, |
| 325 | &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, |
| 326 | &PPC::CRBITRCRegClass, |
| 327 | |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 328 | &PPC::G8RCRegClass, 0 |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 329 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 330 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 331 | if (Subtarget.isMachoABI()) |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 332 | return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : |
| 333 | Macho32_CalleeSavedRegClasses; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 334 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 335 | // ELF 32. |
| 336 | return ELF32_CalleeSavedRegClasses; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 337 | } |
| 338 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 339 | // needsFP - Return true if the specified function should have a dedicated frame |
| 340 | // pointer register. This is true if the function has variable sized allocas or |
| 341 | // if frame pointer elimination is disabled. |
| 342 | // |
| 343 | static bool needsFP(const MachineFunction &MF) { |
| 344 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 345 | return NoFramePointerElim || MFI->hasVarSizedObjects() || |
| 346 | (PerformTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall()); |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 347 | } |
| 348 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 349 | static bool spillsCR(const MachineFunction &MF) { |
| 350 | const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); |
| 351 | return FuncInfo->isCRSpilled(); |
| 352 | } |
| 353 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 354 | BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 355 | BitVector Reserved(getNumRegs()); |
| 356 | Reserved.set(PPC::R0); |
| 357 | Reserved.set(PPC::R1); |
| 358 | Reserved.set(PPC::LR); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 359 | Reserved.set(PPC::LR8); |
Dale Johannesen | b384ab9 | 2008-10-29 18:26:45 +0000 | [diff] [blame] | 360 | Reserved.set(PPC::RM); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 361 | |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 362 | // The SVR4 ABI reserves r2 and r13 |
| 363 | if (Subtarget.isELF32_ABI()) { |
| 364 | Reserved.set(PPC::R2); // System-reserved register |
| 365 | Reserved.set(PPC::R13); // Small Data Area pointer register |
| 366 | } |
| 367 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 368 | // On PPC64, r13 is the thread pointer. Never allocate this register. Note |
| 369 | // that this is over conservative, as it also prevents allocation of R31 when |
| 370 | // the FP is not needed. |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 371 | if (Subtarget.isPPC64()) { |
| 372 | Reserved.set(PPC::R13); |
| 373 | Reserved.set(PPC::R31); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 374 | |
Bill Wendling | 4a66e9a | 2008-03-10 22:49:16 +0000 | [diff] [blame] | 375 | if (!EnableRegisterScavenging) |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 376 | Reserved.set(PPC::R0); // FIXME (64-bit): Remove |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 377 | |
| 378 | Reserved.set(PPC::X0); |
| 379 | Reserved.set(PPC::X1); |
| 380 | Reserved.set(PPC::X13); |
| 381 | Reserved.set(PPC::X31); |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 382 | } |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 383 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 384 | if (needsFP(MF)) |
| 385 | Reserved.set(PPC::R31); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 386 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 387 | return Reserved; |
| 388 | } |
| 389 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 390 | //===----------------------------------------------------------------------===// |
| 391 | // Stack Frame Processing methods |
| 392 | //===----------------------------------------------------------------------===// |
| 393 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 394 | // hasFP - Return true if the specified function actually has a dedicated frame |
| 395 | // pointer register. This is true if the function needs a frame pointer and has |
| 396 | // a non-zero stack size. |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 397 | bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 398 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 399 | return MFI->getStackSize() && needsFP(MF); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 400 | } |
| 401 | |
Chris Lattner | 73944fb | 2007-12-08 06:39:11 +0000 | [diff] [blame] | 402 | /// MustSaveLR - Return true if this function requires that we save the LR |
Chris Lattner | 3fc027d | 2007-12-08 06:59:59 +0000 | [diff] [blame] | 403 | /// register onto the stack in the prolog and restore it in the epilog of the |
| 404 | /// function. |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 405 | static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { |
Chris Lattner | 3fc027d | 2007-12-08 06:59:59 +0000 | [diff] [blame] | 406 | const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); |
| 407 | |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 408 | // We need a save/restore of LR if there is any def of LR (which is |
| 409 | // defined by calls, including the PIC setup sequence), or if there is |
| 410 | // some use of the LR stack slot (e.g. for builtin_return_address). |
| 411 | // (LR comes in 32 and 64 bit versions.) |
| 412 | MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); |
| 413 | return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 414 | } |
| 415 | |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 416 | |
| 417 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 418 | void PPCRegisterInfo:: |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 419 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 420 | MachineBasicBlock::iterator I) const { |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 421 | if (PerformTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 422 | // Add (actually subtract) back the amount the callee popped on return. |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 423 | if (int CalleeAmt = I->getOperand(1).getImm()) { |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 424 | bool is64Bit = Subtarget.isPPC64(); |
| 425 | CalleeAmt *= -1; |
| 426 | unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; |
| 427 | unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; |
| 428 | unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; |
| 429 | unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; |
| 430 | unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; |
| 431 | unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 432 | MachineInstr *MI = I; |
| 433 | DebugLoc dl = MI->getDebugLoc(); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 434 | |
| 435 | if (isInt16(CalleeAmt)) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 436 | BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 437 | addImm(CalleeAmt); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 438 | } else { |
| 439 | MachineBasicBlock::iterator MBBI = I; |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 440 | BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 441 | .addImm(CalleeAmt >> 16); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 442 | BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 443 | .addReg(TmpReg, RegState::Kill) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 444 | .addImm(CalleeAmt & 0xFFFF); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 445 | BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 446 | .addReg(StackReg) |
| 447 | .addReg(StackReg) |
| 448 | .addReg(TmpReg); |
| 449 | } |
| 450 | } |
| 451 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 452 | // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 453 | MBB.erase(I); |
| 454 | } |
| 455 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 456 | /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered |
| 457 | /// register first and then a spilled callee-saved register if that fails. |
| 458 | static |
| 459 | unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, |
| 460 | const TargetRegisterClass *RC, int SPAdj) { |
| 461 | assert(RS && "Register scavenging must be on"); |
| 462 | unsigned Reg = RS->FindUnusedReg(RC, true); |
| 463 | // FIXME: move ARM callee-saved reg scan to target independent code, then |
| 464 | // search for already spilled CS register here. |
| 465 | if (Reg == 0) |
| 466 | Reg = RS->scavengeRegister(RC, II, SPAdj); |
| 467 | return Reg; |
| 468 | } |
| 469 | |
| 470 | /// lowerDynamicAlloc - Generate the code for allocating an object in the |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 471 | /// current frame. The sequence of code with be in the general form |
| 472 | /// |
Dan Gohman | 0f8b53f | 2009-03-03 02:55:14 +0000 | [diff] [blame] | 473 | /// addi R0, SP, \#frameSize ; get the address of the previous frame |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 474 | /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size |
Dan Gohman | 0f8b53f | 2009-03-03 02:55:14 +0000 | [diff] [blame] | 475 | /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 476 | /// |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 477 | void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, |
| 478 | int SPAdj, RegScavenger *RS) const { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 479 | // Get the instruction. |
| 480 | MachineInstr &MI = *II; |
| 481 | // Get the instruction's basic block. |
| 482 | MachineBasicBlock &MBB = *MI.getParent(); |
| 483 | // Get the basic block's function. |
| 484 | MachineFunction &MF = *MBB.getParent(); |
| 485 | // Get the frame info. |
| 486 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 487 | // Determine whether 64-bit pointers are used. |
| 488 | bool LP64 = Subtarget.isPPC64(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 489 | DebugLoc dl = MI.getDebugLoc(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 490 | |
Evan Cheng | fab0439 | 2007-01-25 22:48:25 +0000 | [diff] [blame] | 491 | // Get the maximum call stack size. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 492 | unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 493 | // Get the total frame size. |
| 494 | unsigned FrameSize = MFI->getStackSize(); |
| 495 | |
| 496 | // Get stack alignments. |
| 497 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 498 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Jim Laskey | d6fa8c1 | 2006-11-17 18:49:39 +0000 | [diff] [blame] | 499 | assert(MaxAlign <= TargetAlign && |
| 500 | "Dynamic alloca with large aligns not supported"); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 501 | |
| 502 | // Determine the previous frame's address. If FrameSize can't be |
| 503 | // represented as 16 bits or we need special alignment, then we load the |
| 504 | // previous frame's address from 0(SP). Why not do an addis of the hi? |
| 505 | // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. |
| 506 | // Constructing the constant and adding would take 3 instructions. |
| 507 | // Fortunately, a frame greater than 32K is rare. |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 508 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
| 509 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
| 510 | const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; |
| 511 | |
| 512 | // FIXME (64-bit): Use "findScratchRegister" |
| 513 | unsigned Reg; |
Bill Wendling | 4a66e9a | 2008-03-10 22:49:16 +0000 | [diff] [blame] | 514 | if (EnableRegisterScavenging) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 515 | Reg = findScratchRegister(II, RS, RC, SPAdj); |
| 516 | else |
| 517 | Reg = PPC::R0; |
| 518 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 519 | if (MaxAlign < TargetAlign && isInt16(FrameSize)) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 520 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 521 | .addReg(PPC::R31) |
| 522 | .addImm(FrameSize); |
| 523 | } else if (LP64) { |
Bill Wendling | 4a66e9a | 2008-03-10 22:49:16 +0000 | [diff] [blame] | 524 | if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 525 | BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 526 | .addImm(0) |
| 527 | .addReg(PPC::X1); |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 528 | else |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 529 | BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 530 | .addImm(0) |
| 531 | .addReg(PPC::X1); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 532 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 533 | BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 534 | .addImm(0) |
| 535 | .addReg(PPC::R1); |
| 536 | } |
| 537 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 538 | // Grow the stack and update the stack pointer link, then determine the |
| 539 | // address of new allocated space. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 540 | if (LP64) { |
Bill Wendling | 4a66e9a | 2008-03-10 22:49:16 +0000 | [diff] [blame] | 541 | if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 542 | BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 543 | .addReg(Reg, RegState::Kill) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 544 | .addReg(PPC::X1) |
| 545 | .addReg(MI.getOperand(1).getReg()); |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 546 | else |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 547 | BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 548 | .addReg(PPC::X0, RegState::Kill) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 549 | .addReg(PPC::X1) |
| 550 | .addReg(MI.getOperand(1).getReg()); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 551 | |
| 552 | if (!MI.getOperand(1).isKill()) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 553 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 554 | .addReg(PPC::X1) |
| 555 | .addImm(maxCallFrameSize); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 556 | else |
| 557 | // Implicitly kill the register. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 558 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 559 | .addReg(PPC::X1) |
| 560 | .addImm(maxCallFrameSize) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 561 | .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 562 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 563 | BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 564 | .addReg(Reg, RegState::Kill) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 565 | .addReg(PPC::R1) |
| 566 | .addReg(MI.getOperand(1).getReg()); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 567 | |
| 568 | if (!MI.getOperand(1).isKill()) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 569 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 570 | .addReg(PPC::R1) |
| 571 | .addImm(maxCallFrameSize); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 572 | else |
| 573 | // Implicitly kill the register. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 574 | BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 575 | .addReg(PPC::R1) |
| 576 | .addImm(maxCallFrameSize) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 577 | .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 578 | } |
| 579 | |
| 580 | // Discard the DYNALLOC instruction. |
| 581 | MBB.erase(II); |
| 582 | } |
| 583 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 584 | /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of |
| 585 | /// reserving a whole register (R0), we scrounge for one here. This generates |
| 586 | /// code like this: |
| 587 | /// |
| 588 | /// mfcr rA ; Move the conditional register into GPR rA. |
| 589 | /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. |
| 590 | /// stw rA, FI ; Store rA to the frame. |
| 591 | /// |
| 592 | void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, |
| 593 | unsigned FrameIndex, int SPAdj, |
| 594 | RegScavenger *RS) const { |
| 595 | // Get the instruction. |
| 596 | MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> |
| 597 | // Get the instruction's basic block. |
| 598 | MachineBasicBlock &MBB = *MI.getParent(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 599 | DebugLoc dl = MI.getDebugLoc(); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 600 | |
| 601 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
| 602 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
| 603 | const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; |
| 604 | unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); |
| 605 | |
Bill Wendling | 2b5fab6 | 2008-03-04 23:27:33 +0000 | [diff] [blame] | 606 | // We need to store the CR in the low 4-bits of the saved value. First, issue |
| 607 | // an MFCR to save all of the CRBits. Add an implicit kill of the CR. |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 608 | if (!MI.getOperand(0).isKill()) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 609 | BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 610 | else |
| 611 | // Implicitly kill the CR register. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 612 | BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 613 | .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill); |
Bill Wendling | 2b5fab6 | 2008-03-04 23:27:33 +0000 | [diff] [blame] | 614 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 615 | // If the saved register wasn't CR0, shift the bits left so that they are in |
| 616 | // CR0's slot. |
| 617 | unsigned SrcReg = MI.getOperand(0).getReg(); |
| 618 | if (SrcReg != PPC::CR0) |
| 619 | // rlwinm rA, rA, ShiftBits, 0, 31. |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 620 | BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 621 | .addReg(Reg, RegState::Kill) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 622 | .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) |
| 623 | .addImm(0) |
| 624 | .addImm(31); |
| 625 | |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 626 | addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 627 | .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 628 | FrameIndex); |
| 629 | |
| 630 | // Discard the pseudo instruction. |
| 631 | MBB.erase(II); |
| 632 | } |
| 633 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 634 | void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 635 | int SPAdj, RegScavenger *RS) const { |
| 636 | assert(SPAdj == 0 && "Unexpected"); |
| 637 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 638 | // Get the instruction. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 639 | MachineInstr &MI = *II; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 640 | // Get the instruction's basic block. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 641 | MachineBasicBlock &MBB = *MI.getParent(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 642 | // Get the basic block's function. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 643 | MachineFunction &MF = *MBB.getParent(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 644 | // Get the frame info. |
| 645 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 646 | DebugLoc dl = MI.getDebugLoc(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 647 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 648 | // Find out which operand is the frame index. |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 649 | unsigned FIOperandNo = 0; |
Dan Gohman | d735b80 | 2008-10-03 15:45:36 +0000 | [diff] [blame] | 650 | while (!MI.getOperand(FIOperandNo).isFI()) { |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 651 | ++FIOperandNo; |
| 652 | assert(FIOperandNo != MI.getNumOperands() && |
| 653 | "Instr doesn't have FrameIndex operand!"); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 654 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 655 | // Take into account whether it's an add or mem instruction |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 656 | unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; |
Chris Lattner | 9aa2895 | 2007-02-01 00:39:08 +0000 | [diff] [blame] | 657 | if (MI.getOpcode() == TargetInstrInfo::INLINEASM) |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 658 | OffsetOperandNo = FIOperandNo-1; |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 659 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 660 | // Get the frame index. |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 661 | int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 662 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 663 | // Get the frame pointer save index. Users of this index are primarily |
| 664 | // DYNALLOC instructions. |
| 665 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 666 | int FPSI = FI->getFramePointerSaveIndex(); |
| 667 | // Get the instruction opcode. |
| 668 | unsigned OpC = MI.getOpcode(); |
| 669 | |
| 670 | // Special case for dynamic alloca. |
| 671 | if (FPSI && FrameIndex == FPSI && |
| 672 | (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 673 | lowerDynamicAlloc(II, SPAdj, RS); |
| 674 | return; |
| 675 | } |
| 676 | |
| 677 | // Special case for pseudo-op SPILL_CR. |
Bill Wendling | 4a66e9a | 2008-03-10 22:49:16 +0000 | [diff] [blame] | 678 | if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 679 | if (OpC == PPC::SPILL_CR) { |
| 680 | lowerCRSpilling(II, FrameIndex, SPAdj, RS); |
| 681 | return; |
| 682 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 683 | |
| 684 | // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 685 | MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, |
| 686 | false); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 687 | |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 688 | // Figure out if the offset in the instruction is shifted right two bits. This |
| 689 | // is true for instructions like "STD", which the machine implicitly adds two |
| 690 | // low zeros to. |
| 691 | bool isIXAddr = false; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 692 | switch (OpC) { |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 693 | case PPC::LWA: |
| 694 | case PPC::LD: |
| 695 | case PPC::STD: |
| 696 | case PPC::STD_32: |
| 697 | isIXAddr = true; |
| 698 | break; |
| 699 | } |
| 700 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 701 | // Now add the frame object offset to the offset from r1. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 702 | int Offset = MFI->getObjectOffset(FrameIndex); |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 703 | if (!isIXAddr) |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 704 | Offset += MI.getOperand(OffsetOperandNo).getImm(); |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 705 | else |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 706 | Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 707 | |
| 708 | // If we're not using a Frame Pointer that has been set to the value of the |
| 709 | // SP before having the stack size subtracted from it, then add the stack size |
| 710 | // to Offset to get the correct offset. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 711 | Offset += MFI->getStackSize(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 712 | |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 713 | // If we can, encode the offset directly into the instruction. If this is a |
| 714 | // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If |
| 715 | // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits |
| 716 | // clear can be encoded. This is extremely uncommon, because normally you |
| 717 | // only "std" to a stack slot that is at least 4-byte aligned, but it can |
| 718 | // happen in invalid code. |
Chris Lattner | d964285 | 2007-12-08 07:04:58 +0000 | [diff] [blame] | 719 | if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) { |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 720 | if (isIXAddr) |
Chris Lattner | 841d12d | 2005-10-18 16:51:22 +0000 | [diff] [blame] | 721 | Offset >>= 2; // The actual encoded value has the low two bits zero. |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 722 | MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 723 | return; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 724 | } |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 725 | |
| 726 | // The offset doesn't fit into a single register, scavenge one to build the |
| 727 | // offset in. |
| 728 | // FIXME: figure out what SPAdj is doing here. |
| 729 | |
| 730 | // FIXME (64-bit): Use "findScratchRegister". |
| 731 | unsigned SReg; |
Bill Wendling | 4a66e9a | 2008-03-10 22:49:16 +0000 | [diff] [blame] | 732 | if (EnableRegisterScavenging) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 733 | SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); |
| 734 | else |
| 735 | SReg = PPC::R0; |
| 736 | |
| 737 | // Insert a set of rA with the full offset value before the ld, st, or add |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 738 | BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 739 | .addImm(Offset >> 16); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 740 | BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 741 | .addReg(SReg, RegState::Kill) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 742 | .addImm(Offset); |
| 743 | |
| 744 | // Convert into indexed form of the instruction: |
| 745 | // |
| 746 | // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 |
| 747 | // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 748 | unsigned OperandBase; |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 749 | |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 750 | if (OpC != TargetInstrInfo::INLINEASM) { |
| 751 | assert(ImmToIdxMap.count(OpC) && |
| 752 | "No indexed form of load or store available!"); |
| 753 | unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; |
Chris Lattner | 5080f4d | 2008-01-11 18:10:50 +0000 | [diff] [blame] | 754 | MI.setDesc(TII.get(NewOpcode)); |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 755 | OperandBase = 1; |
| 756 | } else { |
| 757 | OperandBase = OffsetOperandNo; |
| 758 | } |
| 759 | |
| 760 | unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); |
| 761 | MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 762 | MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 763 | } |
| 764 | |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 765 | /// VRRegNo - Map from a numbered VR register to its enum value. |
| 766 | /// |
| 767 | static const unsigned short VRRegNo[] = { |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 768 | PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , |
| 769 | PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 770 | PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 771 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 |
| 772 | }; |
| 773 | |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 774 | /// RemoveVRSaveCode - We have found that this function does not need any code |
| 775 | /// to manipulate the VRSAVE register, even though it uses vector registers. |
| 776 | /// This can happen when the only registers used are known to be live in or out |
| 777 | /// of the function. Remove all of the VRSAVE related code from the function. |
| 778 | static void RemoveVRSaveCode(MachineInstr *MI) { |
| 779 | MachineBasicBlock *Entry = MI->getParent(); |
| 780 | MachineFunction *MF = Entry->getParent(); |
| 781 | |
| 782 | // We know that the MTVRSAVE instruction immediately follows MI. Remove it. |
| 783 | MachineBasicBlock::iterator MBBI = MI; |
| 784 | ++MBBI; |
| 785 | assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); |
| 786 | MBBI->eraseFromParent(); |
| 787 | |
| 788 | bool RemovedAllMTVRSAVEs = true; |
| 789 | // See if we can find and remove the MTVRSAVE instruction from all of the |
| 790 | // epilog blocks. |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 791 | for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { |
| 792 | // If last instruction is a return instruction, add an epilogue |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 793 | if (!I->empty() && I->back().getDesc().isReturn()) { |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 794 | bool FoundIt = false; |
| 795 | for (MBBI = I->end(); MBBI != I->begin(); ) { |
| 796 | --MBBI; |
| 797 | if (MBBI->getOpcode() == PPC::MTVRSAVE) { |
| 798 | MBBI->eraseFromParent(); // remove it. |
| 799 | FoundIt = true; |
| 800 | break; |
| 801 | } |
| 802 | } |
| 803 | RemovedAllMTVRSAVEs &= FoundIt; |
| 804 | } |
| 805 | } |
| 806 | |
| 807 | // If we found and removed all MTVRSAVE instructions, remove the read of |
| 808 | // VRSAVE as well. |
| 809 | if (RemovedAllMTVRSAVEs) { |
| 810 | MBBI = MI; |
| 811 | assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); |
| 812 | --MBBI; |
| 813 | assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); |
| 814 | MBBI->eraseFromParent(); |
| 815 | } |
| 816 | |
| 817 | // Finally, nuke the UPDATE_VRSAVE. |
| 818 | MI->eraseFromParent(); |
| 819 | } |
| 820 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 821 | // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the |
| 822 | // instruction selector. Based on the vector registers that have been used, |
| 823 | // transform this into the appropriate ORI instruction. |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 824 | static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { |
| 825 | MachineFunction *MF = MI->getParent()->getParent(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 826 | DebugLoc dl = MI->getDebugLoc(); |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 827 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 828 | unsigned UsedRegMask = 0; |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 829 | for (unsigned i = 0; i != 32; ++i) |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 830 | if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 831 | UsedRegMask |= 1 << (31-i); |
| 832 | |
Chris Lattner | 402504b | 2006-04-17 21:22:06 +0000 | [diff] [blame] | 833 | // Live in and live out values already must be in the mask, so don't bother |
| 834 | // marking them. |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 835 | for (MachineRegisterInfo::livein_iterator |
| 836 | I = MF->getRegInfo().livein_begin(), |
| 837 | E = MF->getRegInfo().livein_end(); I != E; ++I) { |
Chris Lattner | 402504b | 2006-04-17 21:22:06 +0000 | [diff] [blame] | 838 | unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); |
| 839 | if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. |
| 840 | UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. |
| 841 | } |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 842 | for (MachineRegisterInfo::liveout_iterator |
| 843 | I = MF->getRegInfo().liveout_begin(), |
| 844 | E = MF->getRegInfo().liveout_end(); I != E; ++I) { |
Chris Lattner | 402504b | 2006-04-17 21:22:06 +0000 | [diff] [blame] | 845 | unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); |
| 846 | if (VRRegNo[RegNo] == *I) // If this really is a vector reg. |
| 847 | UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. |
| 848 | } |
| 849 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 850 | // If no registers are used, turn this into a copy. |
| 851 | if (UsedRegMask == 0) { |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 852 | // Remove all VRSAVE code. |
| 853 | RemoveVRSaveCode(MI); |
| 854 | return; |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 855 | } |
| 856 | |
| 857 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 858 | unsigned DstReg = MI->getOperand(0).getReg(); |
| 859 | |
| 860 | if ((UsedRegMask & 0xFFFF) == UsedRegMask) { |
| 861 | if (DstReg != SrcReg) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 862 | BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 863 | .addReg(SrcReg) |
| 864 | .addImm(UsedRegMask); |
| 865 | else |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 866 | BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 867 | .addReg(SrcReg, RegState::Kill) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 868 | .addImm(UsedRegMask); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 869 | } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 870 | if (DstReg != SrcReg) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 871 | BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 872 | .addReg(SrcReg) |
| 873 | .addImm(UsedRegMask >> 16); |
| 874 | else |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 875 | BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 876 | .addReg(SrcReg, RegState::Kill) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 877 | .addImm(UsedRegMask >> 16); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 878 | } else { |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 879 | if (DstReg != SrcReg) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 880 | BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 881 | .addReg(SrcReg) |
| 882 | .addImm(UsedRegMask >> 16); |
| 883 | else |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 884 | BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 885 | .addReg(SrcReg, RegState::Kill) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 886 | .addImm(UsedRegMask >> 16); |
| 887 | |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 888 | BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 889 | .addReg(DstReg, RegState::Kill) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 890 | .addImm(UsedRegMask & 0xFFFF); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 891 | } |
| 892 | |
| 893 | // Remove the old UPDATE_VRSAVE instruction. |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 894 | MI->eraseFromParent(); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 895 | } |
| 896 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 897 | /// determineFrameLayout - Determine the size of the frame and maximum call |
| 898 | /// frame size. |
| 899 | void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { |
| 900 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 901 | |
| 902 | // Get the number of bytes to allocate from the FrameInfo |
| 903 | unsigned FrameSize = MFI->getStackSize(); |
| 904 | |
| 905 | // Get the alignments provided by the target, and the maximum alignment |
| 906 | // (if any) of the fixed frame objects. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 907 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Evan Cheng | 99403b6 | 2007-01-25 22:25:04 +0000 | [diff] [blame] | 908 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 909 | unsigned AlignMask = TargetAlign - 1; // |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 910 | |
| 911 | // If we are a leaf function, and use up to 224 bytes of stack space, |
| 912 | // don't have a frame pointer, calls, or dynamic alloca then we do not need |
| 913 | // to adjust the stack pointer (we fit in the Red Zone). |
Devang Patel | d18e31a | 2009-06-04 22:05:33 +0000 | [diff] [blame] | 914 | bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 915 | // FIXME SVR4 The SVR4 ABI has no red zone. |
Dan Gohman | 9e79091 | 2009-01-27 19:19:28 +0000 | [diff] [blame] | 916 | if (!DisableRedZone && |
| 917 | FrameSize <= 224 && // Fits in red zone. |
Dale Johannesen | 82e4289 | 2008-03-10 22:59:46 +0000 | [diff] [blame] | 918 | !MFI->hasVarSizedObjects() && // No dynamic alloca. |
| 919 | !MFI->hasCalls() && // No calls. |
| 920 | (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 921 | // No need for frame |
| 922 | MFI->setStackSize(0); |
| 923 | return; |
| 924 | } |
| 925 | |
| 926 | // Get the maximum call frame size of all the calls. |
| 927 | unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); |
| 928 | |
| 929 | // Maximum call frame needs to be at least big enough for linkage and 8 args. |
| 930 | unsigned minCallFrameSize = |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 931 | PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), |
| 932 | Subtarget.isMachoABI()); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 933 | maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); |
| 934 | |
| 935 | // If we have dynamic alloca then maxCallFrameSize needs to be aligned so |
| 936 | // that allocations will be aligned. |
| 937 | if (MFI->hasVarSizedObjects()) |
| 938 | maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; |
| 939 | |
| 940 | // Update maximum call frame size. |
| 941 | MFI->setMaxCallFrameSize(maxCallFrameSize); |
| 942 | |
| 943 | // Include call frame size in total. |
| 944 | FrameSize += maxCallFrameSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 945 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 946 | // Make sure the frame is aligned. |
| 947 | FrameSize = (FrameSize + AlignMask) & ~AlignMask; |
| 948 | |
| 949 | // Update frame info. |
| 950 | MFI->setStackSize(FrameSize); |
| 951 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 952 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 953 | void |
| 954 | PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, |
| 955 | RegScavenger *RS) const { |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 956 | // Save and clear the LR state. |
| 957 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 958 | unsigned LR = getRARegister(); |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 959 | FI->setMustSaveLR(MustSaveLR(MF, LR)); |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 960 | MF.getRegInfo().setPhysRegUnused(LR); |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 961 | |
| 962 | // Save R31 if necessary |
| 963 | int FPSI = FI->getFramePointerSaveIndex(); |
| 964 | bool IsPPC64 = Subtarget.isPPC64(); |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 965 | bool IsELF32_ABI = Subtarget.isELF32_ABI(); |
| 966 | bool IsMachoABI = Subtarget.isMachoABI(); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 967 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 968 | |
| 969 | // If the frame pointer save index hasn't been defined yet. |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 970 | if (!FPSI && needsFP(MF) && IsELF32_ABI) { |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 971 | // Find out what the fix offset of the frame pointer save area. |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 972 | int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, |
| 973 | IsMachoABI); |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 974 | // Allocate the frame index for frame pointer save area. |
| 975 | FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); |
| 976 | // Save the result. |
| 977 | FI->setFramePointerSaveIndex(FPSI); |
| 978 | } |
| 979 | |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 980 | // Reserve stack space to move the linkage area to in case of a tail call. |
| 981 | int TCSPDelta = 0; |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 982 | if (PerformTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { |
| 983 | MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 984 | } |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 985 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 986 | // Reserve a slot closest to SP or frame pointer if we have a dynalloc or |
| 987 | // a large stack, which will require scavenging a register to materialize a |
| 988 | // large offset. |
| 989 | // FIXME: this doesn't actually check stack size, so is a bit pessimistic |
| 990 | // FIXME: doesn't detect whether or not we need to spill vXX, which requires |
| 991 | // r0 for now. |
| 992 | |
Bill Wendling | 4a66e9a | 2008-03-10 22:49:16 +0000 | [diff] [blame] | 993 | if (EnableRegisterScavenging) // FIXME (64-bit): Enable. |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 994 | if (needsFP(MF) || spillsCR(MF)) { |
| 995 | const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; |
| 996 | const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |
| 997 | const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; |
| 998 | RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), |
Chris Lattner | 71a2cb2 | 2008-03-20 01:22:40 +0000 | [diff] [blame] | 999 | RC->getAlignment())); |
Bill Wendling | 880d0f6 | 2008-03-04 23:13:51 +0000 | [diff] [blame] | 1000 | } |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1001 | } |
| 1002 | |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1003 | void |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 1004 | PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) |
| 1005 | const { |
| 1006 | // Early exit if not using the SVR4 ABI. |
| 1007 | if (!Subtarget.isELF32_ABI()) { |
| 1008 | return; |
| 1009 | } |
| 1010 | |
| 1011 | // Get callee saved register information. |
| 1012 | MachineFrameInfo *FFI = MF.getFrameInfo(); |
| 1013 | const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); |
| 1014 | |
| 1015 | // Early exit if no callee saved registers are modified! |
| 1016 | if (CSI.empty() && !needsFP(MF)) { |
| 1017 | return; |
| 1018 | } |
| 1019 | |
| 1020 | unsigned MinGPR = PPC::R31; |
| 1021 | unsigned MinFPR = PPC::F31; |
| 1022 | unsigned MinVR = PPC::V31; |
| 1023 | |
| 1024 | bool HasGPSaveArea = false; |
| 1025 | bool HasFPSaveArea = false; |
| 1026 | bool HasCRSaveArea = false; |
| 1027 | bool HasVRSAVESaveArea = false; |
| 1028 | bool HasVRSaveArea = false; |
| 1029 | |
| 1030 | SmallVector<CalleeSavedInfo, 18> GPRegs; |
| 1031 | SmallVector<CalleeSavedInfo, 18> FPRegs; |
| 1032 | SmallVector<CalleeSavedInfo, 18> VRegs; |
| 1033 | |
| 1034 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 1035 | unsigned Reg = CSI[i].getReg(); |
| 1036 | const TargetRegisterClass *RC = CSI[i].getRegClass(); |
| 1037 | |
| 1038 | if (RC == PPC::GPRCRegisterClass) { |
| 1039 | HasGPSaveArea = true; |
| 1040 | |
| 1041 | GPRegs.push_back(CSI[i]); |
| 1042 | |
| 1043 | if (Reg < MinGPR) { |
| 1044 | MinGPR = Reg; |
| 1045 | } |
| 1046 | } else if (RC == PPC::F8RCRegisterClass) { |
| 1047 | HasFPSaveArea = true; |
| 1048 | |
| 1049 | FPRegs.push_back(CSI[i]); |
| 1050 | |
| 1051 | if (Reg < MinFPR) { |
| 1052 | MinFPR = Reg; |
| 1053 | } |
| 1054 | } else if ( RC == PPC::CRBITRCRegisterClass |
| 1055 | || RC == PPC::CRRCRegisterClass) { |
| 1056 | HasCRSaveArea = true; |
| 1057 | } else if (RC == PPC::VRSAVERCRegisterClass) { |
| 1058 | HasVRSAVESaveArea = true; |
| 1059 | } else if (RC == PPC::VRRCRegisterClass) { |
| 1060 | HasVRSaveArea = true; |
| 1061 | |
| 1062 | VRegs.push_back(CSI[i]); |
| 1063 | |
| 1064 | if (Reg < MinVR) { |
| 1065 | MinVR = Reg; |
| 1066 | } |
| 1067 | } else { |
| 1068 | assert(0 && "Unknown RegisterClass!"); |
| 1069 | } |
| 1070 | } |
| 1071 | |
| 1072 | PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); |
| 1073 | |
| 1074 | int64_t LowerBound = 0; |
| 1075 | |
| 1076 | // Take into account stack space reserved for tail calls. |
| 1077 | int TCSPDelta = 0; |
| 1078 | if (PerformTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { |
| 1079 | LowerBound = TCSPDelta; |
| 1080 | } |
| 1081 | |
| 1082 | // The Floating-point register save area is right below the back chain word |
| 1083 | // of the previous stack frame. |
| 1084 | if (HasFPSaveArea) { |
| 1085 | for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { |
| 1086 | int FI = FPRegs[i].getFrameIdx(); |
| 1087 | |
| 1088 | FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); |
| 1089 | } |
| 1090 | |
| 1091 | LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8; |
| 1092 | } |
| 1093 | |
| 1094 | // Check whether the frame pointer register is allocated. If so, make sure it |
| 1095 | // is spilled to the correct offset. |
| 1096 | if (needsFP(MF)) { |
| 1097 | HasGPSaveArea = true; |
| 1098 | |
| 1099 | int FI = PFI->getFramePointerSaveIndex(); |
| 1100 | assert(FI && "No Frame Pointer Save Slot!"); |
| 1101 | |
| 1102 | FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); |
| 1103 | } |
| 1104 | |
| 1105 | // General register save area starts right below the Floating-point |
| 1106 | // register save area. |
| 1107 | if (HasGPSaveArea) { |
| 1108 | // Move general register save area spill slots down, taking into account |
| 1109 | // the size of the Floating-point register save area. |
| 1110 | for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { |
| 1111 | int FI = GPRegs[i].getFrameIdx(); |
| 1112 | |
| 1113 | FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); |
| 1114 | } |
| 1115 | |
| 1116 | LowerBound -= (31 - getRegisterNumbering(MinGPR) + 1) * 4; |
| 1117 | } |
| 1118 | |
| 1119 | // The CR save area is below the general register save area. |
| 1120 | if (HasCRSaveArea) { |
| 1121 | // FIXME SVR4: Is it actually possible to have multiple elements in CSI |
| 1122 | // which have the CR/CRBIT register class? |
| 1123 | // Adjust the frame index of the CR spill slot. |
| 1124 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 1125 | const TargetRegisterClass *RC = CSI[i].getRegClass(); |
| 1126 | |
| 1127 | if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) { |
| 1128 | int FI = CSI[i].getFrameIdx(); |
| 1129 | |
| 1130 | FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); |
| 1131 | } |
| 1132 | } |
| 1133 | |
| 1134 | LowerBound -= 4; // The CR save area is always 4 bytes long. |
| 1135 | } |
| 1136 | |
| 1137 | if (HasVRSAVESaveArea) { |
| 1138 | // FIXME SVR4: Is it actually possible to have multiple elements in CSI |
| 1139 | // which have the VRSAVE register class? |
| 1140 | // Adjust the frame index of the VRSAVE spill slot. |
| 1141 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 1142 | const TargetRegisterClass *RC = CSI[i].getRegClass(); |
| 1143 | |
| 1144 | if (RC == PPC::VRSAVERCRegisterClass) { |
| 1145 | int FI = CSI[i].getFrameIdx(); |
| 1146 | |
| 1147 | FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); |
| 1148 | } |
| 1149 | } |
| 1150 | |
| 1151 | LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. |
| 1152 | } |
| 1153 | |
| 1154 | if (HasVRSaveArea) { |
| 1155 | // Insert alignment padding, we need 16-byte alignment. |
| 1156 | LowerBound = (LowerBound - 15) & ~(15); |
| 1157 | |
| 1158 | for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { |
| 1159 | int FI = VRegs[i].getFrameIdx(); |
| 1160 | |
| 1161 | FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); |
| 1162 | } |
| 1163 | } |
| 1164 | } |
| 1165 | |
| 1166 | void |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1167 | PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1168 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
| 1169 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 1170 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1171 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1172 | DebugLoc dl = DebugLoc::getUnknownLoc(); |
Dale Johannesen | e004062 | 2008-04-02 17:04:45 +0000 | [diff] [blame] | 1173 | bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || |
Dale Johannesen | 4e1b794 | 2008-04-08 00:10:24 +0000 | [diff] [blame] | 1174 | !MF.getFunction()->doesNotThrow() || |
Dale Johannesen | 3541af7 | 2008-04-14 17:54:17 +0000 | [diff] [blame] | 1175 | UnwindTablesMandatory; |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 1176 | |
Jim Laskey | 072200c | 2007-01-29 18:51:14 +0000 | [diff] [blame] | 1177 | // Prepare for frame info. |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1178 | unsigned FrameLabelId = 0; |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1179 | |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 1180 | // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, |
| 1181 | // process it. |
Chris Lattner | 8aa777d | 2006-03-16 21:31:45 +0000 | [diff] [blame] | 1182 | for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 1183 | if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1184 | HandleVRSaveUpdate(MBBI, TII); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 1185 | break; |
| 1186 | } |
| 1187 | } |
| 1188 | |
| 1189 | // Move MBBI back to the beginning of the function. |
| 1190 | MBBI = MBB.begin(); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1191 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1192 | // Work out frame sizes. |
| 1193 | determineFrameLayout(MF); |
| 1194 | unsigned FrameSize = MFI->getStackSize(); |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 1195 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1196 | int NegFrameSize = -FrameSize; |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1197 | |
| 1198 | // Get processor type. |
| 1199 | bool IsPPC64 = Subtarget.isPPC64(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1200 | // Get operating system |
| 1201 | bool IsMachoABI = Subtarget.isMachoABI(); |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1202 | // Check if the link register (LR) must be saved. |
| 1203 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 1204 | bool MustSaveLR = FI->mustSaveLR(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1205 | // Do we have a frame pointer for this function? |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1206 | bool HasFP = hasFP(MF) && FrameSize; |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1207 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1208 | int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 1209 | |
| 1210 | int FPOffset = 0; |
| 1211 | if (HasFP) { |
| 1212 | if (Subtarget.isELF32_ABI()) { |
| 1213 | MachineFrameInfo *FFI = MF.getFrameInfo(); |
| 1214 | int FPIndex = FI->getFramePointerSaveIndex(); |
| 1215 | assert(FPIndex && "No Frame Pointer Save Slot!"); |
| 1216 | FPOffset = FFI->getObjectOffset(FPIndex); |
| 1217 | } else { |
| 1218 | FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); |
| 1219 | } |
| 1220 | } |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1221 | |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1222 | if (IsPPC64) { |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1223 | if (MustSaveLR) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1224 | BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1225 | |
| 1226 | if (HasFP) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1227 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1228 | .addReg(PPC::X31) |
| 1229 | .addImm(FPOffset/4) |
| 1230 | .addReg(PPC::X1); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1231 | |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1232 | if (MustSaveLR) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1233 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1234 | .addReg(PPC::X0) |
| 1235 | .addImm(LROffset / 4) |
| 1236 | .addReg(PPC::X1); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1237 | } else { |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1238 | if (MustSaveLR) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1239 | BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1240 | |
| 1241 | if (HasFP) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1242 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1243 | .addReg(PPC::R31) |
| 1244 | .addImm(FPOffset) |
| 1245 | .addReg(PPC::R1); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1246 | |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1247 | if (MustSaveLR) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1248 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1249 | .addReg(PPC::R0) |
| 1250 | .addImm(LROffset) |
| 1251 | .addReg(PPC::R1); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1252 | } |
| 1253 | |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1254 | // Skip if a leaf routine. |
| 1255 | if (!FrameSize) return; |
| 1256 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1257 | // Get stack alignments. |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 1258 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 1259 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1260 | |
Dale Johannesen | e004062 | 2008-04-02 17:04:45 +0000 | [diff] [blame] | 1261 | if (needsFrameMoves) { |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1262 | // Mark effective beginning of when frame pointer becomes valid. |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1263 | FrameLabelId = MMI->NextLabelID(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1264 | BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId); |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1265 | } |
| 1266 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1267 | // Adjust stack pointer: r1 += NegFrameSize. |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 1268 | // If there is a preferred stack alignment, align R1 now |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1269 | if (!IsPPC64) { |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1270 | // PPC32. |
Dale Johannesen | 82e4289 | 2008-03-10 22:59:46 +0000 | [diff] [blame] | 1271 | if (ALIGN_STACK && MaxAlign > TargetAlign) { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1272 | assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); |
| 1273 | assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1274 | |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1275 | BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1276 | .addReg(PPC::R1) |
| 1277 | .addImm(0) |
| 1278 | .addImm(32 - Log2_32(MaxAlign)) |
| 1279 | .addImm(31); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1280 | BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 1281 | .addReg(PPC::R0, RegState::Kill) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1282 | .addImm(NegFrameSize); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1283 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1284 | .addReg(PPC::R1) |
| 1285 | .addReg(PPC::R1) |
| 1286 | .addReg(PPC::R0); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1287 | } else if (isInt16(NegFrameSize)) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1288 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1289 | .addReg(PPC::R1) |
| 1290 | .addImm(NegFrameSize) |
| 1291 | .addReg(PPC::R1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1292 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1293 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1294 | .addImm(NegFrameSize >> 16); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1295 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 1296 | .addReg(PPC::R0, RegState::Kill) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1297 | .addImm(NegFrameSize & 0xFFFF); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1298 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1299 | .addReg(PPC::R1) |
| 1300 | .addReg(PPC::R1) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1301 | .addReg(PPC::R0); |
| 1302 | } |
| 1303 | } else { // PPC64. |
Dale Johannesen | 82e4289 | 2008-03-10 22:59:46 +0000 | [diff] [blame] | 1304 | if (ALIGN_STACK && MaxAlign > TargetAlign) { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1305 | assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); |
| 1306 | assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1307 | |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1308 | BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1309 | .addReg(PPC::X1) |
| 1310 | .addImm(0) |
| 1311 | .addImm(64 - Log2_32(MaxAlign)); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1312 | BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1313 | .addReg(PPC::X0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1314 | .addImm(NegFrameSize); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1315 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1316 | .addReg(PPC::X1) |
| 1317 | .addReg(PPC::X1) |
| 1318 | .addReg(PPC::X0); |
Jim Laskey | 2ff5cdb | 2006-11-17 16:09:31 +0000 | [diff] [blame] | 1319 | } else if (isInt16(NegFrameSize)) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1320 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1321 | .addReg(PPC::X1) |
| 1322 | .addImm(NegFrameSize / 4) |
| 1323 | .addReg(PPC::X1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1324 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1325 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1326 | .addImm(NegFrameSize >> 16); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1327 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 1328 | .addReg(PPC::X0, RegState::Kill) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1329 | .addImm(NegFrameSize & 0xFFFF); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1330 | BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1331 | .addReg(PPC::X1) |
| 1332 | .addReg(PPC::X1) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1333 | .addReg(PPC::X0); |
| 1334 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1335 | } |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 1336 | |
Dale Johannesen | e004062 | 2008-04-02 17:04:45 +0000 | [diff] [blame] | 1337 | if (needsFrameMoves) { |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1338 | std::vector<MachineMove> &Moves = MMI->getFrameMoves(); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1339 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1340 | if (NegFrameSize) { |
| 1341 | // Show update of SP. |
| 1342 | MachineLocation SPDst(MachineLocation::VirtualFP); |
| 1343 | MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); |
| 1344 | Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); |
| 1345 | } else { |
| 1346 | MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); |
| 1347 | Moves.push_back(MachineMove(FrameLabelId, SP, SP)); |
| 1348 | } |
Jim Laskey | 4c2c903 | 2006-08-25 19:40:59 +0000 | [diff] [blame] | 1349 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1350 | if (HasFP) { |
| 1351 | MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); |
| 1352 | MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); |
| 1353 | Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); |
| 1354 | } |
Jim Laskey | ce50a16 | 2006-08-29 16:24:26 +0000 | [diff] [blame] | 1355 | |
| 1356 | // Add callee saved registers to move list. |
| 1357 | const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); |
| 1358 | for (unsigned I = 0, E = CSI.size(); I != E; ++I) { |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1359 | int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); |
| 1360 | unsigned Reg = CSI[I].getReg(); |
Dale Johannesen | b384ab9 | 2008-10-29 18:26:45 +0000 | [diff] [blame] | 1361 | if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1362 | MachineLocation CSDst(MachineLocation::VirtualFP, Offset); |
| 1363 | MachineLocation CSSrc(Reg); |
| 1364 | Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); |
Jim Laskey | ce50a16 | 2006-08-29 16:24:26 +0000 | [diff] [blame] | 1365 | } |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1366 | |
Jim Laskey | b82313f | 2007-02-01 16:31:34 +0000 | [diff] [blame] | 1367 | MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); |
| 1368 | MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); |
| 1369 | Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); |
| 1370 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1371 | // Mark effective beginning of when frame pointer is ready. |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1372 | unsigned ReadyLabelId = MMI->NextLabelID(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1373 | BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId); |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1374 | |
| 1375 | MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : |
| 1376 | (IsPPC64 ? PPC::X1 : PPC::R1)); |
| 1377 | MachineLocation FPSrc(MachineLocation::VirtualFP); |
| 1378 | Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1379 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1380 | |
| 1381 | // If there is a frame pointer, copy R1 into R31 |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 1382 | if (HasFP) { |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1383 | if (!IsPPC64) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1384 | BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1385 | .addReg(PPC::R1) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1386 | .addReg(PPC::R1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1387 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1388 | BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) |
Bill Wendling | 7194aaf | 2008-03-03 22:19:16 +0000 | [diff] [blame] | 1389 | .addReg(PPC::X1) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1390 | .addReg(PPC::X1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1391 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1392 | } |
| 1393 | } |
| 1394 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1395 | void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, |
| 1396 | MachineBasicBlock &MBB) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1397 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1398 | unsigned RetOpcode = MBBI->getOpcode(); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1399 | DebugLoc dl = DebugLoc::getUnknownLoc(); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1400 | |
| 1401 | assert( (RetOpcode == PPC::BLR || |
| 1402 | RetOpcode == PPC::TCRETURNri || |
| 1403 | RetOpcode == PPC::TCRETURNdi || |
| 1404 | RetOpcode == PPC::TCRETURNai || |
| 1405 | RetOpcode == PPC::TCRETURNri8 || |
| 1406 | RetOpcode == PPC::TCRETURNdi8 || |
| 1407 | RetOpcode == PPC::TCRETURNai8) && |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1408 | "Can only insert epilog into returning blocks"); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 1409 | |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 1410 | // Get alignment info so we know how to restore r1 |
| 1411 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1412 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1413 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 1414 | |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 1415 | // Get the number of bytes allocated from the FrameInfo. |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1416 | int FrameSize = MFI->getStackSize(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1417 | |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1418 | // Get processor type. |
| 1419 | bool IsPPC64 = Subtarget.isPPC64(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1420 | // Get operating system |
| 1421 | bool IsMachoABI = Subtarget.isMachoABI(); |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1422 | // Check if the link register (LR) has been saved. |
| 1423 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 1424 | bool MustSaveLR = FI->mustSaveLR(); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1425 | // Do we have a frame pointer for this function? |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1426 | bool HasFP = hasFP(MF) && FrameSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1427 | |
| 1428 | int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); |
Tilmann Scheller | ffd0200 | 2009-07-03 06:45:56 +0000 | [diff] [blame^] | 1429 | |
| 1430 | int FPOffset = 0; |
| 1431 | if (HasFP) { |
| 1432 | if (Subtarget.isELF32_ABI()) { |
| 1433 | MachineFrameInfo *FFI = MF.getFrameInfo(); |
| 1434 | int FPIndex = FI->getFramePointerSaveIndex(); |
| 1435 | assert(FPIndex && "No Frame Pointer Save Slot!"); |
| 1436 | FPOffset = FFI->getObjectOffset(FPIndex); |
| 1437 | } else { |
| 1438 | FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); |
| 1439 | } |
| 1440 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1441 | |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1442 | bool UsesTCRet = RetOpcode == PPC::TCRETURNri || |
| 1443 | RetOpcode == PPC::TCRETURNdi || |
| 1444 | RetOpcode == PPC::TCRETURNai || |
| 1445 | RetOpcode == PPC::TCRETURNri8 || |
| 1446 | RetOpcode == PPC::TCRETURNdi8 || |
| 1447 | RetOpcode == PPC::TCRETURNai8; |
| 1448 | |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1449 | if (UsesTCRet) { |
| 1450 | int MaxTCRetDelta = FI->getTailCallSPDelta(); |
| 1451 | MachineOperand &StackAdjust = MBBI->getOperand(1); |
Dan Gohman | d735b80 | 2008-10-03 15:45:36 +0000 | [diff] [blame] | 1452 | assert(StackAdjust.isImm() && "Expecting immediate value."); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1453 | // Adjust stack pointer. |
| 1454 | int StackAdj = StackAdjust.getImm(); |
| 1455 | int Delta = StackAdj - MaxTCRetDelta; |
| 1456 | assert((Delta >= 0) && "Delta must be positive"); |
| 1457 | if (MaxTCRetDelta>0) |
| 1458 | FrameSize += (StackAdj +Delta); |
| 1459 | else |
| 1460 | FrameSize += StackAdj; |
| 1461 | } |
| 1462 | |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1463 | if (FrameSize) { |
| 1464 | // The loaded (or persistent) stack pointer value is offset by the 'stwu' |
| 1465 | // on entry to the function. Add this offset back now. |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1466 | if (!IsPPC64) { |
| 1467 | // If this function contained a fastcc call and PerformTailCallOpt is |
| 1468 | // enabled (=> hasFastCall()==true) the fastcc call might contain a tail |
| 1469 | // call which invalidates the stack pointer value in SP(0). So we use the |
| 1470 | // value of R31 in this case. |
| 1471 | if (FI->hasFastCall() && isInt16(FrameSize)) { |
| 1472 | assert(hasFP(MF) && "Expecting a valid the frame pointer."); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1473 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1474 | .addReg(PPC::R31).addImm(FrameSize); |
| 1475 | } else if(FI->hasFastCall()) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1476 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1477 | .addImm(FrameSize >> 16); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1478 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 1479 | .addReg(PPC::R0, RegState::Kill) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1480 | .addImm(FrameSize & 0xFFFF); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1481 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1482 | .addReg(PPC::R1) |
| 1483 | .addReg(PPC::R31) |
| 1484 | .addReg(PPC::R0); |
| 1485 | } else if (isInt16(FrameSize) && |
| 1486 | (!ALIGN_STACK || TargetAlign >= MaxAlign) && |
| 1487 | !MFI->hasVarSizedObjects()) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1488 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1489 | .addReg(PPC::R1).addImm(FrameSize); |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1490 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1491 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) |
| 1492 | .addImm(0).addReg(PPC::R1); |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1493 | } |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 1494 | } else { |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1495 | if (FI->hasFastCall() && isInt16(FrameSize)) { |
| 1496 | assert(hasFP(MF) && "Expecting a valid the frame pointer."); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1497 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1498 | .addReg(PPC::X31).addImm(FrameSize); |
| 1499 | } else if(FI->hasFastCall()) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1500 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1501 | .addImm(FrameSize >> 16); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1502 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 1503 | .addReg(PPC::X0, RegState::Kill) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1504 | .addImm(FrameSize & 0xFFFF); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1505 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1506 | .addReg(PPC::X1) |
| 1507 | .addReg(PPC::X31) |
| 1508 | .addReg(PPC::X0); |
| 1509 | } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign && |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1510 | !MFI->hasVarSizedObjects()) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1511 | BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1512 | .addReg(PPC::X1).addImm(FrameSize); |
| 1513 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1514 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) |
| 1515 | .addImm(0).addReg(PPC::X1); |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1516 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1517 | } |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1518 | } |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1519 | |
| 1520 | if (IsPPC64) { |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1521 | if (MustSaveLR) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1522 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1523 | .addImm(LROffset/4).addReg(PPC::X1); |
| 1524 | |
| 1525 | if (HasFP) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1526 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1527 | .addImm(FPOffset/4).addReg(PPC::X1); |
| 1528 | |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1529 | if (MustSaveLR) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1530 | BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1531 | } else { |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1532 | if (MustSaveLR) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1533 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1534 | .addImm(LROffset).addReg(PPC::R1); |
| 1535 | |
| 1536 | if (HasFP) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1537 | BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1538 | .addImm(FPOffset).addReg(PPC::R1); |
| 1539 | |
Dale Johannesen | c12e581 | 2008-10-24 21:24:23 +0000 | [diff] [blame] | 1540 | if (MustSaveLR) |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1541 | BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1542 | } |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1543 | |
| 1544 | // Callee pop calling convention. Pop parameter/linkage area. Used for tail |
| 1545 | // call optimization |
| 1546 | if (PerformTailCallOpt && RetOpcode == PPC::BLR && |
| 1547 | MF.getFunction()->getCallingConv() == CallingConv::Fast) { |
| 1548 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 1549 | unsigned CallerAllocatedAmt = FI->getMinReservedArea(); |
| 1550 | unsigned StackReg = IsPPC64 ? PPC::X1 : PPC::R1; |
| 1551 | unsigned FPReg = IsPPC64 ? PPC::X31 : PPC::R31; |
| 1552 | unsigned TmpReg = IsPPC64 ? PPC::X0 : PPC::R0; |
| 1553 | unsigned ADDIInstr = IsPPC64 ? PPC::ADDI8 : PPC::ADDI; |
| 1554 | unsigned ADDInstr = IsPPC64 ? PPC::ADD8 : PPC::ADD4; |
| 1555 | unsigned LISInstr = IsPPC64 ? PPC::LIS8 : PPC::LIS; |
| 1556 | unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI; |
| 1557 | |
| 1558 | if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1559 | BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1560 | .addReg(StackReg).addImm(CallerAllocatedAmt); |
| 1561 | } else { |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1562 | BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1563 | .addImm(CallerAllocatedAmt >> 16); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1564 | BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) |
Bill Wendling | 587daed | 2009-05-13 21:33:08 +0000 | [diff] [blame] | 1565 | .addReg(TmpReg, RegState::Kill) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1566 | .addImm(CallerAllocatedAmt & 0xFFFF); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1567 | BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1568 | .addReg(StackReg) |
| 1569 | .addReg(FPReg) |
| 1570 | .addReg(TmpReg); |
| 1571 | } |
| 1572 | } else if (RetOpcode == PPC::TCRETURNdi) { |
| 1573 | MBBI = prior(MBB.end()); |
| 1574 | MachineOperand &JumpTarget = MBBI->getOperand(0); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1575 | BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1576 | addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); |
| 1577 | } else if (RetOpcode == PPC::TCRETURNri) { |
| 1578 | MBBI = prior(MBB.end()); |
Chris Lattner | 022a27e | 2009-03-26 05:25:59 +0000 | [diff] [blame] | 1579 | assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1580 | BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1581 | } else if (RetOpcode == PPC::TCRETURNai) { |
| 1582 | MBBI = prior(MBB.end()); |
| 1583 | MachineOperand &JumpTarget = MBBI->getOperand(0); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1584 | BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1585 | } else if (RetOpcode == PPC::TCRETURNdi8) { |
| 1586 | MBBI = prior(MBB.end()); |
| 1587 | MachineOperand &JumpTarget = MBBI->getOperand(0); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1588 | BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1589 | addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); |
| 1590 | } else if (RetOpcode == PPC::TCRETURNri8) { |
| 1591 | MBBI = prior(MBB.end()); |
Chris Lattner | 022a27e | 2009-03-26 05:25:59 +0000 | [diff] [blame] | 1592 | assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1593 | BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1594 | } else if (RetOpcode == PPC::TCRETURNai8) { |
| 1595 | MBBI = prior(MBB.end()); |
| 1596 | MachineOperand &JumpTarget = MBBI->getOperand(0); |
Dale Johannesen | 536a2f1 | 2009-02-13 02:27:39 +0000 | [diff] [blame] | 1597 | BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1598 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1599 | } |
| 1600 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1601 | unsigned PPCRegisterInfo::getRARegister() const { |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 1602 | return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1603 | } |
| 1604 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 1605 | unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1606 | if (!Subtarget.isPPC64()) |
| 1607 | return hasFP(MF) ? PPC::R31 : PPC::R1; |
| 1608 | else |
| 1609 | return hasFP(MF) ? PPC::X31 : PPC::X1; |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1610 | } |
| 1611 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1612 | void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1613 | const { |
Jim Laskey | 4c2c903 | 2006-08-25 19:40:59 +0000 | [diff] [blame] | 1614 | // Initial state of the frame pointer is R1. |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1615 | MachineLocation Dst(MachineLocation::VirtualFP); |
| 1616 | MachineLocation Src(PPC::R1, 0); |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1617 | Moves.push_back(MachineMove(0, Dst, Src)); |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 1618 | } |
| 1619 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 1620 | unsigned PPCRegisterInfo::getEHExceptionRegister() const { |
| 1621 | return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; |
| 1622 | } |
| 1623 | |
| 1624 | unsigned PPCRegisterInfo::getEHHandlerRegister() const { |
| 1625 | return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; |
| 1626 | } |
| 1627 | |
Dale Johannesen | b97aec6 | 2007-11-13 19:13:01 +0000 | [diff] [blame] | 1628 | int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { |
Anton Korobeynikov | 3809fbe | 2007-11-12 23:36:13 +0000 | [diff] [blame] | 1629 | // FIXME: Most probably dwarf numbers differs for Linux and Darwin |
| 1630 | return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 1631 | } |
| 1632 | |
Chris Lattner | 4c7b43b | 2005-10-14 23:37:35 +0000 | [diff] [blame] | 1633 | #include "PPCGenRegisterInfo.inc" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1634 | |