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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 35d4912e3b08a8a2d0e01c0ef8b23407f8efa8db / . / lib / Target / ARM / ARMScheduleV7.td
blob: ead022ab24a03c5b235e098cbde0bb7e15d1156a [file] [log] [blame]
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]1//===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM v7 processors.
11//
12//===----------------------------------------------------------------------===//
13
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]14//
15// Scheduling information derived from "Cortex-A8 Technical Reference Manual".
16//
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]17// Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]18//
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]19def CortexA8Itineraries : ProcessorItineraries<[
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]20
21 // Two fully-pipelined integer ALU pipelines
22 //
23 // No operand cycles
24 InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
25 //
26 // Binary Instructions that produce a result
27 InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
28 InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
29 InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
30 InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
31 //
32 // Unary Instructions that produce a result
33 InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
34 InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
35 InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
36 //
37 // Compare instructions
38 InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
39 InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
40 InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
41 InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
42 //
43 // Move instructions, unconditional
44 InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
45 InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
46 InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
47 InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
48 //
49 // Move instructions, conditional
50 InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
51 InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
52 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
53 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
54
55 // Integer multiply pipeline
56 // Result written in E5, but that is relative to the last cycle of multicycle,
57 // so we use 6 for those cases
58 //
59 InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
60 InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe1], 0>,
61 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
62 InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe1], 0>,
63 InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
64 InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe1], 0>,
65 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
66 InstrItinData<IIC_iMUL64 , [InstrStage<2, [FU_Pipe1], 0>,
67 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
68 InstrItinData<IIC_iMAC64 , [InstrStage<2, [FU_Pipe1], 0>,
69 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
70
71 // Integer load pipeline
72 //
David Goodwin48e13592009-08-10 15:56:13 +0000[diff] [blame]73 // loads have an extra cycle of latency, but are fully pipelined
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]74 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]75 //
76 // Immediate offset
77 InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Issue], 0>,
78 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
79 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
80 //
81 // Register offset
82 InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Issue], 0>,
83 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
84 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
85 //
86 // Scaled register offset, issues over 2 cycles
87 InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Issue], 0>,
88 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]89 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]90 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
91 InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
92 //
93 // Immediate offset with update
94 InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Issue], 0>,
95 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
96 InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
97 //
98 // Register offset with update
99 InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Issue], 0>,
100 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
101 InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
102 //
103 // Scaled register offset with update, issues over 2 cycles
104 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
105 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]106 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]107 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
108 InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
109 //
110 // Load multiple
111 InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Issue], 0>,
112 InstrStage<2, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]113 InstrStage<2, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]114 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
115 InstrStage<1, [FU_LdSt0]>]>,
116
117 // Integer store pipeline
118 //
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]119 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]120 //
121 // Immediate offset
122 InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Issue], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]123 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
124 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]125 //
126 // Register offset
127 InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Issue], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]128 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
129 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]130 //
131 // Scaled register offset, issues over 2 cycles
132 InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
133 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]134 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]135 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
136 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
137 //
138 // Immediate offset with update
139 InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
140 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
141 InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
142 //
143 // Register offset with update
144 InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Issue], 0>,
145 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
146 InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
147 //
148 // Scaled register offset with update, issues over 2 cycles
149 InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
150 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]151 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]152 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
153 InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
154 //
155 // Store multiple
156 InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Issue], 0>,
157 InstrStage<2, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]158 InstrStage<2, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]159 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
160 InstrStage<1, [FU_LdSt0]>]>,
161
162 // Branch
163 //
David Goodwin48e13592009-08-10 15:56:13 +0000[diff] [blame]164 // no delay slots, so the latency of a branch is unimportant
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]165 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
166
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]167 // VFP
168 // Issue through integer pipeline, and execute in NEON unit. We assume
169 // RunFast mode so that NFP pipeline is used for single-precision when
170 // possible.
171 //
172 // FP Special Register to Integer Register File Move
173 InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
174 InstrStage<1, [FU_NLSPipe], 1>]>,
175 //
176 // Integer to Single-Precision FP Register File Move
177 InstrItinData<IIC_fpMOVIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
178 InstrStage<1, [FU_NLSPipe], 1>]>,
179 //
180 // Integer to Double-Precision FP Register File Move
181 InstrItinData<IIC_fpMOVID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
182 InstrStage<1, [FU_NLSPipe], 1>]>,
183 //
184 // Single-Precision FP to Integer Register File Move
185 InstrItinData<IIC_fpMOVSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
186 InstrStage<1, [FU_NLSPipe], 1>], [20, 1]>,
187 //
188 // Double-Precision FP to Integer Register File Move
189 InstrItinData<IIC_fpMOVDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
190 InstrStage<1, [FU_NLSPipe], 1>], [20, 20, 1]>,
191 //
192 // Single-precision FP Unary
193 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
194 InstrStage<1, [FU_NPipe]>], [7, 1]>,
195 //
196 // Double-precision FP Unary
197 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
198 InstrStage<4, [FU_NPipe], 0>,
199 InstrStage<4, [FU_NLSPipe]>]>,
200 //
201 // Single-precision FP Compare
202 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
203 InstrStage<1, [FU_NPipe]>], [7, 1]>,
204 //
205 // Double-precision FP Compare
206 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
207 InstrStage<4, [FU_NPipe], 0>,
208 InstrStage<4, [FU_NLSPipe]>]>,
209 //
210 // Single to Double FP Convert
211 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
212 InstrStage<7, [FU_NPipe], 0>,
213 InstrStage<7, [FU_NLSPipe]>]>,
214 //
215 // Double to Single FP Convert
216 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
217 InstrStage<5, [FU_NPipe], 0>,
218 InstrStage<5, [FU_NLSPipe]>]>,
219 //
220 // Single-Precision FP to Integer Convert
221 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
222 InstrStage<1, [FU_NPipe]>], [7, 1]>,
223 //
224 // Double-Precision FP to Integer Convert
225 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
226 InstrStage<8, [FU_NPipe], 0>,
227 InstrStage<8, [FU_NLSPipe]>]>,
228 //
229 // Integer to Single-Precision FP Convert
230 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
231 InstrStage<1, [FU_NPipe]>], [7, 1]>,
232 //
233 // Integer to Double-Precision FP Convert
234 InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
235 InstrStage<8, [FU_NPipe], 0>,
236 InstrStage<8, [FU_NLSPipe]>]>,
237 //
238 // Single-precision FP ALU
239 InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
240 InstrStage<1, [FU_NPipe]>], [7, 1]>,
241 //
242 // Double-precision FP ALU
243 InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
244 InstrStage<9, [FU_NPipe], 0>,
245 InstrStage<9, [FU_NLSPipe]>]>,
246 //
247 // Single-precision FP Multiply
248 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
249 InstrStage<1, [FU_NPipe]>], [7, 1]>,
250 //
251 // Double-precision FP Multiply
252 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
253 InstrStage<11, [FU_NPipe], 0>,
254 InstrStage<11, [FU_NLSPipe]>]>,
255 //
256 // Single-precision FP MAC
257 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
258 InstrStage<1, [FU_NPipe]>], [7, 1]>,
259 //
260 // Double-precision FP MAC
261 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
262 InstrStage<19, [FU_NPipe], 0>,
263 InstrStage<19, [FU_NLSPipe]>]>,
264 //
265 // Single-precision FP DIV
266 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
267 InstrStage<20, [FU_NPipe], 0>,
268 InstrStage<20, [FU_NLSPipe]>]>,
269 //
270 // Double-precision FP DIV
271 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
272 InstrStage<29, [FU_NPipe], 0>,
273 InstrStage<29, [FU_NLSPipe]>]>,
274 //
275 // Single-precision FP SQRT
276 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
277 InstrStage<19, [FU_NPipe], 0>,
278 InstrStage<19, [FU_NLSPipe]>]>,
279 //
280 // Double-precision FP SQRT
281 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
282 InstrStage<29, [FU_NPipe], 0>,
283 InstrStage<29, [FU_NLSPipe]>]>,
284 //
285 // Single-precision FP Load
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]286 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]287 InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_Issue], 0>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]288 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]289 InstrStage<1, [FU_LdSt0], 0>,
290 InstrStage<1, [FU_NLSPipe]>]>,
291 //
292 // Double-precision FP Load
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]293 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]294 InstrItinData<IIC_fpLoad64, [InstrStage<2, [FU_Issue], 0>,
295 InstrStage<1, [FU_Pipe0], 0>,
296 InstrStage<1, [FU_Pipe1]>,
297 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
298 InstrStage<1, [FU_LdSt0], 0>,
299 InstrStage<1, [FU_NLSPipe]>]>,
300 //
301 // FP Load Multiple
302 // use FU_Issue to enforce the 1 load/store per cycle limit
303 InstrItinData<IIC_fpLoadm, [InstrStage<3, [FU_Issue], 0>,
304 InstrStage<2, [FU_Pipe0], 0>,
305 InstrStage<2, [FU_Pipe1]>,
306 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
307 InstrStage<1, [FU_LdSt0], 0>,
308 InstrStage<1, [FU_NLSPipe]>]>,
309 //
310 // Single-precision FP Store
311 // use FU_Issue to enforce the 1 load/store per cycle limit
312 InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_Issue], 0>,
313 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
314 InstrStage<1, [FU_LdSt0], 0>,
315 InstrStage<1, [FU_NLSPipe]>]>,
316 //
317 // Double-precision FP Store
318 // use FU_Issue to enforce the 1 load/store per cycle limit
319 InstrItinData<IIC_fpStore64,[InstrStage<2, [FU_Issue], 0>,
320 InstrStage<1, [FU_Pipe0], 0>,
321 InstrStage<1, [FU_Pipe1]>,
322 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
323 InstrStage<1, [FU_LdSt0], 0>,
324 InstrStage<1, [FU_NLSPipe]>]>,
325 //
326 // FP Store Multiple
327 // use FU_Issue to enforce the 1 load/store per cycle limit
328 InstrItinData<IIC_fpStore64,[InstrStage<3, [FU_Issue], 0>,
329 InstrStage<2, [FU_Pipe0], 0>,
330 InstrStage<2, [FU_Pipe1]>,
331 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
332 InstrStage<1, [FU_LdSt0], 0>,
333 InstrStage<1, [FU_NLSPipe]>]>
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]334]>;
335
336// FIXME
337def CortexA9Itineraries : ProcessorItineraries<[
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]338 InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
339 InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
340 InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
341 InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
342 InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
343 InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
344 InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
345 InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
346 InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
347 InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
348 InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
349 InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
350 InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
351 InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
352 InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
353 InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
354 InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
355 InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
356 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
357 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
358 InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
359 InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
360 InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
361 InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
362 InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
363 InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
364 InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
Evan Chengff5c7c42009-08-15 07:59:10 +0000[diff] [blame]365 InstrStage<1, [FU_LdSt0]>]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]366 InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
367 InstrStage<1, [FU_LdSt0]>]>,
368 InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
369 InstrStage<1, [FU_LdSt0]>]>,
370 InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
371 InstrStage<1, [FU_LdSt0]>]>,
372 InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
373 InstrStage<1, [FU_LdSt0]>]>,
374 InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
375 InstrStage<1, [FU_LdSt0]>]>,
376 InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
377 InstrStage<2, [FU_LdSt0]>]>,
378 InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
379 InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
380 InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
381 InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
382 InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
383 InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
384 InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame^]385 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
386 InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0]>]>,
387 InstrItinData<IIC_fpMOVSI , [InstrStage<1, [FU_Pipe0]>]>,
388 InstrItinData<IIC_fpMOVDI , [InstrStage<1, [FU_Pipe0]>]>,
389 InstrItinData<IIC_fpMOVIS , [InstrStage<1, [FU_Pipe0]>]>,
390 InstrItinData<IIC_fpMOVID , [InstrStage<1, [FU_Pipe0]>]>,
391 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0]>]>,
392 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0]>]>,
393 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0]>]>,
394 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0]>]>,
395 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0]>]>,
396 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0]>]>,
397 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0]>]>,
398 InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0]>]>,
399 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0]>]>,
400 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0]>]>,
401 InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0]>]>,
402 InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0]>]>,
403 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
404 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
405 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
406 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
407 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0]>]>,
408 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0]>]>,
409 InstrItinData<IIC_fpSQRT32 , [InstrStage<1, [FU_Pipe0]>]>,
410 InstrItinData<IIC_fpSQRT64 , [InstrStage<1, [FU_Pipe0]>]>,
411 InstrItinData<IIC_fpLoad32 , [InstrStage<1, [FU_Pipe0]>,
412 InstrStage<1, [FU_LdSt0]>]>,
413 InstrItinData<IIC_fpLoad64 , [InstrStage<1, [FU_Pipe0]>,
414 InstrStage<1, [FU_LdSt0]>]>,
415 InstrItinData<IIC_fpLoadm , [InstrStage<1, [FU_Pipe0]>,
416 InstrStage<1, [FU_LdSt0]>]>,
417 InstrItinData<IIC_fpStore32, [InstrStage<1, [FU_Pipe0]>]>,
418 InstrItinData<IIC_fpStore64, [InstrStage<1, [FU_Pipe0]>]>,
419 InstrItinData<IIC_fpStorem , [InstrStage<1, [FU_Pipe0]>]>
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]420]>;