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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 5211b42949b3302635f8b8c869aa84430708b357 / . / lib / Target / X86 / X86.td
blob: 8867298abb8120b7d2bd1ef31a968228d4b067d9 [file] [log] [blame]
Arnold Schwaighofer373e8652007-10-12 21:30:57 +0000[diff] [blame]1//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This is a target description file for the Intel i386 architecture, refered to
11// here as the "X86" architecture.
12//
13//===----------------------------------------------------------------------===//
14
15// Get the target-independent interfaces which we are implementing...
16//
Evan Cheng301aaf52008-11-24 07:34:46 +0000[diff] [blame]17include "llvm/Target/Target.td"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]18
19//===----------------------------------------------------------------------===//
20// X86 Subtarget features.
21//===----------------------------------------------------------------------===//
22
23def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
24 "Enable MMX instructions">;
25def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
26 "Enable SSE instructions",
27 [FeatureMMX]>;
28def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
29 "Enable SSE2 instructions",
30 [FeatureSSE1]>;
31def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
32 "Enable SSE3 instructions",
33 [FeatureSSE2]>;
34def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
35 "Enable SSSE3 instructions",
36 [FeatureSSE3]>;
Nate Begemanb2975562008-02-03 07:18:54 +0000[diff] [blame]37def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
38 "Enable SSE 4.1 instructions",
39 [FeatureSSSE3]>;
40def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
41 "Enable SSE 4.2 instructions",
42 [FeatureSSE41]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]43def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
44 "Enable 3DNow! instructions">;
45def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
46 "Enable 3DNow! Athlon instructions",
47 [Feature3DNow]>;
48def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
49 "Support 64-bit instructions",
50 [FeatureSSE2]>;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000[diff] [blame]51def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
52 "Bit testing of memory is slow">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]53
54//===----------------------------------------------------------------------===//
55// X86 processors supported.
56//===----------------------------------------------------------------------===//
57
58class Proc<string Name, list<SubtargetFeature> Features>
59 : Processor<Name, NoItineraries, Features>;
60
61def : Proc<"generic", []>;
62def : Proc<"i386", []>;
63def : Proc<"i486", []>;
Dale Johannesen68a99ca2008-10-14 22:06:33 +0000[diff] [blame]64def : Proc<"i586", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]65def : Proc<"pentium", []>;
66def : Proc<"pentium-mmx", [FeatureMMX]>;
67def : Proc<"i686", []>;
68def : Proc<"pentiumpro", []>;
69def : Proc<"pentium2", [FeatureMMX]>;
70def : Proc<"pentium3", [FeatureSSE1]>;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000[diff] [blame]71def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]72def : Proc<"pentium4", [FeatureSSE2]>;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000[diff] [blame]73def : Proc<"x86-64", [Feature64Bit, FeatureSlowBTMem]>;
74def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
75def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
76def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
77def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>;
78def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]79
80def : Proc<"k6", [FeatureMMX]>;
81def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
82def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000[diff] [blame]83def : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
84def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
85def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
86def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
87def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
88def : Proc<"k8", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
89def : Proc<"opteron", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
90def : Proc<"athlon64", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
91def : Proc<"athlon-fx", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]92
93def : Proc<"winchip-c6", [FeatureMMX]>;
94def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
95def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
96def : Proc<"c3-2", [FeatureSSE1]>;
97
98//===----------------------------------------------------------------------===//
99// Register File Description
100//===----------------------------------------------------------------------===//
101
102include "X86RegisterInfo.td"
103
104//===----------------------------------------------------------------------===//
105// Instruction Descriptions
106//===----------------------------------------------------------------------===//
107
108include "X86InstrInfo.td"
109
110def X86InstrInfo : InstrInfo {
111
112 // Define how we want to layout our TargetSpecific information field... This
113 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
114 let TSFlagsFields = ["FormBits",
115 "hasOpSizePrefix",
116 "hasAdSizePrefix",
117 "Prefix",
118 "hasREX_WPrefix",
119 "ImmTypeBits",
120 "FPFormBits",
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +0000[diff] [blame]121 "hasLockPrefix",
Anton Korobeynikov975e1472008-10-11 19:09:15 +0000[diff] [blame]122 "SegOvrBits",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]123 "Opcode"];
124 let TSFlagsShifts = [0,
125 6,
126 7,
127 8,
128 12,
129 13,
130 16,
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +0000[diff] [blame]131 19,
Anton Korobeynikov975e1472008-10-11 19:09:15 +0000[diff] [blame]132 20,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]133 24];
134}
135
136//===----------------------------------------------------------------------===//
137// Calling Conventions
138//===----------------------------------------------------------------------===//
139
140include "X86CallingConv.td"
141
142
143//===----------------------------------------------------------------------===//
144// Assembly Printers
145//===----------------------------------------------------------------------===//
146
147// The X86 target supports two different syntaxes for emitting machine code.
148// This is controlled by the -x86-asm-syntax={att|intel}
149def ATTAsmWriter : AsmWriter {
150 string AsmWriterClassName = "ATTAsmPrinter";
151 int Variant = 0;
152}
153def IntelAsmWriter : AsmWriter {
154 string AsmWriterClassName = "IntelAsmPrinter";
155 int Variant = 1;
156}
157
158
159def X86 : Target {
160 // Information about the instructions...
161 let InstructionSet = X86InstrInfo;
162
163 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
164}