Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file implements the VirtRegMap class. |
| 11 | // |
| 12 | // It also contains implementations of the the Spiller interface, which, given a |
| 13 | // virtual register map and a machine function, eliminates all virtual |
| 14 | // references by replacing them with physical register references - adding spill |
| 15 | // code as necessary. |
| 16 | // |
| 17 | //===----------------------------------------------------------------------===// |
| 18 | |
| 19 | #define DEBUG_TYPE "spiller" |
| 20 | #include "VirtRegMap.h" |
| 21 | #include "llvm/Function.h" |
| 22 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 23 | #include "llvm/CodeGen/MachineFunction.h" |
| 24 | #include "llvm/CodeGen/SSARegMap.h" |
| 25 | #include "llvm/Target/TargetMachine.h" |
| 26 | #include "llvm/Target/TargetInstrInfo.h" |
| 27 | #include "llvm/Support/CommandLine.h" |
| 28 | #include "llvm/Support/Debug.h" |
| 29 | #include "llvm/Support/Compiler.h" |
| 30 | #include "llvm/ADT/BitVector.h" |
| 31 | #include "llvm/ADT/Statistic.h" |
| 32 | #include "llvm/ADT/STLExtras.h" |
| 33 | #include "llvm/ADT/SmallSet.h" |
| 34 | #include <algorithm> |
| 35 | using namespace llvm; |
| 36 | |
| 37 | STATISTIC(NumSpills, "Number of register spills"); |
| 38 | STATISTIC(NumReMats, "Number of re-materialization"); |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 39 | STATISTIC(NumDRM , "Number of re-materializable defs elided"); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 40 | STATISTIC(NumStores, "Number of stores added"); |
| 41 | STATISTIC(NumLoads , "Number of loads added"); |
| 42 | STATISTIC(NumReused, "Number of values reused"); |
| 43 | STATISTIC(NumDSE , "Number of dead stores elided"); |
| 44 | STATISTIC(NumDCE , "Number of copies elided"); |
| 45 | |
| 46 | namespace { |
| 47 | enum SpillerName { simple, local }; |
| 48 | |
| 49 | static cl::opt<SpillerName> |
| 50 | SpillerOpt("spiller", |
| 51 | cl::desc("Spiller to use: (default: local)"), |
| 52 | cl::Prefix, |
| 53 | cl::values(clEnumVal(simple, " simple spiller"), |
| 54 | clEnumVal(local, " local spiller"), |
| 55 | clEnumValEnd), |
| 56 | cl::init(local)); |
| 57 | } |
| 58 | |
| 59 | //===----------------------------------------------------------------------===// |
| 60 | // VirtRegMap implementation |
| 61 | //===----------------------------------------------------------------------===// |
| 62 | |
| 63 | VirtRegMap::VirtRegMap(MachineFunction &mf) |
| 64 | : TII(*mf.getTarget().getInstrInfo()), MF(mf), |
| 65 | Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 66 | Virt2ReMatIdMap(NO_STACK_SLOT), ReMatMap(NULL), |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 67 | ReMatId(MAX_STACK_SLOT+1) { |
| 68 | grow(); |
| 69 | } |
| 70 | |
| 71 | void VirtRegMap::grow() { |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 72 | unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg(); |
| 73 | Virt2PhysMap.grow(LastVirtReg); |
| 74 | Virt2StackSlotMap.grow(LastVirtReg); |
| 75 | Virt2ReMatIdMap.grow(LastVirtReg); |
| 76 | ReMatMap.grow(LastVirtReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { |
| 80 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
| 81 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && |
| 82 | "attempt to assign stack slot to already spilled register"); |
| 83 | const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); |
| 84 | int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), |
| 85 | RC->getAlignment()); |
| 86 | Virt2StackSlotMap[virtReg] = frameIndex; |
| 87 | ++NumSpills; |
| 88 | return frameIndex; |
| 89 | } |
| 90 | |
| 91 | void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { |
| 92 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
| 93 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && |
| 94 | "attempt to assign stack slot to already spilled register"); |
| 95 | assert((frameIndex >= 0 || |
| 96 | (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) && |
| 97 | "illegal fixed frame index"); |
| 98 | Virt2StackSlotMap[virtReg] = frameIndex; |
| 99 | } |
| 100 | |
| 101 | int VirtRegMap::assignVirtReMatId(unsigned virtReg) { |
| 102 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 103 | assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 104 | "attempt to assign re-mat id to already spilled register"); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 105 | Virt2ReMatIdMap[virtReg] = ReMatId; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 106 | return ReMatId++; |
| 107 | } |
| 108 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 109 | void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { |
| 110 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
| 111 | assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && |
| 112 | "attempt to assign re-mat id to already spilled register"); |
| 113 | Virt2ReMatIdMap[virtReg] = id; |
| 114 | } |
| 115 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 116 | void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, |
| 117 | unsigned OpNo, MachineInstr *NewMI) { |
| 118 | // Move previous memory references folded to new instruction. |
| 119 | MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); |
| 120 | for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), |
| 121 | E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { |
| 122 | MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); |
| 123 | MI2VirtMap.erase(I++); |
| 124 | } |
| 125 | |
| 126 | ModRef MRInfo; |
| 127 | const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor(); |
| 128 | if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 || |
| 129 | TID->findTiedToSrcOperand(OpNo) != -1) { |
| 130 | // Folded a two-address operand. |
| 131 | MRInfo = isModRef; |
| 132 | } else if (OldMI->getOperand(OpNo).isDef()) { |
| 133 | MRInfo = isMod; |
| 134 | } else { |
| 135 | MRInfo = isRef; |
| 136 | } |
| 137 | |
| 138 | // add new memory reference |
| 139 | MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); |
| 140 | } |
| 141 | |
| 142 | void VirtRegMap::print(std::ostream &OS) const { |
| 143 | const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); |
| 144 | |
| 145 | OS << "********** REGISTER MAP **********\n"; |
| 146 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, |
| 147 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { |
| 148 | if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) |
| 149 | OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; |
| 150 | |
| 151 | } |
| 152 | |
| 153 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, |
| 154 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) |
| 155 | if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) |
| 156 | OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; |
| 157 | OS << '\n'; |
| 158 | } |
| 159 | |
| 160 | void VirtRegMap::dump() const { |
| 161 | print(DOUT); |
| 162 | } |
| 163 | |
| 164 | |
| 165 | //===----------------------------------------------------------------------===// |
| 166 | // Simple Spiller Implementation |
| 167 | //===----------------------------------------------------------------------===// |
| 168 | |
| 169 | Spiller::~Spiller() {} |
| 170 | |
| 171 | namespace { |
| 172 | struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { |
| 173 | bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); |
| 174 | }; |
| 175 | } |
| 176 | |
| 177 | bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { |
| 178 | DOUT << "********** REWRITE MACHINE CODE **********\n"; |
| 179 | DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; |
| 180 | const TargetMachine &TM = MF.getTarget(); |
| 181 | const MRegisterInfo &MRI = *TM.getRegisterInfo(); |
| 182 | |
| 183 | // LoadedRegs - Keep track of which vregs are loaded, so that we only load |
| 184 | // each vreg once (in the case where a spilled vreg is used by multiple |
| 185 | // operands). This is always smaller than the number of operands to the |
| 186 | // current machine instr, so it should be small. |
| 187 | std::vector<unsigned> LoadedRegs; |
| 188 | |
| 189 | for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); |
| 190 | MBBI != E; ++MBBI) { |
| 191 | DOUT << MBBI->getBasicBlock()->getName() << ":\n"; |
| 192 | MachineBasicBlock &MBB = *MBBI; |
| 193 | for (MachineBasicBlock::iterator MII = MBB.begin(), |
| 194 | E = MBB.end(); MII != E; ++MII) { |
| 195 | MachineInstr &MI = *MII; |
| 196 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 197 | MachineOperand &MO = MI.getOperand(i); |
| 198 | if (MO.isRegister() && MO.getReg()) |
| 199 | if (MRegisterInfo::isVirtualRegister(MO.getReg())) { |
| 200 | unsigned VirtReg = MO.getReg(); |
| 201 | unsigned PhysReg = VRM.getPhys(VirtReg); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 202 | if (!VRM.isAssignedReg(VirtReg)) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 203 | int StackSlot = VRM.getStackSlot(VirtReg); |
| 204 | const TargetRegisterClass* RC = |
| 205 | MF.getSSARegMap()->getRegClass(VirtReg); |
| 206 | |
| 207 | if (MO.isUse() && |
| 208 | std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) |
| 209 | == LoadedRegs.end()) { |
| 210 | MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); |
| 211 | LoadedRegs.push_back(VirtReg); |
| 212 | ++NumLoads; |
| 213 | DOUT << '\t' << *prior(MII); |
| 214 | } |
| 215 | |
| 216 | if (MO.isDef()) { |
| 217 | MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); |
| 218 | ++NumStores; |
| 219 | } |
| 220 | } |
| 221 | MF.setPhysRegUsed(PhysReg); |
| 222 | MI.getOperand(i).setReg(PhysReg); |
| 223 | } else { |
| 224 | MF.setPhysRegUsed(MO.getReg()); |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | DOUT << '\t' << MI; |
| 229 | LoadedRegs.clear(); |
| 230 | } |
| 231 | } |
| 232 | return true; |
| 233 | } |
| 234 | |
| 235 | //===----------------------------------------------------------------------===// |
| 236 | // Local Spiller Implementation |
| 237 | //===----------------------------------------------------------------------===// |
| 238 | |
| 239 | namespace { |
| 240 | /// LocalSpiller - This spiller does a simple pass over the machine basic |
| 241 | /// block to attempt to keep spills in registers as much as possible for |
| 242 | /// blocks that have low register pressure (the vreg may be spilled due to |
| 243 | /// register pressure in other blocks). |
| 244 | class VISIBILITY_HIDDEN LocalSpiller : public Spiller { |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 245 | SSARegMap *RegMap; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 246 | const MRegisterInfo *MRI; |
| 247 | const TargetInstrInfo *TII; |
| 248 | public: |
| 249 | bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 250 | RegMap = MF.getSSARegMap(); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 251 | MRI = MF.getTarget().getRegisterInfo(); |
| 252 | TII = MF.getTarget().getInstrInfo(); |
| 253 | DOUT << "\n**** Local spiller rewriting function '" |
| 254 | << MF.getFunction()->getName() << "':\n"; |
David Greene | a1c1e78 | 2007-09-06 16:36:39 +0000 | [diff] [blame] | 255 | DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n"; |
| 256 | DEBUG(MF.dump()); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 257 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 258 | for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); |
| 259 | MBB != E; ++MBB) |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 260 | RewriteMBB(*MBB, VRM); |
David Greene | a1c1e78 | 2007-09-06 16:36:39 +0000 | [diff] [blame] | 261 | |
| 262 | DOUT << "**** Post Machine Instrs ****\n"; |
| 263 | DEBUG(MF.dump()); |
| 264 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 265 | return true; |
| 266 | } |
| 267 | private: |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 268 | void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 269 | }; |
| 270 | } |
| 271 | |
| 272 | /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 273 | /// top down, keep track of which spills slots or remat are available in each |
| 274 | /// register. |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 275 | /// |
| 276 | /// Note that not all physregs are created equal here. In particular, some |
| 277 | /// physregs are reloads that we are allowed to clobber or ignore at any time. |
| 278 | /// Other physregs are values that the register allocated program is using that |
| 279 | /// we cannot CHANGE, but we can read if we like. We keep track of this on a |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 280 | /// per-stack-slot / remat id basis as the low bit in the value of the |
| 281 | /// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks |
| 282 | /// this bit and addAvailable sets it if. |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 283 | namespace { |
| 284 | class VISIBILITY_HIDDEN AvailableSpills { |
| 285 | const MRegisterInfo *MRI; |
| 286 | const TargetInstrInfo *TII; |
| 287 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 288 | // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled |
| 289 | // or remat'ed virtual register values that are still available, due to being |
| 290 | // loaded or stored to, but not invalidated yet. |
| 291 | std::map<int, unsigned> SpillSlotsOrReMatsAvailable; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 292 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 293 | // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable, |
| 294 | // indicating which stack slot values are currently held by a physreg. This |
| 295 | // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a |
| 296 | // physreg is modified. |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 297 | std::multimap<unsigned, int> PhysRegsAvailable; |
| 298 | |
| 299 | void disallowClobberPhysRegOnly(unsigned PhysReg); |
| 300 | |
| 301 | void ClobberPhysRegOnly(unsigned PhysReg); |
| 302 | public: |
| 303 | AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) |
| 304 | : MRI(mri), TII(tii) { |
| 305 | } |
| 306 | |
| 307 | const MRegisterInfo *getRegInfo() const { return MRI; } |
| 308 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 309 | /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is |
| 310 | /// available in a physical register, return that PhysReg, otherwise |
| 311 | /// return 0. |
| 312 | unsigned getSpillSlotOrReMatPhysReg(int Slot) const { |
| 313 | std::map<int, unsigned>::const_iterator I = |
| 314 | SpillSlotsOrReMatsAvailable.find(Slot); |
| 315 | if (I != SpillSlotsOrReMatsAvailable.end()) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 316 | return I->second >> 1; // Remove the CanClobber bit. |
| 317 | } |
| 318 | return 0; |
| 319 | } |
| 320 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 321 | /// addAvailable - Mark that the specified stack slot / remat is available in |
| 322 | /// the specified physreg. If CanClobber is true, the physreg can be modified |
| 323 | /// at any time without changing the semantics of the program. |
| 324 | void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 325 | bool CanClobber = true) { |
| 326 | // If this stack slot is thought to be available in some other physreg, |
| 327 | // remove its record. |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 328 | ModifyStackSlotOrReMat(SlotOrReMat); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 329 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 330 | PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat)); |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 331 | SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 332 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 333 | if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) |
| 334 | DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 335 | else |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 336 | DOUT << "Remembering SS#" << SlotOrReMat; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 337 | DOUT << " in physreg " << MRI->getName(Reg) << "\n"; |
| 338 | } |
| 339 | |
| 340 | /// canClobberPhysReg - Return true if the spiller is allowed to change the |
| 341 | /// value of the specified stackslot register if it desires. The specified |
| 342 | /// stack slot must be available in a physreg for this query to make sense. |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 343 | bool canClobberPhysReg(int SlotOrReMat) const { |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 344 | assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && |
| 345 | "Value not available!"); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 346 | return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 347 | } |
| 348 | |
| 349 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified |
| 350 | /// stackslot register. The register is still available but is no longer |
| 351 | /// allowed to be modifed. |
| 352 | void disallowClobberPhysReg(unsigned PhysReg); |
| 353 | |
| 354 | /// ClobberPhysReg - This is called when the specified physreg changes |
| 355 | /// value. We use this to invalidate any info about stuff we thing lives in |
| 356 | /// it and any of its aliases. |
| 357 | void ClobberPhysReg(unsigned PhysReg); |
| 358 | |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 359 | /// ModifyStackSlotOrReMat - This method is called when the value in a stack |
| 360 | /// slot changes. This removes information about which register the previous |
| 361 | /// value for this slot lives in (as the previous value is dead now). |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 362 | void ModifyStackSlotOrReMat(int SlotOrReMat); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 363 | }; |
| 364 | } |
| 365 | |
| 366 | /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified |
| 367 | /// stackslot register. The register is still available but is no longer |
| 368 | /// allowed to be modifed. |
| 369 | void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { |
| 370 | std::multimap<unsigned, int>::iterator I = |
| 371 | PhysRegsAvailable.lower_bound(PhysReg); |
| 372 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 373 | int SlotOrReMat = I->second; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 374 | I++; |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 375 | assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 376 | "Bidirectional map mismatch!"); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 377 | SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 378 | DOUT << "PhysReg " << MRI->getName(PhysReg) |
| 379 | << " copied, it is available for use but can no longer be modified\n"; |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified |
| 384 | /// stackslot register and its aliases. The register and its aliases may |
| 385 | /// still available but is no longer allowed to be modifed. |
| 386 | void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { |
| 387 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) |
| 388 | disallowClobberPhysRegOnly(*AS); |
| 389 | disallowClobberPhysRegOnly(PhysReg); |
| 390 | } |
| 391 | |
| 392 | /// ClobberPhysRegOnly - This is called when the specified physreg changes |
| 393 | /// value. We use this to invalidate any info about stuff we thing lives in it. |
| 394 | void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { |
| 395 | std::multimap<unsigned, int>::iterator I = |
| 396 | PhysRegsAvailable.lower_bound(PhysReg); |
| 397 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 398 | int SlotOrReMat = I->second; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 399 | PhysRegsAvailable.erase(I++); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 400 | assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 401 | "Bidirectional map mismatch!"); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 402 | SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 403 | DOUT << "PhysReg " << MRI->getName(PhysReg) |
| 404 | << " clobbered, invalidating "; |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 405 | if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) |
| 406 | DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 407 | else |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 408 | DOUT << "SS#" << SlotOrReMat << "\n"; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 409 | } |
| 410 | } |
| 411 | |
| 412 | /// ClobberPhysReg - This is called when the specified physreg changes |
| 413 | /// value. We use this to invalidate any info about stuff we thing lives in |
| 414 | /// it and any of its aliases. |
| 415 | void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { |
| 416 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) |
| 417 | ClobberPhysRegOnly(*AS); |
| 418 | ClobberPhysRegOnly(PhysReg); |
| 419 | } |
| 420 | |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 421 | /// ModifyStackSlotOrReMat - This method is called when the value in a stack |
| 422 | /// slot changes. This removes information about which register the previous |
| 423 | /// value for this slot lives in (as the previous value is dead now). |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 424 | void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 425 | std::map<int, unsigned>::iterator It = |
| 426 | SpillSlotsOrReMatsAvailable.find(SlotOrReMat); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 427 | if (It == SpillSlotsOrReMatsAvailable.end()) return; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 428 | unsigned Reg = It->second >> 1; |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 429 | SpillSlotsOrReMatsAvailable.erase(It); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 430 | |
| 431 | // This register may hold the value of multiple stack slots, only remove this |
| 432 | // stack slot from the set of values the register contains. |
| 433 | std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); |
| 434 | for (; ; ++I) { |
| 435 | assert(I != PhysRegsAvailable.end() && I->first == Reg && |
| 436 | "Map inverse broken!"); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 437 | if (I->second == SlotOrReMat) break; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 438 | } |
| 439 | PhysRegsAvailable.erase(I); |
| 440 | } |
| 441 | |
| 442 | |
| 443 | |
| 444 | /// InvalidateKills - MI is going to be deleted. If any of its operands are |
| 445 | /// marked kill, then invalidate the information. |
| 446 | static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, |
Evan Cheng | eec85c5 | 2007-08-14 20:23:13 +0000 | [diff] [blame] | 447 | std::vector<MachineOperand*> &KillOps, |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 448 | SmallVector<unsigned, 1> *KillRegs = NULL) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 449 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 450 | MachineOperand &MO = MI.getOperand(i); |
Dan Gohman | 38a9a9f | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 451 | if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 452 | continue; |
| 453 | unsigned Reg = MO.getReg(); |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 454 | if (KillRegs) |
| 455 | KillRegs->push_back(Reg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 456 | if (KillOps[Reg] == &MO) { |
| 457 | RegKills.reset(Reg); |
| 458 | KillOps[Reg] = NULL; |
| 459 | } |
| 460 | } |
| 461 | } |
| 462 | |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 463 | /// InvalidateRegDef - If the def operand of the specified def MI is now dead |
| 464 | /// (since it's spill instruction is removed), mark it isDead. Also checks if |
| 465 | /// the def MI has other definition operands that are not dead. Returns it by |
| 466 | /// reference. |
| 467 | static bool InvalidateRegDef(MachineBasicBlock::iterator I, |
| 468 | MachineInstr &NewDef, unsigned Reg, |
| 469 | bool &HasLiveDef) { |
| 470 | // Due to remat, it's possible this reg isn't being reused. That is, |
| 471 | // the def of this reg (by prev MI) is now dead. |
| 472 | MachineInstr *DefMI = I; |
| 473 | MachineOperand *DefOp = NULL; |
| 474 | for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { |
| 475 | MachineOperand &MO = DefMI->getOperand(i); |
Dan Gohman | 38a9a9f | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 476 | if (MO.isRegister() && MO.isDef()) { |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 477 | if (MO.getReg() == Reg) |
| 478 | DefOp = &MO; |
| 479 | else if (!MO.isDead()) |
| 480 | HasLiveDef = true; |
| 481 | } |
| 482 | } |
| 483 | if (!DefOp) |
| 484 | return false; |
| 485 | |
| 486 | bool FoundUse = false, Done = false; |
| 487 | MachineBasicBlock::iterator E = NewDef; |
| 488 | ++I; ++E; |
| 489 | for (; !Done && I != E; ++I) { |
| 490 | MachineInstr *NMI = I; |
| 491 | for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { |
| 492 | MachineOperand &MO = NMI->getOperand(j); |
Dan Gohman | 38a9a9f | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 493 | if (!MO.isRegister() || MO.getReg() != Reg) |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 494 | continue; |
| 495 | if (MO.isUse()) |
| 496 | FoundUse = true; |
| 497 | Done = true; // Stop after scanning all the operands of this MI. |
| 498 | } |
| 499 | } |
| 500 | if (!FoundUse) { |
| 501 | // Def is dead! |
| 502 | DefOp->setIsDead(); |
| 503 | return true; |
| 504 | } |
| 505 | return false; |
| 506 | } |
| 507 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 508 | /// UpdateKills - Track and update kill info. If a MI reads a register that is |
| 509 | /// marked kill, then it must be due to register reuse. Transfer the kill info |
| 510 | /// over. |
| 511 | static void UpdateKills(MachineInstr &MI, BitVector &RegKills, |
| 512 | std::vector<MachineOperand*> &KillOps) { |
| 513 | const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); |
| 514 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 515 | MachineOperand &MO = MI.getOperand(i); |
Dan Gohman | 38a9a9f | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 516 | if (!MO.isRegister() || !MO.isUse()) |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 517 | continue; |
| 518 | unsigned Reg = MO.getReg(); |
| 519 | if (Reg == 0) |
| 520 | continue; |
| 521 | |
| 522 | if (RegKills[Reg]) { |
| 523 | // That can't be right. Register is killed but not re-defined and it's |
| 524 | // being reused. Let's fix that. |
| 525 | KillOps[Reg]->unsetIsKill(); |
| 526 | if (i < TID->numOperands && |
| 527 | TID->getOperandConstraint(i, TOI::TIED_TO) == -1) |
| 528 | // Unless it's a two-address operand, this is the new kill. |
| 529 | MO.setIsKill(); |
| 530 | } |
| 531 | |
| 532 | if (MO.isKill()) { |
| 533 | RegKills.set(Reg); |
| 534 | KillOps[Reg] = &MO; |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 539 | const MachineOperand &MO = MI.getOperand(i); |
Dan Gohman | 38a9a9f | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 540 | if (!MO.isRegister() || !MO.isDef()) |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 541 | continue; |
| 542 | unsigned Reg = MO.getReg(); |
| 543 | RegKills.reset(Reg); |
| 544 | KillOps[Reg] = NULL; |
| 545 | } |
| 546 | } |
| 547 | |
| 548 | |
| 549 | // ReusedOp - For each reused operand, we keep track of a bit of information, in |
| 550 | // case we need to rollback upon processing a new operand. See comments below. |
| 551 | namespace { |
| 552 | struct ReusedOp { |
| 553 | // The MachineInstr operand that reused an available value. |
| 554 | unsigned Operand; |
| 555 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 556 | // StackSlotOrReMat - The spill slot or remat id of the value being reused. |
| 557 | unsigned StackSlotOrReMat; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 558 | |
| 559 | // PhysRegReused - The physical register the value was available in. |
| 560 | unsigned PhysRegReused; |
| 561 | |
| 562 | // AssignedPhysReg - The physreg that was assigned for use by the reload. |
| 563 | unsigned AssignedPhysReg; |
| 564 | |
| 565 | // VirtReg - The virtual register itself. |
| 566 | unsigned VirtReg; |
| 567 | |
| 568 | ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, |
| 569 | unsigned vreg) |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 570 | : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), |
| 571 | AssignedPhysReg(apr), VirtReg(vreg) {} |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 572 | }; |
| 573 | |
| 574 | /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that |
| 575 | /// is reused instead of reloaded. |
| 576 | class VISIBILITY_HIDDEN ReuseInfo { |
| 577 | MachineInstr &MI; |
| 578 | std::vector<ReusedOp> Reuses; |
| 579 | BitVector PhysRegsClobbered; |
| 580 | public: |
| 581 | ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { |
| 582 | PhysRegsClobbered.resize(mri->getNumRegs()); |
| 583 | } |
| 584 | |
| 585 | bool hasReuses() const { |
| 586 | return !Reuses.empty(); |
| 587 | } |
| 588 | |
| 589 | /// addReuse - If we choose to reuse a virtual register that is already |
| 590 | /// available instead of reloading it, remember that we did so. |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 591 | void addReuse(unsigned OpNo, unsigned StackSlotOrReMat, |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 592 | unsigned PhysRegReused, unsigned AssignedPhysReg, |
| 593 | unsigned VirtReg) { |
| 594 | // If the reload is to the assigned register anyway, no undo will be |
| 595 | // required. |
| 596 | if (PhysRegReused == AssignedPhysReg) return; |
| 597 | |
| 598 | // Otherwise, remember this. |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 599 | Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused, |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 600 | AssignedPhysReg, VirtReg)); |
| 601 | } |
| 602 | |
| 603 | void markClobbered(unsigned PhysReg) { |
| 604 | PhysRegsClobbered.set(PhysReg); |
| 605 | } |
| 606 | |
| 607 | bool isClobbered(unsigned PhysReg) const { |
| 608 | return PhysRegsClobbered.test(PhysReg); |
| 609 | } |
| 610 | |
| 611 | /// GetRegForReload - We are about to emit a reload into PhysReg. If there |
| 612 | /// is some other operand that is using the specified register, either pick |
| 613 | /// a new register to use, or evict the previous reload and use this reg. |
| 614 | unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, |
| 615 | AvailableSpills &Spills, |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 616 | std::vector<MachineInstr*> &MaybeDeadStores, |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 617 | SmallSet<unsigned, 8> &Rejected, |
| 618 | BitVector &RegKills, |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 619 | std::vector<MachineOperand*> &KillOps, |
| 620 | VirtRegMap &VRM) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 621 | if (Reuses.empty()) return PhysReg; // This is most often empty. |
| 622 | |
| 623 | for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { |
| 624 | ReusedOp &Op = Reuses[ro]; |
| 625 | // If we find some other reuse that was supposed to use this register |
| 626 | // exactly for its reload, we can change this reload to use ITS reload |
| 627 | // register. That is, unless its reload register has already been |
| 628 | // considered and subsequently rejected because it has also been reused |
| 629 | // by another operand. |
| 630 | if (Op.PhysRegReused == PhysReg && |
| 631 | Rejected.count(Op.AssignedPhysReg) == 0) { |
| 632 | // Yup, use the reload register that we didn't use before. |
| 633 | unsigned NewReg = Op.AssignedPhysReg; |
| 634 | Rejected.insert(PhysReg); |
| 635 | return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected, |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 636 | RegKills, KillOps, VRM); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 637 | } else { |
| 638 | // Otherwise, we might also have a problem if a previously reused |
| 639 | // value aliases the new register. If so, codegen the previous reload |
| 640 | // and use this one. |
| 641 | unsigned PRRU = Op.PhysRegReused; |
| 642 | const MRegisterInfo *MRI = Spills.getRegInfo(); |
| 643 | if (MRI->areAliases(PRRU, PhysReg)) { |
| 644 | // Okay, we found out that an alias of a reused register |
| 645 | // was used. This isn't good because it means we have |
| 646 | // to undo a previous reuse. |
| 647 | MachineBasicBlock *MBB = MI->getParent(); |
| 648 | const TargetRegisterClass *AliasRC = |
| 649 | MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg); |
| 650 | |
| 651 | // Copy Op out of the vector and remove it, we're going to insert an |
| 652 | // explicit load for it. |
| 653 | ReusedOp NewOp = Op; |
| 654 | Reuses.erase(Reuses.begin()+ro); |
| 655 | |
| 656 | // Ok, we're going to try to reload the assigned physreg into the |
| 657 | // slot that we were supposed to in the first place. However, that |
| 658 | // register could hold a reuse. Check to see if it conflicts or |
| 659 | // would prefer us to use a different register. |
| 660 | unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, |
| 661 | MI, Spills, MaybeDeadStores, |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 662 | Rejected, RegKills, KillOps, VRM); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 663 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 664 | if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { |
| 665 | MRI->reMaterialize(*MBB, MI, NewPhysReg, |
| 666 | VRM.getReMaterializedMI(NewOp.VirtReg)); |
| 667 | ++NumReMats; |
| 668 | } else { |
| 669 | MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg, |
| 670 | NewOp.StackSlotOrReMat, AliasRC); |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 671 | // Any stores to this stack slot are not dead anymore. |
| 672 | MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL; |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 673 | ++NumLoads; |
| 674 | } |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 675 | Spills.ClobberPhysReg(NewPhysReg); |
| 676 | Spills.ClobberPhysReg(NewOp.PhysRegReused); |
| 677 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 678 | MI->getOperand(NewOp.Operand).setReg(NewPhysReg); |
| 679 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 680 | Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 681 | MachineBasicBlock::iterator MII = MI; |
| 682 | --MII; |
| 683 | UpdateKills(*MII, RegKills, KillOps); |
| 684 | DOUT << '\t' << *MII; |
| 685 | |
| 686 | DOUT << "Reuse undone!\n"; |
| 687 | --NumReused; |
| 688 | |
| 689 | // Finally, PhysReg is now available, go ahead and use it. |
| 690 | return PhysReg; |
| 691 | } |
| 692 | } |
| 693 | } |
| 694 | return PhysReg; |
| 695 | } |
| 696 | |
| 697 | /// GetRegForReload - Helper for the above GetRegForReload(). Add a |
| 698 | /// 'Rejected' set to remember which registers have been considered and |
| 699 | /// rejected for the reload. This avoids infinite looping in case like |
| 700 | /// this: |
| 701 | /// t1 := op t2, t3 |
| 702 | /// t2 <- assigned r0 for use by the reload but ended up reuse r1 |
| 703 | /// t3 <- assigned r1 for use by the reload but ended up reuse r0 |
| 704 | /// t1 <- desires r1 |
| 705 | /// sees r1 is taken by t2, tries t2's reload register r0 |
| 706 | /// sees r0 is taken by t3, tries t3's reload register r1 |
| 707 | /// sees r1 is taken by t2, tries t2's reload register r0 ... |
| 708 | unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, |
| 709 | AvailableSpills &Spills, |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 710 | std::vector<MachineInstr*> &MaybeDeadStores, |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 711 | BitVector &RegKills, |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 712 | std::vector<MachineOperand*> &KillOps, |
| 713 | VirtRegMap &VRM) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 714 | SmallSet<unsigned, 8> Rejected; |
| 715 | return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected, |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 716 | RegKills, KillOps, VRM); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 717 | } |
| 718 | }; |
| 719 | } |
| 720 | |
| 721 | |
| 722 | /// rewriteMBB - Keep track of which spills are available even after the |
| 723 | /// register allocator is done with them. If possible, avoid reloading vregs. |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 724 | void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 725 | DOUT << MBB.getBasicBlock()->getName() << ":\n"; |
| 726 | |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 727 | MachineFunction &MF = *MBB.getParent(); |
| 728 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 729 | // Spills - Keep track of which spilled values are available in physregs so |
| 730 | // that we can choose to reuse the physregs instead of emitting reloads. |
| 731 | AvailableSpills Spills(MRI, TII); |
| 732 | |
| 733 | // MaybeDeadStores - When we need to write a value back into a stack slot, |
| 734 | // keep track of the inserted store. If the stack slot value is never read |
| 735 | // (because the value was used from some available register, for example), and |
| 736 | // subsequently stored to, the original store is dead. This map keeps track |
| 737 | // of inserted stores that are not used. If we see a subsequent store to the |
| 738 | // same stack slot, the original store is deleted. |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 739 | std::vector<MachineInstr*> MaybeDeadStores; |
| 740 | MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 741 | |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 742 | // ReMatDefs - These are rematerializable def MIs which are not deleted. |
| 743 | SmallSet<MachineInstr*, 4> ReMatDefs; |
| 744 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 745 | // Keep track of kill information. |
| 746 | BitVector RegKills(MRI->getNumRegs()); |
| 747 | std::vector<MachineOperand*> KillOps; |
| 748 | KillOps.resize(MRI->getNumRegs(), NULL); |
| 749 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 750 | for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); |
| 751 | MII != E; ) { |
| 752 | MachineInstr &MI = *MII; |
| 753 | MachineBasicBlock::iterator NextMII = MII; ++NextMII; |
| 754 | VirtRegMap::MI2VirtMapTy::const_iterator I, End; |
| 755 | |
| 756 | bool Erased = false; |
| 757 | bool BackTracked = false; |
| 758 | |
| 759 | /// ReusedOperands - Keep track of operand reuse in case we need to undo |
| 760 | /// reuse. |
| 761 | ReuseInfo ReusedOperands(MI, MRI); |
| 762 | |
| 763 | // Loop over all of the implicit defs, clearing them from our available |
| 764 | // sets. |
| 765 | const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 766 | if (TID->ImplicitDefs) { |
| 767 | const unsigned *ImpDef = TID->ImplicitDefs; |
| 768 | for ( ; *ImpDef; ++ImpDef) { |
| 769 | MF.setPhysRegUsed(*ImpDef); |
| 770 | ReusedOperands.markClobbered(*ImpDef); |
| 771 | Spills.ClobberPhysReg(*ImpDef); |
| 772 | } |
| 773 | } |
| 774 | |
| 775 | // Process all of the spilled uses and all non spilled reg references. |
| 776 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 777 | MachineOperand &MO = MI.getOperand(i); |
| 778 | if (!MO.isRegister() || MO.getReg() == 0) |
| 779 | continue; // Ignore non-register operands. |
| 780 | |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 781 | unsigned VirtReg = MO.getReg(); |
| 782 | if (MRegisterInfo::isPhysicalRegister(VirtReg)) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 783 | // Ignore physregs for spilling, but remember that it is used by this |
| 784 | // function. |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 785 | MF.setPhysRegUsed(VirtReg); |
| 786 | ReusedOperands.markClobbered(VirtReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 787 | continue; |
| 788 | } |
| 789 | |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 790 | assert(MRegisterInfo::isVirtualRegister(VirtReg) && |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 791 | "Not a virtual or a physical register?"); |
| 792 | |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 793 | unsigned SubIdx = 0; |
| 794 | bool isSubReg = RegMap->isSubRegister(VirtReg); |
| 795 | if (isSubReg) { |
| 796 | SubIdx = RegMap->getSubRegisterIndex(VirtReg); |
| 797 | VirtReg = RegMap->getSuperRegister(VirtReg); |
| 798 | } |
| 799 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 800 | if (VRM.isAssignedReg(VirtReg)) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 801 | // This virtual register was assigned a physreg! |
| 802 | unsigned Phys = VRM.getPhys(VirtReg); |
| 803 | MF.setPhysRegUsed(Phys); |
| 804 | if (MO.isDef()) |
| 805 | ReusedOperands.markClobbered(Phys); |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 806 | unsigned RReg = isSubReg ? MRI->getSubReg(Phys, SubIdx) : Phys; |
| 807 | MI.getOperand(i).setReg(RReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 808 | continue; |
| 809 | } |
| 810 | |
| 811 | // This virtual register is now known to be a spilled value. |
| 812 | if (!MO.isUse()) |
| 813 | continue; // Handle defs in the loop below (handle use&def here though) |
| 814 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 815 | bool DoReMat = VRM.isReMaterialized(VirtReg); |
| 816 | int SSorRMId = DoReMat |
| 817 | ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 818 | int ReuseSlot = SSorRMId; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 819 | |
| 820 | // Check to see if this stack slot is available. |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 821 | unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); |
| 822 | if (!PhysReg && DoReMat) { |
| 823 | // This use is rematerializable. But perhaps the value is available in |
| 824 | // stack if the definition is not deleted. If so, check if we can |
| 825 | // reuse the value. |
| 826 | ReuseSlot = VRM.getStackSlot(VirtReg); |
| 827 | if (ReuseSlot != VirtRegMap::NO_STACK_SLOT) |
| 828 | PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot); |
| 829 | } |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 830 | |
| 831 | // If this is a sub-register use, make sure the reuse register is in the |
| 832 | // right register class. For example, for x86 not all of the 32-bit |
| 833 | // registers have accessible sub-registers. |
| 834 | // Similarly so for EXTRACT_SUBREG. Consider this: |
| 835 | // EDI = op |
| 836 | // MOV32_mr fi#1, EDI |
| 837 | // ... |
| 838 | // = EXTRACT_SUBREG fi#1 |
| 839 | // fi#1 is available in EDI, but it cannot be reused because it's not in |
| 840 | // the right register file. |
| 841 | if (PhysReg && |
| 842 | (isSubReg || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { |
| 843 | const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); |
| 844 | if (!RC->contains(PhysReg)) |
| 845 | PhysReg = 0; |
| 846 | } |
| 847 | |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 848 | if (PhysReg) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 849 | // This spilled operand might be part of a two-address operand. If this |
| 850 | // is the case, then changing it will necessarily require changing the |
| 851 | // def part of the instruction as well. However, in some cases, we |
| 852 | // aren't allowed to modify the reused register. If none of these cases |
| 853 | // apply, reuse it. |
| 854 | bool CanReuse = true; |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 855 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 856 | int ti = TID->getOperandConstraint(i, TOI::TIED_TO); |
| 857 | if (ti != -1 && |
Dan Gohman | 38a9a9f | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 858 | MI.getOperand(ti).isRegister() && |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 859 | MI.getOperand(ti).getReg() == VirtReg) { |
| 860 | // Okay, we have a two address operand. We can reuse this physreg as |
| 861 | // long as we are allowed to clobber the value and there isn't an |
| 862 | // earlier def that has already clobbered the physreg. |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 863 | CanReuse = Spills.canClobberPhysReg(ReuseSlot) && |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 864 | !ReusedOperands.isClobbered(PhysReg); |
| 865 | } |
| 866 | |
| 867 | if (CanReuse) { |
| 868 | // If this stack slot value is already available, reuse it! |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 869 | if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) |
| 870 | DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 871 | else |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 872 | DOUT << "Reusing SS#" << ReuseSlot; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 873 | DOUT << " from physreg " |
| 874 | << MRI->getName(PhysReg) << " for vreg" |
| 875 | << VirtReg <<" instead of reloading into physreg " |
| 876 | << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 877 | unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; |
| 878 | MI.getOperand(i).setReg(RReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 879 | |
| 880 | // The only technical detail we have is that we don't know that |
| 881 | // PhysReg won't be clobbered by a reloaded stack slot that occurs |
| 882 | // later in the instruction. In particular, consider 'op V1, V2'. |
| 883 | // If V1 is available in physreg R0, we would choose to reuse it |
| 884 | // here, instead of reloading it into the register the allocator |
| 885 | // indicated (say R1). However, V2 might have to be reloaded |
| 886 | // later, and it might indicate that it needs to live in R0. When |
| 887 | // this occurs, we need to have information available that |
| 888 | // indicates it is safe to use R1 for the reload instead of R0. |
| 889 | // |
| 890 | // To further complicate matters, we might conflict with an alias, |
| 891 | // or R0 and R1 might not be compatible with each other. In this |
| 892 | // case, we actually insert a reload for V1 in R1, ensuring that |
| 893 | // we can get at R0 or its alias. |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 894 | ReusedOperands.addReuse(i, ReuseSlot, PhysReg, |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 895 | VRM.getPhys(VirtReg), VirtReg); |
| 896 | if (ti != -1) |
| 897 | // Only mark it clobbered if this is a use&def operand. |
| 898 | ReusedOperands.markClobbered(PhysReg); |
| 899 | ++NumReused; |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 900 | |
| 901 | if (MI.getOperand(i).isKill() && |
| 902 | ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) { |
| 903 | // This was the last use and the spilled value is still available |
| 904 | // for reuse. That means the spill was unnecessary! |
| 905 | MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot]; |
| 906 | if (DeadStore) { |
| 907 | DOUT << "Removed dead store:\t" << *DeadStore; |
| 908 | InvalidateKills(*DeadStore, RegKills, KillOps); |
| 909 | MBB.erase(DeadStore); |
| 910 | VRM.RemoveFromFoldedVirtMap(DeadStore); |
| 911 | MaybeDeadStores[ReuseSlot] = NULL; |
| 912 | ++NumDSE; |
| 913 | } |
| 914 | } |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 915 | continue; |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 916 | } // CanReuse |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 917 | |
| 918 | // Otherwise we have a situation where we have a two-address instruction |
| 919 | // whose mod/ref operand needs to be reloaded. This reload is already |
| 920 | // available in some register "PhysReg", but if we used PhysReg as the |
| 921 | // operand to our 2-addr instruction, the instruction would modify |
| 922 | // PhysReg. This isn't cool if something later uses PhysReg and expects |
| 923 | // to get its initial value. |
| 924 | // |
| 925 | // To avoid this problem, and to avoid doing a load right after a store, |
| 926 | // we emit a copy from PhysReg into the designated register for this |
| 927 | // operand. |
| 928 | unsigned DesignatedReg = VRM.getPhys(VirtReg); |
| 929 | assert(DesignatedReg && "Must map virtreg to physreg!"); |
| 930 | |
| 931 | // Note that, if we reused a register for a previous operand, the |
| 932 | // register we want to reload into might not actually be |
| 933 | // available. If this occurs, use the register indicated by the |
| 934 | // reuser. |
| 935 | if (ReusedOperands.hasReuses()) |
| 936 | DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 937 | Spills, MaybeDeadStores, RegKills, KillOps, VRM); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 938 | |
| 939 | // If the mapped designated register is actually the physreg we have |
| 940 | // incoming, we don't need to inserted a dead copy. |
| 941 | if (DesignatedReg == PhysReg) { |
| 942 | // If this stack slot value is already available, reuse it! |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 943 | if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) |
| 944 | DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 945 | else |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 946 | DOUT << "Reusing SS#" << ReuseSlot; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 947 | DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg" |
| 948 | << VirtReg |
| 949 | << " instead of reloading into same physreg.\n"; |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 950 | unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; |
| 951 | MI.getOperand(i).setReg(RReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 952 | ReusedOperands.markClobbered(PhysReg); |
| 953 | ++NumReused; |
| 954 | continue; |
| 955 | } |
| 956 | |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 957 | const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 958 | MF.setPhysRegUsed(DesignatedReg); |
| 959 | ReusedOperands.markClobbered(DesignatedReg); |
Evan Cheng | b3d91cf | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 960 | MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 961 | |
| 962 | MachineInstr *CopyMI = prior(MII); |
| 963 | UpdateKills(*CopyMI, RegKills, KillOps); |
| 964 | |
| 965 | // This invalidates DesignatedReg. |
| 966 | Spills.ClobberPhysReg(DesignatedReg); |
| 967 | |
Evan Cheng | 67cf11c | 2007-08-14 05:42:54 +0000 | [diff] [blame] | 968 | Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 969 | unsigned RReg = |
| 970 | isSubReg ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; |
| 971 | MI.getOperand(i).setReg(RReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 972 | DOUT << '\t' << *prior(MII); |
| 973 | ++NumReused; |
| 974 | continue; |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 975 | } // is (PhysReg) |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 976 | |
| 977 | // Otherwise, reload it and remember that we have it. |
| 978 | PhysReg = VRM.getPhys(VirtReg); |
| 979 | assert(PhysReg && "Must map virtreg to physreg!"); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 980 | |
| 981 | // Note that, if we reused a register for a previous operand, the |
| 982 | // register we want to reload into might not actually be |
| 983 | // available. If this occurs, use the register indicated by the |
| 984 | // reuser. |
| 985 | if (ReusedOperands.hasReuses()) |
| 986 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 987 | Spills, MaybeDeadStores, RegKills, KillOps, VRM); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 988 | |
| 989 | MF.setPhysRegUsed(PhysReg); |
| 990 | ReusedOperands.markClobbered(PhysReg); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 991 | if (DoReMat) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 992 | MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); |
| 993 | ++NumReMats; |
| 994 | } else { |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 995 | const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 996 | MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 997 | ++NumLoads; |
| 998 | } |
| 999 | // This invalidates PhysReg. |
| 1000 | Spills.ClobberPhysReg(PhysReg); |
| 1001 | |
| 1002 | // Any stores to this stack slot are not dead anymore. |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1003 | if (!DoReMat) |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1004 | MaybeDeadStores[SSorRMId] = NULL; |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1005 | Spills.addAvailable(SSorRMId, &MI, PhysReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1006 | // Assumes this is the last use. IsKill will be unset if reg is reused |
| 1007 | // unless it's a two-address operand. |
| 1008 | if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1) |
| 1009 | MI.getOperand(i).setIsKill(); |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 1010 | unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; |
| 1011 | MI.getOperand(i).setReg(RReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1012 | UpdateKills(*prior(MII), RegKills, KillOps); |
| 1013 | DOUT << '\t' << *prior(MII); |
| 1014 | } |
| 1015 | |
| 1016 | DOUT << '\t' << MI; |
| 1017 | |
| 1018 | // If we have folded references to memory operands, make sure we clear all |
| 1019 | // physical registers that may contain the value of the spilled virtual |
| 1020 | // register |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 1021 | SmallSet<int, 1> FoldedSS; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1022 | for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { |
| 1023 | DOUT << "Folded vreg: " << I->second.first << " MR: " |
| 1024 | << I->second.second; |
| 1025 | unsigned VirtReg = I->second.first; |
| 1026 | VirtRegMap::ModRef MR = I->second.second; |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1027 | if (VRM.isAssignedReg(VirtReg)) { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1028 | DOUT << ": No stack slot!\n"; |
| 1029 | continue; |
| 1030 | } |
| 1031 | int SS = VRM.getStackSlot(VirtReg); |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 1032 | FoldedSS.insert(SS); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1033 | DOUT << " - StackSlot: " << SS << "\n"; |
| 1034 | |
| 1035 | // If this folded instruction is just a use, check to see if it's a |
| 1036 | // straight load from the virt reg slot. |
| 1037 | if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { |
| 1038 | int FrameIdx; |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 1039 | unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx); |
| 1040 | if (DestReg && FrameIdx == SS) { |
| 1041 | // If this spill slot is available, turn it into a copy (or nothing) |
| 1042 | // instead of leaving it as a load! |
| 1043 | if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { |
| 1044 | DOUT << "Promoted Load To Copy: " << MI; |
| 1045 | if (DestReg != InReg) { |
| 1046 | const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); |
| 1047 | MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); |
| 1048 | // Revisit the copy so we make sure to notice the effects of the |
| 1049 | // operation on the destreg (either needing to RA it if it's |
| 1050 | // virtual or needing to clobber any values if it's physical). |
| 1051 | NextMII = &MI; |
| 1052 | --NextMII; // backtrack to the copy. |
| 1053 | BackTracked = true; |
| 1054 | } else |
| 1055 | DOUT << "Removing now-noop copy: " << MI; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1056 | |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 1057 | VRM.RemoveFromFoldedVirtMap(&MI); |
| 1058 | MBB.erase(&MI); |
| 1059 | Erased = true; |
| 1060 | goto ProcessNextInst; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1061 | } |
| 1062 | } |
| 1063 | } |
| 1064 | |
| 1065 | // If this reference is not a use, any previous store is now dead. |
| 1066 | // Otherwise, the store to this stack slot is not dead anymore. |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1067 | MachineInstr* DeadStore = MaybeDeadStores[SS]; |
| 1068 | if (DeadStore) { |
| 1069 | if (!(MR & VirtRegMap::isRef)) { // Previous store is dead. |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1070 | // If we get here, the store is dead, nuke it now. |
| 1071 | assert(VirtRegMap::isMod && "Can't be modref!"); |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1072 | DOUT << "Removed dead store:\t" << *DeadStore; |
| 1073 | InvalidateKills(*DeadStore, RegKills, KillOps); |
| 1074 | MBB.erase(DeadStore); |
| 1075 | VRM.RemoveFromFoldedVirtMap(DeadStore); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1076 | ++NumDSE; |
| 1077 | } |
Evan Cheng | d368d82 | 2007-08-14 09:11:18 +0000 | [diff] [blame] | 1078 | MaybeDeadStores[SS] = NULL; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1079 | } |
| 1080 | |
| 1081 | // If the spill slot value is available, and this is a new definition of |
| 1082 | // the value, the value is not available anymore. |
| 1083 | if (MR & VirtRegMap::isMod) { |
| 1084 | // Notice that the value in this stack slot has been modified. |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1085 | Spills.ModifyStackSlotOrReMat(SS); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1086 | |
| 1087 | // If this is *just* a mod of the value, check to see if this is just a |
| 1088 | // store to the spill slot (i.e. the spill got merged into the copy). If |
| 1089 | // so, realize that the vreg is available now, and add the store to the |
| 1090 | // MaybeDeadStore info. |
| 1091 | int StackSlot; |
| 1092 | if (!(MR & VirtRegMap::isRef)) { |
| 1093 | if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { |
| 1094 | assert(MRegisterInfo::isPhysicalRegister(SrcReg) && |
| 1095 | "Src hasn't been allocated yet?"); |
| 1096 | // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark |
| 1097 | // this as a potentially dead store in case there is a subsequent |
| 1098 | // store into the stack slot without a read from it. |
| 1099 | MaybeDeadStores[StackSlot] = &MI; |
| 1100 | |
| 1101 | // If the stack slot value was previously available in some other |
| 1102 | // register, change it now. Otherwise, make the register available, |
| 1103 | // in PhysReg. |
| 1104 | Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/); |
| 1105 | } |
| 1106 | } |
| 1107 | } |
| 1108 | } |
| 1109 | |
| 1110 | // Process all of the spilled defs. |
| 1111 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 1112 | MachineOperand &MO = MI.getOperand(i); |
| 1113 | if (MO.isRegister() && MO.getReg() && MO.isDef()) { |
| 1114 | unsigned VirtReg = MO.getReg(); |
| 1115 | |
| 1116 | if (!MRegisterInfo::isVirtualRegister(VirtReg)) { |
| 1117 | // Check to see if this is a noop copy. If so, eliminate the |
| 1118 | // instruction before considering the dest reg to be changed. |
| 1119 | unsigned Src, Dst; |
| 1120 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { |
| 1121 | ++NumDCE; |
| 1122 | DOUT << "Removing now-noop copy: " << MI; |
| 1123 | MBB.erase(&MI); |
| 1124 | Erased = true; |
| 1125 | VRM.RemoveFromFoldedVirtMap(&MI); |
| 1126 | Spills.disallowClobberPhysReg(VirtReg); |
| 1127 | goto ProcessNextInst; |
| 1128 | } |
| 1129 | |
| 1130 | // If it's not a no-op copy, it clobbers the value in the destreg. |
| 1131 | Spills.ClobberPhysReg(VirtReg); |
| 1132 | ReusedOperands.markClobbered(VirtReg); |
| 1133 | |
| 1134 | // Check to see if this instruction is a load from a stack slot into |
| 1135 | // a register. If so, this provides the stack slot value in the reg. |
| 1136 | int FrameIdx; |
| 1137 | if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { |
| 1138 | assert(DestReg == VirtReg && "Unknown load situation!"); |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 1139 | |
| 1140 | // If it is a folded reference, then it's not safe to clobber. |
| 1141 | bool Folded = FoldedSS.count(FrameIdx); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1142 | // Otherwise, if it wasn't available, remember that it is now! |
Evan Cheng | 7efc942 | 2007-08-15 20:20:34 +0000 | [diff] [blame] | 1143 | Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1144 | goto ProcessNextInst; |
| 1145 | } |
| 1146 | |
| 1147 | continue; |
| 1148 | } |
| 1149 | |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 1150 | bool DoReMat = VRM.isReMaterialized(VirtReg); |
| 1151 | if (DoReMat) |
| 1152 | ReMatDefs.insert(&MI); |
| 1153 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1154 | // The only vregs left are stack slot definitions. |
| 1155 | int StackSlot = VRM.getStackSlot(VirtReg); |
Evan Cheng | 687d108 | 2007-10-12 08:50:34 +0000 | [diff] [blame^] | 1156 | const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1157 | |
| 1158 | // If this def is part of a two-address operand, make sure to execute |
| 1159 | // the store from the correct physical register. |
| 1160 | unsigned PhysReg; |
| 1161 | int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i); |
| 1162 | if (TiedOp != -1) |
| 1163 | PhysReg = MI.getOperand(TiedOp).getReg(); |
| 1164 | else { |
| 1165 | PhysReg = VRM.getPhys(VirtReg); |
| 1166 | if (ReusedOperands.isClobbered(PhysReg)) { |
| 1167 | // Another def has taken the assigned physreg. It must have been a |
| 1168 | // use&def which got it due to reuse. Undo the reuse! |
| 1169 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 1170 | Spills, MaybeDeadStores, RegKills, KillOps, VRM); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1171 | } |
| 1172 | } |
| 1173 | |
| 1174 | MF.setPhysRegUsed(PhysReg); |
| 1175 | ReusedOperands.markClobbered(PhysReg); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1176 | MI.getOperand(i).setReg(PhysReg); |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 1177 | if (!MO.isDead()) { |
| 1178 | MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); |
| 1179 | DOUT << "Store:\t" << *next(MII); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1180 | |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 1181 | // If there is a dead store to this stack slot, nuke it now. |
| 1182 | MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; |
| 1183 | if (LastStore) { |
| 1184 | DOUT << "Removed dead store:\t" << *LastStore; |
| 1185 | ++NumDSE; |
| 1186 | SmallVector<unsigned, 1> KillRegs; |
| 1187 | InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs); |
| 1188 | MachineBasicBlock::iterator PrevMII = LastStore; |
| 1189 | bool CheckDef = PrevMII != MBB.begin(); |
| 1190 | if (CheckDef) |
| 1191 | --PrevMII; |
| 1192 | MBB.erase(LastStore); |
| 1193 | VRM.RemoveFromFoldedVirtMap(LastStore); |
| 1194 | if (CheckDef) { |
| 1195 | // Look at defs of killed registers on the store. Mark the defs |
| 1196 | // as dead since the store has been deleted and they aren't |
| 1197 | // being reused. |
| 1198 | for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) { |
| 1199 | bool HasOtherDef = false; |
| 1200 | if (InvalidateRegDef(PrevMII, MI, KillRegs[j], HasOtherDef)) { |
| 1201 | MachineInstr *DeadDef = PrevMII; |
| 1202 | if (ReMatDefs.count(DeadDef) && !HasOtherDef) { |
| 1203 | // FIXME: This assumes a remat def does not have side |
| 1204 | // effects. |
| 1205 | MBB.erase(DeadDef); |
| 1206 | VRM.RemoveFromFoldedVirtMap(DeadDef); |
| 1207 | ++NumDRM; |
| 1208 | } |
| 1209 | } |
| 1210 | } |
| 1211 | } |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1212 | } |
Evan Cheng | 498949b | 2007-08-14 23:25:37 +0000 | [diff] [blame] | 1213 | LastStore = next(MII); |
| 1214 | |
| 1215 | // If the stack slot value was previously available in some other |
| 1216 | // register, change it now. Otherwise, make the register available, |
| 1217 | // in PhysReg. |
| 1218 | Spills.ModifyStackSlotOrReMat(StackSlot); |
| 1219 | Spills.ClobberPhysReg(PhysReg); |
| 1220 | Spills.addAvailable(StackSlot, LastStore, PhysReg); |
| 1221 | ++NumStores; |
| 1222 | |
| 1223 | // Check to see if this is a noop copy. If so, eliminate the |
| 1224 | // instruction before considering the dest reg to be changed. |
| 1225 | { |
| 1226 | unsigned Src, Dst; |
| 1227 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { |
| 1228 | ++NumDCE; |
| 1229 | DOUT << "Removing now-noop copy: " << MI; |
| 1230 | MBB.erase(&MI); |
| 1231 | Erased = true; |
| 1232 | VRM.RemoveFromFoldedVirtMap(&MI); |
| 1233 | UpdateKills(*LastStore, RegKills, KillOps); |
| 1234 | goto ProcessNextInst; |
| 1235 | } |
| 1236 | } |
| 1237 | } |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1238 | } |
| 1239 | } |
| 1240 | ProcessNextInst: |
| 1241 | if (!Erased && !BackTracked) |
| 1242 | for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II) |
| 1243 | UpdateKills(*II, RegKills, KillOps); |
| 1244 | MII = NextMII; |
| 1245 | } |
| 1246 | } |
| 1247 | |
| 1248 | |
| 1249 | llvm::Spiller* llvm::createSpiller() { |
| 1250 | switch (SpillerOpt) { |
| 1251 | default: assert(0 && "Unreachable!"); |
| 1252 | case local: |
| 1253 | return new LocalSpiller(); |
| 1254 | case simple: |
| 1255 | return new SimpleSpiller(); |
| 1256 | } |
| 1257 | } |