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Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]6 <title>Writing an LLVM Compiler Backend</title>
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8</head>
9
10<body>
11
Chris Lattner611944b2008-11-11 19:31:26 +0000[diff] [blame]12<div class="doc_title">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]13 Writing an LLVM Compiler Backend
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]14</div>
15
16<ol>
17 <li><a href="#intro">Introduction</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]18 <ul>
19 <li><a href="#Audience">Audience</a></li>
20 <li><a href="#Prerequisite">Prerequisite Reading</a></li>
21 <li><a href="#Basic">Basic Steps</a></li>
22 <li><a href="#Preliminaries">Preliminaries</a></li>
23 </ul>
24 <li><a href="#TargetMachine">Target Machine</a></li>
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]25 <li><a href="#TargetRegistration">Target Registration</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]26 <li><a href="#RegisterSet">Register Set and Register Classes</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]27 <ul>
28 <li><a href="#RegisterDef">Defining a Register</a></li>
29 <li><a href="#RegisterClassDef">Defining a Register Class</a></li>
30 <li><a href="#implementRegister">Implement a subclass of TargetRegisterInfo</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]31 </ul></li>
32 <li><a href="#InstructionSet">Instruction Set</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]33 <ul>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]34 <li><a href="#operandMapping">Instruction Operand Mapping</a></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]35 <li><a href="#implementInstr">Implement a subclass of TargetInstrInfo</a></li>
36 <li><a href="#branchFolding">Branch Folding and If Conversion</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]37 </ul></li>
38 <li><a href="#InstructionSelector">Instruction Selector</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]39 <ul>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]40 <li><a href="#LegalizePhase">The SelectionDAG Legalize Phase</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]41 <ul>
42 <li><a href="#promote">Promote</a></li>
43 <li><a href="#expand">Expand</a></li>
44 <li><a href="#custom">Custom</a></li>
45 <li><a href="#legal">Legal</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]46 </ul></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]47 <li><a href="#callingConventions">Calling Conventions</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]48 </ul></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]49 <li><a href="#assemblyPrinter">Assembly Printer</a></li>
50 <li><a href="#subtargetSupport">Subtarget Support</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]51 <li><a href="#jitSupport">JIT Support</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]52 <ul>
53 <li><a href="#mce">Machine Code Emitter</a></li>
54 <li><a href="#targetJITInfo">Target JIT Info</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]55 </ul></li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]56</ol>
57
58<div class="doc_author">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]59 <p>Written by <a href="http://www.woo.com">Mason Woo</a> and
60 <a href="http://misha.brukman.net">Misha Brukman</a></p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]61</div>
62
63<!-- *********************************************************************** -->
64<div class="doc_section">
65 <a name="intro">Introduction</a>
66</div>
67<!-- *********************************************************************** -->
68
69<div class="doc_text">
70
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]71<p>
72This document describes techniques for writing compiler backends that convert
73the LLVM Intermediate Representation (IR) to code for a specified machine or
74other languages. Code intended for a specific machine can take the form of
75either assembly code or binary code (usable for a JIT compiler).
76</p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]77
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]78<p>
79The backend of LLVM features a target-independent code generator that may create
80output for several types of target CPUs &mdash; including X86, PowerPC, Alpha,
81and SPARC. The backend may also be used to generate code targeted at SPUs of the
82Cell processor or GPUs to support the execution of compute kernels.
83</p>
84
85<p>
86The document focuses on existing examples found in subdirectories
87of <tt>llvm/lib/Target</tt> in a downloaded LLVM release. In particular, this
88document focuses on the example of creating a static compiler (one that emits
89text assembly) for a SPARC target, because SPARC has fairly standard
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]90characteristics, such as a RISC instruction set and straightforward calling
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]91conventions.
92</p>
93
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]94</div>
95
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]96<div class="doc_subsection">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]97 <a name="Audience">Audience</a>
98</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]99
100<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]101
102<p>
103The audience for this document is anyone who needs to write an LLVM backend to
104generate code for a specific hardware or software target.
105</p>
106
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]107</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]108
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]109<div class="doc_subsection">
110 <a name="Prerequisite">Prerequisite Reading</a>
111</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]112
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]113<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]114
115<p>
116These essential documents must be read before reading this document:
117</p>
118
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]119<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]120<li><i><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference
121 Manual</a></i> &mdash; a reference manual for the LLVM assembly language.</li>
122
123<li><i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
124 Target-Independent Code Generator</a></i> &mdash; a guide to the components
125 (classes and code generation algorithms) for translating the LLVM internal
126 representation into machine code for a specified target. Pay particular
127 attention to the descriptions of code generation stages: Instruction
128 Selection, Scheduling and Formation, SSA-based Optimization, Register
129 Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations,
130 and Code Emission.</li>
131
132<li><i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen
133 Fundamentals</a></i> &mdash;a document that describes the TableGen
134 (<tt>tblgen</tt>) application that manages domain-specific information to
135 support LLVM code generation. TableGen processes input from a target
136 description file (<tt>.td</tt> suffix) and generates C++ code that can be
137 used for code generation.</li>
138
139<li><i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM
140 Pass</a></i> &mdash; The assembly printer is a <tt>FunctionPass</tt>, as are
141 several SelectionDAG processing steps.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]142</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]143
144<p>
145To follow the SPARC examples in this document, have a copy of
146<i><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture
147Manual, Version 8</a></i> for reference. For details about the ARM instruction
148set, refer to the <i><a href="http://infocenter.arm.com/">ARM Architecture
149Reference Manual</a></i>. For more about the GNU Assembler format
150(<tt>GAS</tt>), see
151<i><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></i>,
152especially for the assembly printer. <i>Using As</i> contains a list of target
153machine dependent features.
154</p>
155
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]156</div>
157
158<div class="doc_subsection">
159 <a name="Basic">Basic Steps</a>
160</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]161
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]162<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]163
164<p>
165To write a compiler backend for LLVM that converts the LLVM IR to code for a
166specified target (machine or other language), follow these steps:
167</p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]168
169<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]170<li>Create a subclass of the TargetMachine class that describes characteristics
171 of your target machine. Copy existing examples of specific TargetMachine
172 class and header files; for example, start with
173 <tt>SparcTargetMachine.cpp</tt> and <tt>SparcTargetMachine.h</tt>, but
174 change the file names for your target. Similarly, change code that
175 references "Sparc" to reference your target. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]176
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]177<li>Describe the register set of the target. Use TableGen to generate code for
178 register definition, register aliases, and register classes from a
179 target-specific <tt>RegisterInfo.td</tt> input file. You should also write
180 additional code for a subclass of the TargetRegisterInfo class that
181 represents the class register file data used for register allocation and
182 also describes the interactions between registers.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]183
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]184<li>Describe the instruction set of the target. Use TableGen to generate code
185 for target-specific instructions from target-specific versions of
186 <tt>TargetInstrFormats.td</tt> and <tt>TargetInstrInfo.td</tt>. You should
187 write additional code for a subclass of the TargetInstrInfo class to
188 represent machine instructions supported by the target machine. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]189
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]190<li>Describe the selection and conversion of the LLVM IR from a Directed Acyclic
191 Graph (DAG) representation of instructions to native target-specific
192 instructions. Use TableGen to generate code that matches patterns and
193 selects instructions based on additional information in a target-specific
194 version of <tt>TargetInstrInfo.td</tt>. Write code
195 for <tt>XXXISelDAGToDAG.cpp</tt>, where XXX identifies the specific target,
196 to perform pattern matching and DAG-to-DAG instruction selection. Also write
197 code in <tt>XXXISelLowering.cpp</tt> to replace or remove operations and
198 data types that are not supported natively in a SelectionDAG. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]199
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]200<li>Write code for an assembly printer that converts LLVM IR to a GAS format for
201 your target machine. You should add assembly strings to the instructions
202 defined in your target-specific version of <tt>TargetInstrInfo.td</tt>. You
203 should also write code for a subclass of AsmPrinter that performs the
204 LLVM-to-assembly conversion and a trivial subclass of TargetAsmInfo.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]205
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]206<li>Optionally, add support for subtargets (i.e., variants with different
207 capabilities). You should also write code for a subclass of the
208 TargetSubtarget class, which allows you to use the <tt>-mcpu=</tt>
209 and <tt>-mattr=</tt> command-line options.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]210
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]211<li>Optionally, add JIT support and create a machine code emitter (subclass of
212 TargetJITInfo) that is used to emit binary code directly into memory. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]213</ul>
214
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]215<p>
216In the <tt>.cpp</tt> and <tt>.h</tt>. files, initially stub up these methods and
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]217then implement them later. Initially, you may not know which private members
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]218that the class will need and which components will need to be subclassed.
219</p>
220
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]221</div>
222
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]223<div class="doc_subsection">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]224 <a name="Preliminaries">Preliminaries</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]225</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]226
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]227<div class="doc_text">
228
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]229<p>
230To actually create your compiler backend, you need to create and modify a few
231files. The absolute minimum is discussed here. But to actually use the LLVM
232target-independent code generator, you must perform the steps described in
233the <a href="http://www.llvm.org/docs/CodeGenerator.html">LLVM
234Target-Independent Code Generator</a> document.
235</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]236
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]237<p>
238First, you should create a subdirectory under <tt>lib/Target</tt> to hold all
239the files related to your target. If your target is called "Dummy," create the
240directory <tt>lib/Target/Dummy</tt>.
241</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]242
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]243<p>
244In this new
245directory, create a <tt>Makefile</tt>. It is easiest to copy a
246<tt>Makefile</tt> of another target and modify it. It should at least contain
247the <tt>LEVEL</tt>, <tt>LIBRARYNAME</tt> and <tt>TARGET</tt> variables, and then
248include <tt>$(LEVEL)/Makefile.common</tt>. The library can be
249named <tt>LLVMDummy</tt> (for example, see the MIPS target). Alternatively, you
250can split the library into <tt>LLVMDummyCodeGen</tt>
251and <tt>LLVMDummyAsmPrinter</tt>, the latter of which should be implemented in a
252subdirectory below <tt>lib/Target/Dummy</tt> (for example, see the PowerPC
253target).
254</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]255
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]256<p>
257Note that these two naming schemes are hardcoded into <tt>llvm-config</tt>.
258Using any other naming scheme will confuse <tt>llvm-config</tt> and produce a
259lot of (seemingly unrelated) linker errors when linking <tt>llc</tt>.
260</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]261
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]262<p>
263To make your target actually do something, you need to implement a subclass of
264<tt>TargetMachine</tt>. This implementation should typically be in the file
265<tt>lib/Target/DummyTargetMachine.cpp</tt>, but any file in
266the <tt>lib/Target</tt> directory will be built and should work. To use LLVM's
267target independent code generator, you should do what all current machine
268backends do: create a subclass of <tt>LLVMTargetMachine</tt>. (To create a
269target from scratch, create a subclass of <tt>TargetMachine</tt>.)
270</p>
271
272<p>
273To get LLVM to actually build and link your target, you need to add it to
274the <tt>TARGETS_TO_BUILD</tt> variable. To do this, you modify the configure
275script to know about your target when parsing the <tt>--enable-targets</tt>
276option. Search the configure script for <tt>TARGETS_TO_BUILD</tt>, add your
277target to the lists there (some creativity required), and then
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]278reconfigure. Alternatively, you can change <tt>autotools/configure.ac</tt> and
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]279regenerate configure by running <tt>./autoconf/AutoRegen.sh</tt>.
280</p>
281
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]282</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]283
284<!-- *********************************************************************** -->
285<div class="doc_section">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]286 <a name="TargetMachine">Target Machine</a>
287</div>
288<!-- *********************************************************************** -->
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]289
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]290<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]291
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]292<p>
293<tt>LLVMTargetMachine</tt> is designed as a base class for targets implemented
294with the LLVM target-independent code generator. The <tt>LLVMTargetMachine</tt>
295class should be specialized by a concrete target class that implements the
296various virtual methods. <tt>LLVMTargetMachine</tt> is defined as a subclass of
297<tt>TargetMachine</tt> in <tt>include/llvm/Target/TargetMachine.h</tt>. The
298<tt>TargetMachine</tt> class implementation (<tt>TargetMachine.cpp</tt>) also
299processes numerous command-line options.
300</p>
301
302<p>
303To create a concrete target-specific subclass of <tt>LLVMTargetMachine</tt>,
304start by copying an existing <tt>TargetMachine</tt> class and header. You
305should name the files that you create to reflect your specific target. For
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]306instance, for the SPARC target, name the files <tt>SparcTargetMachine.h</tt> and
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]307<tt>SparcTargetMachine.cpp</tt>.
308</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]309
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]310<p>
311For a target machine <tt>XXX</tt>, the implementation of
312<tt>XXXTargetMachine</tt> must have access methods to obtain objects that
313represent target components. These methods are named <tt>get*Info</tt>, and are
314intended to obtain the instruction set (<tt>getInstrInfo</tt>), register set
315(<tt>getRegisterInfo</tt>), stack frame layout (<tt>getFrameInfo</tt>), and
316similar information. <tt>XXXTargetMachine</tt> must also implement the
317<tt>getTargetData</tt> method to access an object with target-specific data
318characteristics, such as data type size and alignment requirements.
319</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]320
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]321<p>
322For instance, for the SPARC target, the header file
323<tt>SparcTargetMachine.h</tt> declares prototypes for several <tt>get*Info</tt>
324and <tt>getTargetData</tt> methods that simply return a class member.
325</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]326
327<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]328<pre>
329namespace llvm {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]330
331class Module;
332
333class SparcTargetMachine : public LLVMTargetMachine {
334 const TargetData DataLayout; // Calculates type size &amp; alignment
335 SparcSubtarget Subtarget;
336 SparcInstrInfo InstrInfo;
337 TargetFrameInfo FrameInfo;
338
339protected:
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]340 virtual const TargetAsmInfo *createTargetAsmInfo() const;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]341
342public:
343 SparcTargetMachine(const Module &amp;M, const std::string &amp;FS);
344
345 virtual const SparcInstrInfo *getInstrInfo() const {return &amp;InstrInfo; }
346 virtual const TargetFrameInfo *getFrameInfo() const {return &amp;FrameInfo; }
347 virtual const TargetSubtarget *getSubtargetImpl() const{return &amp;Subtarget; }
348 virtual const TargetRegisterInfo *getRegisterInfo() const {
349 return &amp;InstrInfo.getRegisterInfo();
350 }
351 virtual const TargetData *getTargetData() const { return &amp;DataLayout; }
352 static unsigned getModuleMatchQuality(const Module &amp;M);
353
354 // Pass Pipeline Configuration
355 virtual bool addInstSelector(PassManagerBase &amp;PM, bool Fast);
356 virtual bool addPreEmitPass(PassManagerBase &amp;PM, bool Fast);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]357};
358
359} // end namespace llvm
360</pre>
361</div>
362
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]363</div>
364
365
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]366<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]367
368<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]369<li><tt>getInstrInfo()</tt></li>
370<li><tt>getRegisterInfo()</tt></li>
371<li><tt>getFrameInfo()</tt></li>
372<li><tt>getTargetData()</tt></li>
373<li><tt>getSubtargetImpl()</tt></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]374</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]375
376<p>For some targets, you also need to support the following methods:</p>
377
378<ul>
379<li><tt>getTargetLowering()</tt></li>
380<li><tt>getJITInfo()</tt></li>
381</ul>
382
383<p>
384In addition, the <tt>XXXTargetMachine</tt> constructor should specify a
385<tt>TargetDescription</tt> string that determines the data layout for the target
386machine, including characteristics such as pointer size, alignment, and
387endianness. For example, the constructor for SparcTargetMachine contains the
388following:
389</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]390
391<div class="doc_code">
392<pre>
393SparcTargetMachine::SparcTargetMachine(const Module &amp;M, const std::string &amp;FS)
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]394 : DataLayout("E-p:32:32-f128:128:128"),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]395 Subtarget(M, FS), InstrInfo(Subtarget),
396 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
397}
398</pre>
399</div>
400
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]401</div>
402
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]403<div class="doc_text">
404
405<p>Hyphens separate portions of the <tt>TargetDescription</tt> string.</p>
406
407<ul>
408<li>An upper-case "<tt>E</tt>" in the string indicates a big-endian target data
409 model. a lower-case "<tt>e</tt>" indicates little-endian.</li>
410
411<li>"<tt>p:</tt>" is followed by pointer information: size, ABI alignment, and
412 preferred alignment. If only two figures follow "<tt>p:</tt>", then the
413 first value is pointer size, and the second value is both ABI and preferred
414 alignment.</li>
415
416<li>Then a letter for numeric type alignment: "<tt>i</tt>", "<tt>f</tt>",
417 "<tt>v</tt>", or "<tt>a</tt>" (corresponding to integer, floating point,
418 vector, or aggregate). "<tt>i</tt>", "<tt>v</tt>", or "<tt>a</tt>" are
419 followed by ABI alignment and preferred alignment. "<tt>f</tt>" is followed
420 by three values: the first indicates the size of a long double, then ABI
421 alignment, and then ABI preferred alignment.</li>
422</ul>
423
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]424</div>
425
426<!-- *********************************************************************** -->
427<div class="doc_section">
428 <a name="TargetRegistration">Target Registration</a>
429</div>
430<!-- *********************************************************************** -->
431
432<div class="doc_text">
433
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]434<p>
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]435You must also register your target with the <tt>TargetRegistry</tt>, which is
436what other LLVM tools use to be able to lookup and use your target at
437runtime. The <tt>TargetRegistry</tt> can be used directly, but for most targets
438there are helper templates which should take care of the work for you.</p>
439
440<p>
441All targets should declare a global <tt>Target</tt> object which is used to
442represent the target during registration. Then, in the target's TargetInfo
443library, the target should define that object and use
444the <tt>RegisterTarget</tt> template to register the target. For example, the Sparc registration code looks like this:
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]445</p>
446
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]447<div class="doc_code">
448<pre>
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]449Target llvm::TheSparcTarget;
450
451extern "C" void LLVMInitializeSparcTargetInfo() {
Benjamin Kramere15192b2009-08-05 15:42:44 +0000[diff] [blame]452 RegisterTarget&lt;Triple::sparc, /*HasJIT=*/false&gt;
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]453 X(TheSparcTarget, "sparc", "Sparc");
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]454}
455</pre>
456</div>
457
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]458<p>
459This allows the <tt>TargetRegistry</tt> to look up the target by name or by
460target triple. In addition, most targets will also register additional features
461which are available in separate libraries. These registration steps are
462separate, because some clients may wish to only link in some parts of the target
463-- the JIT code generator does not require the use of the assembler printer, for
464example. Here is an example of registering the Sparc assembly printer:
465</p>
466
467<div class="doc_code">
468<pre>
469extern "C" void LLVMInitializeSparcAsmPrinter() {
Benjamin Kramere15192b2009-08-05 15:42:44 +0000[diff] [blame]470 RegisterAsmPrinter&lt;SparcAsmPrinter&gt; X(TheSparcTarget);
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]471}
472</pre>
473</div>
474
475<p>
476For more information, see
477"<a href="/doxygen/TargetRegistry_8h-source.html">llvm/Target/TargetRegistry.h</a>".
478</p>
479
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]480</div>
481
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]482<!-- *********************************************************************** -->
483<div class="doc_section">
484 <a name="RegisterSet">Register Set and Register Classes</a>
485</div>
486<!-- *********************************************************************** -->
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]487
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]488<div class="doc_text">
489
490<p>
491You should describe a concrete target-specific class that represents the
492register file of a target machine. This class is called <tt>XXXRegisterInfo</tt>
493(where <tt>XXX</tt> identifies the target) and represents the class register
494file data that is used for register allocation. It also describes the
495interactions between registers.
496</p>
497
498<p>
499You also need to define register classes to categorize related registers. A
500register class should be added for groups of registers that are all treated the
501same way for some instruction. Typical examples are register classes for
502integer, floating-point, or vector registers. A register allocator allows an
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]503instruction to use any register in a specified register class to perform the
504instruction in a similar manner. Register classes allocate virtual registers to
505instructions from these sets, and register classes let the target-independent
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]506register allocator automatically choose the actual registers.
507</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]508
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]509<p>
510Much of the code for registers, including register definition, register aliases,
511and register classes, is generated by TableGen from <tt>XXXRegisterInfo.td</tt>
512input files and placed in <tt>XXXGenRegisterInfo.h.inc</tt> and
513<tt>XXXGenRegisterInfo.inc</tt> output files. Some of the code in the
514implementation of <tt>XXXRegisterInfo</tt> requires hand-coding.
515</p>
516
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]517</div>
518
519<!-- ======================================================================= -->
520<div class="doc_subsection">
521 <a name="RegisterDef">Defining a Register</a>
522</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]523
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]524<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]525
526<p>
527The <tt>XXXRegisterInfo.td</tt> file typically starts with register definitions
528for a target machine. The <tt>Register</tt> class (specified
529in <tt>Target.td</tt>) is used to define an object for each register. The
530specified string <tt>n</tt> becomes the <tt>Name</tt> of the register. The
531basic <tt>Register</tt> object does not have any subregisters and does not
532specify any aliases.
533</p>
534
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]535<div class="doc_code">
536<pre>
537class Register&lt;string n&gt; {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]538 string Namespace = "";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]539 string AsmName = n;
540 string Name = n;
541 int SpillSize = 0;
542 int SpillAlignment = 0;
543 list&lt;Register&gt; Aliases = [];
544 list&lt;Register&gt; SubRegs = [];
545 list&lt;int&gt; DwarfNumbers = [];
546}
547</pre>
548</div>
549
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]550<p>
551For example, in the <tt>X86RegisterInfo.td</tt> file, there are register
552definitions that utilize the Register class, such as:
553</p>
554
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]555<div class="doc_code">
556<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]557def AL : Register&lt;"AL"&gt;, DwarfRegNum&lt;[0, 0, 0]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]558</pre>
559</div>
560
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]561<p>
562This defines the register <tt>AL</tt> and assigns it values (with
563<tt>DwarfRegNum</tt>) that are used by <tt>gcc</tt>, <tt>gdb</tt>, or a debug
Chris Lattnerc3107782010-04-05 04:11:11 +0000[diff] [blame]564information writer to identify a register. For register
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]565<tt>AL</tt>, <tt>DwarfRegNum</tt> takes an array of 3 values representing 3
566different modes: the first element is for X86-64, the second for exception
567handling (EH) on X86-32, and the third is generic. -1 is a special Dwarf number
568that indicates the gcc number is undefined, and -2 indicates the register number
569is invalid for this mode.
570</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]571
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]572<p>
573From the previously described line in the <tt>X86RegisterInfo.td</tt> file,
574TableGen generates this code in the <tt>X86GenRegisterInfo.inc</tt> file:
575</p>
576
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]577<div class="doc_code">
578<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]579static const unsigned GR8[] = { X86::AL, ... };
580
581const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
582
583const TargetRegisterDesc RegisterDescriptors[] = {
584 ...
585{ "AL", "AL", AL_AliasSet, Empty_SubRegsSet, Empty_SubRegsSet, AL_SuperRegsSet }, ...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]586</pre>
587</div>
588
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]589<p>
590From the register info file, TableGen generates a <tt>TargetRegisterDesc</tt>
591object for each register. <tt>TargetRegisterDesc</tt> is defined in
592<tt>include/llvm/Target/TargetRegisterInfo.h</tt> with the following fields:
593</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]594
595<div class="doc_code">
596<pre>
597struct TargetRegisterDesc {
598 const char *AsmName; // Assembly language name for the register
599 const char *Name; // Printable name for the reg (for debugging)
600 const unsigned *AliasSet; // Register Alias Set
601 const unsigned *SubRegs; // Sub-register set
602 const unsigned *ImmSubRegs; // Immediate sub-register set
603 const unsigned *SuperRegs; // Super-register set
604};</pre>
605</div>
606
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]607<p>
608TableGen uses the entire target description file (<tt>.td</tt>) to determine
609text names for the register (in the <tt>AsmName</tt> and <tt>Name</tt> fields of
610<tt>TargetRegisterDesc</tt>) and the relationships of other registers to the
611defined register (in the other <tt>TargetRegisterDesc</tt> fields). In this
612example, other definitions establish the registers "<tt>AX</tt>",
613"<tt>EAX</tt>", and "<tt>RAX</tt>" as aliases for one another, so TableGen
614generates a null-terminated array (<tt>AL_AliasSet</tt>) for this register alias
615set.
616</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]617
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]618<p>
619The <tt>Register</tt> class is commonly used as a base class for more complex
620classes. In <tt>Target.td</tt>, the <tt>Register</tt> class is the base for the
621<tt>RegisterWithSubRegs</tt> class that is used to define registers that need to
622specify subregisters in the <tt>SubRegs</tt> list, as shown here:
623</p>
624
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]625<div class="doc_code">
626<pre>
627class RegisterWithSubRegs&lt;string n,
628list&lt;Register&gt; subregs&gt; : Register&lt;n&gt; {
629 let SubRegs = subregs;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]630}
631</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]632</div>
633
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]634<p>
635In <tt>SparcRegisterInfo.td</tt>, additional register classes are defined for
636SPARC: a Register subclass, SparcReg, and further subclasses: <tt>Ri</tt>,
637<tt>Rf</tt>, and <tt>Rd</tt>. SPARC registers are identified by 5-bit ID
638numbers, which is a feature common to these subclasses. Note the use of
639'<tt>let</tt>' expressions to override values that are initially defined in a
640superclass (such as <tt>SubRegs</tt> field in the <tt>Rd</tt> class).
641</p>
642
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]643<div class="doc_code">
644<pre>
645class SparcReg&lt;string n&gt; : Register&lt;n&gt; {
646 field bits&lt;5&gt; Num;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]647 let Namespace = "SP";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]648}
649// Ri - 32-bit integer registers
650class Ri&lt;bits&lt;5&gt; num, string n&gt; :
651SparcReg&lt;n&gt; {
652 let Num = num;
653}
654// Rf - 32-bit floating-point registers
655class Rf&lt;bits&lt;5&gt; num, string n&gt; :
656SparcReg&lt;n&gt; {
657 let Num = num;
658}
659// Rd - Slots in the FP register file for 64-bit
660floating-point values.
661class Rd&lt;bits&lt;5&gt; num, string n,
662list&lt;Register&gt; subregs&gt; : SparcReg&lt;n&gt; {
663 let Num = num;
664 let SubRegs = subregs;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]665}
666</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]667</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]668
669<p>
670In the <tt>SparcRegisterInfo.td</tt> file, there are register definitions that
671utilize these subclasses of <tt>Register</tt>, such as:
672</p>
673
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]674<div class="doc_code">
675<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]676def G0 : Ri&lt; 0, "G0"&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]677DwarfRegNum&lt;[0]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]678def G1 : Ri&lt; 1, "G1"&gt;, DwarfRegNum&lt;[1]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]679...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]680def F0 : Rf&lt; 0, "F0"&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]681DwarfRegNum&lt;[32]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]682def F1 : Rf&lt; 1, "F1"&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]683DwarfRegNum&lt;[33]&gt;;
684...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]685def D0 : Rd&lt; 0, "F0", [F0, F1]&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]686DwarfRegNum&lt;[32]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]687def D1 : Rd&lt; 2, "F2", [F2, F3]&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]688DwarfRegNum&lt;[34]&gt;;
689</pre>
690</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]691
692<p>
693The last two registers shown above (<tt>D0</tt> and <tt>D1</tt>) are
694double-precision floating-point registers that are aliases for pairs of
695single-precision floating-point sub-registers. In addition to aliases, the
696sub-register and super-register relationships of the defined register are in
697fields of a register's TargetRegisterDesc.
698</p>
699
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]700</div>
701
702<!-- ======================================================================= -->
703<div class="doc_subsection">
704 <a name="RegisterClassDef">Defining a Register Class</a>
705</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]706
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]707<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]708
709<p>
710The <tt>RegisterClass</tt> class (specified in <tt>Target.td</tt>) is used to
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]711define an object that represents a group of related registers and also defines
712the default allocation order of the registers. A target description file
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]713<tt>XXXRegisterInfo.td</tt> that uses <tt>Target.td</tt> can construct register
714classes using the following class:
715</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]716
717<div class="doc_code">
718<pre>
719class RegisterClass&lt;string namespace,
720list&lt;ValueType&gt; regTypes, int alignment,
721 list&lt;Register&gt; regList&gt; {
722 string Namespace = namespace;
723 list&lt;ValueType&gt; RegTypes = regTypes;
724 int Size = 0; // spill size, in bits; zero lets tblgen pick the size
725 int Alignment = alignment;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]726
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]727 // CopyCost is the cost of copying a value between two registers
728 // default value 1 means a single instruction
729 // A negative value means copying is extremely expensive or impossible
730 int CopyCost = 1;
731 list&lt;Register&gt; MemberList = regList;
732
733 // for register classes that are subregisters of this class
734 list&lt;RegisterClass&gt; SubRegClassList = [];
735
736 code MethodProtos = [{}]; // to insert arbitrary code
737 code MethodBodies = [{}];
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]738}
739</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]740</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]741
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]742<p>To define a RegisterClass, use the following 4 arguments:</p>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]743
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]744<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]745<li>The first argument of the definition is the name of the namespace.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]746
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]747<li>The second argument is a list of <tt>ValueType</tt> register type values
748 that are defined in <tt>include/llvm/CodeGen/ValueTypes.td</tt>. Defined
749 values include integer types (such as <tt>i16</tt>, <tt>i32</tt>,
750 and <tt>i1</tt> for Boolean), floating-point types
751 (<tt>f32</tt>, <tt>f64</tt>), and vector types (for example, <tt>v8i16</tt>
752 for an <tt>8 x i16</tt> vector). All registers in a <tt>RegisterClass</tt>
753 must have the same <tt>ValueType</tt>, but some registers may store vector
754 data in different configurations. For example a register that can process a
755 128-bit vector may be able to handle 16 8-bit integer elements, 8 16-bit
756 integers, 4 32-bit integers, and so on. </li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]757
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]758<li>The third argument of the <tt>RegisterClass</tt> definition specifies the
759 alignment required of the registers when they are stored or loaded to
760 memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]761
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]762<li>The final argument, <tt>regList</tt>, specifies which registers are in this
763 class. If an <tt>allocation_order_*</tt> method is not specified,
764 then <tt>regList</tt> also defines the order of allocation used by the
765 register allocator.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]766</ul>
767
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]768<p>
769In <tt>SparcRegisterInfo.td</tt>, three RegisterClass objects are defined:
770<tt>FPRegs</tt>, <tt>DFPRegs</tt>, and <tt>IntRegs</tt>. For all three register
771classes, the first argument defines the namespace with the string
772'<tt>SP</tt>'. <tt>FPRegs</tt> defines a group of 32 single-precision
773floating-point registers (<tt>F0</tt> to <tt>F31</tt>); <tt>DFPRegs</tt> defines
774a group of 16 double-precision registers
775(<tt>D0-D15</tt>). For <tt>IntRegs</tt>, the <tt>MethodProtos</tt>
776and <tt>MethodBodies</tt> methods are used by TableGen to insert the specified
777code into generated output.
778</p>
779
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]780<div class="doc_code">
781<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]782def FPRegs : RegisterClass&lt;"SP", [f32], 32,
783 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
784 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]&gt;;
785
786def DFPRegs : RegisterClass&lt;"SP", [f64], 64,
787 [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]788&nbsp;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]789def IntRegs : RegisterClass&lt;"SP", [i32], 32,
790 [L0, L1, L2, L3, L4, L5, L6, L7,
791 I0, I1, I2, I3, I4, I5,
792 O0, O1, O2, O3, O4, O5, O7,
793 G1,
794 // Non-allocatable regs:
795 G2, G3, G4,
796 O6, // stack ptr
797 I6, // frame ptr
798 I7, // return address
799 G0, // constant zero
800 G5, G6, G7 // reserved for kernel
801 ]&gt; {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]802 let MethodProtos = [{
803 iterator allocation_order_end(const MachineFunction &amp;MF) const;
804 }];
805 let MethodBodies = [{
806 IntRegsClass::iterator
807 IntRegsClass::allocation_order_end(const MachineFunction &amp;MF) const {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]808 return end() - 10 // Don't allocate special registers
809 -1;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]810 }
811 }];
812}
813</pre>
814</div>
815
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]816<p>
817Using <tt>SparcRegisterInfo.td</tt> with TableGen generates several output files
818that are intended for inclusion in other source code that you write.
819<tt>SparcRegisterInfo.td</tt> generates <tt>SparcGenRegisterInfo.h.inc</tt>,
820which should be included in the header file for the implementation of the SPARC
821register implementation that you write (<tt>SparcRegisterInfo.h</tt>). In
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]822<tt>SparcGenRegisterInfo.h.inc</tt> a new structure is defined called
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]823<tt>SparcGenRegisterInfo</tt> that uses <tt>TargetRegisterInfo</tt> as its
824base. It also specifies types, based upon the defined register
825classes: <tt>DFPRegsClass</tt>, <tt>FPRegsClass</tt>, and <tt>IntRegsClass</tt>.
826</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]827
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]828<p>
829<tt>SparcRegisterInfo.td</tt> also generates <tt>SparcGenRegisterInfo.inc</tt>,
830which is included at the bottom of <tt>SparcRegisterInfo.cpp</tt>, the SPARC
831register implementation. The code below shows only the generated integer
832registers and associated register classes. The order of registers
833in <tt>IntRegs</tt> reflects the order in the definition of <tt>IntRegs</tt> in
834the target description file. Take special note of the use
835of <tt>MethodBodies</tt> in <tt>SparcRegisterInfo.td</tt> to create code in
836<tt>SparcGenRegisterInfo.inc</tt>. <tt>MethodProtos</tt> generates similar code
837in <tt>SparcGenRegisterInfo.h.inc</tt>.
838</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]839
840<div class="doc_code">
841<pre> // IntRegs Register Class...
842 static const unsigned IntRegs[] = {
843 SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5,
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]844 SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3,
845 SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3,
846 SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3,
847 SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5,
848 SP::G6, SP::G7,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]849 };
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]850
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]851 // IntRegsVTs Register Class Value Types...
852 static const MVT::ValueType IntRegsVTs[] = {
853 MVT::i32, MVT::Other
854 };
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]855
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]856namespace SP { // Register class instances
857 DFPRegsClass&nbsp;&nbsp;&nbsp; DFPRegsRegClass;
858 FPRegsClass&nbsp;&nbsp;&nbsp;&nbsp; FPRegsRegClass;
859 IntRegsClass&nbsp;&nbsp;&nbsp; IntRegsRegClass;
860...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]861 // IntRegs Sub-register Classess...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]862 static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
863 NULL
864 };
865...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]866 // IntRegs Super-register Classess...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]867 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
868 NULL
869 };
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]870...
871 // IntRegs Register Class sub-classes...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]872 static const TargetRegisterClass* const IntRegsSubclasses [] = {
873 NULL
874 };
875...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]876 // IntRegs Register Class super-classes...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]877 static const TargetRegisterClass* const IntRegsSuperclasses [] = {
878 NULL
879 };
880...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]881 IntRegsClass::iterator
882 IntRegsClass::allocation_order_end(const MachineFunction &amp;MF) const {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]883 return end()-10 // Don't allocate special registers
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]884 -1;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]885 }
886
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]887 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID,
888 IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses,
889 IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]890}
891</pre>
892</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]893
894</div>
895
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]896<!-- ======================================================================= -->
897<div class="doc_subsection">
Chris Lattner7d12b4b2008-11-11 19:36:31 +0000[diff] [blame]898 <a name="implementRegister">Implement a subclass of</a>
899 <a href="http://www.llvm.org/docs/CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]900</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]901
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]902<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]903
904<p>
905The final step is to hand code portions of <tt>XXXRegisterInfo</tt>, which
906implements the interface described in <tt>TargetRegisterInfo.h</tt>. These
907functions return <tt>0</tt>, <tt>NULL</tt>, or <tt>false</tt>, unless
908overridden. Here is a list of functions that are overridden for the SPARC
909implementation in <tt>SparcRegisterInfo.cpp</tt>:
910</p>
911
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]912<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]913<li><tt>getCalleeSavedRegs</tt> &mdash; Returns a list of callee-saved registers
914 in the order of the desired callee-save stack frame offset.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]915
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]916<li><tt>getReservedRegs</tt> &mdash; Returns a bitset indexed by physical
917 register numbers, indicating if a particular register is unavailable.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]918
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]919<li><tt>hasFP</tt> &mdash; Return a Boolean indicating if a function should have
920 a dedicated frame pointer register.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]921
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]922<li><tt>eliminateCallFramePseudoInstr</tt> &mdash; If call frame setup or
923 destroy pseudo instructions are used, this can be called to eliminate
924 them.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]925
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]926<li><tt>eliminateFrameIndex</tt> &mdash; Eliminate abstract frame indices from
927 instructions that may use them.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]928
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]929<li><tt>emitPrologue</tt> &mdash; Insert prologue code into the function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]930
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]931<li><tt>emitEpilogue</tt> &mdash; Insert epilogue code into the function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]932</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]933
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]934</div>
935
936<!-- *********************************************************************** -->
937<div class="doc_section">
938 <a name="InstructionSet">Instruction Set</a>
939</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]940
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]941<!-- *********************************************************************** -->
942<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]943
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]944<p>
945During the early stages of code generation, the LLVM IR code is converted to a
946<tt>SelectionDAG</tt> with nodes that are instances of the <tt>SDNode</tt> class
947containing target instructions. An <tt>SDNode</tt> has an opcode, operands, type
948requirements, and operation properties. For example, is an operation
949commutative, does an operation load from memory. The various operation node
950types are described in the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
951file (values of the <tt>NodeType</tt> enum in the <tt>ISD</tt> namespace).
952</p>
953
954<p>
955TableGen uses the following target description (<tt>.td</tt>) input files to
956generate much of the code for instruction definition:
957</p>
958
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]959<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]960<li><tt>Target.td</tt> &mdash; Where the <tt>Instruction</tt>, <tt>Operand</tt>,
961 <tt>InstrInfo</tt>, and other fundamental classes are defined.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]962
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]963<li><tt>TargetSelectionDAG.td</tt>&mdash; Used by <tt>SelectionDAG</tt>
964 instruction selection generators, contains <tt>SDTC*</tt> classes (selection
965 DAG type constraint), definitions of <tt>SelectionDAG</tt> nodes (such as
966 <tt>imm</tt>, <tt>cond</tt>, <tt>bb</tt>, <tt>add</tt>, <tt>fadd</tt>,
967 <tt>sub</tt>), and pattern support (<tt>Pattern</tt>, <tt>Pat</tt>,
968 <tt>PatFrag</tt>, <tt>PatLeaf</tt>, <tt>ComplexPattern</tt>.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]969
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]970<li><tt>XXXInstrFormats.td</tt> &mdash; Patterns for definitions of
971 target-specific instructions.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]972
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]973<li><tt>XXXInstrInfo.td</tt> &mdash; Target-specific definitions of instruction
974 templates, condition codes, and instructions of an instruction set. For
975 architecture modifications, a different file name may be used. For example,
976 for Pentium with SSE instruction, this file is <tt>X86InstrSSE.td</tt>, and
977 for Pentium with MMX, this file is <tt>X86InstrMMX.td</tt>.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]978</ul>
979
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]980<p>
981There is also a target-specific <tt>XXX.td</tt> file, where <tt>XXX</tt> is the
982name of the target. The <tt>XXX.td</tt> file includes the other <tt>.td</tt>
983input files, but its contents are only directly important for subtargets.
984</p>
985
986<p>
987You should describe a concrete target-specific class <tt>XXXInstrInfo</tt> that
988represents machine instructions supported by a target machine.
989<tt>XXXInstrInfo</tt> contains an array of <tt>XXXInstrDescriptor</tt> objects,
990each of which describes one instruction. An instruction descriptor defines:</p>
991
992<ul>
993<li>Opcode mnemonic</li>
994
995<li>Number of operands</li>
996
997<li>List of implicit register definitions and uses</li>
998
999<li>Target-independent properties (such as memory access, is commutable)</li>
1000
1001<li>Target-specific flags </li>
1002</ul>
1003
1004<p>
1005The Instruction class (defined in <tt>Target.td</tt>) is mostly used as a base
1006for more complex instruction classes.
1007</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1008
1009<div class="doc_code">
1010<pre>class Instruction {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1011 string Namespace = "";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1012 dag OutOperandList; // An dag containing the MI def operand list.
1013 dag InOperandList; // An dag containing the MI use operand list.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1014 string AsmString = ""; // The .s format to print the instruction with.
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1015 list&lt;dag&gt; Pattern; // Set to the DAG pattern for this instruction
1016 list&lt;Register&gt; Uses = [];
1017 list&lt;Register&gt; Defs = [];
1018 list&lt;Predicate&gt; Predicates = []; // predicates turned into isel match code
1019 ... remainder not shown for space ...
1020}
1021</pre>
1022</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1023
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1024<p>
1025A <tt>SelectionDAG</tt> node (<tt>SDNode</tt>) should contain an object
1026representing a target-specific instruction that is defined
1027in <tt>XXXInstrInfo.td</tt>. The instruction objects should represent
1028instructions from the architecture manual of the target machine (such as the
1029SPARC Architecture Manual for the SPARC target).
1030</p>
1031
1032<p>
1033A single instruction from the architecture manual is often modeled as multiple
1034target instructions, depending upon its operands. For example, a manual might
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1035describe an add instruction that takes a register or an immediate operand. An
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1036LLVM target could model this with two instructions named <tt>ADDri</tt> and
1037<tt>ADDrr</tt>.
1038</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1039
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1040<p>
1041You should define a class for each instruction category and define each opcode
1042as a subclass of the category with appropriate parameters such as the fixed
1043binary encoding of opcodes and extended opcodes. You should map the register
1044bits to the bits of the instruction in which they are encoded (for the
1045JIT). Also you should specify how the instruction should be printed when the
1046automatic assembly printer is used.
1047</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1048
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1049<p>
1050As is described in the SPARC Architecture Manual, Version 8, there are three
1051major 32-bit formats for instructions. Format 1 is only for the <tt>CALL</tt>
1052instruction. Format 2 is for branch on condition codes and <tt>SETHI</tt> (set
1053high bits of a register) instructions. Format 3 is for other instructions.
1054</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1055
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1056<p>
1057Each of these formats has corresponding classes in <tt>SparcInstrFormat.td</tt>.
1058<tt>InstSP</tt> is a base class for other instruction classes. Additional base
1059classes are specified for more precise formats: for example
1060in <tt>SparcInstrFormat.td</tt>, <tt>F2_1</tt> is for <tt>SETHI</tt>,
1061and <tt>F2_2</tt> is for branches. There are three other base
1062classes: <tt>F3_1</tt> for register/register operations, <tt>F3_2</tt> for
1063register/immediate operations, and <tt>F3_3</tt> for floating-point
1064operations. <tt>SparcInstrInfo.td</tt> also adds the base class Pseudo for
1065synthetic SPARC instructions.
1066</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1067
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1068<p>
1069<tt>SparcInstrInfo.td</tt> largely consists of operand and instruction
1070definitions for the SPARC target. In <tt>SparcInstrInfo.td</tt>, the following
1071target description file entry, <tt>LDrr</tt>, defines the Load Integer
1072instruction for a Word (the <tt>LD</tt> SPARC opcode) from a memory address to a
1073register. The first parameter, the value 3 (<tt>11<sub>2</sub></tt>), is the
1074operation value for this category of operation. The second parameter
1075(<tt>000000<sub>2</sub></tt>) is the specific operation value
1076for <tt>LD</tt>/Load Word. The third parameter is the output destination, which
1077is a register operand and defined in the <tt>Register</tt> target description
1078file (<tt>IntRegs</tt>).
1079</p>
1080
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1081<div class="doc_code">
1082<pre>def LDrr : F3_1 &lt;3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1083 "ld [$addr], $dst",
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1084 [(set IntRegs:$dst, (load ADDRrr:$addr))]&gt;;
1085</pre>
1086</div>
1087
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1088<p>
1089The fourth parameter is the input source, which uses the address
1090operand <tt>MEMrr</tt> that is defined earlier in <tt>SparcInstrInfo.td</tt>:
1091</p>
1092
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1093<div class="doc_code">
1094<pre>def MEMrr : Operand&lt;i32&gt; {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1095 let PrintMethod = "printMemOperand";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1096 let MIOperandInfo = (ops IntRegs, IntRegs);
1097}
1098</pre>
1099</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1100
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1101<p>
1102The fifth parameter is a string that is used by the assembly printer and can be
1103left as an empty string until the assembly printer interface is implemented. The
1104sixth and final parameter is the pattern used to match the instruction during
1105the SelectionDAG Select Phase described in
1106(<a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
1107Target-Independent Code Generator</a>). This parameter is detailed in the next
1108section, <a href="#InstructionSelector">Instruction Selector</a>.
1109</p>
1110
1111<p>
1112Instruction class definitions are not overloaded for different operand types, so
1113separate versions of instructions are needed for register, memory, or immediate
1114value operands. For example, to perform a Load Integer instruction for a Word
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1115from an immediate operand to a register, the following instruction class is
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1116defined:
1117</p>
1118
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1119<div class="doc_code">
1120<pre>def LDri : F3_2 &lt;3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1121 "ld [$addr], $dst",
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1122 [(set IntRegs:$dst, (load ADDRri:$addr))]&gt;;
1123</pre>
1124</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1125
1126<p>
1127Writing these definitions for so many similar instructions can involve a lot of
1128cut and paste. In td files, the <tt>multiclass</tt> directive enables the
1129creation of templates to define several instruction classes at once (using
1130the <tt>defm</tt> directive). For example in <tt>SparcInstrInfo.td</tt>, the
1131<tt>multiclass</tt> pattern <tt>F3_12</tt> is defined to create 2 instruction
1132classes each time <tt>F3_12</tt> is invoked:
1133</p>
1134
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1135<div class="doc_code">
1136<pre>multiclass F3_12 &lt;string OpcStr, bits&lt;6&gt; Op3Val, SDNode OpNode&gt; {
1137 def rr : F3_1 &lt;2, Op3Val,
1138 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1139 !strconcat(OpcStr, " $b, $c, $dst"),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1140 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]&gt;;
1141 def ri : F3_2 &lt;2, Op3Val,
1142 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1143 !strconcat(OpcStr, " $b, $c, $dst"),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1144 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]&gt;;
1145}
1146</pre>
1147</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1148
1149<p>
1150So when the <tt>defm</tt> directive is used for the <tt>XOR</tt>
1151and <tt>ADD</tt> instructions, as seen below, it creates four instruction
1152objects: <tt>XORrr</tt>, <tt>XORri</tt>, <tt>ADDrr</tt>, and <tt>ADDri</tt>.
1153</p>
1154
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1155<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1156<pre>
1157defm XOR : F3_12&lt;"xor", 0b000011, xor&gt;;
1158defm ADD : F3_12&lt;"add", 0b000000, add&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1159</pre>
1160</div>
1161
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1162<p>
1163<tt>SparcInstrInfo.td</tt> also includes definitions for condition codes that
1164are referenced by branch instructions. The following definitions
1165in <tt>SparcInstrInfo.td</tt> indicate the bit location of the SPARC condition
1166code. For example, the 10<sup>th</sup> bit represents the 'greater than'
1167condition for integers, and the 22<sup>nd</sup> bit represents the 'greater
1168than' condition for floats.
1169</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1170
1171<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1172<pre>
1173def ICC_NE : ICC_VAL&lt; 9&gt;; // Not Equal
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1174def ICC_E : ICC_VAL&lt; 1&gt;; // Equal
1175def ICC_G : ICC_VAL&lt;10&gt;; // Greater
1176...
1177def FCC_U : FCC_VAL&lt;23&gt;; // Unordered
1178def FCC_G : FCC_VAL&lt;22&gt;; // Greater
1179def FCC_UG : FCC_VAL&lt;21&gt;; // Unordered or Greater
1180...
1181</pre>
1182</div>
1183
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1184<p>
1185(Note that <tt>Sparc.h</tt> also defines enums that correspond to the same SPARC
1186condition codes. Care must be taken to ensure the values in <tt>Sparc.h</tt>
1187correspond to the values in <tt>SparcInstrInfo.td</tt>. I.e.,
1188<tt>SPCC::ICC_NE = 9</tt>, <tt>SPCC::FCC_U = 23</tt> and so on.)
1189</p>
1190
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1191</div>
1192
1193<!-- ======================================================================= -->
1194<div class="doc_subsection">
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1195 <a name="operandMapping">Instruction Operand Mapping</a>
1196</div>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1197
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1198<div class="doc_text">
1199
1200<p>
1201The code generator backend maps instruction operands to fields in the
1202instruction. Operands are assigned to unbound fields in the instruction in the
1203order they are defined. Fields are bound when they are assigned a value. For
1204example, the Sparc target defines the <tt>XNORrr</tt> instruction as
1205a <tt>F3_1</tt> format instruction having three operands.
1206</p>
1207
1208<div class="doc_code">
1209<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1210def XNORrr : F3_1&lt;2, 0b000111,
1211 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1212 "xnor $b, $c, $dst",
1213 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1214</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1215</div>
1216
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1217<p>
1218The instruction templates in <tt>SparcInstrFormats.td</tt> show the base class
1219for <tt>F3_1</tt> is <tt>InstSP</tt>.
1220</p>
1221
1222<div class="doc_code">
1223<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1224class InstSP&lt;dag outs, dag ins, string asmstr, list&lt;dag&gt; pattern&gt; : Instruction {
1225 field bits&lt;32&gt; Inst;
1226 let Namespace = "SP";
1227 bits&lt;2&gt; op;
1228 let Inst{31-30} = op;
1229 dag OutOperandList = outs;
1230 dag InOperandList = ins;
1231 let AsmString = asmstr;
1232 let Pattern = pattern;
1233}
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1234</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1235</div>
1236
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1237<p><tt>InstSP</tt> leaves the <tt>op</tt> field unbound.</p>
1238
1239<div class="doc_code">
1240<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1241class F3&lt;dag outs, dag ins, string asmstr, list&lt;dag&gt; pattern&gt;
1242 : InstSP&lt;outs, ins, asmstr, pattern&gt; {
1243 bits&lt;5&gt; rd;
1244 bits&lt;6&gt; op3;
1245 bits&lt;5&gt; rs1;
1246 let op{1} = 1; // Op = 2 or 3
1247 let Inst{29-25} = rd;
1248 let Inst{24-19} = op3;
1249 let Inst{18-14} = rs1;
1250}
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1251</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1252</div>
1253
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1254<p>
1255<tt>F3</tt> binds the <tt>op</tt> field and defines the <tt>rd</tt>,
1256<tt>op3</tt>, and <tt>rs1</tt> fields. <tt>F3</tt> format instructions will
1257bind the operands <tt>rd</tt>, <tt>op3</tt>, and <tt>rs1</tt> fields.
1258</p>
1259
1260<div class="doc_code">
1261<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1262class F3_1&lt;bits&lt;2&gt; opVal, bits&lt;6&gt; op3val, dag outs, dag ins,
1263 string asmstr, list&lt;dag&gt; pattern&gt; : F3&lt;outs, ins, asmstr, pattern&gt; {
1264 bits&lt;8&gt; asi = 0; // asi not currently used
1265 bits&lt;5&gt; rs2;
1266 let op = opVal;
1267 let op3 = op3val;
1268 let Inst{13} = 0; // i field = 0
1269 let Inst{12-5} = asi; // address space identifier
1270 let Inst{4-0} = rs2;
1271}
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1272</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1273</div>
1274
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1275<p>
1276<tt>F3_1</tt> binds the <tt>op3</tt> field and defines the <tt>rs2</tt>
1277fields. <tt>F3_1</tt> format instructions will bind the operands to the <tt>rd</tt>,
1278<tt>rs1</tt>, and <tt>rs2</tt> fields. This results in the <tt>XNORrr</tt>
1279instruction binding <tt>$dst</tt>, <tt>$b</tt>, and <tt>$c</tt> operands to
1280the <tt>rd</tt>, <tt>rs1</tt>, and <tt>rs2</tt> fields respectively.
1281</p>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1282
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1283</div>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1284
1285<!-- ======================================================================= -->
1286<div class="doc_subsection">
Chris Lattner7d12b4b2008-11-11 19:36:31 +0000[diff] [blame]1287 <a name="implementInstr">Implement a subclass of </a>
1288 <a href="http://www.llvm.org/docs/CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1289</div>
1290
1291<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1292
1293<p>
1294The final step is to hand code portions of <tt>XXXInstrInfo</tt>, which
1295implements the interface described in <tt>TargetInstrInfo.h</tt>. These
1296functions return <tt>0</tt> or a Boolean or they assert, unless
1297overridden. Here's a list of functions that are overridden for the SPARC
1298implementation in <tt>SparcInstrInfo.cpp</tt>:
1299</p>
1300
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1301<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1302<li><tt>isMoveInstr</tt> &mdash; Return true if the instruction is a register to
1303 register move; false, otherwise.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1304
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1305<li><tt>isLoadFromStackSlot</tt> &mdash; If the specified machine instruction is
1306 a direct load from a stack slot, return the register number of the
1307 destination and the <tt>FrameIndex</tt> of the stack slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1308
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1309<li><tt>isStoreToStackSlot</tt> &mdash; If the specified machine instruction is
1310 a direct store to a stack slot, return the register number of the
1311 destination and the <tt>FrameIndex</tt> of the stack slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1312
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1313<li><tt>copyRegToReg</tt> &mdash; Copy values between a pair of registers.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1314
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1315<li><tt>storeRegToStackSlot</tt> &mdash; Store a register value to a stack
1316 slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1317
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1318<li><tt>loadRegFromStackSlot</tt> &mdash; Load a register value from a stack
1319 slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1320
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1321<li><tt>storeRegToAddr</tt> &mdash; Store a register value to memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1322
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1323<li><tt>loadRegFromAddr</tt> &mdash; Load a register value from memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1324
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1325<li><tt>foldMemoryOperand</tt> &mdash; Attempt to combine instructions of any
1326 load or store instruction for the specified operand(s).</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1327</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1328
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1329</div>
1330
1331<!-- ======================================================================= -->
1332<div class="doc_subsection">
1333 <a name="branchFolding">Branch Folding and If Conversion</a>
1334</div>
1335<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1336
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1337<p>
1338Performance can be improved by combining instructions or by eliminating
1339instructions that are never reached. The <tt>AnalyzeBranch</tt> method
1340in <tt>XXXInstrInfo</tt> may be implemented to examine conditional instructions
1341and remove unnecessary instructions. <tt>AnalyzeBranch</tt> looks at the end of
1342a machine basic block (MBB) for opportunities for improvement, such as branch
1343folding and if conversion. The <tt>BranchFolder</tt> and <tt>IfConverter</tt>
1344machine function passes (see the source files <tt>BranchFolding.cpp</tt> and
1345<tt>IfConversion.cpp</tt> in the <tt>lib/CodeGen</tt> directory) call
1346<tt>AnalyzeBranch</tt> to improve the control flow graph that represents the
1347instructions.
1348</p>
1349
1350<p>
1351Several implementations of <tt>AnalyzeBranch</tt> (for ARM, Alpha, and X86) can
1352be examined as models for your own <tt>AnalyzeBranch</tt> implementation. Since
1353SPARC does not implement a useful <tt>AnalyzeBranch</tt>, the ARM target
1354implementation is shown below.
1355</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1356
1357<p><tt>AnalyzeBranch</tt> returns a Boolean value and takes four parameters:</p>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1358
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1359<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1360<li><tt>MachineBasicBlock &amp;MBB</tt> &mdash; The incoming block to be
1361 examined.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1362
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1363<li><tt>MachineBasicBlock *&amp;TBB</tt> &mdash; A destination block that is
1364 returned. For a conditional branch that evaluates to true, <tt>TBB</tt> is
1365 the destination.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1366
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1367<li><tt>MachineBasicBlock *&amp;FBB</tt> &mdash; For a conditional branch that
1368 evaluates to false, <tt>FBB</tt> is returned as the destination.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1369
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1370<li><tt>std::vector&lt;MachineOperand&gt; &amp;Cond</tt> &mdash; List of
1371 operands to evaluate a condition for a conditional branch.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1372</ul>
1373
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1374<p>
1375In the simplest case, if a block ends without a branch, then it falls through to
1376the successor block. No destination blocks are specified for either <tt>TBB</tt>
1377or <tt>FBB</tt>, so both parameters return <tt>NULL</tt>. The start of
1378the <tt>AnalyzeBranch</tt> (see code below for the ARM target) shows the
1379function parameters and the code for the simplest case.
1380</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1381
1382<div class="doc_code">
1383<pre>bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &amp;MBB,
1384 MachineBasicBlock *&amp;TBB, MachineBasicBlock *&amp;FBB,
1385 std::vector&lt;MachineOperand&gt; &amp;Cond) const
1386{
1387 MachineBasicBlock::iterator I = MBB.end();
1388 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
1389 return false;
1390</pre>
1391</div>
1392
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1393<p>
1394If a block ends with a single unconditional branch instruction, then
1395<tt>AnalyzeBranch</tt> (shown below) should return the destination of that
1396branch in the <tt>TBB</tt> parameter.
1397</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1398
1399<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1400<pre>
1401 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
1402 TBB = LastInst-&gt;getOperand(0).getMBB();
1403 return false;
1404 }
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1405</pre>
1406</div>
1407
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1408<p>
1409If a block ends with two unconditional branches, then the second branch is never
1410reached. In that situation, as shown below, remove the last branch instruction
1411and return the penultimate branch in the <tt>TBB</tt> parameter.
1412</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1413
1414<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1415<pre>
1416 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &amp;&amp;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1417 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
1418 TBB = SecondLastInst-&gt;getOperand(0).getMBB();
1419 I = LastInst;
1420 I-&gt;eraseFromParent();
1421 return false;
1422 }
1423</pre>
1424</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1425
1426<p>
1427A block may end with a single conditional branch instruction that falls through
1428to successor block if the condition evaluates to false. In that case,
1429<tt>AnalyzeBranch</tt> (shown below) should return the destination of that
1430conditional branch in the <tt>TBB</tt> parameter and a list of operands in
1431the <tt>Cond</tt> parameter to evaluate the condition.
1432</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1433
1434<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1435<pre>
1436 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
1437 // Block ends with fall-through condbranch.
1438 TBB = LastInst-&gt;getOperand(0).getMBB();
1439 Cond.push_back(LastInst-&gt;getOperand(1));
1440 Cond.push_back(LastInst-&gt;getOperand(2));
1441 return false;
1442 }
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1443</pre>
1444</div>
1445
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1446<p>
1447If a block ends with both a conditional branch and an ensuing unconditional
1448branch, then <tt>AnalyzeBranch</tt> (shown below) should return the conditional
1449branch destination (assuming it corresponds to a conditional evaluation of
1450'<tt>true</tt>') in the <tt>TBB</tt> parameter and the unconditional branch
1451destination in the <tt>FBB</tt> (corresponding to a conditional evaluation of
1452'<tt>false</tt>'). A list of operands to evaluate the condition should be
1453returned in the <tt>Cond</tt> parameter.
1454</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1455
1456<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1457<pre>
1458 unsigned SecondLastOpc = SecondLastInst-&gt;getOpcode();
1459
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1460 if ((SecondLastOpc == ARM::Bcc &amp;&amp; LastOpc == ARM::B) ||
1461 (SecondLastOpc == ARM::tBcc &amp;&amp; LastOpc == ARM::tB)) {
1462 TBB = SecondLastInst-&gt;getOperand(0).getMBB();
1463 Cond.push_back(SecondLastInst-&gt;getOperand(1));
1464 Cond.push_back(SecondLastInst-&gt;getOperand(2));
1465 FBB = LastInst-&gt;getOperand(0).getMBB();
1466 return false;
1467 }
1468</pre>
1469</div>
1470
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1471<p>
1472For the last two cases (ending with a single conditional branch or ending with
1473one conditional and one unconditional branch), the operands returned in
1474the <tt>Cond</tt> parameter can be passed to methods of other instructions to
1475create new branches or perform other operations. An implementation
1476of <tt>AnalyzeBranch</tt> requires the helper methods <tt>RemoveBranch</tt>
1477and <tt>InsertBranch</tt> to manage subsequent operations.
1478</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1479
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1480<p>
1481<tt>AnalyzeBranch</tt> should return false indicating success in most circumstances.
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1482<tt>AnalyzeBranch</tt> should only return true when the method is stumped about what to
1483do, for example, if a block has three terminating branches. <tt>AnalyzeBranch</tt> may
1484return true if it encounters a terminator it cannot handle, such as an indirect
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1485branch.
1486</p>
1487
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1488</div>
1489
1490<!-- *********************************************************************** -->
1491<div class="doc_section">
1492 <a name="InstructionSelector">Instruction Selector</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]1493</div>
1494<!-- *********************************************************************** -->
1495
1496<div class="doc_text">
1497
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1498<p>
1499LLVM uses a <tt>SelectionDAG</tt> to represent LLVM IR instructions, and nodes
1500of the <tt>SelectionDAG</tt> ideally represent native target
1501instructions. During code generation, instruction selection passes are performed
1502to convert non-native DAG instructions into native target-specific
1503instructions. The pass described in <tt>XXXISelDAGToDAG.cpp</tt> is used to
1504match patterns and perform DAG-to-DAG instruction selection. Optionally, a pass
1505may be defined (in <tt>XXXBranchSelector.cpp</tt>) to perform similar DAG-to-DAG
1506operations for branch instructions. Later, the code in
1507<tt>XXXISelLowering.cpp</tt> replaces or removes operations and data types not
1508supported natively (legalizes) in a <tt>SelectionDAG</tt>.
1509</p>
1510
1511<p>
1512TableGen generates code for instruction selection using the following target
1513description input files:
1514</p>
1515
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]1516<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1517<li><tt>XXXInstrInfo.td</tt> &mdash; Contains definitions of instructions in a
1518 target-specific instruction set, generates <tt>XXXGenDAGISel.inc</tt>, which
1519 is included in <tt>XXXISelDAGToDAG.cpp</tt>.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1520
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1521<li><tt>XXXCallingConv.td</tt> &mdash; Contains the calling and return value
1522 conventions for the target architecture, and it generates
1523 <tt>XXXGenCallingConv.inc</tt>, which is included in
1524 <tt>XXXISelLowering.cpp</tt>.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]1525</ul>
1526
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1527<p>
1528The implementation of an instruction selection pass must include a header that
1529declares the <tt>FunctionPass</tt> class or a subclass of <tt>FunctionPass</tt>. In
1530<tt>XXXTargetMachine.cpp</tt>, a Pass Manager (PM) should add each instruction
1531selection pass into the queue of passes to run.
1532</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1533
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1534<p>
1535The LLVM static compiler (<tt>llc</tt>) is an excellent tool for visualizing the
1536contents of DAGs. To display the <tt>SelectionDAG</tt> before or after specific
1537processing phases, use the command line options for <tt>llc</tt>, described
1538at <a href="http://llvm.org/docs/CodeGenerator.html#selectiondag_process">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1539SelectionDAG Instruction Selection Process</a>.
1540</p>
1541
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1542<p>
1543To describe instruction selector behavior, you should add patterns for lowering
1544LLVM code into a <tt>SelectionDAG</tt> as the last parameter of the instruction
1545definitions in <tt>XXXInstrInfo.td</tt>. For example, in
1546<tt>SparcInstrInfo.td</tt>, this entry defines a register store operation, and
1547the last parameter describes a pattern with the store DAG operator.
1548</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1549
1550<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1551<pre>
1552def STrr : F3_1&lt; 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
1553 "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1554</pre>
1555</div>
1556
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1557<p>
1558<tt>ADDRrr</tt> is a memory mode that is also defined in
1559<tt>SparcInstrInfo.td</tt>:
1560</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1561
1562<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1563<pre>
1564def ADDRrr : ComplexPattern&lt;i32, 2, "SelectADDRrr", [], []&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1565</pre>
1566</div>
1567
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1568<p>
1569The definition of <tt>ADDRrr</tt> refers to <tt>SelectADDRrr</tt>, which is a
1570function defined in an implementation of the Instructor Selector (such
1571as <tt>SparcISelDAGToDAG.cpp</tt>).
1572</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1573
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1574<p>
1575In <tt>lib/Target/TargetSelectionDAG.td</tt>, the DAG operator for store is
1576defined below:
1577</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1578
1579<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1580<pre>
1581def store : PatFrag&lt;(ops node:$val, node:$ptr),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1582 (st node:$val, node:$ptr), [{
1583 if (StoreSDNode *ST = dyn_cast&lt;StoreSDNode&gt;(N))
1584 return !ST-&gt;isTruncatingStore() &amp;&amp;
1585 ST-&gt;getAddressingMode() == ISD::UNINDEXED;
1586 return false;
1587}]&gt;;
1588</pre>
1589</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1590
1591<p>
1592<tt>XXXInstrInfo.td</tt> also generates (in <tt>XXXGenDAGISel.inc</tt>) the
1593<tt>SelectCode</tt> method that is used to call the appropriate processing
1594method for an instruction. In this example, <tt>SelectCode</tt>
1595calls <tt>Select_ISD_STORE</tt> for the <tt>ISD::STORE</tt> opcode.
1596</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1597
1598<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1599<pre>
1600SDNode *SelectCode(SDValue N) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1601 ...
Dan Gohman50ef90d2009-01-28 21:36:46 +0000[diff] [blame]1602 MVT::ValueType NVT = N.getNode()-&gt;getValueType(0);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1603 switch (N.getOpcode()) {
1604 case ISD::STORE: {
1605 switch (NVT) {
1606 default:
1607 return Select_ISD_STORE(N);
1608 break;
1609 }
1610 break;
1611 }
1612 ...
1613</pre>
1614</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1615
1616<p>
1617The pattern for <tt>STrr</tt> is matched, so elsewhere in
1618<tt>XXXGenDAGISel.inc</tt>, code for <tt>STrr</tt> is created for
1619<tt>Select_ISD_STORE</tt>. The <tt>Emit_22</tt> method is also generated
1620in <tt>XXXGenDAGISel.inc</tt> to complete the processing of this
1621instruction.
1622</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1623
1624<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1625<pre>
1626SDNode *Select_ISD_STORE(const SDValue &amp;N) {
Dan Gohman50ef90d2009-01-28 21:36:46 +0000[diff] [blame]1627 SDValue Chain = N.getOperand(0);
1628 if (Predicate_store(N.getNode())) {
1629 SDValue N1 = N.getOperand(1);
1630 SDValue N2 = N.getOperand(2);
1631 SDValue CPTmp0;
1632 SDValue CPTmp1;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1633
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1634 // Pattern: (st:void IntRegs:i32:$src,
1635 // ADDRrr:i32:$addr)&lt;&lt;P:Predicate_store&gt;&gt;
1636 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
1637 // Pattern complexity = 13 cost = 1 size = 0
1638 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &amp;&amp;
Dan Gohman50ef90d2009-01-28 21:36:46 +0000[diff] [blame]1639 N1.getNode()-&gt;getValueType(0) == MVT::i32 &amp;&amp;
1640 N2.getNode()-&gt;getValueType(0) == MVT::i32) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1641 return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
1642 }
1643...
1644</pre>
1645</div>
1646
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1647</div>
1648
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1649<!-- ======================================================================= -->
1650<div class="doc_subsection">
1651 <a name="LegalizePhase">The SelectionDAG Legalize Phase</a>
1652</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1653
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1654<div class="doc_text">
1655
1656<p>
1657The Legalize phase converts a DAG to use types and operations that are natively
1658supported by the target. For natively unsupported types and operations, you need
1659to add code to the target-specific XXXTargetLowering implementation to convert
1660unsupported types and operations to supported ones.
1661</p>
1662
1663<p>
1664In the constructor for the <tt>XXXTargetLowering</tt> class, first use the
1665<tt>addRegisterClass</tt> method to specify which types are supports and which
1666register classes are associated with them. The code for the register classes are
1667generated by TableGen from <tt>XXXRegisterInfo.td</tt> and placed
1668in <tt>XXXGenRegisterInfo.h.inc</tt>. For example, the implementation of the
1669constructor for the SparcTargetLowering class (in
1670<tt>SparcISelLowering.cpp</tt>) starts with the following code:
1671</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1672
1673<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1674<pre>
1675addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1676addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1677addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
1678</pre>
1679</div>
1680
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1681<p>
1682You should examine the node types in the <tt>ISD</tt> namespace
1683(<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>) and determine which
1684operations the target natively supports. For operations that do <b>not</b> have
1685native support, add a callback to the constructor for the XXXTargetLowering
1686class, so the instruction selection process knows what to do. The TargetLowering
1687class callback methods (declared in <tt>llvm/Target/TargetLowering.h</tt>) are:
1688</p>
1689
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1690<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1691<li><tt>setOperationAction</tt> &mdash; General operation.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1692
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1693<li><tt>setLoadExtAction</tt> &mdash; Load with extension.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1694
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1695<li><tt>setTruncStoreAction</tt> &mdash; Truncating store.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1696
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1697<li><tt>setIndexedLoadAction</tt> &mdash; Indexed load.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1698
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1699<li><tt>setIndexedStoreAction</tt> &mdash; Indexed store.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1700
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1701<li><tt>setConvertAction</tt> &mdash; Type conversion.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1702
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1703<li><tt>setCondCodeAction</tt> &mdash; Support for a given condition code.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1704</ul>
1705
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1706<p>
1707Note: on older releases, <tt>setLoadXAction</tt> is used instead
1708of <tt>setLoadExtAction</tt>. Also, on older releases,
1709<tt>setCondCodeAction</tt> may not be supported. Examine your release
1710to see what methods are specifically supported.
1711</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1712
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1713<p>
1714These callbacks are used to determine that an operation does or does not work
1715with a specified type (or types). And in all cases, the third parameter is
1716a <tt>LegalAction</tt> type enum value: <tt>Promote</tt>, <tt>Expand</tt>,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1717<tt>Custom</tt>, or <tt>Legal</tt>. <tt>SparcISelLowering.cpp</tt>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1718contains examples of all four <tt>LegalAction</tt> values.
1719</p>
1720
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1721</div>
1722
1723<!-- _______________________________________________________________________ -->
1724<div class="doc_subsubsection">
1725 <a name="promote">Promote</a>
1726</div>
1727
1728<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1729
1730<p>
1731For an operation without native support for a given type, the specified type may
1732be promoted to a larger type that is supported. For example, SPARC does not
1733support a sign-extending load for Boolean values (<tt>i1</tt> type), so
1734in <tt>SparcISelLowering.cpp</tt> the third parameter below, <tt>Promote</tt>,
1735changes <tt>i1</tt> type values to a large type before loading.
1736</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1737
1738<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1739<pre>
1740setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1741</pre>
1742</div>
1743
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1744</div>
1745
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1746<!-- _______________________________________________________________________ -->
1747<div class="doc_subsubsection">
1748 <a name="expand">Expand</a>
1749</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1750
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1751<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1752
1753<p>
1754For a type without native support, a value may need to be broken down further,
1755rather than promoted. For an operation without native support, a combination of
1756other operations may be used to similar effect. In SPARC, the floating-point
1757sine and cosine trig operations are supported by expansion to other operations,
1758as indicated by the third parameter, <tt>Expand</tt>, to
1759<tt>setOperationAction</tt>:
1760</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1761
1762<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1763<pre>
1764setOperationAction(ISD::FSIN, MVT::f32, Expand);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1765setOperationAction(ISD::FCOS, MVT::f32, Expand);
1766</pre>
1767</div>
1768
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1769</div>
1770
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1771<!-- _______________________________________________________________________ -->
1772<div class="doc_subsubsection">
1773 <a name="custom">Custom</a>
1774</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1775
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1776<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1777
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1778<p>
1779For some operations, simple type promotion or operation expansion may be
1780insufficient. In some cases, a special intrinsic function must be implemented.
1781</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1782
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1783<p>
1784For example, a constant value may require special treatment, or an operation may
1785require spilling and restoring registers in the stack and working with register
1786allocators.
1787</p>
1788
1789<p>
1790As seen in <tt>SparcISelLowering.cpp</tt> code below, to perform a type
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1791conversion from a floating point value to a signed integer, first the
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1792<tt>setOperationAction</tt> should be called with <tt>Custom</tt> as the third
1793parameter:
1794</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1795
1796<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1797<pre>
1798setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1799</pre>
1800</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1801
1802<p>
1803In the <tt>LowerOperation</tt> method, for each <tt>Custom</tt> operation, a
1804case statement should be added to indicate what function to call. In the
1805following code, an <tt>FP_TO_SINT</tt> opcode will call
1806the <tt>LowerFP_TO_SINT</tt> method:
1807</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1808
1809<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1810<pre>
1811SDValue SparcTargetLowering::LowerOperation(SDValue Op, SelectionDAG &amp;DAG) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1812 switch (Op.getOpcode()) {
1813 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1814 ...
1815 }
1816}
1817</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1818</div>
1819
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1820<p>
1821Finally, the <tt>LowerFP_TO_SINT</tt> method is implemented, using an FP
1822register to convert the floating-point value to an integer.
1823</p>
1824
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1825<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1826<pre>
1827static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &amp;DAG) {
1828 assert(Op.getValueType() == MVT::i32);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1829 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
1830 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1831}
1832</pre>
1833</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1834
1835</div>
1836
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1837<!-- _______________________________________________________________________ -->
1838<div class="doc_subsubsection">
1839 <a name="legal">Legal</a>
1840</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1841
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1842<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1843
1844<p>
1845The <tt>Legal</tt> LegalizeAction enum value simply indicates that an
1846operation <b>is</b> natively supported. <tt>Legal</tt> represents the default
1847condition, so it is rarely used. In <tt>SparcISelLowering.cpp</tt>, the action
1848for <tt>CTPOP</tt> (an operation to count the bits set in an integer) is
1849natively supported only for SPARC v9. The following code enables
1850the <tt>Expand</tt> conversion technique for non-v9 SPARC implementations.
1851</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1852
1853<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1854<pre>
1855setOperationAction(ISD::CTPOP, MVT::i32, Expand);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1856...
1857if (TM.getSubtarget&lt;SparcSubtarget&gt;().isV9())
1858 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1859 case ISD::SETULT: return SPCC::ICC_CS;
1860 case ISD::SETULE: return SPCC::ICC_LEU;
1861 case ISD::SETUGT: return SPCC::ICC_GU;
1862 case ISD::SETUGE: return SPCC::ICC_CC;
1863 }
1864}
1865</pre>
1866</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1867
1868</div>
1869
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1870<!-- ======================================================================= -->
1871<div class="doc_subsection">
1872 <a name="callingConventions">Calling Conventions</a>
1873</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1874
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1875<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1876
1877<p>
1878To support target-specific calling conventions, <tt>XXXGenCallingConv.td</tt>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1879uses interfaces (such as CCIfType and CCAssignToReg) that are defined in
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1880<tt>lib/Target/TargetCallingConv.td</tt>. TableGen can take the target
1881descriptor file <tt>XXXGenCallingConv.td</tt> and generate the header
1882file <tt>XXXGenCallingConv.inc</tt>, which is typically included
1883in <tt>XXXISelLowering.cpp</tt>. You can use the interfaces in
1884<tt>TargetCallingConv.td</tt> to specify:
1885</p>
1886
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1887<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1888<li>The order of parameter allocation.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1889
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1890<li>Where parameters and return values are placed (that is, on the stack or in
1891 registers).</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1892
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1893<li>Which registers may be used.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1894
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1895<li>Whether the caller or callee unwinds the stack.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1896</ul>
1897
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1898<p>
1899The following example demonstrates the use of the <tt>CCIfType</tt> and
1900<tt>CCAssignToReg</tt> interfaces. If the <tt>CCIfType</tt> predicate is true
1901(that is, if the current argument is of type <tt>f32</tt> or <tt>f64</tt>), then
1902the action is performed. In this case, the <tt>CCAssignToReg</tt> action assigns
1903the argument value to the first available register: either <tt>R0</tt>
1904or <tt>R1</tt>.
1905</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1906
1907<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1908<pre>
1909CCIfType&lt;[f32,f64], CCAssignToReg&lt;[R0, R1]&gt;&gt;
1910</pre>
1911</div>
1912
1913<p>
1914<tt>SparcCallingConv.td</tt> contains definitions for a target-specific
1915return-value calling convention (RetCC_Sparc32) and a basic 32-bit C calling
1916convention (<tt>CC_Sparc32</tt>). The definition of <tt>RetCC_Sparc32</tt>
1917(shown below) indicates which registers are used for specified scalar return
1918types. A single-precision float is returned to register <tt>F0</tt>, and a
1919double-precision float goes to register <tt>D0</tt>. A 32-bit integer is
1920returned in register <tt>I0</tt> or <tt>I1</tt>.
1921</p>
1922
1923<div class="doc_code">
1924<pre>
1925def RetCC_Sparc32 : CallingConv&lt;[
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1926 CCIfType&lt;[i32], CCAssignToReg&lt;[I0, I1]&gt;&gt;,
1927 CCIfType&lt;[f32], CCAssignToReg&lt;[F0]&gt;&gt;,
1928 CCIfType&lt;[f64], CCAssignToReg&lt;[D0]&gt;&gt;
1929]&gt;;
1930</pre>
1931</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1932
1933<p>
1934The definition of <tt>CC_Sparc32</tt> in <tt>SparcCallingConv.td</tt> introduces
1935<tt>CCAssignToStack</tt>, which assigns the value to a stack slot with the
1936specified size and alignment. In the example below, the first parameter, 4,
1937indicates the size of the slot, and the second parameter, also 4, indicates the
1938stack alignment along 4-byte units. (Special cases: if size is zero, then the
1939ABI size is used; if alignment is zero, then the ABI alignment is used.)
1940</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1941
1942<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1943<pre>
1944def CC_Sparc32 : CallingConv&lt;[
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1945 // All arguments get passed in integer registers if there is space.
1946 CCIfType&lt;[i32, f32, f64], CCAssignToReg&lt;[I0, I1, I2, I3, I4, I5]&gt;&gt;,
1947 CCAssignToStack&lt;4, 4&gt;
1948]&gt;;
1949</pre>
1950</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1951
1952<p>
1953<tt>CCDelegateTo</tt> is another commonly used interface, which tries to find a
1954specified sub-calling convention, and, if a match is found, it is invoked. In
1955the following example (in <tt>X86CallingConv.td</tt>), the definition of
1956<tt>RetCC_X86_32_C</tt> ends with <tt>CCDelegateTo</tt>. After the current value
1957is assigned to the register <tt>ST0</tt> or <tt>ST1</tt>,
1958the <tt>RetCC_X86Common</tt> is invoked.
1959</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1960
1961<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1962<pre>
1963def RetCC_X86_32_C : CallingConv&lt;[
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1964 CCIfType&lt;[f32], CCAssignToReg&lt;[ST0, ST1]&gt;&gt;,
1965 CCIfType&lt;[f64], CCAssignToReg&lt;[ST0, ST1]&gt;&gt;,
1966 CCDelegateTo&lt;RetCC_X86Common&gt;
1967]&gt;;
1968</pre>
1969</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1970
1971<p>
1972<tt>CCIfCC</tt> is an interface that attempts to match the given name to the
1973current calling convention. If the name identifies the current calling
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1974convention, then a specified action is invoked. In the following example (in
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1975<tt>X86CallingConv.td</tt>), if the <tt>Fast</tt> calling convention is in use,
1976then <tt>RetCC_X86_32_Fast</tt> is invoked. If the <tt>SSECall</tt> calling
1977convention is in use, then <tt>RetCC_X86_32_SSE</tt> is invoked.
1978</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1979
1980<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1981<pre>
1982def RetCC_X86_32 : CallingConv&lt;[
1983 CCIfCC&lt;"CallingConv::Fast", CCDelegateTo&lt;RetCC_X86_32_Fast&gt;&gt;,
1984 CCIfCC&lt;"CallingConv::X86_SSECall", CCDelegateTo&lt;RetCC_X86_32_SSE&gt;&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1985 CCDelegateTo&lt;RetCC_X86_32_C&gt;
1986]&gt;;
1987</pre>
1988</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1989
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1990<p>Other calling convention interfaces include:</p>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1991
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1992<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1993<li><tt>CCIf &lt;predicate, action&gt;</tt> &mdash; If the predicate matches,
1994 apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1995
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1996<li><tt>CCIfInReg &lt;action&gt;</tt> &mdash; If the argument is marked with the
1997 '<tt>inreg</tt>' attribute, then apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1998
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1999<li><tt>CCIfNest &lt;action&gt;</tt> &mdash; Inf the argument is marked with the
2000 '<tt>nest</tt>' attribute, then apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2001
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2002<li><tt>CCIfNotVarArg &lt;action&gt;</tt> &mdash; If the current function does
2003 not take a variable number of arguments, apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2004
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2005<li><tt>CCAssignToRegWithShadow &lt;registerList, shadowList&gt;</tt> &mdash;
2006 similar to <tt>CCAssignToReg</tt>, but with a shadow list of registers.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2007
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2008<li><tt>CCPassByVal &lt;size, align&gt;</tt> &mdash; Assign value to a stack
2009 slot with the minimum specified size and alignment.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2010
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2011<li><tt>CCPromoteToType &lt;type&gt;</tt> &mdash; Promote the current value to
2012 the specified type.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2013
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2014<li><tt>CallingConv &lt;[actions]&gt;</tt> &mdash; Define each calling
2015 convention that is supported.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2016</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2017
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2018</div>
2019
2020<!-- *********************************************************************** -->
2021<div class="doc_section">
2022 <a name="assemblyPrinter">Assembly Printer</a>
2023</div>
2024<!-- *********************************************************************** -->
2025
2026<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2027
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2028<p>
2029During the code emission stage, the code generator may utilize an LLVM pass to
2030produce assembly output. To do this, you want to implement the code for a
2031printer that converts LLVM IR to a GAS-format assembly language for your target
2032machine, using the following steps:
2033</p>
2034
2035<ul>
2036<li>Define all the assembly strings for your target, adding them to the
2037 instructions defined in the <tt>XXXInstrInfo.td</tt> file.
2038 (See <a href="#InstructionSet">Instruction Set</a>.) TableGen will produce
2039 an output file (<tt>XXXGenAsmWriter.inc</tt>) with an implementation of
2040 the <tt>printInstruction</tt> method for the XXXAsmPrinter class.</li>
2041
2042<li>Write <tt>XXXTargetAsmInfo.h</tt>, which contains the bare-bones declaration
2043 of the <tt>XXXTargetAsmInfo</tt> class (a subclass
2044 of <tt>TargetAsmInfo</tt>).</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2045
2046<li>Write <tt>XXXTargetAsmInfo.cpp</tt>, which contains target-specific values
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2047 for <tt>TargetAsmInfo</tt> properties and sometimes new implementations for
2048 methods.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2049
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2050<li>Write <tt>XXXAsmPrinter.cpp</tt>, which implements the <tt>AsmPrinter</tt>
2051 class that performs the LLVM-to-assembly conversion.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2052</ul>
2053
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2054<p>
2055The code in <tt>XXXTargetAsmInfo.h</tt> is usually a trivial declaration of the
2056<tt>XXXTargetAsmInfo</tt> class for use in <tt>XXXTargetAsmInfo.cpp</tt>.
2057Similarly, <tt>XXXTargetAsmInfo.cpp</tt> usually has a few declarations of
2058<tt>XXXTargetAsmInfo</tt> replacement values that override the default values
2059in <tt>TargetAsmInfo.cpp</tt>. For example in <tt>SparcTargetAsmInfo.cpp</tt>:
2060</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2061
2062<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2063<pre>
2064SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &amp;TM) {
2065 Data16bitsDirective = "\t.half\t";
2066 Data32bitsDirective = "\t.word\t";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2067 Data64bitsDirective = 0; // .xword is only supported by V9.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2068 ZeroDirective = "\t.skip\t";
2069 CommentString = "!";
2070 ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2071}
2072</pre>
2073</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2074
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2075<p>
2076The X86 assembly printer implementation (<tt>X86TargetAsmInfo</tt>) is an
Chris Lattnerb6d66742009-08-02 04:02:52 +0000[diff] [blame]2077example where the target specific <tt>TargetAsmInfo</tt> class uses an
2078overridden methods: <tt>ExpandInlineAsm</tt>.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2079</p>
2080
2081<p>
2082A target-specific implementation of AsmPrinter is written in
2083<tt>XXXAsmPrinter.cpp</tt>, which implements the <tt>AsmPrinter</tt> class that
2084converts the LLVM to printable assembly. The implementation must include the
2085following headers that have declarations for the <tt>AsmPrinter</tt> and
2086<tt>MachineFunctionPass</tt> classes. The <tt>MachineFunctionPass</tt> is a
2087subclass of <tt>FunctionPass</tt>.
2088</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2089
2090<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2091<pre>
2092#include "llvm/CodeGen/AsmPrinter.h"
2093#include "llvm/CodeGen/MachineFunctionPass.h"
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2094</pre>
2095</div>
2096
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2097<p>
2098As a <tt>FunctionPass</tt>, <tt>AsmPrinter</tt> first
2099calls <tt>doInitialization</tt> to set up the <tt>AsmPrinter</tt>. In
2100<tt>SparcAsmPrinter</tt>, a <tt>Mangler</tt> object is instantiated to process
2101variable names.
2102</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2103
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2104<p>
2105In <tt>XXXAsmPrinter.cpp</tt>, the <tt>runOnMachineFunction</tt> method
2106(declared in <tt>MachineFunctionPass</tt>) must be implemented
2107for <tt>XXXAsmPrinter</tt>. In <tt>MachineFunctionPass</tt>,
2108the <tt>runOnFunction</tt> method invokes <tt>runOnMachineFunction</tt>.
2109Target-specific implementations of <tt>runOnMachineFunction</tt> differ, but
2110generally do the following to process each machine function:
2111</p>
2112
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2113<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2114<li>Call <tt>SetupMachineFunction</tt> to perform initialization.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2115
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2116<li>Call <tt>EmitConstantPool</tt> to print out (to the output stream) constants
2117 which have been spilled to memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2118
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2119<li>Call <tt>EmitJumpTableInfo</tt> to print out jump tables used by the current
2120 function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2121
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2122<li>Print out the label for the current function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2123
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2124<li>Print out the code for the function, including basic block labels and the
2125 assembly for the instruction (using <tt>printInstruction</tt>)</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2126</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2127
2128<p>
2129The <tt>XXXAsmPrinter</tt> implementation must also include the code generated
2130by TableGen that is output in the <tt>XXXGenAsmWriter.inc</tt> file. The code
2131in <tt>XXXGenAsmWriter.inc</tt> contains an implementation of the
2132<tt>printInstruction</tt> method that may call these methods:
2133</p>
2134
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2135<ul>
2136<li><tt>printOperand</tt></li>
2137
2138<li><tt>printMemOperand</tt></li>
2139
2140<li><tt>printCCOperand (for conditional statements)</tt></li>
2141
2142<li><tt>printDataDirective</tt></li>
2143
2144<li><tt>printDeclare</tt></li>
2145
2146<li><tt>printImplicitDef</tt></li>
2147
2148<li><tt>printInlineAsm</tt></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2149</ul>
2150
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2151<p>
2152The implementations of <tt>printDeclare</tt>, <tt>printImplicitDef</tt>,
2153<tt>printInlineAsm</tt>, and <tt>printLabel</tt> in <tt>AsmPrinter.cpp</tt> are
2154generally adequate for printing assembly and do not need to be
Chris Lattnerdeb8c152009-09-12 22:57:37 +0000[diff] [blame]2155overridden.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2156</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2157
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2158<p>
2159The <tt>printOperand</tt> method is implemented with a long switch/case
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2160statement for the type of operand: register, immediate, basic block, external
2161symbol, global address, constant pool index, or jump table index. For an
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2162instruction with a memory address operand, the <tt>printMemOperand</tt> method
2163should be implemented to generate the proper output. Similarly,
2164<tt>printCCOperand</tt> should be used to print a conditional operand.
2165</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2166
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2167<p><tt>doFinalization</tt> should be overridden in <tt>XXXAsmPrinter</tt>, and
2168it should be called to shut down the assembly printer. During
2169<tt>doFinalization</tt>, global variables and constants are printed to
2170output.
2171</p>
2172
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2173</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2174
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2175<!-- *********************************************************************** -->
2176<div class="doc_section">
2177 <a name="subtargetSupport">Subtarget Support</a>
2178</div>
2179<!-- *********************************************************************** -->
2180
2181<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2182
2183<p>
2184Subtarget support is used to inform the code generation process of instruction
2185set variations for a given chip set. For example, the LLVM SPARC implementation
2186provided covers three major versions of the SPARC microprocessor architecture:
2187Version 8 (V8, which is a 32-bit architecture), Version 9 (V9, a 64-bit
2188architecture), and the UltraSPARC architecture. V8 has 16 double-precision
2189floating-point registers that are also usable as either 32 single-precision or 8
2190quad-precision registers. V8 is also purely big-endian. V9 has 32
2191double-precision floating-point registers that are also usable as 16
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2192quad-precision registers, but cannot be used as single-precision registers. The
2193UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2194extensions.
2195</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2196
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2197<p>
2198If subtarget support is needed, you should implement a target-specific
2199XXXSubtarget class for your architecture. This class should process the
2200command-line options <tt>-mcpu=</tt> and <tt>-mattr=</tt>.
2201</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2202
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2203<p>
2204TableGen uses definitions in the <tt>Target.td</tt> and <tt>Sparc.td</tt> files
2205to generate code in <tt>SparcGenSubtarget.inc</tt>. In <tt>Target.td</tt>, shown
2206below, the <tt>SubtargetFeature</tt> interface is defined. The first 4 string
2207parameters of the <tt>SubtargetFeature</tt> interface are a feature name, an
2208attribute set by the feature, the value of the attribute, and a description of
2209the feature. (The fifth parameter is a list of features whose presence is
2210implied, and its default value is an empty array.)
2211</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2212
2213<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2214<pre>
2215class SubtargetFeature&lt;string n, string a, string v, string d,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2216 list&lt;SubtargetFeature&gt; i = []&gt; {
2217 string Name = n;
2218 string Attribute = a;
2219 string Value = v;
2220 string Desc = d;
2221 list&lt;SubtargetFeature&gt; Implies = i;
2222}
2223</pre>
2224</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2225
2226<p>
2227In the <tt>Sparc.td</tt> file, the SubtargetFeature is used to define the
2228following features.
2229</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2230
2231<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2232<pre>
2233def FeatureV9 : SubtargetFeature&lt;"v9", "IsV9", "true",
2234 "Enable SPARC-V9 instructions"&gt;;
2235def FeatureV8Deprecated : SubtargetFeature&lt;"deprecated-v8",
2236 "V8DeprecatedInsts", "true",
2237 "Enable deprecated V8 instructions in V9 mode"&gt;;
2238def FeatureVIS : SubtargetFeature&lt;"vis", "IsVIS", "true",
2239 "Enable UltraSPARC Visual Instruction Set extensions"&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2240</pre>
2241</div>
2242
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2243<p>
2244Elsewhere in <tt>Sparc.td</tt>, the Proc class is defined and then is used to
2245define particular SPARC processor subtypes that may have the previously
2246described features.
2247</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2248
2249<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2250<pre>
2251class Proc&lt;string Name, list&lt;SubtargetFeature&gt; Features&gt;
2252 : Processor&lt;Name, NoItineraries, Features&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2253&nbsp;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2254def : Proc&lt;"generic", []&gt;;
2255def : Proc&lt;"v8", []&gt;;
2256def : Proc&lt;"supersparc", []&gt;;
2257def : Proc&lt;"sparclite", []&gt;;
2258def : Proc&lt;"f934", []&gt;;
2259def : Proc&lt;"hypersparc", []&gt;;
2260def : Proc&lt;"sparclite86x", []&gt;;
2261def : Proc&lt;"sparclet", []&gt;;
2262def : Proc&lt;"tsc701", []&gt;;
2263def : Proc&lt;"v9", [FeatureV9]&gt;;
2264def : Proc&lt;"ultrasparc", [FeatureV9, FeatureV8Deprecated]&gt;;
2265def : Proc&lt;"ultrasparc3", [FeatureV9, FeatureV8Deprecated]&gt;;
2266def : Proc&lt;"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2267</pre>
2268</div>
2269
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2270<p>
2271From <tt>Target.td</tt> and <tt>Sparc.td</tt> files, the resulting
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2272SparcGenSubtarget.inc specifies enum values to identify the features, arrays of
2273constants to represent the CPU features and CPU subtypes, and the
2274ParseSubtargetFeatures method that parses the features string that sets
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2275specified subtarget options. The generated <tt>SparcGenSubtarget.inc</tt> file
2276should be included in the <tt>SparcSubtarget.cpp</tt>. The target-specific
2277implementation of the XXXSubtarget method should follow this pseudocode:
2278</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2279
2280<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2281<pre>
2282XXXSubtarget::XXXSubtarget(const Module &amp;M, const std::string &amp;FS) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2283 // Set the default features
2284 // Determine default and user specified characteristics of the CPU
2285 // Call ParseSubtargetFeatures(FS, CPU) to parse the features string
2286 // Perform any additional operations
2287}
2288</pre>
2289</div>
2290
Bill Wendlinge9e6fd92009-04-05 00:43:04 +0000[diff] [blame]2291</div>
2292
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2293<!-- *********************************************************************** -->
2294<div class="doc_section">
2295 <a name="jitSupport">JIT Support</a>
2296</div>
2297<!-- *********************************************************************** -->
2298
2299<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2300
2301<p>
2302The implementation of a target machine optionally includes a Just-In-Time (JIT)
2303code generator that emits machine code and auxiliary structures as binary output
2304that can be written directly to memory. To do this, implement JIT code
2305generation by performing the following steps:
2306</p>
2307
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2308<ul>
2309<li>Write an <tt>XXXCodeEmitter.cpp</tt> file that contains a machine function
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2310 pass that transforms target-machine instructions into relocatable machine
2311 code.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2312
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2313<li>Write an <tt>XXXJITInfo.cpp</tt> file that implements the JIT interfaces for
2314 target-specific code-generation activities, such as emitting machine code
2315 and stubs.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2316
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2317<li>Modify <tt>XXXTargetMachine</tt> so that it provides a
2318 <tt>TargetJITInfo</tt> object through its <tt>getJITInfo</tt> method.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2319</ul>
2320
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2321<p>
2322There are several different approaches to writing the JIT support code. For
2323instance, TableGen and target descriptor files may be used for creating a JIT
2324code generator, but are not mandatory. For the Alpha and PowerPC target
2325machines, TableGen is used to generate <tt>XXXGenCodeEmitter.inc</tt>, which
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2326contains the binary coding of machine instructions and the
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2327<tt>getBinaryCodeForInstr</tt> method to access those codes. Other JIT
2328implementations do not.
2329</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2330
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2331<p>
2332Both <tt>XXXJITInfo.cpp</tt> and <tt>XXXCodeEmitter.cpp</tt> must include the
2333<tt>llvm/CodeGen/MachineCodeEmitter.h</tt> header file that defines the
2334<tt>MachineCodeEmitter</tt> class containing code for several callback functions
2335that write data (in bytes, words, strings, etc.) to the output stream.
2336</p>
2337
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2338</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2339
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2340<!-- ======================================================================= -->
2341<div class="doc_subsection">
2342 <a name="mce">Machine Code Emitter</a>
2343</div>
2344
2345<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2346
2347<p>
2348In <tt>XXXCodeEmitter.cpp</tt>, a target-specific of the <tt>Emitter</tt> class
2349is implemented as a function pass (subclass
2350of <tt>MachineFunctionPass</tt>). The target-specific implementation
2351of <tt>runOnMachineFunction</tt> (invoked by
2352<tt>runOnFunction</tt> in <tt>MachineFunctionPass</tt>) iterates through the
2353<tt>MachineBasicBlock</tt> calls <tt>emitInstruction</tt> to process each
2354instruction and emit binary code. <tt>emitInstruction</tt> is largely
2355implemented with case statements on the instruction types defined in
2356<tt>XXXInstrInfo.h</tt>. For example, in <tt>X86CodeEmitter.cpp</tt>,
2357the <tt>emitInstruction</tt> method is built around the following switch/case
2358statements:
2359</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2360
2361<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2362<pre>
2363switch (Desc-&gt;TSFlags &amp; X86::FormMask) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2364case X86II::Pseudo: // for not yet implemented instructions
2365 ... // or pseudo-instructions
2366 break;
2367case X86II::RawFrm: // for instructions with a fixed opcode value
2368 ...
2369 break;
2370case X86II::AddRegFrm: // for instructions that have one register operand
2371 ... // added to their opcode
2372 break;
2373case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
2374 ... // to specify a destination (register)
2375 break;
2376case X86II::MRMDestMem:// for instructions that use the Mod/RM byte
2377 ... // to specify a destination (memory)
2378 break;
2379case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte
2380 ... // to specify a source (register)
2381 break;
2382case X86II::MRMSrcMem: // for instructions that use the Mod/RM byte
2383 ... // to specify a source (memory)
2384 break;
2385case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
2386case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
2387case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
2388case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
2389 ...
2390 break;
2391case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on
2392case X86II::MRM2m: case X86II::MRM3m: // a MEMORY r/m operand and
2393case X86II::MRM4m: case X86II::MRM5m: // use the Mod/RM byte and a field
2394case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data
2395 ...
2396 break;
2397case X86II::MRMInitReg: // for instructions whose source and
2398 ... // destination are the same register
2399 break;
2400}
2401</pre>
2402</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2403
2404<p>
2405The implementations of these case statements often first emit the opcode and
2406then get the operand(s). Then depending upon the operand, helper methods may be
2407called to process the operand(s). For example, in <tt>X86CodeEmitter.cpp</tt>,
2408for the <tt>X86II::AddRegFrm</tt> case, the first data emitted
2409(by <tt>emitByte</tt>) is the opcode added to the register operand. Then an
2410object representing the machine operand, <tt>MO1</tt>, is extracted. The helper
2411methods such as <tt>isImmediate</tt>,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2412<tt>isGlobalAddress</tt>, <tt>isExternalSymbol</tt>, <tt>isConstantPoolIndex</tt>, and
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2413<tt>isJumpTableIndex</tt> determine the operand
2414type. (<tt>X86CodeEmitter.cpp</tt> also has private methods such
2415as <tt>emitConstant</tt>, <tt>emitGlobalAddress</tt>,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2416<tt>emitExternalSymbolAddress</tt>, <tt>emitConstPoolAddress</tt>,
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2417and <tt>emitJumpTableAddress</tt> that emit the data into the output stream.)
2418</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2419
2420<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2421<pre>
2422case X86II::AddRegFrm:
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2423 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
2424
2425 if (CurOp != NumOps) {
2426 const MachineOperand &amp;MO1 = MI.getOperand(CurOp++);
2427 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2428 if (MO1.isImmediate())
2429 emitConstant(MO1.getImm(), Size);
2430 else {
2431 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
2432 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
2433 if (Opcode == X86::MOV64ri)
2434 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
2435 if (MO1.isGlobalAddress()) {
2436 bool NeedStub = isa&lt;Function&gt;(MO1.getGlobal());
2437 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
2438 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
2439 NeedStub, isLazy);
2440 } else if (MO1.isExternalSymbol())
2441 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
2442 else if (MO1.isConstantPoolIndex())
2443 emitConstPoolAddress(MO1.getIndex(), rt);
2444 else if (MO1.isJumpTableIndex())
2445 emitJumpTableAddress(MO1.getIndex(), rt);
2446 }
2447 }
2448 break;
2449</pre>
2450</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2451
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2452<p>
2453In the previous example, <tt>XXXCodeEmitter.cpp</tt> uses the
2454variable <tt>rt</tt>, which is a RelocationType enum that may be used to
2455relocate addresses (for example, a global address with a PIC base offset). The
2456<tt>RelocationType</tt> enum for that target is defined in the short
2457target-specific <tt>XXXRelocations.h</tt> file. The <tt>RelocationType</tt> is used by
2458the <tt>relocate</tt> method defined in <tt>XXXJITInfo.cpp</tt> to rewrite
2459addresses for referenced global symbols.
2460</p>
2461
2462<p>
2463For example, <tt>X86Relocations.h</tt> specifies the following relocation types
2464for the X86 addresses. In all four cases, the relocated value is added to the
2465value already in memory. For <tt>reloc_pcrel_word</tt>
2466and <tt>reloc_picrel_word</tt>, there is an additional initial adjustment.
2467</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2468
2469<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2470<pre>
2471enum RelocationType {
2472 reloc_pcrel_word = 0, // add reloc value after adjusting for the PC loc
2473 reloc_picrel_word = 1, // add reloc value after adjusting for the PIC base
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2474 reloc_absolute_word = 2, // absolute relocation; no additional adjustment
2475 reloc_absolute_dword = 3 // absolute relocation; no additional adjustment
2476};
2477</pre>
2478</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2479
2480</div>
2481
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2482<!-- ======================================================================= -->
2483<div class="doc_subsection">
2484 <a name="targetJITInfo">Target JIT Info</a>
2485</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2486
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2487<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2488
2489<p>
2490<tt>XXXJITInfo.cpp</tt> implements the JIT interfaces for target-specific
2491code-generation activities, such as emitting machine code and stubs. At minimum,
2492a target-specific version of <tt>XXXJITInfo</tt> implements the following:
2493</p>
2494
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2495<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2496<li><tt>getLazyResolverFunction</tt> &mdash; Initializes the JIT, gives the
2497 target a function that is used for compilation.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2498
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2499<li><tt>emitFunctionStub</tt> &mdash; Returns a native function with a specified
2500 address for a callback function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2501
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2502<li><tt>relocate</tt> &mdash; Changes the addresses of referenced globals, based
2503 on relocation types.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2504
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2505<li>Callback function that are wrappers to a function stub that is used when the
2506 real target is not initially known.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2507</ul>
2508
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2509<p>
2510<tt>getLazyResolverFunction</tt> is generally trivial to implement. It makes the
2511incoming parameter as the global <tt>JITCompilerFunction</tt> and returns the
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2512callback function that will be used a function wrapper. For the Alpha target
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2513(in <tt>AlphaJITInfo.cpp</tt>), the <tt>getLazyResolverFunction</tt>
2514implementation is simply:
2515</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2516
2517<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2518<pre>
2519TargetJITInfo::LazyResolverFn AlphaJITInfo::getLazyResolverFunction(
2520 JITCompilerFn F) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2521 JITCompilerFunction = F;
2522 return AlphaCompilationCallback;
2523}
2524</pre>
2525</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2526
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2527<p>
2528For the X86 target, the <tt>getLazyResolverFunction</tt> implementation is a
2529little more complication, because it returns a different callback function for
2530processors with SSE instructions and XMM registers.
2531</p>
2532
2533<p>
2534The callback function initially saves and later restores the callee register
2535values, incoming arguments, and frame and return address. The callback function
2536needs low-level access to the registers or stack, so it is typically implemented
2537with assembler.
2538</p>
2539
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2540</div>
2541
2542<!-- *********************************************************************** -->
2543
2544<hr>
2545<address>
2546 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
Misha Brukman44408702008-12-11 17:34:48 +0000[diff] [blame]2547 src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2548 <a href="http://validator.w3.org/check/referer"><img
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Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2550
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2551 <a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]2552 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2553 <br>
2554 Last modified: $Date$
2555</address>
2556
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2558</html>