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Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]6 <title>Writing an LLVM Compiler Backend</title>
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8</head>
9
10<body>
11
Chris Lattner611944b2008-11-11 19:31:26 +0000[diff] [blame]12<div class="doc_title">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]13 Writing an LLVM Compiler Backend
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]14</div>
15
16<ol>
17 <li><a href="#intro">Introduction</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]18 <ul>
19 <li><a href="#Audience">Audience</a></li>
20 <li><a href="#Prerequisite">Prerequisite Reading</a></li>
21 <li><a href="#Basic">Basic Steps</a></li>
22 <li><a href="#Preliminaries">Preliminaries</a></li>
23 </ul>
24 <li><a href="#TargetMachine">Target Machine</a></li>
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]25 <li><a href="#TargetRegistration">Target Registration</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]26 <li><a href="#RegisterSet">Register Set and Register Classes</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]27 <ul>
28 <li><a href="#RegisterDef">Defining a Register</a></li>
29 <li><a href="#RegisterClassDef">Defining a Register Class</a></li>
30 <li><a href="#implementRegister">Implement a subclass of TargetRegisterInfo</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]31 </ul></li>
32 <li><a href="#InstructionSet">Instruction Set</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]33 <ul>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]34 <li><a href="#operandMapping">Instruction Operand Mapping</a></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]35 <li><a href="#implementInstr">Implement a subclass of TargetInstrInfo</a></li>
36 <li><a href="#branchFolding">Branch Folding and If Conversion</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]37 </ul></li>
38 <li><a href="#InstructionSelector">Instruction Selector</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]39 <ul>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]40 <li><a href="#LegalizePhase">The SelectionDAG Legalize Phase</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]41 <ul>
42 <li><a href="#promote">Promote</a></li>
43 <li><a href="#expand">Expand</a></li>
44 <li><a href="#custom">Custom</a></li>
45 <li><a href="#legal">Legal</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]46 </ul></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]47 <li><a href="#callingConventions">Calling Conventions</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]48 </ul></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]49 <li><a href="#assemblyPrinter">Assembly Printer</a></li>
50 <li><a href="#subtargetSupport">Subtarget Support</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]51 <li><a href="#jitSupport">JIT Support</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]52 <ul>
53 <li><a href="#mce">Machine Code Emitter</a></li>
54 <li><a href="#targetJITInfo">Target JIT Info</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]55 </ul></li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]56</ol>
57
58<div class="doc_author">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]59 <p>Written by <a href="http://www.woo.com">Mason Woo</a> and
60 <a href="http://misha.brukman.net">Misha Brukman</a></p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]61</div>
62
63<!-- *********************************************************************** -->
64<div class="doc_section">
65 <a name="intro">Introduction</a>
66</div>
67<!-- *********************************************************************** -->
68
69<div class="doc_text">
70
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]71<p>
72This document describes techniques for writing compiler backends that convert
73the LLVM Intermediate Representation (IR) to code for a specified machine or
74other languages. Code intended for a specific machine can take the form of
75either assembly code or binary code (usable for a JIT compiler).
76</p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]77
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]78<p>
79The backend of LLVM features a target-independent code generator that may create
80output for several types of target CPUs &mdash; including X86, PowerPC, Alpha,
81and SPARC. The backend may also be used to generate code targeted at SPUs of the
82Cell processor or GPUs to support the execution of compute kernels.
83</p>
84
85<p>
86The document focuses on existing examples found in subdirectories
87of <tt>llvm/lib/Target</tt> in a downloaded LLVM release. In particular, this
88document focuses on the example of creating a static compiler (one that emits
89text assembly) for a SPARC target, because SPARC has fairly standard
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]90characteristics, such as a RISC instruction set and straightforward calling
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]91conventions.
92</p>
93
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]94</div>
95
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]96<div class="doc_subsection">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]97 <a name="Audience">Audience</a>
98</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]99
100<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]101
102<p>
103The audience for this document is anyone who needs to write an LLVM backend to
104generate code for a specific hardware or software target.
105</p>
106
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]107</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]108
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]109<div class="doc_subsection">
110 <a name="Prerequisite">Prerequisite Reading</a>
111</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]112
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]113<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]114
115<p>
116These essential documents must be read before reading this document:
117</p>
118
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]119<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]120<li><i><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference
121 Manual</a></i> &mdash; a reference manual for the LLVM assembly language.</li>
122
123<li><i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
124 Target-Independent Code Generator</a></i> &mdash; a guide to the components
125 (classes and code generation algorithms) for translating the LLVM internal
126 representation into machine code for a specified target. Pay particular
127 attention to the descriptions of code generation stages: Instruction
128 Selection, Scheduling and Formation, SSA-based Optimization, Register
129 Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations,
130 and Code Emission.</li>
131
132<li><i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen
133 Fundamentals</a></i> &mdash;a document that describes the TableGen
134 (<tt>tblgen</tt>) application that manages domain-specific information to
135 support LLVM code generation. TableGen processes input from a target
136 description file (<tt>.td</tt> suffix) and generates C++ code that can be
137 used for code generation.</li>
138
139<li><i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM
140 Pass</a></i> &mdash; The assembly printer is a <tt>FunctionPass</tt>, as are
141 several SelectionDAG processing steps.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]142</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]143
144<p>
145To follow the SPARC examples in this document, have a copy of
146<i><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture
147Manual, Version 8</a></i> for reference. For details about the ARM instruction
148set, refer to the <i><a href="http://infocenter.arm.com/">ARM Architecture
149Reference Manual</a></i>. For more about the GNU Assembler format
150(<tt>GAS</tt>), see
151<i><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></i>,
152especially for the assembly printer. <i>Using As</i> contains a list of target
153machine dependent features.
154</p>
155
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]156</div>
157
158<div class="doc_subsection">
159 <a name="Basic">Basic Steps</a>
160</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]161
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]162<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]163
164<p>
165To write a compiler backend for LLVM that converts the LLVM IR to code for a
166specified target (machine or other language), follow these steps:
167</p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]168
169<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]170<li>Create a subclass of the TargetMachine class that describes characteristics
171 of your target machine. Copy existing examples of specific TargetMachine
172 class and header files; for example, start with
173 <tt>SparcTargetMachine.cpp</tt> and <tt>SparcTargetMachine.h</tt>, but
174 change the file names for your target. Similarly, change code that
175 references "Sparc" to reference your target. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]176
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]177<li>Describe the register set of the target. Use TableGen to generate code for
178 register definition, register aliases, and register classes from a
179 target-specific <tt>RegisterInfo.td</tt> input file. You should also write
180 additional code for a subclass of the TargetRegisterInfo class that
181 represents the class register file data used for register allocation and
182 also describes the interactions between registers.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]183
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]184<li>Describe the instruction set of the target. Use TableGen to generate code
185 for target-specific instructions from target-specific versions of
186 <tt>TargetInstrFormats.td</tt> and <tt>TargetInstrInfo.td</tt>. You should
187 write additional code for a subclass of the TargetInstrInfo class to
188 represent machine instructions supported by the target machine. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]189
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]190<li>Describe the selection and conversion of the LLVM IR from a Directed Acyclic
191 Graph (DAG) representation of instructions to native target-specific
192 instructions. Use TableGen to generate code that matches patterns and
193 selects instructions based on additional information in a target-specific
194 version of <tt>TargetInstrInfo.td</tt>. Write code
195 for <tt>XXXISelDAGToDAG.cpp</tt>, where XXX identifies the specific target,
196 to perform pattern matching and DAG-to-DAG instruction selection. Also write
197 code in <tt>XXXISelLowering.cpp</tt> to replace or remove operations and
198 data types that are not supported natively in a SelectionDAG. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]199
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]200<li>Write code for an assembly printer that converts LLVM IR to a GAS format for
201 your target machine. You should add assembly strings to the instructions
202 defined in your target-specific version of <tt>TargetInstrInfo.td</tt>. You
203 should also write code for a subclass of AsmPrinter that performs the
204 LLVM-to-assembly conversion and a trivial subclass of TargetAsmInfo.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]205
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]206<li>Optionally, add support for subtargets (i.e., variants with different
207 capabilities). You should also write code for a subclass of the
208 TargetSubtarget class, which allows you to use the <tt>-mcpu=</tt>
209 and <tt>-mattr=</tt> command-line options.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]210
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]211<li>Optionally, add JIT support and create a machine code emitter (subclass of
212 TargetJITInfo) that is used to emit binary code directly into memory. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]213</ul>
214
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]215<p>
216In the <tt>.cpp</tt> and <tt>.h</tt>. files, initially stub up these methods and
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]217then implement them later. Initially, you may not know which private members
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]218that the class will need and which components will need to be subclassed.
219</p>
220
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]221</div>
222
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]223<div class="doc_subsection">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]224 <a name="Preliminaries">Preliminaries</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]225</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]226
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]227<div class="doc_text">
228
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]229<p>
230To actually create your compiler backend, you need to create and modify a few
231files. The absolute minimum is discussed here. But to actually use the LLVM
232target-independent code generator, you must perform the steps described in
233the <a href="http://www.llvm.org/docs/CodeGenerator.html">LLVM
234Target-Independent Code Generator</a> document.
235</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]236
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]237<p>
238First, you should create a subdirectory under <tt>lib/Target</tt> to hold all
239the files related to your target. If your target is called "Dummy," create the
240directory <tt>lib/Target/Dummy</tt>.
241</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]242
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]243<p>
244In this new
245directory, create a <tt>Makefile</tt>. It is easiest to copy a
246<tt>Makefile</tt> of another target and modify it. It should at least contain
247the <tt>LEVEL</tt>, <tt>LIBRARYNAME</tt> and <tt>TARGET</tt> variables, and then
248include <tt>$(LEVEL)/Makefile.common</tt>. The library can be
249named <tt>LLVMDummy</tt> (for example, see the MIPS target). Alternatively, you
250can split the library into <tt>LLVMDummyCodeGen</tt>
251and <tt>LLVMDummyAsmPrinter</tt>, the latter of which should be implemented in a
252subdirectory below <tt>lib/Target/Dummy</tt> (for example, see the PowerPC
253target).
254</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]255
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]256<p>
257Note that these two naming schemes are hardcoded into <tt>llvm-config</tt>.
258Using any other naming scheme will confuse <tt>llvm-config</tt> and produce a
259lot of (seemingly unrelated) linker errors when linking <tt>llc</tt>.
260</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]261
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]262<p>
263To make your target actually do something, you need to implement a subclass of
264<tt>TargetMachine</tt>. This implementation should typically be in the file
265<tt>lib/Target/DummyTargetMachine.cpp</tt>, but any file in
266the <tt>lib/Target</tt> directory will be built and should work. To use LLVM's
267target independent code generator, you should do what all current machine
268backends do: create a subclass of <tt>LLVMTargetMachine</tt>. (To create a
269target from scratch, create a subclass of <tt>TargetMachine</tt>.)
270</p>
271
272<p>
273To get LLVM to actually build and link your target, you need to add it to
274the <tt>TARGETS_TO_BUILD</tt> variable. To do this, you modify the configure
275script to know about your target when parsing the <tt>--enable-targets</tt>
276option. Search the configure script for <tt>TARGETS_TO_BUILD</tt>, add your
277target to the lists there (some creativity required), and then
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]278reconfigure. Alternatively, you can change <tt>autotools/configure.ac</tt> and
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]279regenerate configure by running <tt>./autoconf/AutoRegen.sh</tt>.
280</p>
281
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]282</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]283
284<!-- *********************************************************************** -->
285<div class="doc_section">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]286 <a name="TargetMachine">Target Machine</a>
287</div>
288<!-- *********************************************************************** -->
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]289
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]290<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]291
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]292<p>
293<tt>LLVMTargetMachine</tt> is designed as a base class for targets implemented
294with the LLVM target-independent code generator. The <tt>LLVMTargetMachine</tt>
295class should be specialized by a concrete target class that implements the
296various virtual methods. <tt>LLVMTargetMachine</tt> is defined as a subclass of
297<tt>TargetMachine</tt> in <tt>include/llvm/Target/TargetMachine.h</tt>. The
298<tt>TargetMachine</tt> class implementation (<tt>TargetMachine.cpp</tt>) also
299processes numerous command-line options.
300</p>
301
302<p>
303To create a concrete target-specific subclass of <tt>LLVMTargetMachine</tt>,
304start by copying an existing <tt>TargetMachine</tt> class and header. You
305should name the files that you create to reflect your specific target. For
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]306instance, for the SPARC target, name the files <tt>SparcTargetMachine.h</tt> and
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]307<tt>SparcTargetMachine.cpp</tt>.
308</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]309
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]310<p>
311For a target machine <tt>XXX</tt>, the implementation of
312<tt>XXXTargetMachine</tt> must have access methods to obtain objects that
313represent target components. These methods are named <tt>get*Info</tt>, and are
314intended to obtain the instruction set (<tt>getInstrInfo</tt>), register set
315(<tt>getRegisterInfo</tt>), stack frame layout (<tt>getFrameInfo</tt>), and
316similar information. <tt>XXXTargetMachine</tt> must also implement the
317<tt>getTargetData</tt> method to access an object with target-specific data
318characteristics, such as data type size and alignment requirements.
319</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]320
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]321<p>
322For instance, for the SPARC target, the header file
323<tt>SparcTargetMachine.h</tt> declares prototypes for several <tt>get*Info</tt>
324and <tt>getTargetData</tt> methods that simply return a class member.
325</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]326
327<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]328<pre>
329namespace llvm {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]330
331class Module;
332
333class SparcTargetMachine : public LLVMTargetMachine {
334 const TargetData DataLayout; // Calculates type size &amp; alignment
335 SparcSubtarget Subtarget;
336 SparcInstrInfo InstrInfo;
337 TargetFrameInfo FrameInfo;
338
339protected:
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]340 virtual const TargetAsmInfo *createTargetAsmInfo() const;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]341
342public:
343 SparcTargetMachine(const Module &amp;M, const std::string &amp;FS);
344
345 virtual const SparcInstrInfo *getInstrInfo() const {return &amp;InstrInfo; }
346 virtual const TargetFrameInfo *getFrameInfo() const {return &amp;FrameInfo; }
347 virtual const TargetSubtarget *getSubtargetImpl() const{return &amp;Subtarget; }
348 virtual const TargetRegisterInfo *getRegisterInfo() const {
349 return &amp;InstrInfo.getRegisterInfo();
350 }
351 virtual const TargetData *getTargetData() const { return &amp;DataLayout; }
352 static unsigned getModuleMatchQuality(const Module &amp;M);
353
354 // Pass Pipeline Configuration
355 virtual bool addInstSelector(PassManagerBase &amp;PM, bool Fast);
356 virtual bool addPreEmitPass(PassManagerBase &amp;PM, bool Fast);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]357};
358
359} // end namespace llvm
360</pre>
361</div>
362
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]363</div>
364
365
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]366<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]367
368<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]369<li><tt>getInstrInfo()</tt></li>
370<li><tt>getRegisterInfo()</tt></li>
371<li><tt>getFrameInfo()</tt></li>
372<li><tt>getTargetData()</tt></li>
373<li><tt>getSubtargetImpl()</tt></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]374</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]375
376<p>For some targets, you also need to support the following methods:</p>
377
378<ul>
379<li><tt>getTargetLowering()</tt></li>
380<li><tt>getJITInfo()</tt></li>
381</ul>
382
383<p>
384In addition, the <tt>XXXTargetMachine</tt> constructor should specify a
385<tt>TargetDescription</tt> string that determines the data layout for the target
386machine, including characteristics such as pointer size, alignment, and
387endianness. For example, the constructor for SparcTargetMachine contains the
388following:
389</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]390
391<div class="doc_code">
392<pre>
393SparcTargetMachine::SparcTargetMachine(const Module &amp;M, const std::string &amp;FS)
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]394 : DataLayout("E-p:32:32-f128:128:128"),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]395 Subtarget(M, FS), InstrInfo(Subtarget),
396 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
397}
398</pre>
399</div>
400
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]401</div>
402
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]403<div class="doc_text">
404
405<p>Hyphens separate portions of the <tt>TargetDescription</tt> string.</p>
406
407<ul>
408<li>An upper-case "<tt>E</tt>" in the string indicates a big-endian target data
409 model. a lower-case "<tt>e</tt>" indicates little-endian.</li>
410
411<li>"<tt>p:</tt>" is followed by pointer information: size, ABI alignment, and
412 preferred alignment. If only two figures follow "<tt>p:</tt>", then the
413 first value is pointer size, and the second value is both ABI and preferred
414 alignment.</li>
415
416<li>Then a letter for numeric type alignment: "<tt>i</tt>", "<tt>f</tt>",
417 "<tt>v</tt>", or "<tt>a</tt>" (corresponding to integer, floating point,
418 vector, or aggregate). "<tt>i</tt>", "<tt>v</tt>", or "<tt>a</tt>" are
419 followed by ABI alignment and preferred alignment. "<tt>f</tt>" is followed
420 by three values: the first indicates the size of a long double, then ABI
421 alignment, and then ABI preferred alignment.</li>
422</ul>
423
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]424</div>
425
426<!-- *********************************************************************** -->
427<div class="doc_section">
428 <a name="TargetRegistration">Target Registration</a>
429</div>
430<!-- *********************************************************************** -->
431
432<div class="doc_text">
433
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]434<p>
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]435You must also register your target with the <tt>TargetRegistry</tt>, which is
436what other LLVM tools use to be able to lookup and use your target at
437runtime. The <tt>TargetRegistry</tt> can be used directly, but for most targets
438there are helper templates which should take care of the work for you.</p>
439
440<p>
441All targets should declare a global <tt>Target</tt> object which is used to
442represent the target during registration. Then, in the target's TargetInfo
443library, the target should define that object and use
444the <tt>RegisterTarget</tt> template to register the target. For example, the Sparc registration code looks like this:
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]445</p>
446
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]447<div class="doc_code">
448<pre>
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]449Target llvm::TheSparcTarget;
450
451extern "C" void LLVMInitializeSparcTargetInfo() {
Benjamin Kramere15192b2009-08-05 15:42:44 +0000[diff] [blame]452 RegisterTarget&lt;Triple::sparc, /*HasJIT=*/false&gt;
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]453 X(TheSparcTarget, "sparc", "Sparc");
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]454}
455</pre>
456</div>
457
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]458<p>
459This allows the <tt>TargetRegistry</tt> to look up the target by name or by
460target triple. In addition, most targets will also register additional features
461which are available in separate libraries. These registration steps are
462separate, because some clients may wish to only link in some parts of the target
463-- the JIT code generator does not require the use of the assembler printer, for
464example. Here is an example of registering the Sparc assembly printer:
465</p>
466
467<div class="doc_code">
468<pre>
469extern "C" void LLVMInitializeSparcAsmPrinter() {
Benjamin Kramere15192b2009-08-05 15:42:44 +0000[diff] [blame]470 RegisterAsmPrinter&lt;SparcAsmPrinter&gt; X(TheSparcTarget);
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]471}
472</pre>
473</div>
474
475<p>
476For more information, see
477"<a href="/doxygen/TargetRegistry_8h-source.html">llvm/Target/TargetRegistry.h</a>".
478</p>
479
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]480</div>
481
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]482<!-- *********************************************************************** -->
483<div class="doc_section">
484 <a name="RegisterSet">Register Set and Register Classes</a>
485</div>
486<!-- *********************************************************************** -->
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]487
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]488<div class="doc_text">
489
490<p>
491You should describe a concrete target-specific class that represents the
492register file of a target machine. This class is called <tt>XXXRegisterInfo</tt>
493(where <tt>XXX</tt> identifies the target) and represents the class register
494file data that is used for register allocation. It also describes the
495interactions between registers.
496</p>
497
498<p>
499You also need to define register classes to categorize related registers. A
500register class should be added for groups of registers that are all treated the
501same way for some instruction. Typical examples are register classes for
502integer, floating-point, or vector registers. A register allocator allows an
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]503instruction to use any register in a specified register class to perform the
504instruction in a similar manner. Register classes allocate virtual registers to
505instructions from these sets, and register classes let the target-independent
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]506register allocator automatically choose the actual registers.
507</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]508
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]509<p>
510Much of the code for registers, including register definition, register aliases,
511and register classes, is generated by TableGen from <tt>XXXRegisterInfo.td</tt>
512input files and placed in <tt>XXXGenRegisterInfo.h.inc</tt> and
513<tt>XXXGenRegisterInfo.inc</tt> output files. Some of the code in the
514implementation of <tt>XXXRegisterInfo</tt> requires hand-coding.
515</p>
516
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]517</div>
518
519<!-- ======================================================================= -->
520<div class="doc_subsection">
521 <a name="RegisterDef">Defining a Register</a>
522</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]523
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]524<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]525
526<p>
527The <tt>XXXRegisterInfo.td</tt> file typically starts with register definitions
528for a target machine. The <tt>Register</tt> class (specified
529in <tt>Target.td</tt>) is used to define an object for each register. The
530specified string <tt>n</tt> becomes the <tt>Name</tt> of the register. The
531basic <tt>Register</tt> object does not have any subregisters and does not
532specify any aliases.
533</p>
534
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]535<div class="doc_code">
536<pre>
537class Register&lt;string n&gt; {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]538 string Namespace = "";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]539 string AsmName = n;
540 string Name = n;
541 int SpillSize = 0;
542 int SpillAlignment = 0;
543 list&lt;Register&gt; Aliases = [];
544 list&lt;Register&gt; SubRegs = [];
545 list&lt;int&gt; DwarfNumbers = [];
546}
547</pre>
548</div>
549
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]550<p>
551For example, in the <tt>X86RegisterInfo.td</tt> file, there are register
552definitions that utilize the Register class, such as:
553</p>
554
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]555<div class="doc_code">
556<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]557def AL : Register&lt;"AL"&gt;, DwarfRegNum&lt;[0, 0, 0]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]558</pre>
559</div>
560
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]561<p>
562This defines the register <tt>AL</tt> and assigns it values (with
563<tt>DwarfRegNum</tt>) that are used by <tt>gcc</tt>, <tt>gdb</tt>, or a debug
Chris Lattnerc3107782010-04-05 04:11:11 +0000[diff] [blame^]564information writer to identify a register. For register
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]565<tt>AL</tt>, <tt>DwarfRegNum</tt> takes an array of 3 values representing 3
566different modes: the first element is for X86-64, the second for exception
567handling (EH) on X86-32, and the third is generic. -1 is a special Dwarf number
568that indicates the gcc number is undefined, and -2 indicates the register number
569is invalid for this mode.
570</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]571
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]572<p>
573From the previously described line in the <tt>X86RegisterInfo.td</tt> file,
574TableGen generates this code in the <tt>X86GenRegisterInfo.inc</tt> file:
575</p>
576
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]577<div class="doc_code">
578<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]579static const unsigned GR8[] = { X86::AL, ... };
580
581const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
582
583const TargetRegisterDesc RegisterDescriptors[] = {
584 ...
585{ "AL", "AL", AL_AliasSet, Empty_SubRegsSet, Empty_SubRegsSet, AL_SuperRegsSet }, ...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]586</pre>
587</div>
588
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]589<p>
590From the register info file, TableGen generates a <tt>TargetRegisterDesc</tt>
591object for each register. <tt>TargetRegisterDesc</tt> is defined in
592<tt>include/llvm/Target/TargetRegisterInfo.h</tt> with the following fields:
593</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]594
595<div class="doc_code">
596<pre>
597struct TargetRegisterDesc {
598 const char *AsmName; // Assembly language name for the register
599 const char *Name; // Printable name for the reg (for debugging)
600 const unsigned *AliasSet; // Register Alias Set
601 const unsigned *SubRegs; // Sub-register set
602 const unsigned *ImmSubRegs; // Immediate sub-register set
603 const unsigned *SuperRegs; // Super-register set
604};</pre>
605</div>
606
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]607<p>
608TableGen uses the entire target description file (<tt>.td</tt>) to determine
609text names for the register (in the <tt>AsmName</tt> and <tt>Name</tt> fields of
610<tt>TargetRegisterDesc</tt>) and the relationships of other registers to the
611defined register (in the other <tt>TargetRegisterDesc</tt> fields). In this
612example, other definitions establish the registers "<tt>AX</tt>",
613"<tt>EAX</tt>", and "<tt>RAX</tt>" as aliases for one another, so TableGen
614generates a null-terminated array (<tt>AL_AliasSet</tt>) for this register alias
615set.
616</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]617
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]618<p>
619The <tt>Register</tt> class is commonly used as a base class for more complex
620classes. In <tt>Target.td</tt>, the <tt>Register</tt> class is the base for the
621<tt>RegisterWithSubRegs</tt> class that is used to define registers that need to
622specify subregisters in the <tt>SubRegs</tt> list, as shown here:
623</p>
624
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]625<div class="doc_code">
626<pre>
627class RegisterWithSubRegs&lt;string n,
628list&lt;Register&gt; subregs&gt; : Register&lt;n&gt; {
629 let SubRegs = subregs;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]630}
631</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]632</div>
633
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]634<p>
635In <tt>SparcRegisterInfo.td</tt>, additional register classes are defined for
636SPARC: a Register subclass, SparcReg, and further subclasses: <tt>Ri</tt>,
637<tt>Rf</tt>, and <tt>Rd</tt>. SPARC registers are identified by 5-bit ID
638numbers, which is a feature common to these subclasses. Note the use of
639'<tt>let</tt>' expressions to override values that are initially defined in a
640superclass (such as <tt>SubRegs</tt> field in the <tt>Rd</tt> class).
641</p>
642
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]643<div class="doc_code">
644<pre>
645class SparcReg&lt;string n&gt; : Register&lt;n&gt; {
646 field bits&lt;5&gt; Num;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]647 let Namespace = "SP";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]648}
649// Ri - 32-bit integer registers
650class Ri&lt;bits&lt;5&gt; num, string n&gt; :
651SparcReg&lt;n&gt; {
652 let Num = num;
653}
654// Rf - 32-bit floating-point registers
655class Rf&lt;bits&lt;5&gt; num, string n&gt; :
656SparcReg&lt;n&gt; {
657 let Num = num;
658}
659// Rd - Slots in the FP register file for 64-bit
660floating-point values.
661class Rd&lt;bits&lt;5&gt; num, string n,
662list&lt;Register&gt; subregs&gt; : SparcReg&lt;n&gt; {
663 let Num = num;
664 let SubRegs = subregs;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]665}
666</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]667</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]668
669<p>
670In the <tt>SparcRegisterInfo.td</tt> file, there are register definitions that
671utilize these subclasses of <tt>Register</tt>, such as:
672</p>
673
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]674<div class="doc_code">
675<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]676def G0 : Ri&lt; 0, "G0"&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]677DwarfRegNum&lt;[0]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]678def G1 : Ri&lt; 1, "G1"&gt;, DwarfRegNum&lt;[1]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]679...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]680def F0 : Rf&lt; 0, "F0"&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]681DwarfRegNum&lt;[32]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]682def F1 : Rf&lt; 1, "F1"&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]683DwarfRegNum&lt;[33]&gt;;
684...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]685def D0 : Rd&lt; 0, "F0", [F0, F1]&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]686DwarfRegNum&lt;[32]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]687def D1 : Rd&lt; 2, "F2", [F2, F3]&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]688DwarfRegNum&lt;[34]&gt;;
689</pre>
690</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]691
692<p>
693The last two registers shown above (<tt>D0</tt> and <tt>D1</tt>) are
694double-precision floating-point registers that are aliases for pairs of
695single-precision floating-point sub-registers. In addition to aliases, the
696sub-register and super-register relationships of the defined register are in
697fields of a register's TargetRegisterDesc.
698</p>
699
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]700</div>
701
702<!-- ======================================================================= -->
703<div class="doc_subsection">
704 <a name="RegisterClassDef">Defining a Register Class</a>
705</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]706
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]707<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]708
709<p>
710The <tt>RegisterClass</tt> class (specified in <tt>Target.td</tt>) is used to
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]711define an object that represents a group of related registers and also defines
712the default allocation order of the registers. A target description file
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]713<tt>XXXRegisterInfo.td</tt> that uses <tt>Target.td</tt> can construct register
714classes using the following class:
715</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]716
717<div class="doc_code">
718<pre>
719class RegisterClass&lt;string namespace,
720list&lt;ValueType&gt; regTypes, int alignment,
721 list&lt;Register&gt; regList&gt; {
722 string Namespace = namespace;
723 list&lt;ValueType&gt; RegTypes = regTypes;
724 int Size = 0; // spill size, in bits; zero lets tblgen pick the size
725 int Alignment = alignment;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]726
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]727 // CopyCost is the cost of copying a value between two registers
728 // default value 1 means a single instruction
729 // A negative value means copying is extremely expensive or impossible
730 int CopyCost = 1;
731 list&lt;Register&gt; MemberList = regList;
732
733 // for register classes that are subregisters of this class
734 list&lt;RegisterClass&gt; SubRegClassList = [];
735
736 code MethodProtos = [{}]; // to insert arbitrary code
737 code MethodBodies = [{}];
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]738}
739</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]740</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]741
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]742<p>To define a RegisterClass, use the following 4 arguments:</p>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]743
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]744<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]745<li>The first argument of the definition is the name of the namespace.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]746
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]747<li>The second argument is a list of <tt>ValueType</tt> register type values
748 that are defined in <tt>include/llvm/CodeGen/ValueTypes.td</tt>. Defined
749 values include integer types (such as <tt>i16</tt>, <tt>i32</tt>,
750 and <tt>i1</tt> for Boolean), floating-point types
751 (<tt>f32</tt>, <tt>f64</tt>), and vector types (for example, <tt>v8i16</tt>
752 for an <tt>8 x i16</tt> vector). All registers in a <tt>RegisterClass</tt>
753 must have the same <tt>ValueType</tt>, but some registers may store vector
754 data in different configurations. For example a register that can process a
755 128-bit vector may be able to handle 16 8-bit integer elements, 8 16-bit
756 integers, 4 32-bit integers, and so on. </li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]757
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]758<li>The third argument of the <tt>RegisterClass</tt> definition specifies the
759 alignment required of the registers when they are stored or loaded to
760 memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]761
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]762<li>The final argument, <tt>regList</tt>, specifies which registers are in this
763 class. If an <tt>allocation_order_*</tt> method is not specified,
764 then <tt>regList</tt> also defines the order of allocation used by the
765 register allocator.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]766</ul>
767
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]768<p>
769In <tt>SparcRegisterInfo.td</tt>, three RegisterClass objects are defined:
770<tt>FPRegs</tt>, <tt>DFPRegs</tt>, and <tt>IntRegs</tt>. For all three register
771classes, the first argument defines the namespace with the string
772'<tt>SP</tt>'. <tt>FPRegs</tt> defines a group of 32 single-precision
773floating-point registers (<tt>F0</tt> to <tt>F31</tt>); <tt>DFPRegs</tt> defines
774a group of 16 double-precision registers
775(<tt>D0-D15</tt>). For <tt>IntRegs</tt>, the <tt>MethodProtos</tt>
776and <tt>MethodBodies</tt> methods are used by TableGen to insert the specified
777code into generated output.
778</p>
779
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]780<div class="doc_code">
781<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]782def FPRegs : RegisterClass&lt;"SP", [f32], 32,
783 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
784 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]&gt;;
785
786def DFPRegs : RegisterClass&lt;"SP", [f64], 64,
787 [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]788&nbsp;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]789def IntRegs : RegisterClass&lt;"SP", [i32], 32,
790 [L0, L1, L2, L3, L4, L5, L6, L7,
791 I0, I1, I2, I3, I4, I5,
792 O0, O1, O2, O3, O4, O5, O7,
793 G1,
794 // Non-allocatable regs:
795 G2, G3, G4,
796 O6, // stack ptr
797 I6, // frame ptr
798 I7, // return address
799 G0, // constant zero
800 G5, G6, G7 // reserved for kernel
801 ]&gt; {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]802 let MethodProtos = [{
803 iterator allocation_order_end(const MachineFunction &amp;MF) const;
804 }];
805 let MethodBodies = [{
806 IntRegsClass::iterator
807 IntRegsClass::allocation_order_end(const MachineFunction &amp;MF) const {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]808 return end() - 10 // Don't allocate special registers
809 -1;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]810 }
811 }];
812}
813</pre>
814</div>
815
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]816<p>
817Using <tt>SparcRegisterInfo.td</tt> with TableGen generates several output files
818that are intended for inclusion in other source code that you write.
819<tt>SparcRegisterInfo.td</tt> generates <tt>SparcGenRegisterInfo.h.inc</tt>,
820which should be included in the header file for the implementation of the SPARC
821register implementation that you write (<tt>SparcRegisterInfo.h</tt>). In
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]822<tt>SparcGenRegisterInfo.h.inc</tt> a new structure is defined called
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]823<tt>SparcGenRegisterInfo</tt> that uses <tt>TargetRegisterInfo</tt> as its
824base. It also specifies types, based upon the defined register
825classes: <tt>DFPRegsClass</tt>, <tt>FPRegsClass</tt>, and <tt>IntRegsClass</tt>.
826</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]827
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]828<p>
829<tt>SparcRegisterInfo.td</tt> also generates <tt>SparcGenRegisterInfo.inc</tt>,
830which is included at the bottom of <tt>SparcRegisterInfo.cpp</tt>, the SPARC
831register implementation. The code below shows only the generated integer
832registers and associated register classes. The order of registers
833in <tt>IntRegs</tt> reflects the order in the definition of <tt>IntRegs</tt> in
834the target description file. Take special note of the use
835of <tt>MethodBodies</tt> in <tt>SparcRegisterInfo.td</tt> to create code in
836<tt>SparcGenRegisterInfo.inc</tt>. <tt>MethodProtos</tt> generates similar code
837in <tt>SparcGenRegisterInfo.h.inc</tt>.
838</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]839
840<div class="doc_code">
841<pre> // IntRegs Register Class...
842 static const unsigned IntRegs[] = {
843 SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5,
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]844 SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3,
845 SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3,
846 SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3,
847 SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5,
848 SP::G6, SP::G7,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]849 };
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]850
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]851 // IntRegsVTs Register Class Value Types...
852 static const MVT::ValueType IntRegsVTs[] = {
853 MVT::i32, MVT::Other
854 };
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]855
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]856namespace SP { // Register class instances
857 DFPRegsClass&nbsp;&nbsp;&nbsp; DFPRegsRegClass;
858 FPRegsClass&nbsp;&nbsp;&nbsp;&nbsp; FPRegsRegClass;
859 IntRegsClass&nbsp;&nbsp;&nbsp; IntRegsRegClass;
860...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]861 // IntRegs Sub-register Classess...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]862 static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
863 NULL
864 };
865...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]866 // IntRegs Super-register Classess...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]867 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
868 NULL
869 };
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]870...
871 // IntRegs Register Class sub-classes...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]872 static const TargetRegisterClass* const IntRegsSubclasses [] = {
873 NULL
874 };
875...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]876 // IntRegs Register Class super-classes...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]877 static const TargetRegisterClass* const IntRegsSuperclasses [] = {
878 NULL
879 };
880...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]881 IntRegsClass::iterator
882 IntRegsClass::allocation_order_end(const MachineFunction &amp;MF) const {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]883 return end()-10 // Don't allocate special registers
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]884 -1;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]885 }
886
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]887 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID,
888 IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses,
889 IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]890}
891</pre>
892</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]893
894</div>
895
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]896<!-- ======================================================================= -->
897<div class="doc_subsection">
Chris Lattner7d12b4b2008-11-11 19:36:31 +0000[diff] [blame]898 <a name="implementRegister">Implement a subclass of</a>
899 <a href="http://www.llvm.org/docs/CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]900</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]901
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]902<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]903
904<p>
905The final step is to hand code portions of <tt>XXXRegisterInfo</tt>, which
906implements the interface described in <tt>TargetRegisterInfo.h</tt>. These
907functions return <tt>0</tt>, <tt>NULL</tt>, or <tt>false</tt>, unless
908overridden. Here is a list of functions that are overridden for the SPARC
909implementation in <tt>SparcRegisterInfo.cpp</tt>:
910</p>
911
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]912<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]913<li><tt>getCalleeSavedRegs</tt> &mdash; Returns a list of callee-saved registers
914 in the order of the desired callee-save stack frame offset.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]915
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]916<li><tt>getCalleeSavedRegClasses</tt> &mdash; Returns a list of preferred
917 register classes with which to spill each callee saved register.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]918
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]919<li><tt>getReservedRegs</tt> &mdash; Returns a bitset indexed by physical
920 register numbers, indicating if a particular register is unavailable.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]921
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]922<li><tt>hasFP</tt> &mdash; Return a Boolean indicating if a function should have
923 a dedicated frame pointer register.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]924
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]925<li><tt>eliminateCallFramePseudoInstr</tt> &mdash; If call frame setup or
926 destroy pseudo instructions are used, this can be called to eliminate
927 them.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]928
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]929<li><tt>eliminateFrameIndex</tt> &mdash; Eliminate abstract frame indices from
930 instructions that may use them.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]931
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]932<li><tt>emitPrologue</tt> &mdash; Insert prologue code into the function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]933
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]934<li><tt>emitEpilogue</tt> &mdash; Insert epilogue code into the function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]935</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]936
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]937</div>
938
939<!-- *********************************************************************** -->
940<div class="doc_section">
941 <a name="InstructionSet">Instruction Set</a>
942</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]943
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]944<!-- *********************************************************************** -->
945<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]946
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]947<p>
948During the early stages of code generation, the LLVM IR code is converted to a
949<tt>SelectionDAG</tt> with nodes that are instances of the <tt>SDNode</tt> class
950containing target instructions. An <tt>SDNode</tt> has an opcode, operands, type
951requirements, and operation properties. For example, is an operation
952commutative, does an operation load from memory. The various operation node
953types are described in the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
954file (values of the <tt>NodeType</tt> enum in the <tt>ISD</tt> namespace).
955</p>
956
957<p>
958TableGen uses the following target description (<tt>.td</tt>) input files to
959generate much of the code for instruction definition:
960</p>
961
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]962<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]963<li><tt>Target.td</tt> &mdash; Where the <tt>Instruction</tt>, <tt>Operand</tt>,
964 <tt>InstrInfo</tt>, and other fundamental classes are defined.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]965
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]966<li><tt>TargetSelectionDAG.td</tt>&mdash; Used by <tt>SelectionDAG</tt>
967 instruction selection generators, contains <tt>SDTC*</tt> classes (selection
968 DAG type constraint), definitions of <tt>SelectionDAG</tt> nodes (such as
969 <tt>imm</tt>, <tt>cond</tt>, <tt>bb</tt>, <tt>add</tt>, <tt>fadd</tt>,
970 <tt>sub</tt>), and pattern support (<tt>Pattern</tt>, <tt>Pat</tt>,
971 <tt>PatFrag</tt>, <tt>PatLeaf</tt>, <tt>ComplexPattern</tt>.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]972
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]973<li><tt>XXXInstrFormats.td</tt> &mdash; Patterns for definitions of
974 target-specific instructions.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]975
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]976<li><tt>XXXInstrInfo.td</tt> &mdash; Target-specific definitions of instruction
977 templates, condition codes, and instructions of an instruction set. For
978 architecture modifications, a different file name may be used. For example,
979 for Pentium with SSE instruction, this file is <tt>X86InstrSSE.td</tt>, and
980 for Pentium with MMX, this file is <tt>X86InstrMMX.td</tt>.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]981</ul>
982
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]983<p>
984There is also a target-specific <tt>XXX.td</tt> file, where <tt>XXX</tt> is the
985name of the target. The <tt>XXX.td</tt> file includes the other <tt>.td</tt>
986input files, but its contents are only directly important for subtargets.
987</p>
988
989<p>
990You should describe a concrete target-specific class <tt>XXXInstrInfo</tt> that
991represents machine instructions supported by a target machine.
992<tt>XXXInstrInfo</tt> contains an array of <tt>XXXInstrDescriptor</tt> objects,
993each of which describes one instruction. An instruction descriptor defines:</p>
994
995<ul>
996<li>Opcode mnemonic</li>
997
998<li>Number of operands</li>
999
1000<li>List of implicit register definitions and uses</li>
1001
1002<li>Target-independent properties (such as memory access, is commutable)</li>
1003
1004<li>Target-specific flags </li>
1005</ul>
1006
1007<p>
1008The Instruction class (defined in <tt>Target.td</tt>) is mostly used as a base
1009for more complex instruction classes.
1010</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1011
1012<div class="doc_code">
1013<pre>class Instruction {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1014 string Namespace = "";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1015 dag OutOperandList; // An dag containing the MI def operand list.
1016 dag InOperandList; // An dag containing the MI use operand list.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1017 string AsmString = ""; // The .s format to print the instruction with.
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1018 list&lt;dag&gt; Pattern; // Set to the DAG pattern for this instruction
1019 list&lt;Register&gt; Uses = [];
1020 list&lt;Register&gt; Defs = [];
1021 list&lt;Predicate&gt; Predicates = []; // predicates turned into isel match code
1022 ... remainder not shown for space ...
1023}
1024</pre>
1025</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1026
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1027<p>
1028A <tt>SelectionDAG</tt> node (<tt>SDNode</tt>) should contain an object
1029representing a target-specific instruction that is defined
1030in <tt>XXXInstrInfo.td</tt>. The instruction objects should represent
1031instructions from the architecture manual of the target machine (such as the
1032SPARC Architecture Manual for the SPARC target).
1033</p>
1034
1035<p>
1036A single instruction from the architecture manual is often modeled as multiple
1037target instructions, depending upon its operands. For example, a manual might
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1038describe an add instruction that takes a register or an immediate operand. An
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1039LLVM target could model this with two instructions named <tt>ADDri</tt> and
1040<tt>ADDrr</tt>.
1041</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1042
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1043<p>
1044You should define a class for each instruction category and define each opcode
1045as a subclass of the category with appropriate parameters such as the fixed
1046binary encoding of opcodes and extended opcodes. You should map the register
1047bits to the bits of the instruction in which they are encoded (for the
1048JIT). Also you should specify how the instruction should be printed when the
1049automatic assembly printer is used.
1050</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1051
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1052<p>
1053As is described in the SPARC Architecture Manual, Version 8, there are three
1054major 32-bit formats for instructions. Format 1 is only for the <tt>CALL</tt>
1055instruction. Format 2 is for branch on condition codes and <tt>SETHI</tt> (set
1056high bits of a register) instructions. Format 3 is for other instructions.
1057</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1058
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1059<p>
1060Each of these formats has corresponding classes in <tt>SparcInstrFormat.td</tt>.
1061<tt>InstSP</tt> is a base class for other instruction classes. Additional base
1062classes are specified for more precise formats: for example
1063in <tt>SparcInstrFormat.td</tt>, <tt>F2_1</tt> is for <tt>SETHI</tt>,
1064and <tt>F2_2</tt> is for branches. There are three other base
1065classes: <tt>F3_1</tt> for register/register operations, <tt>F3_2</tt> for
1066register/immediate operations, and <tt>F3_3</tt> for floating-point
1067operations. <tt>SparcInstrInfo.td</tt> also adds the base class Pseudo for
1068synthetic SPARC instructions.
1069</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1070
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1071<p>
1072<tt>SparcInstrInfo.td</tt> largely consists of operand and instruction
1073definitions for the SPARC target. In <tt>SparcInstrInfo.td</tt>, the following
1074target description file entry, <tt>LDrr</tt>, defines the Load Integer
1075instruction for a Word (the <tt>LD</tt> SPARC opcode) from a memory address to a
1076register. The first parameter, the value 3 (<tt>11<sub>2</sub></tt>), is the
1077operation value for this category of operation. The second parameter
1078(<tt>000000<sub>2</sub></tt>) is the specific operation value
1079for <tt>LD</tt>/Load Word. The third parameter is the output destination, which
1080is a register operand and defined in the <tt>Register</tt> target description
1081file (<tt>IntRegs</tt>).
1082</p>
1083
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1084<div class="doc_code">
1085<pre>def LDrr : F3_1 &lt;3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1086 "ld [$addr], $dst",
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1087 [(set IntRegs:$dst, (load ADDRrr:$addr))]&gt;;
1088</pre>
1089</div>
1090
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1091<p>
1092The fourth parameter is the input source, which uses the address
1093operand <tt>MEMrr</tt> that is defined earlier in <tt>SparcInstrInfo.td</tt>:
1094</p>
1095
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1096<div class="doc_code">
1097<pre>def MEMrr : Operand&lt;i32&gt; {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1098 let PrintMethod = "printMemOperand";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1099 let MIOperandInfo = (ops IntRegs, IntRegs);
1100}
1101</pre>
1102</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1103
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1104<p>
1105The fifth parameter is a string that is used by the assembly printer and can be
1106left as an empty string until the assembly printer interface is implemented. The
1107sixth and final parameter is the pattern used to match the instruction during
1108the SelectionDAG Select Phase described in
1109(<a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
1110Target-Independent Code Generator</a>). This parameter is detailed in the next
1111section, <a href="#InstructionSelector">Instruction Selector</a>.
1112</p>
1113
1114<p>
1115Instruction class definitions are not overloaded for different operand types, so
1116separate versions of instructions are needed for register, memory, or immediate
1117value operands. For example, to perform a Load Integer instruction for a Word
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1118from an immediate operand to a register, the following instruction class is
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1119defined:
1120</p>
1121
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1122<div class="doc_code">
1123<pre>def LDri : F3_2 &lt;3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1124 "ld [$addr], $dst",
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1125 [(set IntRegs:$dst, (load ADDRri:$addr))]&gt;;
1126</pre>
1127</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1128
1129<p>
1130Writing these definitions for so many similar instructions can involve a lot of
1131cut and paste. In td files, the <tt>multiclass</tt> directive enables the
1132creation of templates to define several instruction classes at once (using
1133the <tt>defm</tt> directive). For example in <tt>SparcInstrInfo.td</tt>, the
1134<tt>multiclass</tt> pattern <tt>F3_12</tt> is defined to create 2 instruction
1135classes each time <tt>F3_12</tt> is invoked:
1136</p>
1137
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1138<div class="doc_code">
1139<pre>multiclass F3_12 &lt;string OpcStr, bits&lt;6&gt; Op3Val, SDNode OpNode&gt; {
1140 def rr : F3_1 &lt;2, Op3Val,
1141 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1142 !strconcat(OpcStr, " $b, $c, $dst"),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1143 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]&gt;;
1144 def ri : F3_2 &lt;2, Op3Val,
1145 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1146 !strconcat(OpcStr, " $b, $c, $dst"),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1147 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]&gt;;
1148}
1149</pre>
1150</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1151
1152<p>
1153So when the <tt>defm</tt> directive is used for the <tt>XOR</tt>
1154and <tt>ADD</tt> instructions, as seen below, it creates four instruction
1155objects: <tt>XORrr</tt>, <tt>XORri</tt>, <tt>ADDrr</tt>, and <tt>ADDri</tt>.
1156</p>
1157
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1158<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1159<pre>
1160defm XOR : F3_12&lt;"xor", 0b000011, xor&gt;;
1161defm ADD : F3_12&lt;"add", 0b000000, add&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1162</pre>
1163</div>
1164
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1165<p>
1166<tt>SparcInstrInfo.td</tt> also includes definitions for condition codes that
1167are referenced by branch instructions. The following definitions
1168in <tt>SparcInstrInfo.td</tt> indicate the bit location of the SPARC condition
1169code. For example, the 10<sup>th</sup> bit represents the 'greater than'
1170condition for integers, and the 22<sup>nd</sup> bit represents the 'greater
1171than' condition for floats.
1172</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1173
1174<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1175<pre>
1176def ICC_NE : ICC_VAL&lt; 9&gt;; // Not Equal
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1177def ICC_E : ICC_VAL&lt; 1&gt;; // Equal
1178def ICC_G : ICC_VAL&lt;10&gt;; // Greater
1179...
1180def FCC_U : FCC_VAL&lt;23&gt;; // Unordered
1181def FCC_G : FCC_VAL&lt;22&gt;; // Greater
1182def FCC_UG : FCC_VAL&lt;21&gt;; // Unordered or Greater
1183...
1184</pre>
1185</div>
1186
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1187<p>
1188(Note that <tt>Sparc.h</tt> also defines enums that correspond to the same SPARC
1189condition codes. Care must be taken to ensure the values in <tt>Sparc.h</tt>
1190correspond to the values in <tt>SparcInstrInfo.td</tt>. I.e.,
1191<tt>SPCC::ICC_NE = 9</tt>, <tt>SPCC::FCC_U = 23</tt> and so on.)
1192</p>
1193
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1194</div>
1195
1196<!-- ======================================================================= -->
1197<div class="doc_subsection">
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1198 <a name="operandMapping">Instruction Operand Mapping</a>
1199</div>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1200
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1201<div class="doc_text">
1202
1203<p>
1204The code generator backend maps instruction operands to fields in the
1205instruction. Operands are assigned to unbound fields in the instruction in the
1206order they are defined. Fields are bound when they are assigned a value. For
1207example, the Sparc target defines the <tt>XNORrr</tt> instruction as
1208a <tt>F3_1</tt> format instruction having three operands.
1209</p>
1210
1211<div class="doc_code">
1212<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1213def XNORrr : F3_1&lt;2, 0b000111,
1214 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1215 "xnor $b, $c, $dst",
1216 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1217</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1218</div>
1219
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1220<p>
1221The instruction templates in <tt>SparcInstrFormats.td</tt> show the base class
1222for <tt>F3_1</tt> is <tt>InstSP</tt>.
1223</p>
1224
1225<div class="doc_code">
1226<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1227class InstSP&lt;dag outs, dag ins, string asmstr, list&lt;dag&gt; pattern&gt; : Instruction {
1228 field bits&lt;32&gt; Inst;
1229 let Namespace = "SP";
1230 bits&lt;2&gt; op;
1231 let Inst{31-30} = op;
1232 dag OutOperandList = outs;
1233 dag InOperandList = ins;
1234 let AsmString = asmstr;
1235 let Pattern = pattern;
1236}
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1237</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1238</div>
1239
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1240<p><tt>InstSP</tt> leaves the <tt>op</tt> field unbound.</p>
1241
1242<div class="doc_code">
1243<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1244class F3&lt;dag outs, dag ins, string asmstr, list&lt;dag&gt; pattern&gt;
1245 : InstSP&lt;outs, ins, asmstr, pattern&gt; {
1246 bits&lt;5&gt; rd;
1247 bits&lt;6&gt; op3;
1248 bits&lt;5&gt; rs1;
1249 let op{1} = 1; // Op = 2 or 3
1250 let Inst{29-25} = rd;
1251 let Inst{24-19} = op3;
1252 let Inst{18-14} = rs1;
1253}
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1254</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1255</div>
1256
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1257<p>
1258<tt>F3</tt> binds the <tt>op</tt> field and defines the <tt>rd</tt>,
1259<tt>op3</tt>, and <tt>rs1</tt> fields. <tt>F3</tt> format instructions will
1260bind the operands <tt>rd</tt>, <tt>op3</tt>, and <tt>rs1</tt> fields.
1261</p>
1262
1263<div class="doc_code">
1264<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1265class F3_1&lt;bits&lt;2&gt; opVal, bits&lt;6&gt; op3val, dag outs, dag ins,
1266 string asmstr, list&lt;dag&gt; pattern&gt; : F3&lt;outs, ins, asmstr, pattern&gt; {
1267 bits&lt;8&gt; asi = 0; // asi not currently used
1268 bits&lt;5&gt; rs2;
1269 let op = opVal;
1270 let op3 = op3val;
1271 let Inst{13} = 0; // i field = 0
1272 let Inst{12-5} = asi; // address space identifier
1273 let Inst{4-0} = rs2;
1274}
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1275</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1276</div>
1277
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1278<p>
1279<tt>F3_1</tt> binds the <tt>op3</tt> field and defines the <tt>rs2</tt>
1280fields. <tt>F3_1</tt> format instructions will bind the operands to the <tt>rd</tt>,
1281<tt>rs1</tt>, and <tt>rs2</tt> fields. This results in the <tt>XNORrr</tt>
1282instruction binding <tt>$dst</tt>, <tt>$b</tt>, and <tt>$c</tt> operands to
1283the <tt>rd</tt>, <tt>rs1</tt>, and <tt>rs2</tt> fields respectively.
1284</p>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1285
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1286</div>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1287
1288<!-- ======================================================================= -->
1289<div class="doc_subsection">
Chris Lattner7d12b4b2008-11-11 19:36:31 +0000[diff] [blame]1290 <a name="implementInstr">Implement a subclass of </a>
1291 <a href="http://www.llvm.org/docs/CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1292</div>
1293
1294<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1295
1296<p>
1297The final step is to hand code portions of <tt>XXXInstrInfo</tt>, which
1298implements the interface described in <tt>TargetInstrInfo.h</tt>. These
1299functions return <tt>0</tt> or a Boolean or they assert, unless
1300overridden. Here's a list of functions that are overridden for the SPARC
1301implementation in <tt>SparcInstrInfo.cpp</tt>:
1302</p>
1303
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1304<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1305<li><tt>isMoveInstr</tt> &mdash; Return true if the instruction is a register to
1306 register move; false, otherwise.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1307
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1308<li><tt>isLoadFromStackSlot</tt> &mdash; If the specified machine instruction is
1309 a direct load from a stack slot, return the register number of the
1310 destination and the <tt>FrameIndex</tt> of the stack slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1311
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1312<li><tt>isStoreToStackSlot</tt> &mdash; If the specified machine instruction is
1313 a direct store to a stack slot, return the register number of the
1314 destination and the <tt>FrameIndex</tt> of the stack slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1315
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1316<li><tt>copyRegToReg</tt> &mdash; Copy values between a pair of registers.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1317
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1318<li><tt>storeRegToStackSlot</tt> &mdash; Store a register value to a stack
1319 slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1320
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1321<li><tt>loadRegFromStackSlot</tt> &mdash; Load a register value from a stack
1322 slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1323
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1324<li><tt>storeRegToAddr</tt> &mdash; Store a register value to memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1325
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1326<li><tt>loadRegFromAddr</tt> &mdash; Load a register value from memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1327
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1328<li><tt>foldMemoryOperand</tt> &mdash; Attempt to combine instructions of any
1329 load or store instruction for the specified operand(s).</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1330</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1331
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1332</div>
1333
1334<!-- ======================================================================= -->
1335<div class="doc_subsection">
1336 <a name="branchFolding">Branch Folding and If Conversion</a>
1337</div>
1338<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1339
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1340<p>
1341Performance can be improved by combining instructions or by eliminating
1342instructions that are never reached. The <tt>AnalyzeBranch</tt> method
1343in <tt>XXXInstrInfo</tt> may be implemented to examine conditional instructions
1344and remove unnecessary instructions. <tt>AnalyzeBranch</tt> looks at the end of
1345a machine basic block (MBB) for opportunities for improvement, such as branch
1346folding and if conversion. The <tt>BranchFolder</tt> and <tt>IfConverter</tt>
1347machine function passes (see the source files <tt>BranchFolding.cpp</tt> and
1348<tt>IfConversion.cpp</tt> in the <tt>lib/CodeGen</tt> directory) call
1349<tt>AnalyzeBranch</tt> to improve the control flow graph that represents the
1350instructions.
1351</p>
1352
1353<p>
1354Several implementations of <tt>AnalyzeBranch</tt> (for ARM, Alpha, and X86) can
1355be examined as models for your own <tt>AnalyzeBranch</tt> implementation. Since
1356SPARC does not implement a useful <tt>AnalyzeBranch</tt>, the ARM target
1357implementation is shown below.
1358</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1359
1360<p><tt>AnalyzeBranch</tt> returns a Boolean value and takes four parameters:</p>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1361
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1362<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1363<li><tt>MachineBasicBlock &amp;MBB</tt> &mdash; The incoming block to be
1364 examined.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1365
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1366<li><tt>MachineBasicBlock *&amp;TBB</tt> &mdash; A destination block that is
1367 returned. For a conditional branch that evaluates to true, <tt>TBB</tt> is
1368 the destination.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1369
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1370<li><tt>MachineBasicBlock *&amp;FBB</tt> &mdash; For a conditional branch that
1371 evaluates to false, <tt>FBB</tt> is returned as the destination.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1372
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1373<li><tt>std::vector&lt;MachineOperand&gt; &amp;Cond</tt> &mdash; List of
1374 operands to evaluate a condition for a conditional branch.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1375</ul>
1376
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1377<p>
1378In the simplest case, if a block ends without a branch, then it falls through to
1379the successor block. No destination blocks are specified for either <tt>TBB</tt>
1380or <tt>FBB</tt>, so both parameters return <tt>NULL</tt>. The start of
1381the <tt>AnalyzeBranch</tt> (see code below for the ARM target) shows the
1382function parameters and the code for the simplest case.
1383</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1384
1385<div class="doc_code">
1386<pre>bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &amp;MBB,
1387 MachineBasicBlock *&amp;TBB, MachineBasicBlock *&amp;FBB,
1388 std::vector&lt;MachineOperand&gt; &amp;Cond) const
1389{
1390 MachineBasicBlock::iterator I = MBB.end();
1391 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
1392 return false;
1393</pre>
1394</div>
1395
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1396<p>
1397If a block ends with a single unconditional branch instruction, then
1398<tt>AnalyzeBranch</tt> (shown below) should return the destination of that
1399branch in the <tt>TBB</tt> parameter.
1400</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1401
1402<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1403<pre>
1404 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
1405 TBB = LastInst-&gt;getOperand(0).getMBB();
1406 return false;
1407 }
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1408</pre>
1409</div>
1410
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1411<p>
1412If a block ends with two unconditional branches, then the second branch is never
1413reached. In that situation, as shown below, remove the last branch instruction
1414and return the penultimate branch in the <tt>TBB</tt> parameter.
1415</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1416
1417<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1418<pre>
1419 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &amp;&amp;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1420 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
1421 TBB = SecondLastInst-&gt;getOperand(0).getMBB();
1422 I = LastInst;
1423 I-&gt;eraseFromParent();
1424 return false;
1425 }
1426</pre>
1427</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1428
1429<p>
1430A block may end with a single conditional branch instruction that falls through
1431to successor block if the condition evaluates to false. In that case,
1432<tt>AnalyzeBranch</tt> (shown below) should return the destination of that
1433conditional branch in the <tt>TBB</tt> parameter and a list of operands in
1434the <tt>Cond</tt> parameter to evaluate the condition.
1435</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1436
1437<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1438<pre>
1439 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
1440 // Block ends with fall-through condbranch.
1441 TBB = LastInst-&gt;getOperand(0).getMBB();
1442 Cond.push_back(LastInst-&gt;getOperand(1));
1443 Cond.push_back(LastInst-&gt;getOperand(2));
1444 return false;
1445 }
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1446</pre>
1447</div>
1448
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1449<p>
1450If a block ends with both a conditional branch and an ensuing unconditional
1451branch, then <tt>AnalyzeBranch</tt> (shown below) should return the conditional
1452branch destination (assuming it corresponds to a conditional evaluation of
1453'<tt>true</tt>') in the <tt>TBB</tt> parameter and the unconditional branch
1454destination in the <tt>FBB</tt> (corresponding to a conditional evaluation of
1455'<tt>false</tt>'). A list of operands to evaluate the condition should be
1456returned in the <tt>Cond</tt> parameter.
1457</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1458
1459<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1460<pre>
1461 unsigned SecondLastOpc = SecondLastInst-&gt;getOpcode();
1462
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1463 if ((SecondLastOpc == ARM::Bcc &amp;&amp; LastOpc == ARM::B) ||
1464 (SecondLastOpc == ARM::tBcc &amp;&amp; LastOpc == ARM::tB)) {
1465 TBB = SecondLastInst-&gt;getOperand(0).getMBB();
1466 Cond.push_back(SecondLastInst-&gt;getOperand(1));
1467 Cond.push_back(SecondLastInst-&gt;getOperand(2));
1468 FBB = LastInst-&gt;getOperand(0).getMBB();
1469 return false;
1470 }
1471</pre>
1472</div>
1473
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1474<p>
1475For the last two cases (ending with a single conditional branch or ending with
1476one conditional and one unconditional branch), the operands returned in
1477the <tt>Cond</tt> parameter can be passed to methods of other instructions to
1478create new branches or perform other operations. An implementation
1479of <tt>AnalyzeBranch</tt> requires the helper methods <tt>RemoveBranch</tt>
1480and <tt>InsertBranch</tt> to manage subsequent operations.
1481</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1482
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1483<p>
1484<tt>AnalyzeBranch</tt> should return false indicating success in most circumstances.
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1485<tt>AnalyzeBranch</tt> should only return true when the method is stumped about what to
1486do, for example, if a block has three terminating branches. <tt>AnalyzeBranch</tt> may
1487return true if it encounters a terminator it cannot handle, such as an indirect
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1488branch.
1489</p>
1490
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1491</div>
1492
1493<!-- *********************************************************************** -->
1494<div class="doc_section">
1495 <a name="InstructionSelector">Instruction Selector</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]1496</div>
1497<!-- *********************************************************************** -->
1498
1499<div class="doc_text">
1500
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1501<p>
1502LLVM uses a <tt>SelectionDAG</tt> to represent LLVM IR instructions, and nodes
1503of the <tt>SelectionDAG</tt> ideally represent native target
1504instructions. During code generation, instruction selection passes are performed
1505to convert non-native DAG instructions into native target-specific
1506instructions. The pass described in <tt>XXXISelDAGToDAG.cpp</tt> is used to
1507match patterns and perform DAG-to-DAG instruction selection. Optionally, a pass
1508may be defined (in <tt>XXXBranchSelector.cpp</tt>) to perform similar DAG-to-DAG
1509operations for branch instructions. Later, the code in
1510<tt>XXXISelLowering.cpp</tt> replaces or removes operations and data types not
1511supported natively (legalizes) in a <tt>SelectionDAG</tt>.
1512</p>
1513
1514<p>
1515TableGen generates code for instruction selection using the following target
1516description input files:
1517</p>
1518
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]1519<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1520<li><tt>XXXInstrInfo.td</tt> &mdash; Contains definitions of instructions in a
1521 target-specific instruction set, generates <tt>XXXGenDAGISel.inc</tt>, which
1522 is included in <tt>XXXISelDAGToDAG.cpp</tt>.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1523
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1524<li><tt>XXXCallingConv.td</tt> &mdash; Contains the calling and return value
1525 conventions for the target architecture, and it generates
1526 <tt>XXXGenCallingConv.inc</tt>, which is included in
1527 <tt>XXXISelLowering.cpp</tt>.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]1528</ul>
1529
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1530<p>
1531The implementation of an instruction selection pass must include a header that
1532declares the <tt>FunctionPass</tt> class or a subclass of <tt>FunctionPass</tt>. In
1533<tt>XXXTargetMachine.cpp</tt>, a Pass Manager (PM) should add each instruction
1534selection pass into the queue of passes to run.
1535</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1536
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1537<p>
1538The LLVM static compiler (<tt>llc</tt>) is an excellent tool for visualizing the
1539contents of DAGs. To display the <tt>SelectionDAG</tt> before or after specific
1540processing phases, use the command line options for <tt>llc</tt>, described
1541at <a href="http://llvm.org/docs/CodeGenerator.html#selectiondag_process">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1542SelectionDAG Instruction Selection Process</a>.
1543</p>
1544
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1545<p>
1546To describe instruction selector behavior, you should add patterns for lowering
1547LLVM code into a <tt>SelectionDAG</tt> as the last parameter of the instruction
1548definitions in <tt>XXXInstrInfo.td</tt>. For example, in
1549<tt>SparcInstrInfo.td</tt>, this entry defines a register store operation, and
1550the last parameter describes a pattern with the store DAG operator.
1551</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1552
1553<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1554<pre>
1555def STrr : F3_1&lt; 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
1556 "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1557</pre>
1558</div>
1559
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1560<p>
1561<tt>ADDRrr</tt> is a memory mode that is also defined in
1562<tt>SparcInstrInfo.td</tt>:
1563</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1564
1565<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1566<pre>
1567def ADDRrr : ComplexPattern&lt;i32, 2, "SelectADDRrr", [], []&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1568</pre>
1569</div>
1570
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1571<p>
1572The definition of <tt>ADDRrr</tt> refers to <tt>SelectADDRrr</tt>, which is a
1573function defined in an implementation of the Instructor Selector (such
1574as <tt>SparcISelDAGToDAG.cpp</tt>).
1575</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1576
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1577<p>
1578In <tt>lib/Target/TargetSelectionDAG.td</tt>, the DAG operator for store is
1579defined below:
1580</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1581
1582<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1583<pre>
1584def store : PatFrag&lt;(ops node:$val, node:$ptr),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1585 (st node:$val, node:$ptr), [{
1586 if (StoreSDNode *ST = dyn_cast&lt;StoreSDNode&gt;(N))
1587 return !ST-&gt;isTruncatingStore() &amp;&amp;
1588 ST-&gt;getAddressingMode() == ISD::UNINDEXED;
1589 return false;
1590}]&gt;;
1591</pre>
1592</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1593
1594<p>
1595<tt>XXXInstrInfo.td</tt> also generates (in <tt>XXXGenDAGISel.inc</tt>) the
1596<tt>SelectCode</tt> method that is used to call the appropriate processing
1597method for an instruction. In this example, <tt>SelectCode</tt>
1598calls <tt>Select_ISD_STORE</tt> for the <tt>ISD::STORE</tt> opcode.
1599</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1600
1601<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1602<pre>
1603SDNode *SelectCode(SDValue N) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1604 ...
Dan Gohman50ef90d2009-01-28 21:36:46 +0000[diff] [blame]1605 MVT::ValueType NVT = N.getNode()-&gt;getValueType(0);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1606 switch (N.getOpcode()) {
1607 case ISD::STORE: {
1608 switch (NVT) {
1609 default:
1610 return Select_ISD_STORE(N);
1611 break;
1612 }
1613 break;
1614 }
1615 ...
1616</pre>
1617</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1618
1619<p>
1620The pattern for <tt>STrr</tt> is matched, so elsewhere in
1621<tt>XXXGenDAGISel.inc</tt>, code for <tt>STrr</tt> is created for
1622<tt>Select_ISD_STORE</tt>. The <tt>Emit_22</tt> method is also generated
1623in <tt>XXXGenDAGISel.inc</tt> to complete the processing of this
1624instruction.
1625</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1626
1627<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1628<pre>
1629SDNode *Select_ISD_STORE(const SDValue &amp;N) {
Dan Gohman50ef90d2009-01-28 21:36:46 +0000[diff] [blame]1630 SDValue Chain = N.getOperand(0);
1631 if (Predicate_store(N.getNode())) {
1632 SDValue N1 = N.getOperand(1);
1633 SDValue N2 = N.getOperand(2);
1634 SDValue CPTmp0;
1635 SDValue CPTmp1;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1636
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1637 // Pattern: (st:void IntRegs:i32:$src,
1638 // ADDRrr:i32:$addr)&lt;&lt;P:Predicate_store&gt;&gt;
1639 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
1640 // Pattern complexity = 13 cost = 1 size = 0
1641 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &amp;&amp;
Dan Gohman50ef90d2009-01-28 21:36:46 +0000[diff] [blame]1642 N1.getNode()-&gt;getValueType(0) == MVT::i32 &amp;&amp;
1643 N2.getNode()-&gt;getValueType(0) == MVT::i32) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1644 return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
1645 }
1646...
1647</pre>
1648</div>
1649
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1650</div>
1651
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1652<!-- ======================================================================= -->
1653<div class="doc_subsection">
1654 <a name="LegalizePhase">The SelectionDAG Legalize Phase</a>
1655</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1656
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1657<div class="doc_text">
1658
1659<p>
1660The Legalize phase converts a DAG to use types and operations that are natively
1661supported by the target. For natively unsupported types and operations, you need
1662to add code to the target-specific XXXTargetLowering implementation to convert
1663unsupported types and operations to supported ones.
1664</p>
1665
1666<p>
1667In the constructor for the <tt>XXXTargetLowering</tt> class, first use the
1668<tt>addRegisterClass</tt> method to specify which types are supports and which
1669register classes are associated with them. The code for the register classes are
1670generated by TableGen from <tt>XXXRegisterInfo.td</tt> and placed
1671in <tt>XXXGenRegisterInfo.h.inc</tt>. For example, the implementation of the
1672constructor for the SparcTargetLowering class (in
1673<tt>SparcISelLowering.cpp</tt>) starts with the following code:
1674</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1675
1676<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1677<pre>
1678addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1679addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1680addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
1681</pre>
1682</div>
1683
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1684<p>
1685You should examine the node types in the <tt>ISD</tt> namespace
1686(<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>) and determine which
1687operations the target natively supports. For operations that do <b>not</b> have
1688native support, add a callback to the constructor for the XXXTargetLowering
1689class, so the instruction selection process knows what to do. The TargetLowering
1690class callback methods (declared in <tt>llvm/Target/TargetLowering.h</tt>) are:
1691</p>
1692
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1693<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1694<li><tt>setOperationAction</tt> &mdash; General operation.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1695
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1696<li><tt>setLoadExtAction</tt> &mdash; Load with extension.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1697
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1698<li><tt>setTruncStoreAction</tt> &mdash; Truncating store.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1699
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1700<li><tt>setIndexedLoadAction</tt> &mdash; Indexed load.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1701
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1702<li><tt>setIndexedStoreAction</tt> &mdash; Indexed store.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1703
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1704<li><tt>setConvertAction</tt> &mdash; Type conversion.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1705
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1706<li><tt>setCondCodeAction</tt> &mdash; Support for a given condition code.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1707</ul>
1708
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1709<p>
1710Note: on older releases, <tt>setLoadXAction</tt> is used instead
1711of <tt>setLoadExtAction</tt>. Also, on older releases,
1712<tt>setCondCodeAction</tt> may not be supported. Examine your release
1713to see what methods are specifically supported.
1714</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1715
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1716<p>
1717These callbacks are used to determine that an operation does or does not work
1718with a specified type (or types). And in all cases, the third parameter is
1719a <tt>LegalAction</tt> type enum value: <tt>Promote</tt>, <tt>Expand</tt>,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1720<tt>Custom</tt>, or <tt>Legal</tt>. <tt>SparcISelLowering.cpp</tt>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1721contains examples of all four <tt>LegalAction</tt> values.
1722</p>
1723
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1724</div>
1725
1726<!-- _______________________________________________________________________ -->
1727<div class="doc_subsubsection">
1728 <a name="promote">Promote</a>
1729</div>
1730
1731<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1732
1733<p>
1734For an operation without native support for a given type, the specified type may
1735be promoted to a larger type that is supported. For example, SPARC does not
1736support a sign-extending load for Boolean values (<tt>i1</tt> type), so
1737in <tt>SparcISelLowering.cpp</tt> the third parameter below, <tt>Promote</tt>,
1738changes <tt>i1</tt> type values to a large type before loading.
1739</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1740
1741<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1742<pre>
1743setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1744</pre>
1745</div>
1746
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1747</div>
1748
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1749<!-- _______________________________________________________________________ -->
1750<div class="doc_subsubsection">
1751 <a name="expand">Expand</a>
1752</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1753
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1754<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1755
1756<p>
1757For a type without native support, a value may need to be broken down further,
1758rather than promoted. For an operation without native support, a combination of
1759other operations may be used to similar effect. In SPARC, the floating-point
1760sine and cosine trig operations are supported by expansion to other operations,
1761as indicated by the third parameter, <tt>Expand</tt>, to
1762<tt>setOperationAction</tt>:
1763</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1764
1765<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1766<pre>
1767setOperationAction(ISD::FSIN, MVT::f32, Expand);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1768setOperationAction(ISD::FCOS, MVT::f32, Expand);
1769</pre>
1770</div>
1771
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1772</div>
1773
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1774<!-- _______________________________________________________________________ -->
1775<div class="doc_subsubsection">
1776 <a name="custom">Custom</a>
1777</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1778
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1779<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1780
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1781<p>
1782For some operations, simple type promotion or operation expansion may be
1783insufficient. In some cases, a special intrinsic function must be implemented.
1784</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1785
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1786<p>
1787For example, a constant value may require special treatment, or an operation may
1788require spilling and restoring registers in the stack and working with register
1789allocators.
1790</p>
1791
1792<p>
1793As seen in <tt>SparcISelLowering.cpp</tt> code below, to perform a type
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1794conversion from a floating point value to a signed integer, first the
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1795<tt>setOperationAction</tt> should be called with <tt>Custom</tt> as the third
1796parameter:
1797</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1798
1799<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1800<pre>
1801setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1802</pre>
1803</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1804
1805<p>
1806In the <tt>LowerOperation</tt> method, for each <tt>Custom</tt> operation, a
1807case statement should be added to indicate what function to call. In the
1808following code, an <tt>FP_TO_SINT</tt> opcode will call
1809the <tt>LowerFP_TO_SINT</tt> method:
1810</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1811
1812<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1813<pre>
1814SDValue SparcTargetLowering::LowerOperation(SDValue Op, SelectionDAG &amp;DAG) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1815 switch (Op.getOpcode()) {
1816 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1817 ...
1818 }
1819}
1820</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1821</div>
1822
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1823<p>
1824Finally, the <tt>LowerFP_TO_SINT</tt> method is implemented, using an FP
1825register to convert the floating-point value to an integer.
1826</p>
1827
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1828<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1829<pre>
1830static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &amp;DAG) {
1831 assert(Op.getValueType() == MVT::i32);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1832 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
1833 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1834}
1835</pre>
1836</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1837
1838</div>
1839
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1840<!-- _______________________________________________________________________ -->
1841<div class="doc_subsubsection">
1842 <a name="legal">Legal</a>
1843</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1844
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1845<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1846
1847<p>
1848The <tt>Legal</tt> LegalizeAction enum value simply indicates that an
1849operation <b>is</b> natively supported. <tt>Legal</tt> represents the default
1850condition, so it is rarely used. In <tt>SparcISelLowering.cpp</tt>, the action
1851for <tt>CTPOP</tt> (an operation to count the bits set in an integer) is
1852natively supported only for SPARC v9. The following code enables
1853the <tt>Expand</tt> conversion technique for non-v9 SPARC implementations.
1854</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1855
1856<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1857<pre>
1858setOperationAction(ISD::CTPOP, MVT::i32, Expand);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1859...
1860if (TM.getSubtarget&lt;SparcSubtarget&gt;().isV9())
1861 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1862 case ISD::SETULT: return SPCC::ICC_CS;
1863 case ISD::SETULE: return SPCC::ICC_LEU;
1864 case ISD::SETUGT: return SPCC::ICC_GU;
1865 case ISD::SETUGE: return SPCC::ICC_CC;
1866 }
1867}
1868</pre>
1869</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1870
1871</div>
1872
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1873<!-- ======================================================================= -->
1874<div class="doc_subsection">
1875 <a name="callingConventions">Calling Conventions</a>
1876</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1877
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1878<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1879
1880<p>
1881To support target-specific calling conventions, <tt>XXXGenCallingConv.td</tt>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1882uses interfaces (such as CCIfType and CCAssignToReg) that are defined in
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1883<tt>lib/Target/TargetCallingConv.td</tt>. TableGen can take the target
1884descriptor file <tt>XXXGenCallingConv.td</tt> and generate the header
1885file <tt>XXXGenCallingConv.inc</tt>, which is typically included
1886in <tt>XXXISelLowering.cpp</tt>. You can use the interfaces in
1887<tt>TargetCallingConv.td</tt> to specify:
1888</p>
1889
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1890<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1891<li>The order of parameter allocation.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1892
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1893<li>Where parameters and return values are placed (that is, on the stack or in
1894 registers).</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1895
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1896<li>Which registers may be used.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1897
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1898<li>Whether the caller or callee unwinds the stack.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1899</ul>
1900
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1901<p>
1902The following example demonstrates the use of the <tt>CCIfType</tt> and
1903<tt>CCAssignToReg</tt> interfaces. If the <tt>CCIfType</tt> predicate is true
1904(that is, if the current argument is of type <tt>f32</tt> or <tt>f64</tt>), then
1905the action is performed. In this case, the <tt>CCAssignToReg</tt> action assigns
1906the argument value to the first available register: either <tt>R0</tt>
1907or <tt>R1</tt>.
1908</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1909
1910<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1911<pre>
1912CCIfType&lt;[f32,f64], CCAssignToReg&lt;[R0, R1]&gt;&gt;
1913</pre>
1914</div>
1915
1916<p>
1917<tt>SparcCallingConv.td</tt> contains definitions for a target-specific
1918return-value calling convention (RetCC_Sparc32) and a basic 32-bit C calling
1919convention (<tt>CC_Sparc32</tt>). The definition of <tt>RetCC_Sparc32</tt>
1920(shown below) indicates which registers are used for specified scalar return
1921types. A single-precision float is returned to register <tt>F0</tt>, and a
1922double-precision float goes to register <tt>D0</tt>. A 32-bit integer is
1923returned in register <tt>I0</tt> or <tt>I1</tt>.
1924</p>
1925
1926<div class="doc_code">
1927<pre>
1928def RetCC_Sparc32 : CallingConv&lt;[
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1929 CCIfType&lt;[i32], CCAssignToReg&lt;[I0, I1]&gt;&gt;,
1930 CCIfType&lt;[f32], CCAssignToReg&lt;[F0]&gt;&gt;,
1931 CCIfType&lt;[f64], CCAssignToReg&lt;[D0]&gt;&gt;
1932]&gt;;
1933</pre>
1934</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1935
1936<p>
1937The definition of <tt>CC_Sparc32</tt> in <tt>SparcCallingConv.td</tt> introduces
1938<tt>CCAssignToStack</tt>, which assigns the value to a stack slot with the
1939specified size and alignment. In the example below, the first parameter, 4,
1940indicates the size of the slot, and the second parameter, also 4, indicates the
1941stack alignment along 4-byte units. (Special cases: if size is zero, then the
1942ABI size is used; if alignment is zero, then the ABI alignment is used.)
1943</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1944
1945<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1946<pre>
1947def CC_Sparc32 : CallingConv&lt;[
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1948 // All arguments get passed in integer registers if there is space.
1949 CCIfType&lt;[i32, f32, f64], CCAssignToReg&lt;[I0, I1, I2, I3, I4, I5]&gt;&gt;,
1950 CCAssignToStack&lt;4, 4&gt;
1951]&gt;;
1952</pre>
1953</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1954
1955<p>
1956<tt>CCDelegateTo</tt> is another commonly used interface, which tries to find a
1957specified sub-calling convention, and, if a match is found, it is invoked. In
1958the following example (in <tt>X86CallingConv.td</tt>), the definition of
1959<tt>RetCC_X86_32_C</tt> ends with <tt>CCDelegateTo</tt>. After the current value
1960is assigned to the register <tt>ST0</tt> or <tt>ST1</tt>,
1961the <tt>RetCC_X86Common</tt> is invoked.
1962</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1963
1964<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1965<pre>
1966def RetCC_X86_32_C : CallingConv&lt;[
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1967 CCIfType&lt;[f32], CCAssignToReg&lt;[ST0, ST1]&gt;&gt;,
1968 CCIfType&lt;[f64], CCAssignToReg&lt;[ST0, ST1]&gt;&gt;,
1969 CCDelegateTo&lt;RetCC_X86Common&gt;
1970]&gt;;
1971</pre>
1972</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1973
1974<p>
1975<tt>CCIfCC</tt> is an interface that attempts to match the given name to the
1976current calling convention. If the name identifies the current calling
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1977convention, then a specified action is invoked. In the following example (in
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1978<tt>X86CallingConv.td</tt>), if the <tt>Fast</tt> calling convention is in use,
1979then <tt>RetCC_X86_32_Fast</tt> is invoked. If the <tt>SSECall</tt> calling
1980convention is in use, then <tt>RetCC_X86_32_SSE</tt> is invoked.
1981</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1982
1983<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1984<pre>
1985def RetCC_X86_32 : CallingConv&lt;[
1986 CCIfCC&lt;"CallingConv::Fast", CCDelegateTo&lt;RetCC_X86_32_Fast&gt;&gt;,
1987 CCIfCC&lt;"CallingConv::X86_SSECall", CCDelegateTo&lt;RetCC_X86_32_SSE&gt;&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1988 CCDelegateTo&lt;RetCC_X86_32_C&gt;
1989]&gt;;
1990</pre>
1991</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1992
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1993<p>Other calling convention interfaces include:</p>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1994
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1995<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1996<li><tt>CCIf &lt;predicate, action&gt;</tt> &mdash; If the predicate matches,
1997 apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1998
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1999<li><tt>CCIfInReg &lt;action&gt;</tt> &mdash; If the argument is marked with the
2000 '<tt>inreg</tt>' attribute, then apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2001
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2002<li><tt>CCIfNest &lt;action&gt;</tt> &mdash; Inf the argument is marked with the
2003 '<tt>nest</tt>' attribute, then apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2004
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2005<li><tt>CCIfNotVarArg &lt;action&gt;</tt> &mdash; If the current function does
2006 not take a variable number of arguments, apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2007
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2008<li><tt>CCAssignToRegWithShadow &lt;registerList, shadowList&gt;</tt> &mdash;
2009 similar to <tt>CCAssignToReg</tt>, but with a shadow list of registers.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2010
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2011<li><tt>CCPassByVal &lt;size, align&gt;</tt> &mdash; Assign value to a stack
2012 slot with the minimum specified size and alignment.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2013
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2014<li><tt>CCPromoteToType &lt;type&gt;</tt> &mdash; Promote the current value to
2015 the specified type.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2016
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2017<li><tt>CallingConv &lt;[actions]&gt;</tt> &mdash; Define each calling
2018 convention that is supported.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2019</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2020
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2021</div>
2022
2023<!-- *********************************************************************** -->
2024<div class="doc_section">
2025 <a name="assemblyPrinter">Assembly Printer</a>
2026</div>
2027<!-- *********************************************************************** -->
2028
2029<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2030
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2031<p>
2032During the code emission stage, the code generator may utilize an LLVM pass to
2033produce assembly output. To do this, you want to implement the code for a
2034printer that converts LLVM IR to a GAS-format assembly language for your target
2035machine, using the following steps:
2036</p>
2037
2038<ul>
2039<li>Define all the assembly strings for your target, adding them to the
2040 instructions defined in the <tt>XXXInstrInfo.td</tt> file.
2041 (See <a href="#InstructionSet">Instruction Set</a>.) TableGen will produce
2042 an output file (<tt>XXXGenAsmWriter.inc</tt>) with an implementation of
2043 the <tt>printInstruction</tt> method for the XXXAsmPrinter class.</li>
2044
2045<li>Write <tt>XXXTargetAsmInfo.h</tt>, which contains the bare-bones declaration
2046 of the <tt>XXXTargetAsmInfo</tt> class (a subclass
2047 of <tt>TargetAsmInfo</tt>).</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2048
2049<li>Write <tt>XXXTargetAsmInfo.cpp</tt>, which contains target-specific values
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2050 for <tt>TargetAsmInfo</tt> properties and sometimes new implementations for
2051 methods.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2052
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2053<li>Write <tt>XXXAsmPrinter.cpp</tt>, which implements the <tt>AsmPrinter</tt>
2054 class that performs the LLVM-to-assembly conversion.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2055</ul>
2056
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2057<p>
2058The code in <tt>XXXTargetAsmInfo.h</tt> is usually a trivial declaration of the
2059<tt>XXXTargetAsmInfo</tt> class for use in <tt>XXXTargetAsmInfo.cpp</tt>.
2060Similarly, <tt>XXXTargetAsmInfo.cpp</tt> usually has a few declarations of
2061<tt>XXXTargetAsmInfo</tt> replacement values that override the default values
2062in <tt>TargetAsmInfo.cpp</tt>. For example in <tt>SparcTargetAsmInfo.cpp</tt>:
2063</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2064
2065<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2066<pre>
2067SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &amp;TM) {
2068 Data16bitsDirective = "\t.half\t";
2069 Data32bitsDirective = "\t.word\t";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2070 Data64bitsDirective = 0; // .xword is only supported by V9.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2071 ZeroDirective = "\t.skip\t";
2072 CommentString = "!";
2073 ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2074}
2075</pre>
2076</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2077
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2078<p>
2079The X86 assembly printer implementation (<tt>X86TargetAsmInfo</tt>) is an
Chris Lattnerb6d66742009-08-02 04:02:52 +0000[diff] [blame]2080example where the target specific <tt>TargetAsmInfo</tt> class uses an
2081overridden methods: <tt>ExpandInlineAsm</tt>.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2082</p>
2083
2084<p>
2085A target-specific implementation of AsmPrinter is written in
2086<tt>XXXAsmPrinter.cpp</tt>, which implements the <tt>AsmPrinter</tt> class that
2087converts the LLVM to printable assembly. The implementation must include the
2088following headers that have declarations for the <tt>AsmPrinter</tt> and
2089<tt>MachineFunctionPass</tt> classes. The <tt>MachineFunctionPass</tt> is a
2090subclass of <tt>FunctionPass</tt>.
2091</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2092
2093<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2094<pre>
2095#include "llvm/CodeGen/AsmPrinter.h"
2096#include "llvm/CodeGen/MachineFunctionPass.h"
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2097</pre>
2098</div>
2099
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2100<p>
2101As a <tt>FunctionPass</tt>, <tt>AsmPrinter</tt> first
2102calls <tt>doInitialization</tt> to set up the <tt>AsmPrinter</tt>. In
2103<tt>SparcAsmPrinter</tt>, a <tt>Mangler</tt> object is instantiated to process
2104variable names.
2105</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2106
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2107<p>
2108In <tt>XXXAsmPrinter.cpp</tt>, the <tt>runOnMachineFunction</tt> method
2109(declared in <tt>MachineFunctionPass</tt>) must be implemented
2110for <tt>XXXAsmPrinter</tt>. In <tt>MachineFunctionPass</tt>,
2111the <tt>runOnFunction</tt> method invokes <tt>runOnMachineFunction</tt>.
2112Target-specific implementations of <tt>runOnMachineFunction</tt> differ, but
2113generally do the following to process each machine function:
2114</p>
2115
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2116<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2117<li>Call <tt>SetupMachineFunction</tt> to perform initialization.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2118
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2119<li>Call <tt>EmitConstantPool</tt> to print out (to the output stream) constants
2120 which have been spilled to memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2121
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2122<li>Call <tt>EmitJumpTableInfo</tt> to print out jump tables used by the current
2123 function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2124
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2125<li>Print out the label for the current function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2126
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2127<li>Print out the code for the function, including basic block labels and the
2128 assembly for the instruction (using <tt>printInstruction</tt>)</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2129</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2130
2131<p>
2132The <tt>XXXAsmPrinter</tt> implementation must also include the code generated
2133by TableGen that is output in the <tt>XXXGenAsmWriter.inc</tt> file. The code
2134in <tt>XXXGenAsmWriter.inc</tt> contains an implementation of the
2135<tt>printInstruction</tt> method that may call these methods:
2136</p>
2137
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2138<ul>
2139<li><tt>printOperand</tt></li>
2140
2141<li><tt>printMemOperand</tt></li>
2142
2143<li><tt>printCCOperand (for conditional statements)</tt></li>
2144
2145<li><tt>printDataDirective</tt></li>
2146
2147<li><tt>printDeclare</tt></li>
2148
2149<li><tt>printImplicitDef</tt></li>
2150
2151<li><tt>printInlineAsm</tt></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2152</ul>
2153
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2154<p>
2155The implementations of <tt>printDeclare</tt>, <tt>printImplicitDef</tt>,
2156<tt>printInlineAsm</tt>, and <tt>printLabel</tt> in <tt>AsmPrinter.cpp</tt> are
2157generally adequate for printing assembly and do not need to be
Chris Lattnerdeb8c152009-09-12 22:57:37 +0000[diff] [blame]2158overridden.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2159</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2160
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2161<p>
2162The <tt>printOperand</tt> method is implemented with a long switch/case
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2163statement for the type of operand: register, immediate, basic block, external
2164symbol, global address, constant pool index, or jump table index. For an
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2165instruction with a memory address operand, the <tt>printMemOperand</tt> method
2166should be implemented to generate the proper output. Similarly,
2167<tt>printCCOperand</tt> should be used to print a conditional operand.
2168</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2169
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2170<p><tt>doFinalization</tt> should be overridden in <tt>XXXAsmPrinter</tt>, and
2171it should be called to shut down the assembly printer. During
2172<tt>doFinalization</tt>, global variables and constants are printed to
2173output.
2174</p>
2175
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2176</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2177
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2178<!-- *********************************************************************** -->
2179<div class="doc_section">
2180 <a name="subtargetSupport">Subtarget Support</a>
2181</div>
2182<!-- *********************************************************************** -->
2183
2184<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2185
2186<p>
2187Subtarget support is used to inform the code generation process of instruction
2188set variations for a given chip set. For example, the LLVM SPARC implementation
2189provided covers three major versions of the SPARC microprocessor architecture:
2190Version 8 (V8, which is a 32-bit architecture), Version 9 (V9, a 64-bit
2191architecture), and the UltraSPARC architecture. V8 has 16 double-precision
2192floating-point registers that are also usable as either 32 single-precision or 8
2193quad-precision registers. V8 is also purely big-endian. V9 has 32
2194double-precision floating-point registers that are also usable as 16
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2195quad-precision registers, but cannot be used as single-precision registers. The
2196UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2197extensions.
2198</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2199
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2200<p>
2201If subtarget support is needed, you should implement a target-specific
2202XXXSubtarget class for your architecture. This class should process the
2203command-line options <tt>-mcpu=</tt> and <tt>-mattr=</tt>.
2204</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2205
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2206<p>
2207TableGen uses definitions in the <tt>Target.td</tt> and <tt>Sparc.td</tt> files
2208to generate code in <tt>SparcGenSubtarget.inc</tt>. In <tt>Target.td</tt>, shown
2209below, the <tt>SubtargetFeature</tt> interface is defined. The first 4 string
2210parameters of the <tt>SubtargetFeature</tt> interface are a feature name, an
2211attribute set by the feature, the value of the attribute, and a description of
2212the feature. (The fifth parameter is a list of features whose presence is
2213implied, and its default value is an empty array.)
2214</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2215
2216<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2217<pre>
2218class SubtargetFeature&lt;string n, string a, string v, string d,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2219 list&lt;SubtargetFeature&gt; i = []&gt; {
2220 string Name = n;
2221 string Attribute = a;
2222 string Value = v;
2223 string Desc = d;
2224 list&lt;SubtargetFeature&gt; Implies = i;
2225}
2226</pre>
2227</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2228
2229<p>
2230In the <tt>Sparc.td</tt> file, the SubtargetFeature is used to define the
2231following features.
2232</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2233
2234<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2235<pre>
2236def FeatureV9 : SubtargetFeature&lt;"v9", "IsV9", "true",
2237 "Enable SPARC-V9 instructions"&gt;;
2238def FeatureV8Deprecated : SubtargetFeature&lt;"deprecated-v8",
2239 "V8DeprecatedInsts", "true",
2240 "Enable deprecated V8 instructions in V9 mode"&gt;;
2241def FeatureVIS : SubtargetFeature&lt;"vis", "IsVIS", "true",
2242 "Enable UltraSPARC Visual Instruction Set extensions"&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2243</pre>
2244</div>
2245
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2246<p>
2247Elsewhere in <tt>Sparc.td</tt>, the Proc class is defined and then is used to
2248define particular SPARC processor subtypes that may have the previously
2249described features.
2250</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2251
2252<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2253<pre>
2254class Proc&lt;string Name, list&lt;SubtargetFeature&gt; Features&gt;
2255 : Processor&lt;Name, NoItineraries, Features&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2256&nbsp;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2257def : Proc&lt;"generic", []&gt;;
2258def : Proc&lt;"v8", []&gt;;
2259def : Proc&lt;"supersparc", []&gt;;
2260def : Proc&lt;"sparclite", []&gt;;
2261def : Proc&lt;"f934", []&gt;;
2262def : Proc&lt;"hypersparc", []&gt;;
2263def : Proc&lt;"sparclite86x", []&gt;;
2264def : Proc&lt;"sparclet", []&gt;;
2265def : Proc&lt;"tsc701", []&gt;;
2266def : Proc&lt;"v9", [FeatureV9]&gt;;
2267def : Proc&lt;"ultrasparc", [FeatureV9, FeatureV8Deprecated]&gt;;
2268def : Proc&lt;"ultrasparc3", [FeatureV9, FeatureV8Deprecated]&gt;;
2269def : Proc&lt;"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2270</pre>
2271</div>
2272
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2273<p>
2274From <tt>Target.td</tt> and <tt>Sparc.td</tt> files, the resulting
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2275SparcGenSubtarget.inc specifies enum values to identify the features, arrays of
2276constants to represent the CPU features and CPU subtypes, and the
2277ParseSubtargetFeatures method that parses the features string that sets
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2278specified subtarget options. The generated <tt>SparcGenSubtarget.inc</tt> file
2279should be included in the <tt>SparcSubtarget.cpp</tt>. The target-specific
2280implementation of the XXXSubtarget method should follow this pseudocode:
2281</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2282
2283<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2284<pre>
2285XXXSubtarget::XXXSubtarget(const Module &amp;M, const std::string &amp;FS) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2286 // Set the default features
2287 // Determine default and user specified characteristics of the CPU
2288 // Call ParseSubtargetFeatures(FS, CPU) to parse the features string
2289 // Perform any additional operations
2290}
2291</pre>
2292</div>
2293
Bill Wendlinge9e6fd92009-04-05 00:43:04 +0000[diff] [blame]2294</div>
2295
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2296<!-- *********************************************************************** -->
2297<div class="doc_section">
2298 <a name="jitSupport">JIT Support</a>
2299</div>
2300<!-- *********************************************************************** -->
2301
2302<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2303
2304<p>
2305The implementation of a target machine optionally includes a Just-In-Time (JIT)
2306code generator that emits machine code and auxiliary structures as binary output
2307that can be written directly to memory. To do this, implement JIT code
2308generation by performing the following steps:
2309</p>
2310
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2311<ul>
2312<li>Write an <tt>XXXCodeEmitter.cpp</tt> file that contains a machine function
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2313 pass that transforms target-machine instructions into relocatable machine
2314 code.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2315
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2316<li>Write an <tt>XXXJITInfo.cpp</tt> file that implements the JIT interfaces for
2317 target-specific code-generation activities, such as emitting machine code
2318 and stubs.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2319
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2320<li>Modify <tt>XXXTargetMachine</tt> so that it provides a
2321 <tt>TargetJITInfo</tt> object through its <tt>getJITInfo</tt> method.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2322</ul>
2323
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2324<p>
2325There are several different approaches to writing the JIT support code. For
2326instance, TableGen and target descriptor files may be used for creating a JIT
2327code generator, but are not mandatory. For the Alpha and PowerPC target
2328machines, TableGen is used to generate <tt>XXXGenCodeEmitter.inc</tt>, which
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2329contains the binary coding of machine instructions and the
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2330<tt>getBinaryCodeForInstr</tt> method to access those codes. Other JIT
2331implementations do not.
2332</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2333
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2334<p>
2335Both <tt>XXXJITInfo.cpp</tt> and <tt>XXXCodeEmitter.cpp</tt> must include the
2336<tt>llvm/CodeGen/MachineCodeEmitter.h</tt> header file that defines the
2337<tt>MachineCodeEmitter</tt> class containing code for several callback functions
2338that write data (in bytes, words, strings, etc.) to the output stream.
2339</p>
2340
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2341</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2342
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2343<!-- ======================================================================= -->
2344<div class="doc_subsection">
2345 <a name="mce">Machine Code Emitter</a>
2346</div>
2347
2348<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2349
2350<p>
2351In <tt>XXXCodeEmitter.cpp</tt>, a target-specific of the <tt>Emitter</tt> class
2352is implemented as a function pass (subclass
2353of <tt>MachineFunctionPass</tt>). The target-specific implementation
2354of <tt>runOnMachineFunction</tt> (invoked by
2355<tt>runOnFunction</tt> in <tt>MachineFunctionPass</tt>) iterates through the
2356<tt>MachineBasicBlock</tt> calls <tt>emitInstruction</tt> to process each
2357instruction and emit binary code. <tt>emitInstruction</tt> is largely
2358implemented with case statements on the instruction types defined in
2359<tt>XXXInstrInfo.h</tt>. For example, in <tt>X86CodeEmitter.cpp</tt>,
2360the <tt>emitInstruction</tt> method is built around the following switch/case
2361statements:
2362</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2363
2364<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2365<pre>
2366switch (Desc-&gt;TSFlags &amp; X86::FormMask) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2367case X86II::Pseudo: // for not yet implemented instructions
2368 ... // or pseudo-instructions
2369 break;
2370case X86II::RawFrm: // for instructions with a fixed opcode value
2371 ...
2372 break;
2373case X86II::AddRegFrm: // for instructions that have one register operand
2374 ... // added to their opcode
2375 break;
2376case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
2377 ... // to specify a destination (register)
2378 break;
2379case X86II::MRMDestMem:// for instructions that use the Mod/RM byte
2380 ... // to specify a destination (memory)
2381 break;
2382case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte
2383 ... // to specify a source (register)
2384 break;
2385case X86II::MRMSrcMem: // for instructions that use the Mod/RM byte
2386 ... // to specify a source (memory)
2387 break;
2388case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
2389case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
2390case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
2391case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
2392 ...
2393 break;
2394case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on
2395case X86II::MRM2m: case X86II::MRM3m: // a MEMORY r/m operand and
2396case X86II::MRM4m: case X86II::MRM5m: // use the Mod/RM byte and a field
2397case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data
2398 ...
2399 break;
2400case X86II::MRMInitReg: // for instructions whose source and
2401 ... // destination are the same register
2402 break;
2403}
2404</pre>
2405</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2406
2407<p>
2408The implementations of these case statements often first emit the opcode and
2409then get the operand(s). Then depending upon the operand, helper methods may be
2410called to process the operand(s). For example, in <tt>X86CodeEmitter.cpp</tt>,
2411for the <tt>X86II::AddRegFrm</tt> case, the first data emitted
2412(by <tt>emitByte</tt>) is the opcode added to the register operand. Then an
2413object representing the machine operand, <tt>MO1</tt>, is extracted. The helper
2414methods such as <tt>isImmediate</tt>,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2415<tt>isGlobalAddress</tt>, <tt>isExternalSymbol</tt>, <tt>isConstantPoolIndex</tt>, and
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2416<tt>isJumpTableIndex</tt> determine the operand
2417type. (<tt>X86CodeEmitter.cpp</tt> also has private methods such
2418as <tt>emitConstant</tt>, <tt>emitGlobalAddress</tt>,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2419<tt>emitExternalSymbolAddress</tt>, <tt>emitConstPoolAddress</tt>,
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2420and <tt>emitJumpTableAddress</tt> that emit the data into the output stream.)
2421</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2422
2423<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2424<pre>
2425case X86II::AddRegFrm:
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2426 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
2427
2428 if (CurOp != NumOps) {
2429 const MachineOperand &amp;MO1 = MI.getOperand(CurOp++);
2430 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2431 if (MO1.isImmediate())
2432 emitConstant(MO1.getImm(), Size);
2433 else {
2434 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
2435 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
2436 if (Opcode == X86::MOV64ri)
2437 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
2438 if (MO1.isGlobalAddress()) {
2439 bool NeedStub = isa&lt;Function&gt;(MO1.getGlobal());
2440 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
2441 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
2442 NeedStub, isLazy);
2443 } else if (MO1.isExternalSymbol())
2444 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
2445 else if (MO1.isConstantPoolIndex())
2446 emitConstPoolAddress(MO1.getIndex(), rt);
2447 else if (MO1.isJumpTableIndex())
2448 emitJumpTableAddress(MO1.getIndex(), rt);
2449 }
2450 }
2451 break;
2452</pre>
2453</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2454
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2455<p>
2456In the previous example, <tt>XXXCodeEmitter.cpp</tt> uses the
2457variable <tt>rt</tt>, which is a RelocationType enum that may be used to
2458relocate addresses (for example, a global address with a PIC base offset). The
2459<tt>RelocationType</tt> enum for that target is defined in the short
2460target-specific <tt>XXXRelocations.h</tt> file. The <tt>RelocationType</tt> is used by
2461the <tt>relocate</tt> method defined in <tt>XXXJITInfo.cpp</tt> to rewrite
2462addresses for referenced global symbols.
2463</p>
2464
2465<p>
2466For example, <tt>X86Relocations.h</tt> specifies the following relocation types
2467for the X86 addresses. In all four cases, the relocated value is added to the
2468value already in memory. For <tt>reloc_pcrel_word</tt>
2469and <tt>reloc_picrel_word</tt>, there is an additional initial adjustment.
2470</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2471
2472<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2473<pre>
2474enum RelocationType {
2475 reloc_pcrel_word = 0, // add reloc value after adjusting for the PC loc
2476 reloc_picrel_word = 1, // add reloc value after adjusting for the PIC base
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2477 reloc_absolute_word = 2, // absolute relocation; no additional adjustment
2478 reloc_absolute_dword = 3 // absolute relocation; no additional adjustment
2479};
2480</pre>
2481</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2482
2483</div>
2484
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2485<!-- ======================================================================= -->
2486<div class="doc_subsection">
2487 <a name="targetJITInfo">Target JIT Info</a>
2488</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2489
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2490<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2491
2492<p>
2493<tt>XXXJITInfo.cpp</tt> implements the JIT interfaces for target-specific
2494code-generation activities, such as emitting machine code and stubs. At minimum,
2495a target-specific version of <tt>XXXJITInfo</tt> implements the following:
2496</p>
2497
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2498<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2499<li><tt>getLazyResolverFunction</tt> &mdash; Initializes the JIT, gives the
2500 target a function that is used for compilation.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2501
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2502<li><tt>emitFunctionStub</tt> &mdash; Returns a native function with a specified
2503 address for a callback function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2504
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2505<li><tt>relocate</tt> &mdash; Changes the addresses of referenced globals, based
2506 on relocation types.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2507
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2508<li>Callback function that are wrappers to a function stub that is used when the
2509 real target is not initially known.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2510</ul>
2511
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2512<p>
2513<tt>getLazyResolverFunction</tt> is generally trivial to implement. It makes the
2514incoming parameter as the global <tt>JITCompilerFunction</tt> and returns the
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2515callback function that will be used a function wrapper. For the Alpha target
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2516(in <tt>AlphaJITInfo.cpp</tt>), the <tt>getLazyResolverFunction</tt>
2517implementation is simply:
2518</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2519
2520<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2521<pre>
2522TargetJITInfo::LazyResolverFn AlphaJITInfo::getLazyResolverFunction(
2523 JITCompilerFn F) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2524 JITCompilerFunction = F;
2525 return AlphaCompilationCallback;
2526}
2527</pre>
2528</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2529
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2530<p>
2531For the X86 target, the <tt>getLazyResolverFunction</tt> implementation is a
2532little more complication, because it returns a different callback function for
2533processors with SSE instructions and XMM registers.
2534</p>
2535
2536<p>
2537The callback function initially saves and later restores the callee register
2538values, incoming arguments, and frame and return address. The callback function
2539needs low-level access to the registers or stack, so it is typically implemented
2540with assembler.
2541</p>
2542
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2543</div>
2544
2545<!-- *********************************************************************** -->
2546
2547<hr>
2548<address>
2549 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
Misha Brukman44408702008-12-11 17:34:48 +0000[diff] [blame]2550 src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2551 <a href="http://validator.w3.org/check/referer"><img
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Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2553
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2554 <a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]2555 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2556 <br>
2557 Last modified: $Date$
2558</address>
2559
2560</body>
2561</html>