Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 1 | //===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===// |
| 2 | // |
Chris Lattner | 33f53b5 | 2002-10-29 20:48:56 +0000 | [diff] [blame] | 3 | // This file contains the X86 implementation of the MachineInstrInfo class. |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 4 | // |
| 5 | //===----------------------------------------------------------------------===// |
| 6 | |
| 7 | #ifndef X86INSTRUCTIONINFO_H |
| 8 | #define X86INSTRUCTIONINFO_H |
| 9 | |
Chris Lattner | 9bbf439 | 2002-10-29 17:43:19 +0000 | [diff] [blame] | 10 | #include "llvm/Target/MachineInstrInfo.h" |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 11 | #include "X86RegisterInfo.h" |
| 12 | |
Chris Lattner | 9d17740 | 2002-10-30 01:09:34 +0000 | [diff] [blame] | 13 | /// X86II - This namespace holds all of the target specific flags that |
| 14 | /// instruction info tracks. |
| 15 | /// |
| 16 | namespace X86II { |
| 17 | enum { |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 18 | //===------------------------------------------------------------------===// |
| 19 | // Instruction types. These are the standard/most common forms for X86 |
| 20 | // instructions. |
| 21 | // |
| 22 | |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 23 | /// Raw - This form is for instructions that don't have any operands, so |
| 24 | /// they are just a fixed opcode value, like 'leave'. |
Chris Lattner | 4aff928 | 2002-12-02 21:40:58 +0000 | [diff] [blame] | 25 | RawFrm = 0, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 26 | |
| 27 | /// AddRegFrm - This form is used for instructions like 'push r32' that have |
| 28 | /// their one register operand added to their opcode. |
Chris Lattner | 4aff928 | 2002-12-02 21:40:58 +0000 | [diff] [blame] | 29 | AddRegFrm = 1, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 30 | |
| 31 | /// MRMDestReg - This form is used for instructions that use the Mod/RM byte |
| 32 | /// to specify a destination, which in this case is a register. |
| 33 | /// |
Chris Lattner | 4aff928 | 2002-12-02 21:40:58 +0000 | [diff] [blame] | 34 | MRMDestReg = 2, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 35 | |
| 36 | /// MRMDestMem - This form is used for instructions that use the Mod/RM byte |
| 37 | /// to specify a destination, which in this case is memory. |
| 38 | /// |
Chris Lattner | 4aff928 | 2002-12-02 21:40:58 +0000 | [diff] [blame] | 39 | MRMDestMem = 3, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 40 | |
| 41 | /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte |
| 42 | /// to specify a source, which in this case is a register. |
| 43 | /// |
Chris Lattner | 4aff928 | 2002-12-02 21:40:58 +0000 | [diff] [blame] | 44 | MRMSrcReg = 4, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 45 | |
| 46 | /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte |
| 47 | /// to specify a source, which in this case is memory. |
| 48 | /// |
Chris Lattner | 4aff928 | 2002-12-02 21:40:58 +0000 | [diff] [blame] | 49 | MRMSrcMem = 5, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 50 | |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 51 | /// MRMS[0-7][rm] - These forms are used to represent instructions that use |
| 52 | /// a Mod/RM byte, and use the middle field to hold extended opcode |
| 53 | /// information. In the intel manual these are represented as /0, /1, ... |
| 54 | /// |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 55 | |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 56 | // First, instructions that operate on a register r/m operand... |
| 57 | MRMS0r = 16, MRMS1r = 17, MRMS2r = 18, MRMS3r = 19, // Format /0 /1 /2 /3 |
| 58 | MRMS4r = 20, MRMS5r = 21, MRMS6r = 22, MRMS7r = 23, // Format /4 /5 /6 /7 |
| 59 | |
| 60 | // Next, instructions that operate on a memory r/m operand... |
| 61 | MRMS0m = 24, MRMS1m = 25, MRMS2m = 26, MRMS3m = 27, // Format /0 /1 /2 /3 |
| 62 | MRMS4m = 28, MRMS5m = 29, MRMS6m = 30, MRMS7m = 31, // Format /4 /5 /6 /7 |
| 63 | |
| 64 | FormMask = 31, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 65 | |
| 66 | //===------------------------------------------------------------------===// |
| 67 | // Actual flags... |
| 68 | |
Chris Lattner | 239dcfd | 2002-11-18 01:59:28 +0000 | [diff] [blame] | 69 | /// Void - Set if this instruction produces no value |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 70 | Void = 1 << 5, |
Chris Lattner | 239dcfd | 2002-11-18 01:59:28 +0000 | [diff] [blame] | 71 | |
| 72 | // TB - TwoByte - Set if this instruction has a two byte opcode, which |
| 73 | // starts with a 0x0F byte before the real opcode. |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 74 | TB = 1 << 6, |
Chris Lattner | 11e53e3 | 2002-11-21 01:32:55 +0000 | [diff] [blame] | 75 | |
Chris Lattner | 15207f4 | 2002-11-21 22:48:01 +0000 | [diff] [blame] | 76 | // FIXME: There are several more two byte opcode escapes: D8-DF |
| 77 | // Handle this. |
| 78 | |
Chris Lattner | 11e53e3 | 2002-11-21 01:32:55 +0000 | [diff] [blame] | 79 | // OpSize - Set if this instruction requires an operand size prefix (0x66), |
| 80 | // which most often indicates that the instruction operates on 16 bit data |
| 81 | // instead of 32 bit data. |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 82 | OpSize = 1 << 7, |
Brian Gaeke | 86764d7 | 2002-12-05 08:30:40 +0000 | [diff] [blame^] | 83 | |
| 84 | // This three-bit field describes the size of a memory operand. |
| 85 | // I'm just being paranoid not using the zero value; there's |
| 86 | // probably no reason you couldn't use it. |
| 87 | MemArg8 = 0x1 << 8, |
| 88 | MemArg16 = 0x2 << 8, |
| 89 | MemArg32 = 0x3 << 8, |
| 90 | MemArg64 = 0x4 << 8, |
| 91 | MemArg80 = 0x5 << 8, |
| 92 | MemArg128 = 0x6 << 8, |
| 93 | MemArgMask = 0x7 << 8, |
Chris Lattner | 9d17740 | 2002-10-30 01:09:34 +0000 | [diff] [blame] | 94 | }; |
| 95 | } |
| 96 | |
Chris Lattner | 055c965 | 2002-10-29 21:05:24 +0000 | [diff] [blame] | 97 | class X86InstrInfo : public MachineInstrInfo { |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 98 | const X86RegisterInfo RI; |
| 99 | public: |
Chris Lattner | 055c965 | 2002-10-29 21:05:24 +0000 | [diff] [blame] | 100 | X86InstrInfo(); |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 101 | |
Chris Lattner | 33f53b5 | 2002-10-29 20:48:56 +0000 | [diff] [blame] | 102 | /// getRegisterInfo - MachineInstrInfo is a superset of MRegister info. As |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 103 | /// such, whenever a client has an instance of instruction info, it should |
| 104 | /// always be able to get register info as well (through this method). |
| 105 | /// |
| 106 | virtual const MRegisterInfo &getRegisterInfo() const { return RI; } |
| 107 | |
Chris Lattner | dbb61c6 | 2002-11-17 22:53:13 +0000 | [diff] [blame] | 108 | /// print - Print out an x86 instruction in intel syntax |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 109 | /// |
Chris Lattner | 927dd09 | 2002-11-17 23:20:37 +0000 | [diff] [blame] | 110 | virtual void print(const MachineInstr *MI, std::ostream &O, |
| 111 | const TargetMachine &TM) const; |
Chris Lattner | 9bbf439 | 2002-10-29 17:43:19 +0000 | [diff] [blame] | 112 | |
Chris Lattner | f21dfcd | 2002-11-18 06:56:24 +0000 | [diff] [blame] | 113 | // getBaseOpcodeFor - This function returns the "base" X86 opcode for the |
| 114 | // specified opcode number. |
| 115 | // |
| 116 | unsigned char getBaseOpcodeFor(unsigned Opcode) const; |
| 117 | |
| 118 | |
Chris Lattner | 9bbf439 | 2002-10-29 17:43:19 +0000 | [diff] [blame] | 119 | |
| 120 | //===--------------------------------------------------------------------===// |
| 121 | // |
| 122 | // These are stubs for pure virtual methods that should be factored out of |
| 123 | // MachineInstrInfo. We never call them, we don't want them, but we need |
| 124 | // stubs so that we can instatiate our class. |
| 125 | // |
| 126 | MachineOpCode getNOPOpCode() const { abort(); } |
| 127 | void CreateCodeToLoadConst(const TargetMachine& target, Function* F, |
| 128 | Value *V, Instruction *I, |
| 129 | std::vector<MachineInstr*>& mvec, |
| 130 | MachineCodeForInstruction& mcfi) const { abort(); } |
| 131 | void CreateCodeToCopyIntToFloat(const TargetMachine& target, |
| 132 | Function* F, Value* val, Instruction* dest, |
| 133 | std::vector<MachineInstr*>& mvec, |
| 134 | MachineCodeForInstruction& mcfi) const { |
| 135 | abort(); |
| 136 | } |
| 137 | void CreateCodeToCopyFloatToInt(const TargetMachine& target, Function* F, |
| 138 | Value* val, Instruction* dest, |
| 139 | std::vector<MachineInstr*>& mvec, |
| 140 | MachineCodeForInstruction& mcfi)const { |
| 141 | abort(); |
| 142 | } |
| 143 | void CreateCopyInstructionsByType(const TargetMachine& target, |
| 144 | Function* F, Value* src, |
| 145 | Instruction* dest, |
| 146 | std::vector<MachineInstr*>& mvec, |
| 147 | MachineCodeForInstruction& mcfi)const { |
| 148 | abort(); |
| 149 | } |
| 150 | |
| 151 | void CreateSignExtensionInstructions(const TargetMachine& target, |
| 152 | Function* F, Value* srcVal, |
| 153 | Value* destVal, unsigned numLowBits, |
| 154 | std::vector<MachineInstr*>& mvec, |
| 155 | MachineCodeForInstruction& mcfi) const { |
| 156 | abort(); |
| 157 | } |
| 158 | |
| 159 | void CreateZeroExtensionInstructions(const TargetMachine& target, |
| 160 | Function* F, Value* srcVal, |
| 161 | Value* destVal, unsigned srcSizeInBits, |
| 162 | std::vector<MachineInstr*>& mvec, |
| 163 | MachineCodeForInstruction& mcfi) const { |
| 164 | abort(); |
| 165 | } |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | |
| 169 | #endif |