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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 19aa2b5015205456b42c426ff2559e9b930e285c / . / lib / Target / PowerPC / PPC.td
blob: ca0aa331ca3a38d4d00d00208c4011f33ad49587 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]7//
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
Evan Cheng027fdbe2008-11-24 07:34:46 +0000[diff] [blame]16include "llvm/Target/Target.td"
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]17
18//===----------------------------------------------------------------------===//
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]19// PowerPC Subtarget features.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]20//
21
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]22//===----------------------------------------------------------------------===//
23// CPU Directives //
24//===----------------------------------------------------------------------===//
25
Hal Finkelc6d08f12011-10-17 04:03:49 +0000[diff] [blame]26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]37def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]38
Chris Lattnera7a58542006-06-16 17:34:12 +0000[diff] [blame]39def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]40 "Enable 64-bit instructions">;
Chris Lattnera7a58542006-06-16 17:34:12 +0000[diff] [blame]41def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
42 "Enable 64-bit registers usage for ppc32 [beta]">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]43def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]44 "Enable Altivec instructions">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]45def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]46 "Enable GPUL instructions">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]47def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
Hal Finkel8ee53e22011-10-14 18:54:13 +0000[diff] [blame]48 "Enable the fsqrt instruction">;
Chris Lattnerbf751e22006-02-28 07:08:22 +0000[diff] [blame]49def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
Hal Finkel8ee53e22011-10-14 18:54:13 +0000[diff] [blame]50 "Enable the stfiwx instruction">;
Hal Finkelc6d08f12011-10-17 04:03:49 +0000[diff] [blame]51def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
52 "Enable Book E instructions">;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]53
54//===----------------------------------------------------------------------===//
Chris Lattnerc8d28892005-10-23 22:08:13 +0000[diff] [blame]55// Register File Description
56//===----------------------------------------------------------------------===//
57
58include "PPCRegisterInfo.td"
59include "PPCSchedule.td"
60include "PPCInstrInfo.td"
61
62//===----------------------------------------------------------------------===//
63// PowerPC processors supported.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]64//
65
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]66def : Processor<"generic", G3Itineraries, [Directive32]>;
Hal Finkelc6d08f12011-10-17 04:03:49 +0000[diff] [blame]67def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>;
68def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]69def : Processor<"601", G3Itineraries, [Directive601]>;
70def : Processor<"602", G3Itineraries, [Directive602]>;
71def : Processor<"603", G3Itineraries, [Directive603]>;
72def : Processor<"603e", G3Itineraries, [Directive603]>;
73def : Processor<"603ev", G3Itineraries, [Directive603]>;
74def : Processor<"604", G3Itineraries, [Directive604]>;
75def : Processor<"604e", G3Itineraries, [Directive604]>;
76def : Processor<"620", G3Itineraries, [Directive620]>;
77def : Processor<"g3", G3Itineraries, [Directive7400]>;
78def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
79def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
80def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
81def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
82def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]83def : Processor<"970", G5Itineraries,
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]84 [Directive970, FeatureAltivec,
85 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]86 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]87def : Processor<"g5", G5Itineraries,
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]88 [Directive970, FeatureAltivec,
89 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
90 Feature64Bit /*, Feature64BitRegs */]>;
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]91def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
92 FeatureFSqrt, FeatureSTFIWX,
93 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]94def : Processor<"ppc", G3Itineraries, [Directive32]>;
95def : Processor<"ppc64", G5Itineraries,
96 [Directive64, FeatureAltivec,
97 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]98 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]99
100
Chris Lattnerb9a7bea2007-03-06 00:59:59 +0000[diff] [blame]101//===----------------------------------------------------------------------===//
102// Calling Conventions
103//===----------------------------------------------------------------------===//
104
105include "PPCCallingConv.td"
106
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]107def PPCInstrInfo : InstrInfo {
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]108 let isLittleEndianEncoding = 1;
109}
110
Chris Lattner84a04ad2010-11-15 03:53:53 +0000[diff] [blame]111def PPCAsmWriter : AsmWriter {
112 string AsmWriterClassName = "InstPrinter";
113 bit isMCAsmWriter = 1;
114}
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]115
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]116def PPC : Target {
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]117 // Information about the instructions.
118 let InstructionSet = PPCInstrInfo;
Chris Lattner84a04ad2010-11-15 03:53:53 +0000[diff] [blame]119
120 let AssemblyWriters = [PPCAsmWriter];
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]121}