David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 1 | //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===// |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 10 | // This file contains the Thumb-1 implementation of the TargetInstrInfo class. |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Evan Cheng | b9803a8 | 2009-11-06 23:52:48 +0000 | [diff] [blame^] | 14 | #include "Thumb1InstrInfo.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 15 | #include "ARM.h" |
Evan Cheng | b9803a8 | 2009-11-06 23:52:48 +0000 | [diff] [blame^] | 16 | #include "ARMConstantPoolValue.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 17 | #include "ARMGenInstrInfo.inc" |
| 18 | #include "ARMMachineFunctionInfo.h" |
Evan Cheng | b9803a8 | 2009-11-06 23:52:48 +0000 | [diff] [blame^] | 19 | #include "llvm/GlobalValue.h" |
| 20 | #include "llvm/CodeGen/MachineConstantPool.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 21 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 22 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineMemOperand.h" |
| 24 | #include "llvm/CodeGen/PseudoSourceValue.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 25 | #include "llvm/ADT/SmallVector.h" |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 26 | #include "Thumb1InstrInfo.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 27 | |
| 28 | using namespace llvm; |
| 29 | |
Anton Korobeynikov | f95215f | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 30 | Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) |
| 31 | : ARMBaseInstrInfo(STI), RI(*this, STI) { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 32 | } |
| 33 | |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 34 | unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 35 | return 0; |
| 36 | } |
| 37 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 38 | bool |
| 39 | Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { |
| 40 | if (MBB.empty()) return false; |
| 41 | |
| 42 | switch (MBB.back().getOpcode()) { |
| 43 | case ARM::tBX_RET: |
| 44 | case ARM::tBX_RET_vararg: |
| 45 | case ARM::tPOP_RET: |
| 46 | case ARM::tB: |
Bob Wilson | 8d4de5a | 2009-10-28 18:26:41 +0000 | [diff] [blame] | 47 | case ARM::tBRIND: |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 48 | case ARM::tBR_JTr: |
| 49 | return true; |
| 50 | default: |
| 51 | break; |
| 52 | } |
| 53 | |
| 54 | return false; |
| 55 | } |
| 56 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 57 | bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 58 | MachineBasicBlock::iterator I, |
| 59 | unsigned DestReg, unsigned SrcReg, |
| 60 | const TargetRegisterClass *DestRC, |
| 61 | const TargetRegisterClass *SrcRC) const { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 62 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 63 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 64 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 65 | if (DestRC == ARM::GPRRegisterClass) { |
| 66 | if (SrcRC == ARM::GPRRegisterClass) { |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 67 | BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 68 | return true; |
| 69 | } else if (SrcRC == ARM::tGPRRegisterClass) { |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 70 | BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 71 | return true; |
| 72 | } |
| 73 | } else if (DestRC == ARM::tGPRRegisterClass) { |
| 74 | if (SrcRC == ARM::GPRRegisterClass) { |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 75 | BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 76 | return true; |
| 77 | } else if (SrcRC == ARM::tGPRRegisterClass) { |
| 78 | BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg); |
| 79 | return true; |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | return false; |
| 84 | } |
| 85 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 86 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 87 | canFoldMemoryOperand(const MachineInstr *MI, |
| 88 | const SmallVectorImpl<unsigned> &Ops) const { |
| 89 | if (Ops.size() != 1) return false; |
| 90 | |
| 91 | unsigned OpNum = Ops[0]; |
| 92 | unsigned Opc = MI->getOpcode(); |
| 93 | switch (Opc) { |
| 94 | default: break; |
| 95 | case ARM::tMOVr: |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 96 | case ARM::tMOVtgpr2gpr: |
| 97 | case ARM::tMOVgpr2tgpr: |
| 98 | case ARM::tMOVgpr2gpr: { |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 99 | if (OpNum == 0) { // move -> store |
| 100 | unsigned SrcReg = MI->getOperand(1).getReg(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 101 | if (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 102 | !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 103 | // tSpill cannot take a high register operand. |
| 104 | return false; |
| 105 | } else { // move -> load |
| 106 | unsigned DstReg = MI->getOperand(0).getReg(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 107 | if (TargetRegisterInfo::isPhysicalRegister(DstReg) && |
| 108 | !isARMLowRegister(DstReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 109 | // tRestore cannot target a high register operand. |
| 110 | return false; |
| 111 | } |
| 112 | return true; |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | return false; |
| 117 | } |
| 118 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 119 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 120 | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 121 | unsigned SrcReg, bool isKill, int FI, |
| 122 | const TargetRegisterClass *RC) const { |
| 123 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 124 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 125 | |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 126 | assert((RC == ARM::tGPRRegisterClass || |
| 127 | (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 128 | isARMLowRegister(SrcReg))) && "Unknown regclass!"); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 129 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 130 | if (RC == ARM::tGPRRegisterClass) { |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 131 | MachineFunction &MF = *MBB.getParent(); |
| 132 | MachineFrameInfo &MFI = *MF.getFrameInfo(); |
| 133 | MachineMemOperand *MMO = |
| 134 | MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), |
| 135 | MachineMemOperand::MOStore, 0, |
| 136 | MFI.getObjectSize(FI), |
| 137 | MFI.getObjectAlignment(FI)); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 138 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill)) |
| 139 | .addReg(SrcReg, getKillRegState(isKill)) |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 140 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 141 | } |
| 142 | } |
| 143 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 144 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 145 | loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 146 | unsigned DestReg, int FI, |
| 147 | const TargetRegisterClass *RC) const { |
| 148 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 149 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 150 | |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 151 | assert((RC == ARM::tGPRRegisterClass || |
| 152 | (TargetRegisterInfo::isPhysicalRegister(DestReg) && |
| 153 | isARMLowRegister(DestReg))) && "Unknown regclass!"); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 154 | |
| 155 | if (RC == ARM::tGPRRegisterClass) { |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 156 | MachineFunction &MF = *MBB.getParent(); |
| 157 | MachineFrameInfo &MFI = *MF.getFrameInfo(); |
| 158 | MachineMemOperand *MMO = |
| 159 | MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), |
| 160 | MachineMemOperand::MOLoad, 0, |
| 161 | MFI.getObjectSize(FI), |
| 162 | MFI.getObjectAlignment(FI)); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 163 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 164 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 165 | } |
| 166 | } |
| 167 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 168 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 169 | spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 170 | MachineBasicBlock::iterator MI, |
| 171 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 172 | if (CSI.empty()) |
| 173 | return false; |
| 174 | |
| 175 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 176 | if (MI != MBB.end()) DL = MI->getDebugLoc(); |
| 177 | |
| 178 | MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 179 | AddDefaultPred(MIB); |
Evan Cheng | 8925979 | 2009-10-02 05:03:07 +0000 | [diff] [blame] | 180 | MIB.addReg(0); // No write back. |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 181 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 182 | unsigned Reg = CSI[i-1].getReg(); |
| 183 | // Add the callee-saved register as live-in. It's killed at the spill. |
| 184 | MBB.addLiveIn(Reg); |
| 185 | MIB.addReg(Reg, RegState::Kill); |
| 186 | } |
| 187 | return true; |
| 188 | } |
| 189 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 190 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 191 | restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 192 | MachineBasicBlock::iterator MI, |
| 193 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 194 | MachineFunction &MF = *MBB.getParent(); |
| 195 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 196 | if (CSI.empty()) |
| 197 | return false; |
| 198 | |
| 199 | bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 200 | DebugLoc DL = MI->getDebugLoc(); |
| 201 | MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP)); |
| 202 | AddDefaultPred(MIB); |
Evan Cheng | 10469f8 | 2009-10-01 20:54:53 +0000 | [diff] [blame] | 203 | MIB.addReg(0); // No write back. |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 204 | |
| 205 | bool NumRegs = 0; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 206 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 207 | unsigned Reg = CSI[i-1].getReg(); |
| 208 | if (Reg == ARM::LR) { |
| 209 | // Special epilogue for vararg functions. See emitEpilogue |
| 210 | if (isVarArg) |
| 211 | continue; |
| 212 | Reg = ARM::PC; |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 213 | (*MIB).setDesc(get(ARM::tPOP_RET)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 214 | MI = MBB.erase(MI); |
| 215 | } |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 216 | MIB.addReg(Reg, getDefRegState(true)); |
| 217 | ++NumRegs; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | // It's illegal to emit pop instruction without operands. |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 221 | if (NumRegs) |
| 222 | MBB.insert(MI, &*MIB); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 223 | |
| 224 | return true; |
| 225 | } |
| 226 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 227 | MachineInstr *Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 228 | foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, |
| 229 | const SmallVectorImpl<unsigned> &Ops, int FI) const { |
| 230 | if (Ops.size() != 1) return NULL; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 231 | |
| 232 | unsigned OpNum = Ops[0]; |
| 233 | unsigned Opc = MI->getOpcode(); |
| 234 | MachineInstr *NewMI = NULL; |
| 235 | switch (Opc) { |
| 236 | default: break; |
| 237 | case ARM::tMOVr: |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 238 | case ARM::tMOVtgpr2gpr: |
| 239 | case ARM::tMOVgpr2tgpr: |
| 240 | case ARM::tMOVgpr2gpr: { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 241 | if (OpNum == 0) { // move -> store |
| 242 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 243 | bool isKill = MI->getOperand(1).isKill(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 244 | if (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 245 | !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 246 | // tSpill cannot take a high register operand. |
| 247 | break; |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 248 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) |
| 249 | .addReg(SrcReg, getKillRegState(isKill)) |
| 250 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 251 | } else { // move -> load |
| 252 | unsigned DstReg = MI->getOperand(0).getReg(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 253 | if (TargetRegisterInfo::isPhysicalRegister(DstReg) && |
| 254 | !isARMLowRegister(DstReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 255 | // tRestore cannot target a high register operand. |
| 256 | break; |
| 257 | bool isDead = MI->getOperand(0).isDead(); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 258 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) |
| 259 | .addReg(DstReg, |
| 260 | RegState::Define | getDeadRegState(isDead)) |
| 261 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 262 | } |
| 263 | break; |
| 264 | } |
| 265 | } |
| 266 | |
| 267 | return NewMI; |
| 268 | } |
Evan Cheng | b9803a8 | 2009-11-06 23:52:48 +0000 | [diff] [blame^] | 269 | |
| 270 | void Thumb1InstrInfo::reMaterialize(MachineBasicBlock &MBB, |
| 271 | MachineBasicBlock::iterator I, |
| 272 | unsigned DestReg, unsigned SubIdx, |
| 273 | const MachineInstr *Orig) const { |
| 274 | DebugLoc dl = Orig->getDebugLoc(); |
| 275 | unsigned Opcode = Orig->getOpcode(); |
| 276 | switch (Opcode) { |
| 277 | default: { |
| 278 | MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); |
| 279 | MI->getOperand(0).setReg(DestReg); |
| 280 | MBB.insert(I, MI); |
| 281 | break; |
| 282 | } |
| 283 | case ARM::tLDRpci_pic: { |
| 284 | MachineFunction &MF = *MBB.getParent(); |
| 285 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 286 | MachineConstantPool *MCP = MF.getConstantPool(); |
| 287 | unsigned CPI = Orig->getOperand(1).getIndex(); |
| 288 | const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; |
| 289 | assert(MCPE.isMachineConstantPoolEntry() && |
| 290 | "Expecting a machine constantpool entry!"); |
| 291 | ARMConstantPoolValue *ACPV = |
| 292 | static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); |
| 293 | assert(ACPV->isGlobalValue() && "Expecting a GV!"); |
| 294 | unsigned PCLabelId = AFI->createConstPoolEntryUId(); |
| 295 | ARMConstantPoolValue *NewCPV = |
| 296 | new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, ARMCP::CPValue, 4); |
| 297 | CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); |
| 298 | MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), |
| 299 | DestReg) |
| 300 | .addConstantPoolIndex(CPI).addImm(PCLabelId); |
| 301 | (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); |
| 302 | break; |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | MachineInstr *NewMI = prior(I); |
| 307 | NewMI->getOperand(0).setSubReg(SubIdx); |
| 308 | } |
| 309 | |