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David Goodwinb50ea5c2009-07-02 22:18:33 +00001//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
Anton Korobeynikovd49ea772009-06-26 21:28:53 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
David Goodwinb50ea5c2009-07-02 22:18:33 +000010// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000011//
12//===----------------------------------------------------------------------===//
13
Evan Chengb9803a82009-11-06 23:52:48 +000014#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000015#include "ARM.h"
Evan Chengb9803a82009-11-06 23:52:48 +000016#include "ARMConstantPoolValue.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000017#include "ARMGenInstrInfo.inc"
18#include "ARMMachineFunctionInfo.h"
Evan Chengb9803a82009-11-06 23:52:48 +000019#include "llvm/GlobalValue.h"
20#include "llvm/CodeGen/MachineConstantPool.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000021#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
Evan Chenge3ce8aa2009-11-01 22:04:35 +000023#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/PseudoSourceValue.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000025#include "llvm/ADT/SmallVector.h"
David Goodwinb50ea5c2009-07-02 22:18:33 +000026#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000027
28using namespace llvm;
29
Anton Korobeynikovf95215f2009-11-02 00:10:38 +000030Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
31 : ARMBaseInstrInfo(STI), RI(*this, STI) {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000032}
33
Evan Cheng446c4282009-07-11 06:43:01 +000034unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
David Goodwin334c2642009-07-08 16:09:28 +000035 return 0;
36}
37
David Goodwin334c2642009-07-08 16:09:28 +000038bool
39Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
40 if (MBB.empty()) return false;
41
42 switch (MBB.back().getOpcode()) {
43 case ARM::tBX_RET:
44 case ARM::tBX_RET_vararg:
45 case ARM::tPOP_RET:
46 case ARM::tB:
Bob Wilson8d4de5a2009-10-28 18:26:41 +000047 case ARM::tBRIND:
David Goodwin334c2642009-07-08 16:09:28 +000048 case ARM::tBR_JTr:
49 return true;
50 default:
51 break;
52 }
53
54 return false;
55}
56
David Goodwinb50ea5c2009-07-02 22:18:33 +000057bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator I,
59 unsigned DestReg, unsigned SrcReg,
60 const TargetRegisterClass *DestRC,
61 const TargetRegisterClass *SrcRC) const {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000062 DebugLoc DL = DebugLoc::getUnknownLoc();
63 if (I != MBB.end()) DL = I->getDebugLoc();
64
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000065 if (DestRC == ARM::GPRRegisterClass) {
66 if (SrcRC == ARM::GPRRegisterClass) {
Evan Chengd8336062009-07-26 23:59:01 +000067 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000068 return true;
69 } else if (SrcRC == ARM::tGPRRegisterClass) {
Evan Chengd8336062009-07-26 23:59:01 +000070 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000071 return true;
72 }
73 } else if (DestRC == ARM::tGPRRegisterClass) {
74 if (SrcRC == ARM::GPRRegisterClass) {
Evan Chengd8336062009-07-26 23:59:01 +000075 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000076 return true;
77 } else if (SrcRC == ARM::tGPRRegisterClass) {
78 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
79 return true;
80 }
81 }
82
83 return false;
84}
85
David Goodwinb50ea5c2009-07-02 22:18:33 +000086bool Thumb1InstrInfo::
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000087canFoldMemoryOperand(const MachineInstr *MI,
88 const SmallVectorImpl<unsigned> &Ops) const {
89 if (Ops.size() != 1) return false;
90
91 unsigned OpNum = Ops[0];
92 unsigned Opc = MI->getOpcode();
93 switch (Opc) {
94 default: break;
95 case ARM::tMOVr:
Evan Chengd8336062009-07-26 23:59:01 +000096 case ARM::tMOVtgpr2gpr:
97 case ARM::tMOVgpr2tgpr:
98 case ARM::tMOVgpr2gpr: {
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000099 if (OpNum == 0) { // move -> store
100 unsigned SrcReg = MI->getOperand(1).getReg();
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000101 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
102 !isARMLowRegister(SrcReg))
Anton Korobeynikova98cbc52009-06-27 12:16:40 +0000103 // tSpill cannot take a high register operand.
104 return false;
105 } else { // move -> load
106 unsigned DstReg = MI->getOperand(0).getReg();
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000107 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
108 !isARMLowRegister(DstReg))
Anton Korobeynikova98cbc52009-06-27 12:16:40 +0000109 // tRestore cannot target a high register operand.
110 return false;
111 }
112 return true;
113 }
114 }
115
116 return false;
117}
118
David Goodwinb50ea5c2009-07-02 22:18:33 +0000119void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000120storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
121 unsigned SrcReg, bool isKill, int FI,
122 const TargetRegisterClass *RC) const {
123 DebugLoc DL = DebugLoc::getUnknownLoc();
124 if (I != MBB.end()) DL = I->getDebugLoc();
125
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000126 assert((RC == ARM::tGPRRegisterClass ||
127 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
128 isARMLowRegister(SrcReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000129
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000130 if (RC == ARM::tGPRRegisterClass) {
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000131 MachineFunction &MF = *MBB.getParent();
132 MachineFrameInfo &MFI = *MF.getFrameInfo();
133 MachineMemOperand *MMO =
134 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
135 MachineMemOperand::MOStore, 0,
136 MFI.getObjectSize(FI),
137 MFI.getObjectAlignment(FI));
Evan Cheng446c4282009-07-11 06:43:01 +0000138 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
139 .addReg(SrcReg, getKillRegState(isKill))
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000140 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000141 }
142}
143
David Goodwinb50ea5c2009-07-02 22:18:33 +0000144void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000145loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
146 unsigned DestReg, int FI,
147 const TargetRegisterClass *RC) const {
148 DebugLoc DL = DebugLoc::getUnknownLoc();
149 if (I != MBB.end()) DL = I->getDebugLoc();
150
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000151 assert((RC == ARM::tGPRRegisterClass ||
152 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
153 isARMLowRegister(DestReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000154
155 if (RC == ARM::tGPRRegisterClass) {
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000156 MachineFunction &MF = *MBB.getParent();
157 MachineFrameInfo &MFI = *MF.getFrameInfo();
158 MachineMemOperand *MMO =
159 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
160 MachineMemOperand::MOLoad, 0,
161 MFI.getObjectSize(FI),
162 MFI.getObjectAlignment(FI));
Evan Cheng446c4282009-07-11 06:43:01 +0000163 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000164 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000165 }
166}
167
David Goodwinb50ea5c2009-07-02 22:18:33 +0000168bool Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000169spillCalleeSavedRegisters(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MI,
171 const std::vector<CalleeSavedInfo> &CSI) const {
172 if (CSI.empty())
173 return false;
174
175 DebugLoc DL = DebugLoc::getUnknownLoc();
176 if (MI != MBB.end()) DL = MI->getDebugLoc();
177
178 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
Evan Cheng4b322e52009-08-11 21:11:32 +0000179 AddDefaultPred(MIB);
Evan Cheng89259792009-10-02 05:03:07 +0000180 MIB.addReg(0); // No write back.
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000181 for (unsigned i = CSI.size(); i != 0; --i) {
182 unsigned Reg = CSI[i-1].getReg();
183 // Add the callee-saved register as live-in. It's killed at the spill.
184 MBB.addLiveIn(Reg);
185 MIB.addReg(Reg, RegState::Kill);
186 }
187 return true;
188}
189
David Goodwinb50ea5c2009-07-02 22:18:33 +0000190bool Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000191restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
192 MachineBasicBlock::iterator MI,
193 const std::vector<CalleeSavedInfo> &CSI) const {
194 MachineFunction &MF = *MBB.getParent();
195 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
196 if (CSI.empty())
197 return false;
198
199 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
Evan Cheng4b322e52009-08-11 21:11:32 +0000200 DebugLoc DL = MI->getDebugLoc();
201 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
202 AddDefaultPred(MIB);
Evan Cheng10469f82009-10-01 20:54:53 +0000203 MIB.addReg(0); // No write back.
Evan Cheng4b322e52009-08-11 21:11:32 +0000204
205 bool NumRegs = 0;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000206 for (unsigned i = CSI.size(); i != 0; --i) {
207 unsigned Reg = CSI[i-1].getReg();
208 if (Reg == ARM::LR) {
209 // Special epilogue for vararg functions. See emitEpilogue
210 if (isVarArg)
211 continue;
212 Reg = ARM::PC;
Evan Cheng4b322e52009-08-11 21:11:32 +0000213 (*MIB).setDesc(get(ARM::tPOP_RET));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000214 MI = MBB.erase(MI);
215 }
Evan Cheng4b322e52009-08-11 21:11:32 +0000216 MIB.addReg(Reg, getDefRegState(true));
217 ++NumRegs;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000218 }
219
220 // It's illegal to emit pop instruction without operands.
Evan Cheng4b322e52009-08-11 21:11:32 +0000221 if (NumRegs)
222 MBB.insert(MI, &*MIB);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000223
224 return true;
225}
226
David Goodwinb50ea5c2009-07-02 22:18:33 +0000227MachineInstr *Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000228foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
229 const SmallVectorImpl<unsigned> &Ops, int FI) const {
230 if (Ops.size() != 1) return NULL;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000231
232 unsigned OpNum = Ops[0];
233 unsigned Opc = MI->getOpcode();
234 MachineInstr *NewMI = NULL;
235 switch (Opc) {
236 default: break;
237 case ARM::tMOVr:
Evan Chengd8336062009-07-26 23:59:01 +0000238 case ARM::tMOVtgpr2gpr:
239 case ARM::tMOVgpr2tgpr:
240 case ARM::tMOVgpr2gpr: {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000241 if (OpNum == 0) { // move -> store
242 unsigned SrcReg = MI->getOperand(1).getReg();
243 bool isKill = MI->getOperand(1).isKill();
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000244 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
245 !isARMLowRegister(SrcReg))
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000246 // tSpill cannot take a high register operand.
247 break;
Evan Cheng446c4282009-07-11 06:43:01 +0000248 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
249 .addReg(SrcReg, getKillRegState(isKill))
250 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000251 } else { // move -> load
252 unsigned DstReg = MI->getOperand(0).getReg();
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000253 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
254 !isARMLowRegister(DstReg))
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000255 // tRestore cannot target a high register operand.
256 break;
257 bool isDead = MI->getOperand(0).isDead();
Evan Cheng446c4282009-07-11 06:43:01 +0000258 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
259 .addReg(DstReg,
260 RegState::Define | getDeadRegState(isDead))
261 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000262 }
263 break;
264 }
265 }
266
267 return NewMI;
268}
Evan Chengb9803a82009-11-06 23:52:48 +0000269
270void Thumb1InstrInfo::reMaterialize(MachineBasicBlock &MBB,
271 MachineBasicBlock::iterator I,
272 unsigned DestReg, unsigned SubIdx,
273 const MachineInstr *Orig) const {
274 DebugLoc dl = Orig->getDebugLoc();
275 unsigned Opcode = Orig->getOpcode();
276 switch (Opcode) {
277 default: {
278 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
279 MI->getOperand(0).setReg(DestReg);
280 MBB.insert(I, MI);
281 break;
282 }
283 case ARM::tLDRpci_pic: {
284 MachineFunction &MF = *MBB.getParent();
285 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
286 MachineConstantPool *MCP = MF.getConstantPool();
287 unsigned CPI = Orig->getOperand(1).getIndex();
288 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
289 assert(MCPE.isMachineConstantPoolEntry() &&
290 "Expecting a machine constantpool entry!");
291 ARMConstantPoolValue *ACPV =
292 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
293 assert(ACPV->isGlobalValue() && "Expecting a GV!");
294 unsigned PCLabelId = AFI->createConstPoolEntryUId();
295 ARMConstantPoolValue *NewCPV =
296 new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, ARMCP::CPValue, 4);
297 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
298 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
299 DestReg)
300 .addConstantPoolIndex(CPI).addImm(PCLabelId);
301 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
302 break;
303 }
304 }
305
306 MachineInstr *NewMI = prior(I);
307 NewMI->getOperand(0).setSubReg(SubIdx);
308}
309