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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / ba4733d901b1c2b994f66707657342b8c81c92bc / . / lib / Target / PowerPC / PPC.td
blob: 6d23657512bd35e94f01fc5da924a1ee87613775 [file] [log] [blame]
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]1//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
16include "../Target.td"
17
18//===----------------------------------------------------------------------===//
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]19// PowerPC Subtarget features.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]20//
21
Chris Lattnera7a58542006-06-16 17:34:12 +0000[diff] [blame]22def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]23 "Enable 64-bit instructions">;
Chris Lattnera7a58542006-06-16 17:34:12 +0000[diff] [blame]24def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
25 "Enable 64-bit registers usage for ppc32 [beta]">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]26def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]27 "Enable Altivec instructions">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]28def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]29 "Enable GPUL instructions">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]30def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]31 "Enable the fsqrt instruction">;
Chris Lattnerbf751e22006-02-28 07:08:22 +0000[diff] [blame]32def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
33 "Enable the stfiwx instruction">;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]34
35//===----------------------------------------------------------------------===//
Chris Lattnerc8d28892005-10-23 22:08:13 +0000[diff] [blame]36// Register File Description
37//===----------------------------------------------------------------------===//
38
39include "PPCRegisterInfo.td"
40include "PPCSchedule.td"
41include "PPCInstrInfo.td"
42
43//===----------------------------------------------------------------------===//
44// PowerPC processors supported.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]45//
46
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]47def : Processor<"generic", G3Itineraries, []>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]48def : Processor<"601", G3Itineraries, []>;
49def : Processor<"602", G3Itineraries, []>;
50def : Processor<"603", G3Itineraries, []>;
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]51def : Processor<"603e", G3Itineraries, []>;
52def : Processor<"603ev", G3Itineraries, []>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]53def : Processor<"604", G3Itineraries, []>;
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]54def : Processor<"604e", G3Itineraries, []>;
55def : Processor<"620", G3Itineraries, []>;
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]56def : Processor<"g3", G3Itineraries, []>;
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]57def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]58def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]59def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]60def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]61def : Processor<"750", G3Itineraries, []>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]62def : Processor<"970", G5Itineraries,
Chris Lattnerbf751e22006-02-28 07:08:22 +0000[diff] [blame]63 [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]64 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]65def : Processor<"g5", G5Itineraries,
Chris Lattnerbf751e22006-02-28 07:08:22 +0000[diff] [blame]66 [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]67 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]68
69
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]70def PPCInstrInfo : InstrInfo {
71 // Define how we want to layout our TargetSpecific information field... This
72 // should be kept up-to-date with the fields in the PPCInstrInfo.h file.
73 let TSFlagsFields = ["PPC970_First",
74 "PPC970_Single",
Chris Lattnerfd977342006-03-13 05:15:10 +0000[diff] [blame]75 "PPC970_Cracked",
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]76 "PPC970_Unit"];
Chris Lattnerfd977342006-03-13 05:15:10 +0000[diff] [blame]77 let TSFlagsShifts = [0, 1, 2, 3];
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]78
79 let isLittleEndianEncoding = 1;
80}
81
82
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]83def PPC : Target {
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]84 // Information about the instructions.
85 let InstructionSet = PPCInstrInfo;
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]86}