Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1 | //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 2 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 7 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 10 | // This file contains the PowerPC implementation of the MRegisterInfo class. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #define DEBUG_TYPE "reginfo" |
Chris Lattner | 2668959 | 2005-10-14 23:51:18 +0000 | [diff] [blame] | 15 | #include "PPC.h" |
Chris Lattner | 26bd0d4 | 2005-10-14 23:45:43 +0000 | [diff] [blame] | 16 | #include "PPCInstrBuilder.h" |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 17 | #include "PPCMachineFunctionInfo.h" |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 18 | #include "PPCRegisterInfo.h" |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 19 | #include "PPCFrameInfo.h" |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 20 | #include "PPCSubtarget.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 21 | #include "llvm/Constants.h" |
| 22 | #include "llvm/Type.h" |
| 23 | #include "llvm/CodeGen/ValueTypes.h" |
| 24 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineModuleInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineFunction.h" |
| 27 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 28 | #include "llvm/CodeGen/MachineLocation.h" |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 29 | #include "llvm/CodeGen/SelectionDAGNodes.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 30 | #include "llvm/Target/TargetFrameInfo.h" |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 31 | #include "llvm/Target/TargetInstrInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 32 | #include "llvm/Target/TargetMachine.h" |
| 33 | #include "llvm/Target/TargetOptions.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 34 | #include "llvm/Support/CommandLine.h" |
| 35 | #include "llvm/Support/Debug.h" |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 36 | #include "llvm/Support/MathExtras.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 37 | #include "llvm/ADT/BitVector.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 38 | #include "llvm/ADT/STLExtras.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 39 | #include <cstdlib> |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 40 | using namespace llvm; |
| 41 | |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 42 | /// getRegisterNumbering - Given the enum value for some register, e.g. |
| 43 | /// PPC::F14, return the number that it corresponds to (e.g. 14). |
| 44 | unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 45 | using namespace PPC; |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 46 | switch (RegEnum) { |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 47 | case R0 : case X0 : case F0 : case V0 : case CR0: return 0; |
| 48 | case R1 : case X1 : case F1 : case V1 : case CR1: return 1; |
| 49 | case R2 : case X2 : case F2 : case V2 : case CR2: return 2; |
| 50 | case R3 : case X3 : case F3 : case V3 : case CR3: return 3; |
| 51 | case R4 : case X4 : case F4 : case V4 : case CR4: return 4; |
| 52 | case R5 : case X5 : case F5 : case V5 : case CR5: return 5; |
| 53 | case R6 : case X6 : case F6 : case V6 : case CR6: return 6; |
| 54 | case R7 : case X7 : case F7 : case V7 : case CR7: return 7; |
| 55 | case R8 : case X8 : case F8 : case V8 : return 8; |
| 56 | case R9 : case X9 : case F9 : case V9 : return 9; |
| 57 | case R10: case X10: case F10: case V10: return 10; |
| 58 | case R11: case X11: case F11: case V11: return 11; |
| 59 | case R12: case X12: case F12: case V12: return 12; |
| 60 | case R13: case X13: case F13: case V13: return 13; |
| 61 | case R14: case X14: case F14: case V14: return 14; |
| 62 | case R15: case X15: case F15: case V15: return 15; |
| 63 | case R16: case X16: case F16: case V16: return 16; |
| 64 | case R17: case X17: case F17: case V17: return 17; |
| 65 | case R18: case X18: case F18: case V18: return 18; |
| 66 | case R19: case X19: case F19: case V19: return 19; |
| 67 | case R20: case X20: case F20: case V20: return 20; |
| 68 | case R21: case X21: case F21: case V21: return 21; |
| 69 | case R22: case X22: case F22: case V22: return 22; |
| 70 | case R23: case X23: case F23: case V23: return 23; |
| 71 | case R24: case X24: case F24: case V24: return 24; |
| 72 | case R25: case X25: case F25: case V25: return 25; |
| 73 | case R26: case X26: case F26: case V26: return 26; |
| 74 | case R27: case X27: case F27: case V27: return 27; |
| 75 | case R28: case X28: case F28: case V28: return 28; |
| 76 | case R29: case X29: case F29: case V29: return 29; |
| 77 | case R30: case X30: case F30: case V30: return 30; |
| 78 | case R31: case X31: case F31: case V31: return 31; |
| 79 | default: |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 80 | cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 81 | abort(); |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 82 | } |
| 83 | } |
| 84 | |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 85 | PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, |
| 86 | const TargetInstrInfo &tii) |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 87 | : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 88 | Subtarget(ST), TII(tii) { |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 89 | ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 90 | ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; |
| 91 | ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; |
| 92 | ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; |
| 93 | ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; |
| 94 | ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; |
| 95 | ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 96 | ImmToIdxMap[PPC::ADDI] = PPC::ADD4; |
Chris Lattner | c88fa74 | 2006-12-07 22:15:58 +0000 | [diff] [blame] | 97 | ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 98 | } |
| 99 | |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 100 | void |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 101 | PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
| 102 | MachineBasicBlock::iterator MI, |
| 103 | unsigned SrcReg, int FrameIdx, |
| 104 | const TargetRegisterClass *RC) const { |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 105 | if (RC == PPC::GPRCRegisterClass) { |
| 106 | if (SrcReg != PPC::LR) { |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 107 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) |
| 108 | .addReg(SrcReg, false, false, true), FrameIdx); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 109 | } else { |
| 110 | // FIXME: this spills LR immediately to memory in one step. To do this, |
| 111 | // we use R11, which we know cannot be used in the prolog/epilog. This is |
| 112 | // a hack. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 113 | BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11); |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 114 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) |
| 115 | .addReg(PPC::R11, false, false, true), FrameIdx); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 116 | } |
| 117 | } else if (RC == PPC::G8RCRegisterClass) { |
| 118 | if (SrcReg != PPC::LR8) { |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 119 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) |
| 120 | .addReg(SrcReg, false, false, true), FrameIdx); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 121 | } else { |
| 122 | // FIXME: this spills LR immediately to memory in one step. To do this, |
| 123 | // we use R11, which we know cannot be used in the prolog/epilog. This is |
| 124 | // a hack. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 125 | BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11); |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 126 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) |
| 127 | .addReg(PPC::X11, false, false, true), FrameIdx); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 128 | } |
| 129 | } else if (RC == PPC::F8RCRegisterClass) { |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 130 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)) |
| 131 | .addReg(SrcReg, false, false, true), FrameIdx); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 132 | } else if (RC == PPC::F4RCRegisterClass) { |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 133 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)) |
| 134 | .addReg(SrcReg, false, false, true), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 135 | } else if (RC == PPC::CRRCRegisterClass) { |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 136 | // FIXME: We use R0 here, because it isn't available for RA. |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 137 | // We need to store the CR in the low 4-bits of the saved value. First, |
| 138 | // issue a MFCR to save all of the CRBits. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 139 | BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 140 | |
| 141 | // If the saved register wasn't CR0, shift the bits left so that they are in |
| 142 | // CR0's slot. |
| 143 | if (SrcReg != PPC::CR0) { |
| 144 | unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 145 | // rlwinm r0, r0, ShiftBits, 0, 31. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 146 | BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 147 | .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 148 | } |
| 149 | |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 150 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) |
| 151 | .addReg(PPC::R0, false, false, true), FrameIdx); |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 152 | } else if (RC == PPC::VRRCRegisterClass) { |
| 153 | // We don't have indexed addressing for vector loads. Emit: |
| 154 | // R11 = ADDI FI# |
| 155 | // Dest = LVX R0, R11 |
| 156 | // |
| 157 | // FIXME: We use R0 here, because it isn't available for RA. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 158 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), |
| 159 | FrameIdx, 0, 0); |
| 160 | BuildMI(MBB, MI, TII.get(PPC::STVX)) |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 161 | .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 162 | } else { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 163 | assert(0 && "Unknown regclass!"); |
| 164 | abort(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 165 | } |
| 166 | } |
| 167 | |
| 168 | void |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 169 | PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 170 | MachineBasicBlock::iterator MI, |
| 171 | unsigned DestReg, int FrameIdx, |
| 172 | const TargetRegisterClass *RC) const { |
| 173 | if (RC == PPC::GPRCRegisterClass) { |
| 174 | if (DestReg != PPC::LR) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 175 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 176 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 177 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx); |
| 178 | BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 179 | } |
| 180 | } else if (RC == PPC::G8RCRegisterClass) { |
| 181 | if (DestReg != PPC::LR8) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 182 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 183 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 184 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx); |
| 185 | BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 186 | } |
| 187 | } else if (RC == PPC::F8RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 188 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 189 | } else if (RC == PPC::F4RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 190 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 191 | } else if (RC == PPC::CRRCRegisterClass) { |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 192 | // FIXME: We use R0 here, because it isn't available for RA. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 193 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 194 | |
| 195 | // If the reloaded register isn't CR0, shift the bits right so that they are |
| 196 | // in the right CR's slot. |
| 197 | if (DestReg != PPC::CR0) { |
| 198 | unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; |
| 199 | // rlwinm r11, r11, 32-ShiftBits, 0, 31. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 200 | BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 201 | .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 202 | } |
| 203 | |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 204 | BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0); |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 205 | } else if (RC == PPC::VRRCRegisterClass) { |
| 206 | // We don't have indexed addressing for vector loads. Emit: |
| 207 | // R11 = ADDI FI# |
| 208 | // Dest = LVX R0, R11 |
| 209 | // |
| 210 | // FIXME: We use R0 here, because it isn't available for RA. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 211 | addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), |
| 212 | FrameIdx, 0, 0); |
| 213 | BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 214 | } else { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 215 | assert(0 && "Unknown regclass!"); |
| 216 | abort(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 217 | } |
| 218 | } |
| 219 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 220 | void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 221 | MachineBasicBlock::iterator MI, |
| 222 | unsigned DestReg, unsigned SrcReg, |
| 223 | const TargetRegisterClass *RC) const { |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 224 | if (RC == PPC::GPRCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 225 | BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 226 | } else if (RC == PPC::G8RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 227 | BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 228 | } else if (RC == PPC::F4RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 229 | BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 230 | } else if (RC == PPC::F8RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 231 | BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 232 | } else if (RC == PPC::CRRCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 233 | BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); |
Chris Lattner | 335fd3c | 2006-03-16 20:03:58 +0000 | [diff] [blame] | 234 | } else if (RC == PPC::VRRCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 235 | BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); |
Nate Begeman | 7af0248 | 2005-04-12 07:04:16 +0000 | [diff] [blame] | 236 | } else { |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 237 | cerr << "Attempt to copy register that is not GPR or FPR"; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 238 | abort(); |
| 239 | } |
| 240 | } |
| 241 | |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 242 | void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, |
| 243 | MachineBasicBlock::iterator I, |
| 244 | unsigned DestReg, |
| 245 | const MachineInstr *Orig) const { |
| 246 | MachineInstr *MI = Orig->clone(); |
| 247 | MI->getOperand(0).setReg(DestReg); |
| 248 | MBB.insert(I, MI); |
| 249 | } |
| 250 | |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 251 | const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const { |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 252 | // 32-bit Darwin calling convention. |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 253 | static const unsigned Macho32_CalleeSavedRegs[] = { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 254 | PPC::R13, PPC::R14, PPC::R15, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 255 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, |
| 256 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, |
| 257 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, |
| 258 | PPC::R28, PPC::R29, PPC::R30, PPC::R31, |
| 259 | |
| 260 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 261 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 262 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 263 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 264 | PPC::F30, PPC::F31, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 265 | |
| 266 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 267 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 268 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 269 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 270 | |
| 271 | PPC::LR, 0 |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 272 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 273 | |
| 274 | static const unsigned ELF32_CalleeSavedRegs[] = { |
| 275 | PPC::R13, PPC::R14, PPC::R15, |
| 276 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, |
| 277 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, |
| 278 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, |
| 279 | PPC::R28, PPC::R29, PPC::R30, PPC::R31, |
| 280 | |
Nicolas Geoffray | ef3c030 | 2007-04-03 10:27:07 +0000 | [diff] [blame] | 281 | PPC::F9, |
| 282 | PPC::F10, PPC::F11, PPC::F12, PPC::F13, |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 283 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 284 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 285 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 286 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 287 | PPC::F30, PPC::F31, |
| 288 | |
| 289 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 290 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 291 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 292 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 293 | |
| 294 | PPC::LR, 0 |
| 295 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 296 | // 64-bit Darwin calling convention. |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 297 | static const unsigned Macho64_CalleeSavedRegs[] = { |
Chris Lattner | bdc571b | 2006-11-20 19:33:51 +0000 | [diff] [blame] | 298 | PPC::X14, PPC::X15, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 299 | PPC::X16, PPC::X17, PPC::X18, PPC::X19, |
| 300 | PPC::X20, PPC::X21, PPC::X22, PPC::X23, |
| 301 | PPC::X24, PPC::X25, PPC::X26, PPC::X27, |
| 302 | PPC::X28, PPC::X29, PPC::X30, PPC::X31, |
| 303 | |
| 304 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 305 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 306 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 307 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 308 | PPC::F30, PPC::F31, |
| 309 | |
| 310 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 311 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 312 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 313 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 314 | |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 315 | PPC::LR8, 0 |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 316 | }; |
| 317 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 318 | if (Subtarget.isMachoABI()) |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 319 | return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : |
| 320 | Macho32_CalleeSavedRegs; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 321 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 322 | // ELF 32. |
| 323 | return ELF32_CalleeSavedRegs; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | const TargetRegisterClass* const* |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 327 | PPCRegisterInfo::getCalleeSavedRegClasses() const { |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 328 | // 32-bit Macho calling convention. |
| 329 | static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 330 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 331 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 332 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 333 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 334 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 335 | |
| 336 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 337 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 338 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 339 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 340 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 341 | |
| 342 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 343 | |
| 344 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 345 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 346 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 347 | |
| 348 | &PPC::GPRCRegClass, 0 |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 349 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 350 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 351 | static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { |
| 352 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 353 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 354 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 355 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 356 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 357 | |
Nicolas Geoffray | cfcd8da | 2007-04-03 10:57:49 +0000 | [diff] [blame] | 358 | &PPC::F8RCRegClass, |
| 359 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 360 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 361 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 362 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 363 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 364 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 365 | |
| 366 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 367 | |
| 368 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 369 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 370 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 371 | |
| 372 | &PPC::GPRCRegClass, 0 |
| 373 | }; |
| 374 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 375 | // 64-bit Macho calling convention. |
| 376 | static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { |
Chris Lattner | bdc571b | 2006-11-20 19:33:51 +0000 | [diff] [blame] | 377 | &PPC::G8RCRegClass,&PPC::G8RCRegClass, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 378 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 379 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 380 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 381 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 382 | |
| 383 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 384 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 385 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 386 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 387 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 388 | |
| 389 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 390 | |
| 391 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 392 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 393 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 394 | |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 395 | &PPC::G8RCRegClass, 0 |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 396 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 397 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 398 | if (Subtarget.isMachoABI()) |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 399 | return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : |
| 400 | Macho32_CalleeSavedRegClasses; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 401 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 402 | // ELF 32. |
| 403 | return ELF32_CalleeSavedRegClasses; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 404 | } |
| 405 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 406 | // needsFP - Return true if the specified function should have a dedicated frame |
| 407 | // pointer register. This is true if the function has variable sized allocas or |
| 408 | // if frame pointer elimination is disabled. |
| 409 | // |
| 410 | static bool needsFP(const MachineFunction &MF) { |
| 411 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 412 | return NoFramePointerElim || MFI->hasVarSizedObjects(); |
| 413 | } |
| 414 | |
| 415 | BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 416 | BitVector Reserved(getNumRegs()); |
| 417 | Reserved.set(PPC::R0); |
| 418 | Reserved.set(PPC::R1); |
| 419 | Reserved.set(PPC::LR); |
| 420 | // In Linux, r2 is reserved for the OS. |
| 421 | if (!Subtarget.isDarwin()) |
| 422 | Reserved.set(PPC::R2); |
| 423 | // On PPC64, r13 is the thread pointer. Never allocate this register. |
| 424 | // Note that this is overconservative, as it also prevents allocation of |
| 425 | // R31 when the FP is not needed. |
| 426 | if (Subtarget.isPPC64()) { |
| 427 | Reserved.set(PPC::R13); |
| 428 | Reserved.set(PPC::R31); |
| 429 | } |
| 430 | if (needsFP(MF)) |
| 431 | Reserved.set(PPC::R31); |
| 432 | return Reserved; |
| 433 | } |
| 434 | |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 435 | /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into |
| 436 | /// copy instructions, turning them into load/store instructions. |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 437 | MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, |
| 438 | unsigned OpNum, |
| 439 | int FrameIndex) const { |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 440 | // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because |
| 441 | // it takes more than one instruction to store it. |
| 442 | unsigned Opc = MI->getOpcode(); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 443 | |
| 444 | MachineInstr *NewMI = NULL; |
Chris Lattner | b410dc9 | 2006-06-20 23:18:58 +0000 | [diff] [blame] | 445 | if ((Opc == PPC::OR && |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 446 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { |
| 447 | if (OpNum == 0) { // move -> store |
| 448 | unsigned InReg = MI->getOperand(1).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 449 | NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), |
| 450 | FrameIndex); |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 451 | } else { // move -> load |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 452 | unsigned OutReg = MI->getOperand(0).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 453 | NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), |
| 454 | FrameIndex); |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 455 | } |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 456 | } else if ((Opc == PPC::OR8 && |
| 457 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { |
| 458 | if (OpNum == 0) { // move -> store |
| 459 | unsigned InReg = MI->getOperand(1).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 460 | NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), |
| 461 | FrameIndex); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 462 | } else { // move -> load |
| 463 | unsigned OutReg = MI->getOperand(0).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 464 | NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 465 | } |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 466 | } else if (Opc == PPC::FMRD) { |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 467 | if (OpNum == 0) { // move -> store |
| 468 | unsigned InReg = MI->getOperand(1).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 469 | NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), |
| 470 | FrameIndex); |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 471 | } else { // move -> load |
| 472 | unsigned OutReg = MI->getOperand(0).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 473 | NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 474 | } |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 475 | } else if (Opc == PPC::FMRS) { |
| 476 | if (OpNum == 0) { // move -> store |
| 477 | unsigned InReg = MI->getOperand(1).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 478 | NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), |
| 479 | FrameIndex); |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 480 | } else { // move -> load |
| 481 | unsigned OutReg = MI->getOperand(0).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 482 | NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 483 | } |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 484 | } |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 485 | |
| 486 | if (NewMI) |
| 487 | NewMI->copyKillDeadInfo(MI); |
| 488 | return NewMI; |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 489 | } |
| 490 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 491 | //===----------------------------------------------------------------------===// |
| 492 | // Stack Frame Processing methods |
| 493 | //===----------------------------------------------------------------------===// |
| 494 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 495 | // hasFP - Return true if the specified function actually has a dedicated frame |
| 496 | // pointer register. This is true if the function needs a frame pointer and has |
| 497 | // a non-zero stack size. |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 498 | bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 499 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 500 | return MFI->getStackSize() && needsFP(MF); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 501 | } |
| 502 | |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 503 | /// usesLR - Returns if the link registers (LR) has been used in the function. |
| 504 | /// |
| 505 | bool PPCRegisterInfo::usesLR(MachineFunction &MF) const { |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 506 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 507 | return FI->usesLR(); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 508 | } |
| 509 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 510 | void PPCRegisterInfo:: |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 511 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 512 | MachineBasicBlock::iterator I) const { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 513 | // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 514 | MBB.erase(I); |
| 515 | } |
| 516 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 517 | /// LowerDynamicAlloc - Generate the code for allocating an object in the |
| 518 | /// current frame. The sequence of code with be in the general form |
| 519 | /// |
| 520 | /// addi R0, SP, #frameSize ; get the address of the previous frame |
| 521 | /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size |
| 522 | /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation |
| 523 | /// |
| 524 | void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { |
| 525 | // Get the instruction. |
| 526 | MachineInstr &MI = *II; |
| 527 | // Get the instruction's basic block. |
| 528 | MachineBasicBlock &MBB = *MI.getParent(); |
| 529 | // Get the basic block's function. |
| 530 | MachineFunction &MF = *MBB.getParent(); |
| 531 | // Get the frame info. |
| 532 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 533 | // Determine whether 64-bit pointers are used. |
| 534 | bool LP64 = Subtarget.isPPC64(); |
| 535 | |
Evan Cheng | fab0439 | 2007-01-25 22:48:25 +0000 | [diff] [blame] | 536 | // Get the maximum call stack size. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 537 | unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 538 | // Get the total frame size. |
| 539 | unsigned FrameSize = MFI->getStackSize(); |
| 540 | |
| 541 | // Get stack alignments. |
| 542 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 543 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Jim Laskey | d6fa8c1 | 2006-11-17 18:49:39 +0000 | [diff] [blame] | 544 | assert(MaxAlign <= TargetAlign && |
| 545 | "Dynamic alloca with large aligns not supported"); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 546 | |
| 547 | // Determine the previous frame's address. If FrameSize can't be |
| 548 | // represented as 16 bits or we need special alignment, then we load the |
| 549 | // previous frame's address from 0(SP). Why not do an addis of the hi? |
| 550 | // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. |
| 551 | // Constructing the constant and adding would take 3 instructions. |
| 552 | // Fortunately, a frame greater than 32K is rare. |
| 553 | if (MaxAlign < TargetAlign && isInt16(FrameSize)) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 554 | BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 555 | .addReg(PPC::R31) |
| 556 | .addImm(FrameSize); |
| 557 | } else if (LP64) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 558 | BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 559 | .addImm(0) |
| 560 | .addReg(PPC::X1); |
| 561 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 562 | BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 563 | .addImm(0) |
| 564 | .addReg(PPC::R1); |
| 565 | } |
| 566 | |
| 567 | // Grow the stack and update the stack pointer link, then |
| 568 | // determine the address of new allocated space. |
| 569 | if (LP64) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 570 | BuildMI(MBB, II, TII.get(PPC::STDUX)) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 571 | .addReg(PPC::X0) |
| 572 | .addReg(PPC::X1) |
| 573 | .addReg(MI.getOperand(1).getReg()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 574 | BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 575 | .addReg(PPC::X1) |
| 576 | .addImm(maxCallFrameSize); |
| 577 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 578 | BuildMI(MBB, II, TII.get(PPC::STWUX)) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 579 | .addReg(PPC::R0) |
| 580 | .addReg(PPC::R1) |
| 581 | .addReg(MI.getOperand(1).getReg()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 582 | BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 583 | .addReg(PPC::R1) |
| 584 | .addImm(maxCallFrameSize); |
| 585 | } |
| 586 | |
| 587 | // Discard the DYNALLOC instruction. |
| 588 | MBB.erase(II); |
| 589 | } |
| 590 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 591 | void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
| 592 | RegScavenger *RS) const { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 593 | // Get the instruction. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 594 | MachineInstr &MI = *II; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 595 | // Get the instruction's basic block. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 596 | MachineBasicBlock &MBB = *MI.getParent(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 597 | // Get the basic block's function. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 598 | MachineFunction &MF = *MBB.getParent(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 599 | // Get the frame info. |
| 600 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 601 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 602 | // Find out which operand is the frame index. |
| 603 | unsigned i = 0; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 604 | while (!MI.getOperand(i).isFrameIndex()) { |
| 605 | ++i; |
| 606 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 607 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 608 | // Take into account whether it's an add or mem instruction |
| 609 | unsigned OffIdx = (i == 2) ? 1 : 2; |
Chris Lattner | 9aa2895 | 2007-02-01 00:39:08 +0000 | [diff] [blame] | 610 | if (MI.getOpcode() == TargetInstrInfo::INLINEASM) |
| 611 | OffIdx = i-1; |
| 612 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 613 | // Get the frame index. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 614 | int FrameIndex = MI.getOperand(i).getFrameIndex(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 615 | |
| 616 | // Get the frame pointer save index. Users of this index are primarily |
| 617 | // DYNALLOC instructions. |
| 618 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 619 | int FPSI = FI->getFramePointerSaveIndex(); |
| 620 | // Get the instruction opcode. |
| 621 | unsigned OpC = MI.getOpcode(); |
| 622 | |
| 623 | // Special case for dynamic alloca. |
| 624 | if (FPSI && FrameIndex == FPSI && |
| 625 | (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { |
| 626 | lowerDynamicAlloc(II); |
| 627 | return; |
| 628 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 629 | |
| 630 | // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 631 | MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 632 | |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 633 | // Figure out if the offset in the instruction is shifted right two bits. This |
| 634 | // is true for instructions like "STD", which the machine implicitly adds two |
| 635 | // low zeros to. |
| 636 | bool isIXAddr = false; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 637 | switch (OpC) { |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 638 | case PPC::LWA: |
| 639 | case PPC::LD: |
| 640 | case PPC::STD: |
| 641 | case PPC::STD_32: |
| 642 | isIXAddr = true; |
| 643 | break; |
| 644 | } |
| 645 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 646 | // Now add the frame object offset to the offset from r1. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 647 | int Offset = MFI->getObjectOffset(FrameIndex); |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 648 | |
| 649 | if (!isIXAddr) |
| 650 | Offset += MI.getOperand(OffIdx).getImmedValue(); |
| 651 | else |
| 652 | Offset += MI.getOperand(OffIdx).getImmedValue() << 2; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 653 | |
| 654 | // If we're not using a Frame Pointer that has been set to the value of the |
| 655 | // SP before having the stack size subtracted from it, then add the stack size |
| 656 | // to Offset to get the correct offset. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 657 | Offset += MFI->getStackSize(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 658 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 659 | if (!isInt16(Offset)) { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 660 | // Insert a set of r0 with the full offset value before the ld, st, or add |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 661 | BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); |
| 662 | BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); |
Chris Lattner | c6d48d3 | 2006-01-11 23:07:57 +0000 | [diff] [blame] | 663 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 664 | // convert into indexed form of the instruction |
| 665 | // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 |
| 666 | // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 667 | assert(ImmToIdxMap.count(OpC) && |
Chris Lattner | 1463019 | 2005-09-09 20:51:08 +0000 | [diff] [blame] | 668 | "No indexed form of load or store available!"); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 669 | unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; |
Evan Cheng | 12a4478 | 2006-11-30 07:12:03 +0000 | [diff] [blame] | 670 | MI.setInstrDescriptor(TII.get(NewOpcode)); |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 671 | MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); |
| 672 | MI.getOperand(2).ChangeToRegister(PPC::R0, false); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 673 | } else { |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 674 | if (isIXAddr) { |
Chris Lattner | 841d12d | 2005-10-18 16:51:22 +0000 | [diff] [blame] | 675 | assert((Offset & 3) == 0 && "Invalid frame offset!"); |
| 676 | Offset >>= 2; // The actual encoded value has the low two bits zero. |
Chris Lattner | 841d12d | 2005-10-18 16:51:22 +0000 | [diff] [blame] | 677 | } |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 678 | MI.getOperand(OffIdx).ChangeToImmediate(Offset); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 679 | } |
| 680 | } |
| 681 | |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 682 | /// VRRegNo - Map from a numbered VR register to its enum value. |
| 683 | /// |
| 684 | static const unsigned short VRRegNo[] = { |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 685 | PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , |
| 686 | PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 687 | PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 688 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 |
| 689 | }; |
| 690 | |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 691 | /// RemoveVRSaveCode - We have found that this function does not need any code |
| 692 | /// to manipulate the VRSAVE register, even though it uses vector registers. |
| 693 | /// This can happen when the only registers used are known to be live in or out |
| 694 | /// of the function. Remove all of the VRSAVE related code from the function. |
| 695 | static void RemoveVRSaveCode(MachineInstr *MI) { |
| 696 | MachineBasicBlock *Entry = MI->getParent(); |
| 697 | MachineFunction *MF = Entry->getParent(); |
| 698 | |
| 699 | // We know that the MTVRSAVE instruction immediately follows MI. Remove it. |
| 700 | MachineBasicBlock::iterator MBBI = MI; |
| 701 | ++MBBI; |
| 702 | assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); |
| 703 | MBBI->eraseFromParent(); |
| 704 | |
| 705 | bool RemovedAllMTVRSAVEs = true; |
| 706 | // See if we can find and remove the MTVRSAVE instruction from all of the |
| 707 | // epilog blocks. |
| 708 | const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); |
| 709 | for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { |
| 710 | // If last instruction is a return instruction, add an epilogue |
| 711 | if (!I->empty() && TII.isReturn(I->back().getOpcode())) { |
| 712 | bool FoundIt = false; |
| 713 | for (MBBI = I->end(); MBBI != I->begin(); ) { |
| 714 | --MBBI; |
| 715 | if (MBBI->getOpcode() == PPC::MTVRSAVE) { |
| 716 | MBBI->eraseFromParent(); // remove it. |
| 717 | FoundIt = true; |
| 718 | break; |
| 719 | } |
| 720 | } |
| 721 | RemovedAllMTVRSAVEs &= FoundIt; |
| 722 | } |
| 723 | } |
| 724 | |
| 725 | // If we found and removed all MTVRSAVE instructions, remove the read of |
| 726 | // VRSAVE as well. |
| 727 | if (RemovedAllMTVRSAVEs) { |
| 728 | MBBI = MI; |
| 729 | assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); |
| 730 | --MBBI; |
| 731 | assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); |
| 732 | MBBI->eraseFromParent(); |
| 733 | } |
| 734 | |
| 735 | // Finally, nuke the UPDATE_VRSAVE. |
| 736 | MI->eraseFromParent(); |
| 737 | } |
| 738 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 739 | // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the |
| 740 | // instruction selector. Based on the vector registers that have been used, |
| 741 | // transform this into the appropriate ORI instruction. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 742 | static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs, |
| 743 | const TargetInstrInfo &TII) { |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 744 | unsigned UsedRegMask = 0; |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 745 | for (unsigned i = 0; i != 32; ++i) |
| 746 | if (UsedRegs[VRRegNo[i]]) |
| 747 | UsedRegMask |= 1 << (31-i); |
| 748 | |
Chris Lattner | 402504b | 2006-04-17 21:22:06 +0000 | [diff] [blame] | 749 | // Live in and live out values already must be in the mask, so don't bother |
| 750 | // marking them. |
| 751 | MachineFunction *MF = MI->getParent()->getParent(); |
| 752 | for (MachineFunction::livein_iterator I = |
| 753 | MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { |
| 754 | unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); |
| 755 | if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. |
| 756 | UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. |
| 757 | } |
| 758 | for (MachineFunction::liveout_iterator I = |
| 759 | MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { |
| 760 | unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); |
| 761 | if (VRRegNo[RegNo] == *I) // If this really is a vector reg. |
| 762 | UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. |
| 763 | } |
| 764 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 765 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 766 | unsigned DstReg = MI->getOperand(0).getReg(); |
| 767 | // If no registers are used, turn this into a copy. |
| 768 | if (UsedRegMask == 0) { |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 769 | // Remove all VRSAVE code. |
| 770 | RemoveVRSaveCode(MI); |
| 771 | return; |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 772 | } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 773 | BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 774 | .addReg(SrcReg).addImm(UsedRegMask); |
| 775 | } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 776 | BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 777 | .addReg(SrcReg).addImm(UsedRegMask >> 16); |
| 778 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 779 | BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 780 | .addReg(SrcReg).addImm(UsedRegMask >> 16); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 781 | BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 782 | .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); |
| 783 | } |
| 784 | |
| 785 | // Remove the old UPDATE_VRSAVE instruction. |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 786 | MI->eraseFromParent(); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 787 | } |
| 788 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 789 | /// determineFrameLayout - Determine the size of the frame and maximum call |
| 790 | /// frame size. |
| 791 | void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { |
| 792 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 793 | |
| 794 | // Get the number of bytes to allocate from the FrameInfo |
| 795 | unsigned FrameSize = MFI->getStackSize(); |
| 796 | |
| 797 | // Get the alignments provided by the target, and the maximum alignment |
| 798 | // (if any) of the fixed frame objects. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 799 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Evan Cheng | 99403b6 | 2007-01-25 22:25:04 +0000 | [diff] [blame] | 800 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 801 | unsigned AlignMask = TargetAlign - 1; // |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 802 | |
| 803 | // If we are a leaf function, and use up to 224 bytes of stack space, |
| 804 | // don't have a frame pointer, calls, or dynamic alloca then we do not need |
| 805 | // to adjust the stack pointer (we fit in the Red Zone). |
| 806 | if (FrameSize <= 224 && // Fits in red zone. |
Jim Laskey | 2ff5cdb | 2006-11-17 16:09:31 +0000 | [diff] [blame] | 807 | !MFI->hasVarSizedObjects() && // No dynamic alloca. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 808 | !MFI->hasCalls() && // No calls. |
| 809 | MaxAlign <= TargetAlign) { // No special alignment. |
| 810 | // No need for frame |
| 811 | MFI->setStackSize(0); |
| 812 | return; |
| 813 | } |
| 814 | |
| 815 | // Get the maximum call frame size of all the calls. |
| 816 | unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); |
| 817 | |
| 818 | // Maximum call frame needs to be at least big enough for linkage and 8 args. |
| 819 | unsigned minCallFrameSize = |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 820 | PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), |
| 821 | Subtarget.isMachoABI()); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 822 | maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); |
| 823 | |
| 824 | // If we have dynamic alloca then maxCallFrameSize needs to be aligned so |
| 825 | // that allocations will be aligned. |
| 826 | if (MFI->hasVarSizedObjects()) |
| 827 | maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; |
| 828 | |
| 829 | // Update maximum call frame size. |
| 830 | MFI->setMaxCallFrameSize(maxCallFrameSize); |
| 831 | |
| 832 | // Include call frame size in total. |
| 833 | FrameSize += maxCallFrameSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 834 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 835 | // Make sure the frame is aligned. |
| 836 | FrameSize = (FrameSize + AlignMask) & ~AlignMask; |
| 837 | |
| 838 | // Update frame info. |
| 839 | MFI->setStackSize(FrameSize); |
| 840 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 841 | |
Evan Cheng | 28b3c45 | 2007-03-06 10:05:14 +0000 | [diff] [blame] | 842 | void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, |
| 843 | RegScavenger *RS) |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 844 | const { |
| 845 | // Save and clear the LR state. |
| 846 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 847 | unsigned LR = getRARegister(); |
| 848 | FI->setUsesLR(MF.isPhysRegUsed(LR)); |
| 849 | MF.changePhyRegUsed(LR, false); |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 850 | |
| 851 | |
| 852 | // Save R31 if necessary |
| 853 | int FPSI = FI->getFramePointerSaveIndex(); |
| 854 | bool IsPPC64 = Subtarget.isPPC64(); |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 855 | bool IsELF32_ABI = Subtarget.isELF32_ABI(); |
| 856 | bool IsMachoABI = Subtarget.isMachoABI(); |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 857 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 858 | |
| 859 | // If the frame pointer save index hasn't been defined yet. |
| 860 | if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 861 | && IsELF32_ABI) { |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 862 | // Find out what the fix offset of the frame pointer save area. |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame^] | 863 | int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, |
| 864 | IsMachoABI); |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 865 | // Allocate the frame index for frame pointer save area. |
| 866 | FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); |
| 867 | // Save the result. |
| 868 | FI->setFramePointerSaveIndex(FPSI); |
| 869 | } |
| 870 | |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 871 | } |
| 872 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 873 | void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 874 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
| 875 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 876 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 877 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 878 | |
Jim Laskey | 072200c | 2007-01-29 18:51:14 +0000 | [diff] [blame] | 879 | // Prepare for frame info. |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 880 | unsigned FrameLabelId = 0; |
| 881 | |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 882 | // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, |
| 883 | // process it. |
Chris Lattner | 8aa777d | 2006-03-16 21:31:45 +0000 | [diff] [blame] | 884 | for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 885 | if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 886 | HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 887 | break; |
| 888 | } |
| 889 | } |
| 890 | |
| 891 | // Move MBBI back to the beginning of the function. |
| 892 | MBBI = MBB.begin(); |
| 893 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 894 | // Work out frame sizes. |
| 895 | determineFrameLayout(MF); |
| 896 | unsigned FrameSize = MFI->getStackSize(); |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 897 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 898 | int NegFrameSize = -FrameSize; |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 899 | |
| 900 | // Get processor type. |
| 901 | bool IsPPC64 = Subtarget.isPPC64(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 902 | // Get operating system |
| 903 | bool IsMachoABI = Subtarget.isMachoABI(); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 904 | // Check if the link register (LR) has been used. |
| 905 | bool UsesLR = MFI->hasCalls() || usesLR(MF); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 906 | // Do we have a frame pointer for this function? |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 907 | bool HasFP = hasFP(MF) && FrameSize; |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 908 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 909 | int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); |
| 910 | int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 911 | |
| 912 | if (IsPPC64) { |
| 913 | if (UsesLR) |
| 914 | BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); |
| 915 | |
| 916 | if (HasFP) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 917 | BuildMI(MBB, MBBI, TII.get(PPC::STD)) |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 918 | .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); |
| 919 | |
| 920 | if (UsesLR) |
| 921 | BuildMI(MBB, MBBI, TII.get(PPC::STD)) |
| 922 | .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); |
| 923 | } else { |
| 924 | if (UsesLR) |
| 925 | BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); |
| 926 | |
| 927 | if (HasFP) |
| 928 | BuildMI(MBB, MBBI, TII.get(PPC::STW)) |
| 929 | .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); |
| 930 | |
| 931 | if (UsesLR) |
| 932 | BuildMI(MBB, MBBI, TII.get(PPC::STW)) |
| 933 | .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 934 | } |
| 935 | |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 936 | // Skip if a leaf routine. |
| 937 | if (!FrameSize) return; |
| 938 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 939 | // Get stack alignments. |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 940 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 941 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 942 | |
Jim Laskey | e078d1a | 2007-01-29 23:20:22 +0000 | [diff] [blame] | 943 | if (MMI && MMI->needsFrameInfo()) { |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 944 | // Mark effective beginning of when frame pointer becomes valid. |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 945 | FrameLabelId = MMI->NextLabelID(); |
Jim Laskey | 1ee2925 | 2007-01-26 14:34:52 +0000 | [diff] [blame] | 946 | BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId); |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 947 | } |
| 948 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 949 | // Adjust stack pointer: r1 += NegFrameSize. |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 950 | // If there is a preferred stack alignment, align R1 now |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 951 | if (!IsPPC64) { |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 952 | // PPC32. |
| 953 | if (MaxAlign > TargetAlign) { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 954 | assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); |
| 955 | assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 956 | BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 957 | .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 958 | BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 959 | .addImm(NegFrameSize); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 960 | BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 961 | .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 962 | } else if (isInt16(NegFrameSize)) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 963 | BuildMI(MBB, MBBI, TII.get(PPC::STWU), |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 964 | PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 965 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 966 | BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); |
| 967 | BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 968 | .addImm(NegFrameSize & 0xFFFF); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 969 | BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 970 | .addReg(PPC::R0); |
| 971 | } |
| 972 | } else { // PPC64. |
| 973 | if (MaxAlign > TargetAlign) { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 974 | assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); |
| 975 | assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 976 | BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 977 | .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 978 | BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 979 | .addImm(NegFrameSize); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 980 | BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 981 | .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); |
Jim Laskey | 2ff5cdb | 2006-11-17 16:09:31 +0000 | [diff] [blame] | 982 | } else if (isInt16(NegFrameSize)) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 983 | BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 984 | .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 985 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 986 | BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); |
| 987 | BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 988 | .addImm(NegFrameSize & 0xFFFF); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 989 | BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 990 | .addReg(PPC::X0); |
| 991 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 992 | } |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 993 | |
Jim Laskey | e078d1a | 2007-01-29 23:20:22 +0000 | [diff] [blame] | 994 | if (MMI && MMI->needsFrameInfo()) { |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 995 | std::vector<MachineMove> &Moves = MMI->getFrameMoves(); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 996 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 997 | if (NegFrameSize) { |
| 998 | // Show update of SP. |
| 999 | MachineLocation SPDst(MachineLocation::VirtualFP); |
| 1000 | MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); |
| 1001 | Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); |
| 1002 | } else { |
| 1003 | MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); |
| 1004 | Moves.push_back(MachineMove(FrameLabelId, SP, SP)); |
| 1005 | } |
Jim Laskey | 4c2c903 | 2006-08-25 19:40:59 +0000 | [diff] [blame] | 1006 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1007 | if (HasFP) { |
| 1008 | MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); |
| 1009 | MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); |
| 1010 | Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); |
| 1011 | } |
Jim Laskey | ce50a16 | 2006-08-29 16:24:26 +0000 | [diff] [blame] | 1012 | |
| 1013 | // Add callee saved registers to move list. |
| 1014 | const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); |
| 1015 | for (unsigned I = 0, E = CSI.size(); I != E; ++I) { |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1016 | int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); |
| 1017 | unsigned Reg = CSI[I].getReg(); |
| 1018 | if (Reg == PPC::LR || Reg == PPC::LR8) continue; |
| 1019 | MachineLocation CSDst(MachineLocation::VirtualFP, Offset); |
| 1020 | MachineLocation CSSrc(Reg); |
| 1021 | Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); |
Jim Laskey | ce50a16 | 2006-08-29 16:24:26 +0000 | [diff] [blame] | 1022 | } |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1023 | |
Jim Laskey | b82313f | 2007-02-01 16:31:34 +0000 | [diff] [blame] | 1024 | MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); |
| 1025 | MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); |
| 1026 | Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); |
| 1027 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1028 | // Mark effective beginning of when frame pointer is ready. |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1029 | unsigned ReadyLabelId = MMI->NextLabelID(); |
Jim Laskey | 1ee2925 | 2007-01-26 14:34:52 +0000 | [diff] [blame] | 1030 | BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId); |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1031 | |
| 1032 | MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : |
| 1033 | (IsPPC64 ? PPC::X1 : PPC::R1)); |
| 1034 | MachineLocation FPSrc(MachineLocation::VirtualFP); |
| 1035 | Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1036 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1037 | |
| 1038 | // If there is a frame pointer, copy R1 into R31 |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 1039 | if (HasFP) { |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1040 | if (!IsPPC64) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1041 | BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) |
| 1042 | .addReg(PPC::R1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1043 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1044 | BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) |
| 1045 | .addReg(PPC::X1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1046 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1047 | } |
| 1048 | } |
| 1049 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1050 | void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, |
| 1051 | MachineBasicBlock &MBB) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1052 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Evan Cheng | 6da8d99 | 2006-01-09 18:28:21 +0000 | [diff] [blame] | 1053 | assert(MBBI->getOpcode() == PPC::BLR && |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1054 | "Can only insert epilog into returning blocks"); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 1055 | |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 1056 | // Get alignment info so we know how to restore r1 |
| 1057 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1058 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1059 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 1060 | |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 1061 | // Get the number of bytes allocated from the FrameInfo. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1062 | unsigned FrameSize = MFI->getStackSize(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1063 | |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1064 | // Get processor type. |
| 1065 | bool IsPPC64 = Subtarget.isPPC64(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1066 | // Get operating system |
| 1067 | bool IsMachoABI = Subtarget.isMachoABI(); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1068 | // Check if the link register (LR) has been used. |
| 1069 | bool UsesLR = MFI->hasCalls() || usesLR(MF); |
| 1070 | // Do we have a frame pointer for this function? |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1071 | bool HasFP = hasFP(MF) && FrameSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1072 | |
| 1073 | int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); |
| 1074 | int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); |
| 1075 | |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1076 | if (FrameSize) { |
| 1077 | // The loaded (or persistent) stack pointer value is offset by the 'stwu' |
| 1078 | // on entry to the function. Add this offset back now. |
| 1079 | if (!Subtarget.isPPC64()) { |
| 1080 | if (isInt16(FrameSize) && TargetAlign >= MaxAlign && |
| 1081 | !MFI->hasVarSizedObjects()) { |
| 1082 | BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) |
| 1083 | .addReg(PPC::R1).addImm(FrameSize); |
| 1084 | } else { |
| 1085 | BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); |
| 1086 | } |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 1087 | } else { |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1088 | if (isInt16(FrameSize) && TargetAlign >= MaxAlign && |
| 1089 | !MFI->hasVarSizedObjects()) { |
| 1090 | BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) |
| 1091 | .addReg(PPC::X1).addImm(FrameSize); |
| 1092 | } else { |
| 1093 | BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); |
| 1094 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1095 | } |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1096 | } |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1097 | |
| 1098 | if (IsPPC64) { |
| 1099 | if (UsesLR) |
| 1100 | BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) |
| 1101 | .addImm(LROffset/4).addReg(PPC::X1); |
| 1102 | |
| 1103 | if (HasFP) |
| 1104 | BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) |
| 1105 | .addImm(FPOffset/4).addReg(PPC::X1); |
| 1106 | |
| 1107 | if (UsesLR) |
| 1108 | BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); |
| 1109 | } else { |
| 1110 | if (UsesLR) |
| 1111 | BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) |
| 1112 | .addImm(LROffset).addReg(PPC::R1); |
| 1113 | |
| 1114 | if (HasFP) |
| 1115 | BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) |
| 1116 | .addImm(FPOffset).addReg(PPC::R1); |
| 1117 | |
| 1118 | if (UsesLR) |
| 1119 | BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1120 | } |
| 1121 | } |
| 1122 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1123 | unsigned PPCRegisterInfo::getRARegister() const { |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 1124 | return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1125 | } |
| 1126 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 1127 | unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1128 | if (!Subtarget.isPPC64()) |
| 1129 | return hasFP(MF) ? PPC::R31 : PPC::R1; |
| 1130 | else |
| 1131 | return hasFP(MF) ? PPC::X31 : PPC::X1; |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1132 | } |
| 1133 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1134 | void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1135 | const { |
Jim Laskey | 4c2c903 | 2006-08-25 19:40:59 +0000 | [diff] [blame] | 1136 | // Initial state of the frame pointer is R1. |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1137 | MachineLocation Dst(MachineLocation::VirtualFP); |
| 1138 | MachineLocation Src(PPC::R1, 0); |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1139 | Moves.push_back(MachineMove(0, Dst, Src)); |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 1140 | } |
| 1141 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 1142 | unsigned PPCRegisterInfo::getEHExceptionRegister() const { |
| 1143 | return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; |
| 1144 | } |
| 1145 | |
| 1146 | unsigned PPCRegisterInfo::getEHHandlerRegister() const { |
| 1147 | return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; |
| 1148 | } |
| 1149 | |
Chris Lattner | 4c7b43b | 2005-10-14 23:37:35 +0000 | [diff] [blame] | 1150 | #include "PPCGenRegisterInfo.inc" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1151 | |