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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / f222e595c0137b8a9571408257f7000c2fb95473 / . / lib / Target / ARM / ARMISelLowering.h
blob: 10c7f6efce1ee3220067bef5b1d72dd2a091d3f9 [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]18#include "ARMSubtarget.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]19#include "llvm/Target/TargetLowering.h"
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]21#include "llvm/CodeGen/FastISel.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]22#include "llvm/CodeGen/SelectionDAG.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +0000[diff] [blame]23#include "llvm/CodeGen/CallingConvLower.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]24#include <vector>
25
26namespace llvm {
27 class ARMConstantPoolValue;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]28
29 namespace ARMISD {
30 // ARM Specific DAG Nodes
31 enum NodeType {
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]32 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +0000[diff] [blame]33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]34
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Cheng53519f02011-01-21 18:55:51 +0000[diff] [blame]37 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
38 // DYN mode.
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000[diff] [blame]39 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
40 // PIC mode.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]41 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]42
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]43 CALL, // Function call.
Evan Cheng277f0742007-06-19 21:05:09 +0000[diff] [blame]44 CALL_PRED, // Function call that's predicable.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
Evan Cheng5657c012009-07-29 02:18:14 +0000[diff] [blame]49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]50 RET_FLAG, // Return with a flag operand.
51
52 PIC_ADD, // Add with a PC operand and a PIC label.
53
54 CMP, // ARM compare instructions.
David Goodwinc0309b42009-06-29 15:33:01 +0000[diff] [blame]55 CMPZ, // ARM compare that sets only Z flag.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]56 CMPFP, // ARM VFP compare instruction, sets FPSCR.
57 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
58 FMSTAT, // ARM fmstat instruction.
59 CMOV, // ARM conditional move instructions.
60 CNEG, // ARM conditional negate instructions.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]61
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]62 BCC_i64,
63
Jim Grosbach3482c802010-01-18 19:58:49 +0000[diff] [blame]64 RBIT, // ARM bitreverse instruction
65
Bob Wilson76a312b2010-03-19 22:51:32 +0000[diff] [blame]66 FTOSI, // FP to sint within a FP register.
67 FTOUI, // FP to uint within a FP register.
68 SITOF, // sint to FP within a FP register.
69 UITOF, // uint to FP within a FP register.
70
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]71 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
72 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
73 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]74
Jim Grosbache5165492009-11-09 00:11:35 +0000[diff] [blame]75 VMOVRRD, // double to two gprs.
76 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000[diff] [blame]77
Jim Grosbache4ad3872010-10-19 23:27:08 +0000[diff] [blame]78 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
79 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
80 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup.
Jim Grosbach0e0da732009-05-12 23:59:14 +0000[diff] [blame]81
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]82 TC_RETURN, // Tail call return pseudo.
83
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]84 THREAD_POINTER,
85
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]86 DYN_ALLOC, // Dynamic allocation on the stack.
87
Bob Wilsonf74a4292010-10-30 00:54:37 +0000[diff] [blame]88 MEMBARRIER, // Memory barrier (DMB)
89 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Chengdfed19f2010-11-03 06:34:55 +0000[diff] [blame]90
91 PRELOAD, // Preload
Nate Begemand1fb5832010-08-03 21:31:55 +0000[diff] [blame]92
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]93 VCEQ, // Vector compare equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]94 VCEQZ, // Vector compare equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]95 VCGE, // Vector compare greater than or equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]96 VCGEZ, // Vector compare greater than or equal to zero.
97 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]98 VCGEU, // Vector compare unsigned greater than or equal.
99 VCGT, // Vector compare greater than.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]100 VCGTZ, // Vector compare greater than zero.
101 VCLTZ, // Vector compare less than zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]102 VCGTU, // Vector compare unsigned greater than.
103 VTST, // Vector test bits.
104
105 // Vector shift by immediate:
106 VSHL, // ...left
107 VSHRs, // ...right (signed)
108 VSHRu, // ...right (unsigned)
109 VSHLLs, // ...left long (signed)
110 VSHLLu, // ...left long (unsigned)
111 VSHLLi, // ...left long (with maximum shift count)
112 VSHRN, // ...right narrow
113
114 // Vector rounding shift by immediate:
115 VRSHRs, // ...right (signed)
116 VRSHRu, // ...right (unsigned)
117 VRSHRN, // ...right narrow
118
119 // Vector saturating shift by immediate:
120 VQSHLs, // ...left (signed)
121 VQSHLu, // ...left (unsigned)
122 VQSHLsu, // ...left (signed to unsigned)
123 VQSHRNs, // ...right narrow (signed)
124 VQSHRNu, // ...right narrow (unsigned)
125 VQSHRNsu, // ...right narrow (signed to unsigned)
126
127 // Vector saturating rounding shift by immediate:
128 VQRSHRNs, // ...right narrow (signed)
129 VQRSHRNu, // ...right narrow (unsigned)
130 VQRSHRNsu, // ...right narrow (signed to unsigned)
131
132 // Vector shift and insert:
133 VSLI, // ...left
134 VSRI, // ...right
135
136 // Vector get lane (VMOV scalar to ARM core register)
137 // (These are used for 8- and 16-bit element types only.)
138 VGETLANEu, // zero-extend vector extract element
139 VGETLANEs, // sign-extend vector extract element
140
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]141 // Vector move immediate and move negated immediate:
Bob Wilsoncba270d2010-07-13 21:16:48 +0000[diff] [blame]142 VMOVIMM,
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]143 VMVNIMM,
144
145 // Vector duplicate:
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]146 VDUP,
Bob Wilson0ce37102009-08-14 05:08:32 +0000[diff] [blame]147 VDUPLANE,
Bob Wilsona599bff2009-08-04 00:36:16 +0000[diff] [blame]148
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]149 // Vector shuffles:
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000[diff] [blame]150 VEXT, // extract
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]151 VREV64, // reverse elements within 64-bit doublewords
152 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +0000[diff] [blame]153 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsonc692cb72009-08-21 20:54:19 +0000[diff] [blame]154 VZIP, // zip (interleave)
155 VUZP, // unzip (deinterleave)
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]156 VTRN, // transpose
157
Bob Wilsond0b69cf2010-09-01 23:50:19 +0000[diff] [blame]158 // Vector multiply long:
159 VMULLs, // ...signed
160 VMULLu, // ...unsigned
161
Bob Wilson40cbe7d2010-06-04 00:04:02 +0000[diff] [blame]162 // Operands of the standard BUILD_VECTOR node are not legalized, which
163 // is fine if BUILD_VECTORs are always lowered to shuffles or other
164 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
165 // operands need to be legalized. Define an ARM-specific version of
166 // BUILD_VECTOR for this purpose.
167 BUILD_VECTOR,
168
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]169 // Floating-point max and min:
170 FMAX,
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]171 FMIN,
172
173 // Bit-field insert
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]174 BFI,
175
176 // Vector OR with immediate
Owen Anderson080c0922010-11-05 19:27:46 +0000[diff] [blame]177 VORRIMM,
178 // Vector AND with NOT of immediate
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]179 VBICIMM,
180
181 // Vector load N-element structure to all lanes:
182 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
183 VLD3DUP,
Bob Wilson1c3ef902011-02-07 17:43:21 +0000[diff] [blame]184 VLD4DUP,
185
186 // NEON loads with post-increment base updates:
187 VLD1_UPD,
188 VLD2_UPD,
189 VLD3_UPD,
190 VLD4_UPD,
191 VLD2LN_UPD,
192 VLD3LN_UPD,
193 VLD4LN_UPD,
194 VLD2DUP_UPD,
195 VLD3DUP_UPD,
196 VLD4DUP_UPD,
197
198 // NEON stores with post-increment base updates:
199 VST1_UPD,
200 VST2_UPD,
201 VST3_UPD,
202 VST4_UPD,
203 VST2LN_UPD,
204 VST3LN_UPD,
205 VST4LN_UPD
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]206 };
207 }
208
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]209 /// Define some predicates that are used for node matching.
210 namespace ARM {
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]211 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
212 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
213 /// instruction, returns its 8-bit integer representation. Otherwise,
214 /// returns -1.
215 int getVFPf32Imm(const APFloat &FPImm);
216 int getVFPf64Imm(const APFloat &FPImm);
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]217 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]218 }
219
Bob Wilson261f2a22009-05-20 16:30:25 +0000[diff] [blame]220 //===--------------------------------------------------------------------===//
Dale Johannesen80dae192007-03-20 00:30:56 +0000[diff] [blame]221 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]222
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]223 class ARMTargetLowering : public TargetLowering {
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]224 public:
Dan Gohman61e729e2007-08-02 21:21:54 +0000[diff] [blame]225 explicit ARMTargetLowering(TargetMachine &TM);
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]226
Jim Grosbache1102ca2010-07-19 17:20:38 +0000[diff] [blame]227 virtual unsigned getJumpTableEncoding(void) const;
228
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]229 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]230
231 /// ReplaceNodeResults - Replace the results of node with an illegal result
232 /// type with new values built out of custom code.
233 ///
234 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]235 SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]236
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]237 virtual const char *getTargetNodeName(unsigned Opcode) const;
238
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000[diff] [blame]239 virtual MachineBasicBlock *
240 EmitInstrWithCustomInserter(MachineInstr *MI,
241 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]242
Evan Cheng31959b12011-02-02 01:06:55 +0000[diff] [blame]243 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
244
245 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
246
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]247 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
248 /// unaligned memory accesses. of the specified type.
249 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
250 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
251
Chris Lattnerc9addb72007-03-30 23:15:24 +0000[diff] [blame]252 /// isLegalAddressingMode - Return true if the addressing mode represented
253 /// by AM is legal for this target, for a load/store of the specified type.
254 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
Evan Chenge6c835f2009-08-14 20:09:37 +0000[diff] [blame]255 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]256
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]257 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]258 /// icmp immediate, that is the target has icmp instructions which can
259 /// compare a register against the immediate without having to materialize
260 /// the immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]261 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]262
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]263 /// getPreIndexedAddressParts - returns true by value, base pointer and
264 /// offset pointer and addressing mode by reference if the node's address
265 /// can be legally represented as pre-indexed load / store address.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]266 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
267 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]268 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]269 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]270
271 /// getPostIndexedAddressParts - returns true by value, base pointer and
272 /// offset pointer and addressing mode by reference if this node can be
273 /// combined with a load / store to form a post-indexed load / store.
274 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]275 SDValue &Base, SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]276 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]277 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]278
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]279 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]280 const APInt &Mask,
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]281 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]282 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]283 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]284 unsigned Depth) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]285
286
Evan Cheng55d42002011-01-08 01:24:27 +0000[diff] [blame]287 virtual bool ExpandInlineAsm(CallInst *CI) const;
288
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]289 ConstraintType getConstraintType(const std::string &Constraint) const;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]290
291 /// Examine constraint string and operand type and determine a weight value.
292 /// The operand object must already have been set up with the operand type.
293 ConstraintWeight getSingleConstraintMatchWeight(
294 AsmOperandInfo &info, const char *constraint) const;
295
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]296 std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]297 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]298 EVT VT) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]299 std::vector<unsigned>
300 getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]301 EVT VT) const;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]302
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]303 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
304 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
305 /// true it means one of the asm constraint of the inline asm instruction
306 /// being processed is 'm'.
307 virtual void LowerAsmOperandForConstraint(SDValue Op,
308 char ConstraintLetter,
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]309 std::vector<SDValue> &Ops,
310 SelectionDAG &DAG) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]311
Dan Gohman419e4f92010-05-11 16:21:03 +0000[diff] [blame]312 const ARMSubtarget* getSubtarget() const {
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]313 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]314 }
315
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]316 /// getRegClassFor - Return the register class that should be used for the
317 /// specified value type.
318 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
319
Bill Wendlingb4202b82009-07-01 18:50:55 +0000[diff] [blame]320 /// getFunctionAlignment - Return the Log2 alignment of this function.
Bill Wendling20c568f2009-06-30 22:38:32 +0000[diff] [blame]321 virtual unsigned getFunctionAlignment(const Function *F) const;
322
Anton Korobeynikovcec36f42010-07-24 21:52:08 +0000[diff] [blame]323 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
324 /// be used for loads / stores from the global.
325 virtual unsigned getMaximalGlobalOffset() const;
326
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]327 /// createFastISel - This method returns a target specific FastISel object,
328 /// or null if the target does not support "fast" ISel.
329 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
330
Evan Cheng1cc39842010-05-20 23:26:43 +0000[diff] [blame]331 Sched::Preference getSchedulingPreference(SDNode *N) const;
332
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]333 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
334 MachineFunction &MF) const;
335
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +0000[diff] [blame]336 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov48e19352009-09-23 19:04:09 +0000[diff] [blame]337 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]338
339 /// isFPImmLegal - Returns true if the target can instruction select the
340 /// specified FP immediate natively. If false, the legalizer will
341 /// materialize the FP immediate as a load from a constant pool.
342 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
343
Bob Wilson65ffec42010-09-21 17:56:22 +0000[diff] [blame]344 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
345 const CallInst &I,
346 unsigned Intrinsic) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]347 protected:
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]348 std::pair<const TargetRegisterClass*, uint8_t>
349 findRepresentativeClass(EVT VT) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]350
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]351 private:
352 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
353 /// make the right decision when generating code for different targets.
354 const ARMSubtarget *Subtarget;
355
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]356 const TargetRegisterInfo *RegInfo;
357
Evan Cheng3ef1c872010-09-10 01:29:16 +0000[diff] [blame]358 const InstrItineraryData *Itins;
359
Bob Wilsond2559bf2009-07-13 18:11:36 +0000[diff] [blame]360 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]361 ///
362 unsigned ARMPCLabelIndex;
363
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]364 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
365 void addDRTypeForNEON(EVT VT);
366 void addQRTypeForNEON(EVT VT);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]367
368 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]369 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]370 SDValue Chain, SDValue &Arg,
371 RegsToPassVector &RegsToPass,
372 CCValAssign &VA, CCValAssign &NextVA,
373 SDValue &StackPtr,
374 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]375 ISD::ArgFlagsTy Flags) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]376 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]377 SDValue &Root, SelectionDAG &DAG,
378 DebugLoc dl) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]379
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]380 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
381 bool isVarArg) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]382 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
383 DebugLoc dl, SelectionDAG &DAG,
384 const CCValAssign &VA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]385 ISD::ArgFlagsTy Flags) const;
Jim Grosbach23ff7cf2010-05-26 20:22:18 +0000[diff] [blame]386 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5eb19512010-05-22 01:06:18 +0000[diff] [blame]387 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbache4ad3872010-10-19 23:27:08 +0000[diff] [blame]388 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha87ded22010-02-08 23:22:00 +0000[diff] [blame]389 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]390 const ARMSubtarget *Subtarget) const;
391 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
392 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
393 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
394 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]395 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]396 SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]397 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]398 SelectionDAG &DAG) const;
399 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
400 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Bill Wendlingde2b1512010-08-11 08:43:16 +0000[diff] [blame]401 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]402 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
403 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng515fe3a2010-07-08 02:08:50 +0000[diff] [blame]404 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng2457f2c2010-05-22 01:47:14 +0000[diff] [blame]405 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]406 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]407 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
408 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemand1fb5832010-08-03 21:31:55 +0000[diff] [blame]409 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Bob Wilson11a1dff2011-01-07 21:37:30 +0000[diff] [blame]410 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
411 const ARMSubtarget *ST) const;
412
413 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola7b73a5d2007-10-19 14:35:17 +0000[diff] [blame]414
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]415 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]416 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]417 const SmallVectorImpl<ISD::InputArg> &Ins,
418 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]419 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]420
421 virtual SDValue
422 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]423 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]424 const SmallVectorImpl<ISD::InputArg> &Ins,
425 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]426 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]427
428 virtual SDValue
Evan Cheng022d9e12010-02-02 23:55:14 +0000[diff] [blame]429 LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]430 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng0c439eb2010-01-27 00:07:07 +0000[diff] [blame]431 bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]432 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]433 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]434 const SmallVectorImpl<ISD::InputArg> &Ins,
435 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]436 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]437
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame^]438 /// HandleByVal - Target-specific cleanup for ByVal support.
439 virtual void HandleByVal(CCState *) const;
440
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]441 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
442 /// for tail call optimization. Targets which want to do tail call
443 /// optimization should implement this function.
444 bool IsEligibleForTailCallOptimization(SDValue Callee,
445 CallingConv::ID CalleeCC,
446 bool isVarArg,
447 bool isCalleeStructRet,
448 bool isCallerStructRet,
449 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]450 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]451 const SmallVectorImpl<ISD::InputArg> &Ins,
452 SelectionDAG& DAG) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]453 virtual SDValue
454 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]455 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]456 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]457 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]458 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]459
Evan Cheng3d2125c2010-11-30 23:55:39 +0000[diff] [blame]460 virtual bool isUsedByReturnOnly(SDNode *N) const;
461
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]462 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]463 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
464 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
465 SelectionDAG &DAG, DebugLoc dl) const;
466
467 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]468
Jim Grosbache801dc42009-12-12 01:40:06 +0000[diff] [blame]469 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
470 MachineBasicBlock *BB,
471 unsigned Size) const;
472 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
473 MachineBasicBlock *BB,
474 unsigned Size,
475 unsigned BinOpcode) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]476
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]477 };
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]478
Owen Anderson36fa3ea2010-11-05 21:57:54 +0000[diff] [blame]479 enum NEONModImmType {
480 VMOVModImm,
481 VMVNModImm,
482 OtherModImm
483 };
484
485
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]486 namespace ARM {
487 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
488 }
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]489}
490
491#endif // ARMISELLOWERING_H