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gerrit-public.fairphone.software / fp2-dev / platform / external / v8 / 097c5b25f8b57b92e6c94f25383a883ff242344f / . / src / compiler / arm / instruction-codes-arm.h
blob: 50fa555eb51a0114d4c424b93b1c42d38e890496 [file] [log] [blame]
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6#define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7
8namespace v8 {
9namespace internal {
10namespace compiler {
11
12// ARM-specific opcodes that specify which assembly sequence to emit.
13// Most opcodes specify a single instruction.
14#define TARGET_ARCH_OPCODE_LIST(V) \
15 V(ArmAdd) \
16 V(ArmAnd) \
17 V(ArmBic) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]18 V(ArmClz) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]19 V(ArmCmp) \
20 V(ArmCmn) \
21 V(ArmTst) \
22 V(ArmTeq) \
23 V(ArmOrr) \
24 V(ArmEor) \
25 V(ArmSub) \
26 V(ArmRsb) \
27 V(ArmMul) \
28 V(ArmMla) \
29 V(ArmMls) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]30 V(ArmSmmul) \
31 V(ArmSmmla) \
32 V(ArmUmull) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]33 V(ArmSdiv) \
34 V(ArmUdiv) \
35 V(ArmMov) \
36 V(ArmMvn) \
37 V(ArmBfc) \
38 V(ArmUbfx) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame^]39 V(ArmSbfx) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]40 V(ArmSxtb) \
41 V(ArmSxth) \
42 V(ArmSxtab) \
43 V(ArmSxtah) \
44 V(ArmUxtb) \
45 V(ArmUxth) \
46 V(ArmUxtab) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame^]47 V(ArmRbit) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]48 V(ArmUxtah) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]49 V(ArmVcmpF32) \
50 V(ArmVaddF32) \
51 V(ArmVsubF32) \
52 V(ArmVmulF32) \
53 V(ArmVmlaF32) \
54 V(ArmVmlsF32) \
55 V(ArmVdivF32) \
56 V(ArmVabsF32) \
57 V(ArmVnegF32) \
58 V(ArmVsqrtF32) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]59 V(ArmVcmpF64) \
60 V(ArmVaddF64) \
61 V(ArmVsubF64) \
62 V(ArmVmulF64) \
63 V(ArmVmlaF64) \
64 V(ArmVmlsF64) \
65 V(ArmVdivF64) \
66 V(ArmVmodF64) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]67 V(ArmVabsF64) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]68 V(ArmVnegF64) \
69 V(ArmVsqrtF64) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]70 V(ArmVrintmF32) \
71 V(ArmVrintmF64) \
72 V(ArmVrintpF32) \
73 V(ArmVrintpF64) \
74 V(ArmVrintzF32) \
75 V(ArmVrintzF64) \
76 V(ArmVrintaF64) \
77 V(ArmVrintnF32) \
78 V(ArmVrintnF64) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]79 V(ArmVcvtF32F64) \
80 V(ArmVcvtF64F32) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame^]81 V(ArmVcvtF32S32) \
82 V(ArmVcvtF32U32) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]83 V(ArmVcvtF64S32) \
84 V(ArmVcvtF64U32) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame^]85 V(ArmVcvtS32F32) \
86 V(ArmVcvtU32F32) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]87 V(ArmVcvtS32F64) \
88 V(ArmVcvtU32F64) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]89 V(ArmVmovLowU32F64) \
90 V(ArmVmovLowF64U32) \
91 V(ArmVmovHighU32F64) \
92 V(ArmVmovHighF64U32) \
93 V(ArmVmovF64U32U32) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]94 V(ArmVldrF32) \
95 V(ArmVstrF32) \
96 V(ArmVldrF64) \
97 V(ArmVstrF64) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]98 V(ArmLdrb) \
99 V(ArmLdrsb) \
100 V(ArmStrb) \
101 V(ArmLdrh) \
102 V(ArmLdrsh) \
103 V(ArmStrh) \
104 V(ArmLdr) \
105 V(ArmStr) \
106 V(ArmPush) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]107 V(ArmPoke)
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]108
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]109// Addressing modes represent the "shape" of inputs to an instruction.
110// Many instructions support multiple addressing modes. Addressing modes
111// are encoded into the InstructionCode of the instruction and tell the
112// code generator after register allocation which assembler method to call.
113#define TARGET_ADDRESSING_MODE_LIST(V) \
114 V(Offset_RI) /* [%r0 + K] */ \
115 V(Offset_RR) /* [%r0 + %r1] */ \
116 V(Operand2_I) /* K */ \
117 V(Operand2_R) /* %r0 */ \
118 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
119 V(Operand2_R_LSL_I) /* %r0 LSL K */ \
120 V(Operand2_R_LSR_I) /* %r0 LSR K */ \
121 V(Operand2_R_ROR_I) /* %r0 ROR K */ \
122 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
123 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
124 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
125 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
126
127} // namespace compiler
128} // namespace internal
129} // namespace v8
130
131#endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_