Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 1 | // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 | // Use of this source code is governed by a BSD-style license that can be |
| 3 | // found in the LICENSE file. |
| 4 | |
| 5 | #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 6 | #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 7 | |
| 8 | namespace v8 { |
| 9 | namespace internal { |
| 10 | namespace compiler { |
| 11 | |
| 12 | // MIPS-specific opcodes that specify which assembly sequence to emit. |
| 13 | // Most opcodes specify a single instruction. |
| 14 | #define TARGET_ARCH_OPCODE_LIST(V) \ |
| 15 | V(MipsAdd) \ |
| 16 | V(MipsAddOvf) \ |
| 17 | V(MipsSub) \ |
| 18 | V(MipsSubOvf) \ |
| 19 | V(MipsMul) \ |
| 20 | V(MipsMulHigh) \ |
| 21 | V(MipsMulHighU) \ |
| 22 | V(MipsDiv) \ |
| 23 | V(MipsDivU) \ |
| 24 | V(MipsMod) \ |
| 25 | V(MipsModU) \ |
| 26 | V(MipsAnd) \ |
| 27 | V(MipsOr) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 28 | V(MipsNor) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 29 | V(MipsXor) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 30 | V(MipsClz) \ |
Ben Murdoch | 097c5b2 | 2016-05-18 11:27:45 +0100 | [diff] [blame] | 31 | V(MipsCtz) \ |
| 32 | V(MipsPopcnt) \ |
Ben Murdoch | c561043 | 2016-08-08 18:44:38 +0100 | [diff] [blame] | 33 | V(MipsLsa) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 34 | V(MipsShl) \ |
| 35 | V(MipsShr) \ |
| 36 | V(MipsSar) \ |
Ben Murdoch | c561043 | 2016-08-08 18:44:38 +0100 | [diff] [blame] | 37 | V(MipsShlPair) \ |
| 38 | V(MipsShrPair) \ |
| 39 | V(MipsSarPair) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 40 | V(MipsExt) \ |
| 41 | V(MipsIns) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 42 | V(MipsRor) \ |
| 43 | V(MipsMov) \ |
| 44 | V(MipsTst) \ |
| 45 | V(MipsCmp) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 46 | V(MipsCmpS) \ |
| 47 | V(MipsAddS) \ |
| 48 | V(MipsSubS) \ |
Ben Murdoch | 61f157c | 2016-09-16 13:49:30 +0100 | [diff] [blame] | 49 | V(MipsSubPreserveNanS) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 50 | V(MipsMulS) \ |
| 51 | V(MipsDivS) \ |
| 52 | V(MipsModS) \ |
| 53 | V(MipsAbsS) \ |
| 54 | V(MipsSqrtS) \ |
| 55 | V(MipsMaxS) \ |
| 56 | V(MipsMinS) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 57 | V(MipsCmpD) \ |
| 58 | V(MipsAddD) \ |
| 59 | V(MipsSubD) \ |
Ben Murdoch | 61f157c | 2016-09-16 13:49:30 +0100 | [diff] [blame] | 60 | V(MipsSubPreserveNanD) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 61 | V(MipsMulD) \ |
| 62 | V(MipsDivD) \ |
| 63 | V(MipsModD) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 64 | V(MipsAbsD) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 65 | V(MipsSqrtD) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 66 | V(MipsMaxD) \ |
| 67 | V(MipsMinD) \ |
Ben Murdoch | c561043 | 2016-08-08 18:44:38 +0100 | [diff] [blame] | 68 | V(MipsAddPair) \ |
| 69 | V(MipsSubPair) \ |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame] | 70 | V(MipsMulPair) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 71 | V(MipsFloat32RoundDown) \ |
| 72 | V(MipsFloat32RoundTruncate) \ |
| 73 | V(MipsFloat32RoundUp) \ |
| 74 | V(MipsFloat32RoundTiesEven) \ |
| 75 | V(MipsFloat64RoundDown) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 76 | V(MipsFloat64RoundTruncate) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 77 | V(MipsFloat64RoundUp) \ |
| 78 | V(MipsFloat64RoundTiesEven) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 79 | V(MipsCvtSD) \ |
| 80 | V(MipsCvtDS) \ |
| 81 | V(MipsTruncWD) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 82 | V(MipsRoundWD) \ |
| 83 | V(MipsFloorWD) \ |
| 84 | V(MipsCeilWD) \ |
| 85 | V(MipsTruncWS) \ |
| 86 | V(MipsRoundWS) \ |
| 87 | V(MipsFloorWS) \ |
| 88 | V(MipsCeilWS) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 89 | V(MipsTruncUwD) \ |
Ben Murdoch | 097c5b2 | 2016-05-18 11:27:45 +0100 | [diff] [blame] | 90 | V(MipsTruncUwS) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 91 | V(MipsCvtDW) \ |
| 92 | V(MipsCvtDUw) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 93 | V(MipsCvtSW) \ |
Ben Murdoch | 097c5b2 | 2016-05-18 11:27:45 +0100 | [diff] [blame] | 94 | V(MipsCvtSUw) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 95 | V(MipsLb) \ |
| 96 | V(MipsLbu) \ |
| 97 | V(MipsSb) \ |
| 98 | V(MipsLh) \ |
| 99 | V(MipsLhu) \ |
| 100 | V(MipsSh) \ |
| 101 | V(MipsLw) \ |
| 102 | V(MipsSw) \ |
| 103 | V(MipsLwc1) \ |
| 104 | V(MipsSwc1) \ |
| 105 | V(MipsLdc1) \ |
| 106 | V(MipsSdc1) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 107 | V(MipsFloat64ExtractLowWord32) \ |
| 108 | V(MipsFloat64ExtractHighWord32) \ |
| 109 | V(MipsFloat64InsertLowWord32) \ |
| 110 | V(MipsFloat64InsertHighWord32) \ |
Ben Murdoch | 61f157c | 2016-09-16 13:49:30 +0100 | [diff] [blame] | 111 | V(MipsFloat64SilenceNaN) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 112 | V(MipsFloat64Max) \ |
| 113 | V(MipsFloat64Min) \ |
| 114 | V(MipsFloat32Max) \ |
| 115 | V(MipsFloat32Min) \ |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 116 | V(MipsPush) \ |
| 117 | V(MipsStoreToStackSlot) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 118 | V(MipsStackClaim) |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 119 | |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 120 | // Addressing modes represent the "shape" of inputs to an instruction. |
| 121 | // Many instructions support multiple addressing modes. Addressing modes |
| 122 | // are encoded into the InstructionCode of the instruction and tell the |
| 123 | // code generator after register allocation which assembler method to call. |
| 124 | // |
| 125 | // We use the following local notation for addressing modes: |
| 126 | // |
| 127 | // R = register |
| 128 | // O = register or stack slot |
| 129 | // D = double register |
| 130 | // I = immediate (handle, external, int32) |
| 131 | // MRI = [register + immediate] |
| 132 | // MRR = [register + register] |
| 133 | // TODO(plind): Add the new r6 address modes. |
| 134 | #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 135 | V(MRI) /* [%r0 + K] */ \ |
| 136 | V(MRR) /* [%r0 + %r1] */ |
| 137 | |
| 138 | |
| 139 | } // namespace compiler |
| 140 | } // namespace internal |
| 141 | } // namespace v8 |
| 142 | |
| 143 | #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |