Channagoud Kadabi | e2ec5a4 | 2013-03-14 16:30:42 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 2 | * |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
Greg Grisco | 6e75477 | 2011-06-23 12:19:39 -0700 | [diff] [blame] | 28 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 29 | #include <string.h> |
| 30 | #include <stdlib.h> |
| 31 | #include <debug.h> |
| 32 | #include <reg.h> |
| 33 | #include "mmc.h" |
| 34 | #include <partition_parser.h> |
| 35 | #include <platform/iomap.h> |
| 36 | #include <platform/timer.h> |
Channagoud Kadabi | 676c2e3 | 2013-04-02 11:39:01 -0700 | [diff] [blame] | 37 | #include <bits.h> |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 38 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 39 | #if MMC_BOOT_ADM |
| 40 | #include "adm.h" |
| 41 | #endif |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 42 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 43 | #if MMC_BOOT_BAM |
| 44 | #include "bam.h" |
| 45 | #include "mmc_dml.h" |
| 46 | #endif |
| 47 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 48 | #ifndef NULL |
| 49 | #define NULL 0 |
| 50 | #endif |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 51 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 52 | #define USEC_PER_SEC (1000000L) |
| 53 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 54 | #define MMC_BOOT_DATA_READ 0 |
| 55 | #define MMC_BOOT_DATA_WRITE 1 |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 56 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 57 | static unsigned int mmc_boot_data_transfer(unsigned int *data_ptr, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 58 | unsigned int data_len, |
| 59 | unsigned char direction); |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 60 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 61 | static unsigned int mmc_boot_fifo_read(unsigned int *data_ptr, |
| 62 | unsigned int data_len); |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 63 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 64 | static unsigned int mmc_boot_fifo_write(unsigned int *data_ptr, |
| 65 | unsigned int data_len); |
Greg Grisco | 6e75477 | 2011-06-23 12:19:39 -0700 | [diff] [blame] | 66 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 67 | static unsigned int mmc_boot_status_error(unsigned mmc_status); |
| 68 | |
| 69 | #if MMC_BOOT_BAM |
| 70 | |
| 71 | void mmc_boot_dml_init(); |
| 72 | |
| 73 | static void mmc_boot_dml_producer_trans_init(unsigned trans_end, |
| 74 | unsigned size); |
| 75 | |
| 76 | static void mmc_boot_dml_consumer_trans_init(); |
| 77 | |
| 78 | static uint32_t mmc_boot_dml_chk_producer_idle(); |
| 79 | |
| 80 | static void mmc_boot_dml_wait_producer_idle(); |
| 81 | static void mmc_boot_dml_wait_consumer_idle(); |
| 82 | static void mmc_boot_dml_reset(); |
| 83 | static int mmc_bam_init(uint32_t bam_base); |
| 84 | static int mmc_bam_transfer_data(); |
| 85 | static unsigned int |
| 86 | mmc_boot_bam_setup_desc(unsigned int *data_ptr, |
| 87 | unsigned int data_len, unsigned char direction); |
| 88 | |
| 89 | |
| 90 | #endif |
| 91 | |
| 92 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 93 | #define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y))) |
Greg Grisco | 6e75477 | 2011-06-23 12:19:39 -0700 | [diff] [blame] | 94 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 95 | /* data access time unit in ns */ |
| 96 | static const unsigned int taac_unit[] = |
| 97 | { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 }; |
| 98 | /* data access time value x 10 */ |
| 99 | static const unsigned int taac_value[] = |
| 100 | { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 }; |
Greg Grisco | 6e75477 | 2011-06-23 12:19:39 -0700 | [diff] [blame] | 101 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 102 | /* data transfer rate in kbit/s */ |
| 103 | static const unsigned int xfer_rate_unit[] = |
| 104 | { 100, 1000, 10000, 100000, 0, 0, 0, 0 }; |
| 105 | /* data transfer rate value x 10*/ |
| 106 | static const unsigned int xfer_rate_value[] = |
| 107 | { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80 }; |
| 108 | |
| 109 | unsigned char mmc_slot = 0; |
| 110 | unsigned int mmc_boot_mci_base = 0; |
| 111 | |
| 112 | static unsigned char ext_csd_buf[512]; |
| 113 | static unsigned char wp_status_buf[8]; |
| 114 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 115 | #if MMC_BOOT_BAM |
| 116 | |
| 117 | static uint32_t mmc_sdc_bam_base[] = |
| 118 | { MSM_SDC1_BAM_BASE, MSM_SDC2_BAM_BASE, MSM_SDC3_BAM_BASE, MSM_SDC4_BAM_BASE }; |
| 119 | |
| 120 | static uint32_t mmc_sdc_dml_base[] = |
| 121 | { MSM_SDC1_DML_BASE, MSM_SDC2_DML_BASE, MSM_SDC3_DML_BASE, MSM_SDC4_DML_BASE }; |
| 122 | |
| 123 | uint32_t dml_base; |
| 124 | static struct bam_instance bam; |
| 125 | |
| 126 | #define MMC_BOOT_BAM_FIFO_SIZE 100 |
| 127 | |
| 128 | #define MMC_BOOT_BAM_READ_PIPE_INDEX 0 |
| 129 | #define MMC_BOOT_BAM_WRITE_PIPE_INDEX 1 |
| 130 | |
| 131 | #define MMC_BOOT_BAM_READ_PIPE 0 |
| 132 | #define MMC_BOOT_BAM_WRITE_PIPE 1 |
| 133 | |
| 134 | /* Align at BAM_DESC_SIZE boundary */ |
| 135 | static struct bam_desc desc_fifo[MMC_BOOT_BAM_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE))); |
| 136 | |
| 137 | #endif |
| 138 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 139 | int mmc_clock_enable_disable(unsigned id, unsigned enable); |
| 140 | int mmc_clock_get_rate(unsigned id); |
| 141 | int mmc_clock_set_rate(unsigned id, unsigned rate); |
| 142 | |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 143 | struct mmc_host mmc_host; |
| 144 | struct mmc_card mmc_card; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 145 | |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 146 | static unsigned int mmc_wp(unsigned int addr, unsigned int size, |
| 147 | unsigned char set_clear_wp); |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 148 | static unsigned int mmc_boot_send_ext_cmd(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 149 | unsigned char *buf); |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 150 | static unsigned int mmc_boot_read_reg(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 151 | unsigned int data_len, |
| 152 | unsigned int command, |
| 153 | unsigned int addr, unsigned int *out); |
| 154 | |
| 155 | unsigned int SWAP_ENDIAN(unsigned int val) |
| 156 | { |
| 157 | return ((val & 0xFF) << 24) | |
| 158 | (((val >> 8) & 0xFF) << 16) | (((val >> 16) & 0xFF) << 8) | (val >> |
| 159 | 24); |
Amol Jadi | 84a546a | 2011-03-02 12:09:11 -0800 | [diff] [blame] | 160 | } |
| 161 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 162 | void mmc_mclk_reg_wr_delay() |
| 163 | { |
| 164 | if (mmc_host.mmc_cont_version) |
| 165 | { |
| 166 | /* Wait for the MMC_BOOT_MCI register write to go through. */ |
| 167 | while(readl(MMC_BOOT_MCI_STATUS2) & MMC_BOOT_MCI_MCLK_REG_WR_ACTIVE); |
| 168 | } |
| 169 | else |
| 170 | udelay((1 + ((3 * USEC_PER_SEC) / (mmc_host.mclk_rate? mmc_host.mclk_rate : MMC_CLK_400KHZ)))); |
| 171 | } |
| 172 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 173 | /* Sets a timeout for read operation. |
| 174 | */ |
| 175 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 176 | mmc_boot_set_read_timeout(struct mmc_host *host, |
| 177 | struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 178 | { |
| 179 | unsigned int timeout_ns = 0; |
Neeti Desai | 5f26aff | 2011-09-30 10:27:40 -0700 | [diff] [blame] | 180 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 181 | if ((host == NULL) || (card == NULL)) { |
| 182 | return MMC_BOOT_E_INVAL; |
| 183 | } |
| 184 | |
| 185 | if ((card->type == MMC_BOOT_TYPE_MMCHC) |
| 186 | || (card->type == MMC_BOOT_TYPE_SDHC)) { |
| 187 | card->rd_timeout_ns = 100000000; |
| 188 | } else if ((card->type == MMC_BOOT_TYPE_STD_SD) |
| 189 | || (card->type == MMC_BOOT_TYPE_STD_MMC)) { |
| 190 | timeout_ns = 10 * ((card->csd.taac_ns) + |
| 191 | (card->csd.nsac_clk_cycle / |
| 192 | (host->mclk_rate / 1000000000))); |
| 193 | card->rd_timeout_ns = timeout_ns; |
| 194 | } else { |
| 195 | return MMC_BOOT_E_NOT_SUPPORTED; |
| 196 | } |
| 197 | |
| 198 | dprintf(SPEW, " Read timeout set: %d ns\n", card->rd_timeout_ns); |
| 199 | |
| 200 | return MMC_BOOT_E_SUCCESS; |
Neeti Desai | 5f26aff | 2011-09-30 10:27:40 -0700 | [diff] [blame] | 201 | } |
| 202 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 203 | /* Sets a timeout for write operation. |
| 204 | */ |
| 205 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 206 | mmc_boot_set_write_timeout(struct mmc_host *host, |
| 207 | struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 208 | { |
| 209 | unsigned int timeout_ns = 0; |
| 210 | |
| 211 | if ((host == NULL) || (card == NULL)) { |
| 212 | return MMC_BOOT_E_INVAL; |
| 213 | } |
| 214 | |
| 215 | if ((card->type == MMC_BOOT_TYPE_MMCHC) |
| 216 | || (card->type == MMC_BOOT_TYPE_SDHC)) { |
| 217 | card->wr_timeout_ns = 100000000; |
| 218 | } else if (card->type == MMC_BOOT_TYPE_STD_SD |
| 219 | || (card->type == MMC_BOOT_TYPE_STD_MMC)) { |
| 220 | timeout_ns = 10 * ((card->csd.taac_ns) + |
| 221 | (card->csd.nsac_clk_cycle / |
| 222 | (host->mclk_rate / 1000000000))); |
| 223 | timeout_ns = timeout_ns << card->csd.r2w_factor; |
| 224 | card->wr_timeout_ns = timeout_ns; |
| 225 | } else { |
| 226 | return MMC_BOOT_E_NOT_SUPPORTED; |
| 227 | } |
| 228 | |
| 229 | dprintf(SPEW, " Write timeout set: %d ns\n", card->wr_timeout_ns); |
| 230 | |
| 231 | return MMC_BOOT_E_SUCCESS; |
| 232 | } |
| 233 | |
| 234 | /* |
| 235 | * Decodes CSD response received from the card. Note that we have defined only |
| 236 | * few of the CSD elements in csd structure. We'll only decode those values. |
| 237 | */ |
| 238 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 239 | mmc_boot_decode_and_save_csd(struct mmc_card *card, unsigned int *raw_csd) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 240 | { |
| 241 | unsigned int mmc_sizeof = 0; |
| 242 | unsigned int mmc_unit = 0; |
| 243 | unsigned int mmc_value = 0; |
| 244 | unsigned int mmc_temp = 0; |
| 245 | |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 246 | struct mmc_csd mmc_csd; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 247 | |
| 248 | if ((card == NULL) || (raw_csd == NULL)) { |
| 249 | return MMC_BOOT_E_INVAL; |
| 250 | } |
| 251 | |
| 252 | mmc_sizeof = sizeof(unsigned int) * 8; |
| 253 | |
| 254 | mmc_csd.cmmc_structure = UNPACK_BITS(raw_csd, 126, 2, mmc_sizeof); |
| 255 | |
| 256 | if ((card->type == MMC_BOOT_TYPE_SDHC) |
| 257 | || (card->type == MMC_BOOT_TYPE_STD_SD)) { |
| 258 | /* Parse CSD according to SD card spec. */ |
| 259 | |
| 260 | /* CSD register is little bit differnet for CSD version 2.0 High Capacity |
| 261 | * and CSD version 1.0/2.0 Standard memory cards. In Version 2.0 some of |
| 262 | * the fields have fixed values and it's not necessary for host to refer |
| 263 | * these fields in CSD sent by card */ |
| 264 | |
| 265 | if (mmc_csd.cmmc_structure == 1) { |
| 266 | /* CSD Version 2.0 */ |
| 267 | mmc_csd.card_cmd_class = |
| 268 | UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof); |
| 269 | mmc_csd.write_blk_len = 512; /* Fixed value is 9 = 2^9 = 512 */ |
| 270 | mmc_csd.read_blk_len = 512; /* Fixed value is 9 = 512 */ |
| 271 | mmc_csd.r2w_factor = 0x2; /* Fixed value: 010b */ |
| 272 | mmc_csd.c_size_mult = 0; /* not there in version 2.0 */ |
| 273 | mmc_csd.c_size = |
| 274 | UNPACK_BITS(raw_csd, 48, 22, mmc_sizeof); |
| 275 | mmc_csd.nsac_clk_cycle = |
| 276 | UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100; |
| 277 | |
| 278 | //TODO: Investigate the nsac and taac. Spec suggests not using this for timeouts. |
| 279 | |
| 280 | mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof); |
| 281 | mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof); |
| 282 | mmc_csd.taac_ns = |
| 283 | (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10; |
| 284 | |
| 285 | mmc_csd.erase_blk_len = 1; |
| 286 | mmc_csd.read_blk_misalign = 0; |
| 287 | mmc_csd.write_blk_misalign = 0; |
| 288 | mmc_csd.read_blk_partial = 0; |
| 289 | mmc_csd.write_blk_partial = 0; |
| 290 | |
| 291 | mmc_unit = UNPACK_BITS(raw_csd, 96, 3, mmc_sizeof); |
| 292 | mmc_value = UNPACK_BITS(raw_csd, 99, 4, mmc_sizeof); |
| 293 | mmc_csd.tran_speed = |
| 294 | (xfer_rate_value[mmc_value] * |
| 295 | xfer_rate_unit[mmc_unit]) / 10; |
| 296 | |
| 297 | mmc_csd.wp_grp_size = 0x0; |
| 298 | mmc_csd.wp_grp_enable = 0x0; |
| 299 | mmc_csd.perm_wp = |
| 300 | UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof); |
| 301 | mmc_csd.temp_wp = |
| 302 | UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof); |
| 303 | |
| 304 | /* Calculate the card capcity */ |
| 305 | card->capacity = (1 + mmc_csd.c_size) * 512 * 1024; |
| 306 | } else { |
| 307 | /* CSD Version 1.0 */ |
| 308 | mmc_csd.card_cmd_class = |
| 309 | UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof); |
| 310 | |
| 311 | mmc_temp = UNPACK_BITS(raw_csd, 22, 4, mmc_sizeof); |
| 312 | mmc_csd.write_blk_len = (mmc_temp > 8 |
| 313 | && mmc_temp < |
| 314 | 12) ? (1 << mmc_temp) : 512; |
| 315 | |
| 316 | mmc_temp = UNPACK_BITS(raw_csd, 80, 4, mmc_sizeof); |
| 317 | mmc_csd.read_blk_len = (mmc_temp > 8 |
| 318 | && mmc_temp < |
| 319 | 12) ? (1 << mmc_temp) : 512; |
| 320 | |
| 321 | mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof); |
| 322 | mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof); |
| 323 | mmc_csd.taac_ns = |
| 324 | (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10; |
| 325 | |
| 326 | mmc_unit = UNPACK_BITS(raw_csd, 96, 3, mmc_sizeof); |
| 327 | mmc_value = UNPACK_BITS(raw_csd, 99, 4, mmc_sizeof); |
| 328 | mmc_csd.tran_speed = |
| 329 | (xfer_rate_value[mmc_value] * |
| 330 | xfer_rate_unit[mmc_unit]) / 10; |
| 331 | |
| 332 | mmc_csd.nsac_clk_cycle = |
| 333 | UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100; |
| 334 | |
| 335 | mmc_csd.r2w_factor = |
| 336 | UNPACK_BITS(raw_csd, 26, 3, mmc_sizeof); |
| 337 | mmc_csd.sector_size = |
| 338 | UNPACK_BITS(raw_csd, 39, 7, mmc_sizeof) + 1; |
| 339 | |
| 340 | mmc_csd.erase_blk_len = |
| 341 | UNPACK_BITS(raw_csd, 46, 1, mmc_sizeof); |
| 342 | mmc_csd.read_blk_misalign = |
| 343 | UNPACK_BITS(raw_csd, 77, 1, mmc_sizeof); |
| 344 | mmc_csd.write_blk_misalign = |
| 345 | UNPACK_BITS(raw_csd, 78, 1, mmc_sizeof); |
| 346 | mmc_csd.read_blk_partial = |
| 347 | UNPACK_BITS(raw_csd, 79, 1, mmc_sizeof); |
| 348 | mmc_csd.write_blk_partial = |
| 349 | UNPACK_BITS(raw_csd, 21, 1, mmc_sizeof); |
| 350 | |
| 351 | mmc_csd.c_size_mult = |
| 352 | UNPACK_BITS(raw_csd, 47, 3, mmc_sizeof); |
| 353 | mmc_csd.c_size = |
| 354 | UNPACK_BITS(raw_csd, 62, 12, mmc_sizeof); |
| 355 | mmc_csd.wp_grp_size = |
| 356 | UNPACK_BITS(raw_csd, 32, 7, mmc_sizeof); |
| 357 | mmc_csd.wp_grp_enable = |
| 358 | UNPACK_BITS(raw_csd, 31, 1, mmc_sizeof); |
| 359 | mmc_csd.perm_wp = |
| 360 | UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof); |
| 361 | mmc_csd.temp_wp = |
| 362 | UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof); |
| 363 | |
| 364 | /* Calculate the card capacity */ |
| 365 | mmc_temp = |
| 366 | (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size + |
| 367 | 1); |
| 368 | card->capacity = mmc_temp * mmc_csd.read_blk_len; |
| 369 | } |
| 370 | } else { |
| 371 | /* Parse CSD according to MMC card spec. */ |
| 372 | mmc_csd.spec_vers = UNPACK_BITS(raw_csd, 122, 4, mmc_sizeof); |
| 373 | mmc_csd.card_cmd_class = |
| 374 | UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof); |
| 375 | mmc_csd.write_blk_len = |
| 376 | 1 << UNPACK_BITS(raw_csd, 22, 4, mmc_sizeof); |
| 377 | mmc_csd.read_blk_len = |
| 378 | 1 << UNPACK_BITS(raw_csd, 80, 4, mmc_sizeof); |
| 379 | mmc_csd.r2w_factor = UNPACK_BITS(raw_csd, 26, 3, mmc_sizeof); |
| 380 | mmc_csd.c_size_mult = UNPACK_BITS(raw_csd, 47, 3, mmc_sizeof); |
| 381 | mmc_csd.c_size = UNPACK_BITS(raw_csd, 62, 12, mmc_sizeof); |
| 382 | mmc_csd.nsac_clk_cycle = |
| 383 | UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100; |
| 384 | |
| 385 | mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof); |
| 386 | mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof); |
| 387 | mmc_csd.taac_ns = |
| 388 | (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10; |
| 389 | |
| 390 | mmc_csd.read_blk_misalign = |
| 391 | UNPACK_BITS(raw_csd, 77, 1, mmc_sizeof); |
| 392 | mmc_csd.write_blk_misalign = |
| 393 | UNPACK_BITS(raw_csd, 78, 1, mmc_sizeof); |
| 394 | mmc_csd.read_blk_partial = |
| 395 | UNPACK_BITS(raw_csd, 79, 1, mmc_sizeof); |
| 396 | mmc_csd.write_blk_partial = |
| 397 | UNPACK_BITS(raw_csd, 21, 1, mmc_sizeof); |
| 398 | mmc_csd.tran_speed = 0x00; /* Ignore -- no use of this value. */ |
| 399 | |
| 400 | mmc_csd.erase_grp_size = |
| 401 | UNPACK_BITS(raw_csd, 42, 5, mmc_sizeof); |
| 402 | mmc_csd.erase_grp_mult = |
| 403 | UNPACK_BITS(raw_csd, 37, 5, mmc_sizeof); |
| 404 | mmc_csd.wp_grp_size = UNPACK_BITS(raw_csd, 32, 5, mmc_sizeof); |
| 405 | mmc_csd.wp_grp_enable = UNPACK_BITS(raw_csd, 31, 1, mmc_sizeof); |
| 406 | mmc_csd.perm_wp = UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof); |
| 407 | mmc_csd.temp_wp = UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof); |
| 408 | |
| 409 | /* Calculate the card capcity */ |
| 410 | if (mmc_csd.c_size != 0xFFF) { |
| 411 | /* For cards less than or equal to 2GB */ |
| 412 | mmc_temp = |
| 413 | (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size + |
| 414 | 1); |
| 415 | card->capacity = mmc_temp * mmc_csd.read_blk_len; |
| 416 | } else { |
| 417 | /* For cards greater than 2GB, Ext CSD register's SEC_COUNT |
| 418 | * is used to calculate the size. |
| 419 | */ |
| 420 | unsigned long long sec_count; |
| 421 | |
| 422 | sec_count = (ext_csd_buf[215] << 24) | |
| 423 | (ext_csd_buf[214] << 16) | |
| 424 | (ext_csd_buf[213] << 8) | ext_csd_buf[212]; |
| 425 | |
| 426 | card->capacity = sec_count * 512; |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | /* save the information in card structure */ |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 431 | memcpy((struct mmc_csd *)&card->csd, |
| 432 | (struct mmc_csd *)&mmc_csd, sizeof(struct mmc_csd)); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 433 | |
| 434 | dprintf(SPEW, "Decoded CSD fields:\n"); |
| 435 | dprintf(SPEW, "cmmc_structure: %d\n", mmc_csd.cmmc_structure); |
| 436 | dprintf(SPEW, "card_cmd_class: %x\n", mmc_csd.card_cmd_class); |
| 437 | dprintf(SPEW, "write_blk_len: %d\n", mmc_csd.write_blk_len); |
| 438 | dprintf(SPEW, "read_blk_len: %d\n", mmc_csd.read_blk_len); |
| 439 | dprintf(SPEW, "r2w_factor: %d\n", mmc_csd.r2w_factor); |
| 440 | dprintf(SPEW, "sector_size: %d\n", mmc_csd.sector_size); |
| 441 | dprintf(SPEW, "c_size_mult:%d\n", mmc_csd.c_size_mult); |
| 442 | dprintf(SPEW, "c_size: %d\n", mmc_csd.c_size); |
| 443 | dprintf(SPEW, "nsac_clk_cycle: %d\n", mmc_csd.nsac_clk_cycle); |
| 444 | dprintf(SPEW, "taac_ns: %d\n", mmc_csd.taac_ns); |
| 445 | dprintf(SPEW, "tran_speed: %d kbps\n", mmc_csd.tran_speed); |
| 446 | dprintf(SPEW, "erase_blk_len: %d\n", mmc_csd.erase_blk_len); |
| 447 | dprintf(SPEW, "read_blk_misalign: %d\n", mmc_csd.read_blk_misalign); |
| 448 | dprintf(SPEW, "write_blk_misalign: %d\n", mmc_csd.write_blk_misalign); |
| 449 | dprintf(SPEW, "read_blk_partial: %d\n", mmc_csd.read_blk_partial); |
| 450 | dprintf(SPEW, "write_blk_partial: %d\n", mmc_csd.write_blk_partial); |
| 451 | dprintf(SPEW, "Card Capacity: %llu Bytes\n", card->capacity); |
| 452 | |
| 453 | return MMC_BOOT_E_SUCCESS; |
| 454 | } |
| 455 | |
| 456 | /* |
| 457 | * Decode CID sent by the card. |
| 458 | */ |
| 459 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 460 | mmc_boot_decode_and_save_cid(struct mmc_card *card, unsigned int *raw_cid) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 461 | { |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 462 | struct mmc_cid mmc_cid; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 463 | unsigned int mmc_sizeof = 0; |
| 464 | int i = 0; |
| 465 | |
| 466 | if ((card == NULL) || (raw_cid == NULL)) { |
| 467 | return MMC_BOOT_E_INVAL; |
| 468 | } |
| 469 | |
| 470 | mmc_sizeof = sizeof(unsigned int) * 8; |
| 471 | |
| 472 | if ((card->type == MMC_BOOT_TYPE_SDHC) |
| 473 | || (card->type == MMC_BOOT_TYPE_STD_SD)) { |
| 474 | mmc_cid.mid = UNPACK_BITS(raw_cid, 120, 8, mmc_sizeof); |
| 475 | mmc_cid.oid = UNPACK_BITS(raw_cid, 104, 16, mmc_sizeof); |
| 476 | |
| 477 | for (i = 0; i < 5; i++) { |
| 478 | mmc_cid.pnm[i] = (unsigned char)UNPACK_BITS(raw_cid, |
| 479 | (104 - |
| 480 | 8 * (i + |
| 481 | 1)), |
| 482 | 8, |
| 483 | mmc_sizeof); |
| 484 | } |
| 485 | mmc_cid.pnm[5] = 0; |
| 486 | mmc_cid.pnm[6] = 0; |
| 487 | |
| 488 | mmc_cid.prv = UNPACK_BITS(raw_cid, 56, 8, mmc_sizeof); |
| 489 | mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 32, mmc_sizeof); |
| 490 | mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof); |
| 491 | mmc_cid.year = UNPACK_BITS(raw_cid, 12, 8, mmc_sizeof); |
| 492 | mmc_cid.year += 2000; |
| 493 | } else { |
| 494 | mmc_cid.mid = UNPACK_BITS(raw_cid, 120, 8, mmc_sizeof); |
| 495 | mmc_cid.oid = UNPACK_BITS(raw_cid, 104, 16, mmc_sizeof); |
| 496 | |
| 497 | for (i = 0; i < 6; i++) { |
| 498 | mmc_cid.pnm[i] = (unsigned char)UNPACK_BITS(raw_cid, |
| 499 | (104 - |
| 500 | 8 * (i + |
| 501 | 1)), |
| 502 | 8, |
| 503 | mmc_sizeof); |
| 504 | } |
| 505 | mmc_cid.pnm[6] = 0; |
| 506 | |
| 507 | mmc_cid.prv = UNPACK_BITS(raw_cid, 48, 8, mmc_sizeof); |
| 508 | mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 32, mmc_sizeof); |
| 509 | mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof); |
| 510 | mmc_cid.year = UNPACK_BITS(raw_cid, 12, 4, mmc_sizeof); |
| 511 | mmc_cid.year += 1997; |
| 512 | } |
| 513 | |
| 514 | /* save it in card database */ |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 515 | memcpy((struct mmc_cid *)&card->cid, |
| 516 | (struct mmc_cid *)&mmc_cid, sizeof(struct mmc_cid)); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 517 | |
| 518 | dprintf(SPEW, "Decoded CID fields:\n"); |
| 519 | dprintf(SPEW, "Manufacturer ID: %x\n", mmc_cid.mid); |
| 520 | dprintf(SPEW, "OEM ID: 0x%x\n", mmc_cid.oid); |
| 521 | dprintf(SPEW, "Product Name: %s\n", mmc_cid.pnm); |
| 522 | dprintf(SPEW, "Product revision: %d.%d\n", (mmc_cid.prv >> 4), |
| 523 | (mmc_cid.prv & 0xF)); |
| 524 | dprintf(SPEW, "Product serial number: %X\n", mmc_cid.psn); |
| 525 | dprintf(SPEW, "Manufacturing date: %d %d\n", mmc_cid.month, |
| 526 | mmc_cid.year); |
| 527 | |
| 528 | return MMC_BOOT_E_SUCCESS; |
| 529 | } |
| 530 | |
| 531 | /* |
| 532 | * Sends specified command to a card and waits for a response. |
| 533 | */ |
| 534 | static unsigned int mmc_boot_send_command(struct mmc_boot_command *cmd) |
| 535 | { |
| 536 | unsigned int mmc_cmd = 0; |
| 537 | unsigned int mmc_status = 0; |
| 538 | unsigned int mmc_resp = 0; |
| 539 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS; |
| 540 | unsigned int cmd_index = 0; |
| 541 | int i = 0; |
| 542 | |
| 543 | /* basic check */ |
| 544 | if (cmd == NULL) { |
| 545 | return MMC_BOOT_E_INVAL; |
| 546 | } |
| 547 | |
| 548 | /* 1. Write command argument to MMC_BOOT_MCI_ARGUMENT register */ |
| 549 | writel(cmd->argument, MMC_BOOT_MCI_ARGUMENT); |
| 550 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 551 | /* 2. Set appropriate fields and write MMC_BOOT_MCI_CMD */ |
| 552 | /* 2a. Write command index in CMD_INDEX field */ |
| 553 | cmd_index = cmd->cmd_index; |
| 554 | mmc_cmd |= cmd->cmd_index; |
Channagoud Kadabi | 54dd531 | 2013-06-18 18:31:44 -0700 | [diff] [blame] | 555 | /* 2b. Set RESPONSE bit to 1 for all cmds except CMD0 |
| 556 | * And dont set RESPONSE bit for commands with no response |
| 557 | */ |
| 558 | if (cmd_index != CMD0_GO_IDLE_STATE && cmd->resp_type != MMC_BOOT_RESP_NONE) { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 559 | mmc_cmd |= MMC_BOOT_MCI_CMD_RESPONSE; |
| 560 | } |
| 561 | |
| 562 | /* 2c. Set LONGRESP bit to 1 for CMD2, CMD9 and CMD10 */ |
| 563 | if (IS_RESP_136_BITS(cmd->resp_type)) { |
| 564 | mmc_cmd |= MMC_BOOT_MCI_CMD_LONGRSP; |
| 565 | } |
| 566 | |
| 567 | /* 2d. Set INTERRUPT bit to 1 to disable command timeout */ |
| 568 | |
| 569 | /* 2e. Set PENDING bit to 1 for CMD12 in the beginning of stream |
| 570 | mode data transfer */ |
| 571 | if (cmd->xfer_mode == MMC_BOOT_XFER_MODE_STREAM) { |
| 572 | mmc_cmd |= MMC_BOOT_MCI_CMD_PENDING; |
| 573 | } |
| 574 | |
| 575 | /* 2f. Set ENABLE bit to 1 */ |
| 576 | mmc_cmd |= MMC_BOOT_MCI_CMD_ENABLE; |
| 577 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 578 | /* 2g. Set PROG_ENA bit */ |
| 579 | if (cmd->prg_enabled) { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 580 | mmc_cmd |= MMC_BOOT_MCI_CMD_PROG_ENA; |
| 581 | } |
| 582 | |
| 583 | /* 2h. Set MCIABORT bit to 1 for CMD12 when working with SDIO card */ |
| 584 | /* 2i. Set CCS_ENABLE bit to 1 for CMD61 when Command Completion Signal |
| 585 | of CE-ATA device is enabled */ |
| 586 | |
| 587 | /* 2j. clear all static status bits */ |
| 588 | writel(MMC_BOOT_MCI_STATIC_STATUS, MMC_BOOT_MCI_CLEAR); |
| 589 | |
| 590 | /* 2k. Write to MMC_BOOT_MCI_CMD register */ |
| 591 | writel(mmc_cmd, MMC_BOOT_MCI_CMD); |
| 592 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 593 | /* Wait for the MMC_BOOT_MCI_CMD write to go through. */ |
| 594 | mmc_mclk_reg_wr_delay(); |
| 595 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 596 | dprintf(SPEW, "Command sent: CMD%d MCI_CMD_REG:%x MCI_ARG:%x\n", |
| 597 | cmd_index, mmc_cmd, cmd->argument); |
| 598 | |
| 599 | /* 3. Wait for interrupt or poll on the following bits of MCI_STATUS |
| 600 | register */ |
| 601 | do { |
| 602 | /* 3a. Read MCI_STATUS register */ |
| 603 | while (readl(MMC_BOOT_MCI_STATUS) & |
| 604 | MMC_BOOT_MCI_STAT_CMD_ACTIVE) ; |
| 605 | |
| 606 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 607 | |
| 608 | /* 3b. CMD_SENT bit supposed to be set to 1 only after CMD0 is sent - |
| 609 | no response required. */ |
| 610 | if ((cmd->resp_type == MMC_BOOT_RESP_NONE) && |
| 611 | (mmc_status & MMC_BOOT_MCI_STAT_CMD_SENT)) { |
| 612 | break; |
| 613 | } |
| 614 | |
| 615 | /* 3c. If CMD_TIMEOUT bit is set then no response was received */ |
| 616 | else if (mmc_status & MMC_BOOT_MCI_STAT_CMD_TIMEOUT) { |
| 617 | mmc_return = MMC_BOOT_E_TIMEOUT; |
| 618 | break; |
| 619 | } |
| 620 | /* 3d. If CMD_RESPONSE_END bit is set to 1 then command's response was |
| 621 | received and CRC check passed |
| 622 | Spcial case for ACMD41: it seems to always fail CRC even if |
| 623 | the response is valid |
| 624 | */ |
| 625 | else if ((mmc_status & MMC_BOOT_MCI_STAT_CMD_RESP_END) |
| 626 | || (cmd_index == CMD1_SEND_OP_COND) |
| 627 | || (cmd_index == CMD8_SEND_IF_COND)) { |
| 628 | /* 3i. Read MCI_RESP_CMD register to verify that response index is |
| 629 | equal to command index */ |
| 630 | mmc_resp = readl(MMC_BOOT_MCI_RESP_CMD) & 0x3F; |
| 631 | |
| 632 | /* However, long response does not contain the command index field. |
| 633 | * In that case, response index field must be set to 111111b (0x3F) */ |
| 634 | if ((mmc_resp == cmd_index) || |
| 635 | (cmd->resp_type == MMC_BOOT_RESP_R2 || |
| 636 | cmd->resp_type == MMC_BOOT_RESP_R3 || |
| 637 | cmd->resp_type == MMC_BOOT_RESP_R6 || |
| 638 | cmd->resp_type == MMC_BOOT_RESP_R7)) { |
| 639 | /* 3j. If resp index is equal to cmd index, read command resp |
| 640 | from MCI_RESPn registers |
| 641 | - MCI_RESP0/1/2/3 for CMD2/9/10 |
| 642 | - MCI_RESP0 for all other registers */ |
| 643 | if (IS_RESP_136_BITS(cmd->resp_type)) { |
| 644 | for (i = 0; i < 4; i++) { |
| 645 | cmd->resp[3 - i] = |
| 646 | readl(MMC_BOOT_MCI_RESP_0 + |
| 647 | (i * 4)); |
| 648 | |
| 649 | } |
| 650 | } else { |
| 651 | cmd->resp[0] = |
| 652 | readl(MMC_BOOT_MCI_RESP_0); |
| 653 | } |
| 654 | } else { |
| 655 | /* command index mis-match */ |
| 656 | mmc_return = MMC_BOOT_E_CMD_INDX_MISMATCH; |
| 657 | } |
| 658 | |
| 659 | dprintf(SPEW, "Command response received: %X\n", |
| 660 | cmd->resp[0]); |
| 661 | break; |
| 662 | } |
| 663 | |
| 664 | /* 3e. If CMD_CRC_FAIL bit is set to 1 then cmd's response was recvd, |
| 665 | but CRC check failed. */ |
| 666 | else if ((mmc_status & MMC_BOOT_MCI_STAT_CMD_CRC_FAIL)) { |
| 667 | if (cmd_index == ACMD41_SEND_OP_COND) { |
| 668 | cmd->resp[0] = readl(MMC_BOOT_MCI_RESP_0); |
| 669 | } else |
| 670 | mmc_return = MMC_BOOT_E_CRC_FAIL; |
| 671 | break; |
| 672 | } |
| 673 | |
| 674 | } |
| 675 | while (1); |
| 676 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 677 | |
| 678 | /* 2k. Write to MMC_BOOT_MCI_CMD register */ |
| 679 | writel(0, MMC_BOOT_MCI_CMD); |
| 680 | |
| 681 | /* Wait for the MMC_BOOT_MCI_CMD write to go through. */ |
| 682 | mmc_mclk_reg_wr_delay(); |
| 683 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 684 | return mmc_return; |
| 685 | } |
| 686 | |
| 687 | /* |
| 688 | * Reset all the cards to idle condition (CMD 0) |
| 689 | */ |
| 690 | static unsigned int mmc_boot_reset_cards(void) |
| 691 | { |
| 692 | struct mmc_boot_command cmd; |
| 693 | |
| 694 | memset((struct mmc_boot_command *)&cmd, 0, |
| 695 | sizeof(struct mmc_boot_command)); |
| 696 | |
| 697 | cmd.cmd_index = CMD0_GO_IDLE_STATE; |
| 698 | cmd.argument = 0; // stuff bits - ignored |
| 699 | cmd.cmd_type = MMC_BOOT_CMD_BCAST; |
| 700 | cmd.resp_type = MMC_BOOT_RESP_NONE; |
| 701 | |
| 702 | /* send command */ |
| 703 | return mmc_boot_send_command(&cmd); |
| 704 | } |
| 705 | |
| 706 | /* |
| 707 | * Send CMD1 to know whether the card supports host VDD profile or not. |
| 708 | */ |
| 709 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 710 | mmc_boot_send_op_cond(struct mmc_host *host, struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 711 | { |
| 712 | struct mmc_boot_command cmd; |
| 713 | unsigned int mmc_resp = 0; |
| 714 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 715 | |
| 716 | /* basic check */ |
| 717 | if ((host == NULL) || (card == NULL)) { |
| 718 | return MMC_BOOT_E_INVAL; |
| 719 | } |
| 720 | |
| 721 | memset((struct mmc_boot_command *)&cmd, 0, |
| 722 | sizeof(struct mmc_boot_command)); |
| 723 | |
| 724 | /* CMD1 format: |
| 725 | * [31] Busy bit |
| 726 | * [30:29] Access mode |
| 727 | * [28:24] reserved |
| 728 | * [23:15] 2.7-3.6 |
| 729 | * [14:8] 2.0-2.6 |
| 730 | * [7] 1.7-1.95 |
| 731 | * [6:0] reserved |
| 732 | */ |
| 733 | |
| 734 | cmd.cmd_index = CMD1_SEND_OP_COND; |
| 735 | cmd.argument = host->ocr; |
| 736 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 737 | cmd.resp_type = MMC_BOOT_RESP_R3; |
| 738 | |
| 739 | mmc_ret = mmc_boot_send_command(&cmd); |
| 740 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 741 | return mmc_ret; |
| 742 | } |
| 743 | |
| 744 | /* Now it's time to examine response */ |
| 745 | mmc_resp = cmd.resp[0]; |
| 746 | |
| 747 | /* Response contains card's ocr. Update card's information */ |
| 748 | card->ocr = mmc_resp; |
| 749 | |
| 750 | /* Check the response for busy status */ |
| 751 | if (!(mmc_resp & MMC_BOOT_OCR_BUSY)) { |
| 752 | return MMC_BOOT_E_CARD_BUSY; |
| 753 | } |
| 754 | |
| 755 | if (mmc_resp & MMC_BOOT_OCR_SEC_MODE) { |
| 756 | card->type = MMC_BOOT_TYPE_MMCHC; |
| 757 | } else { |
| 758 | card->type = MMC_BOOT_TYPE_STD_MMC; |
| 759 | } |
| 760 | return MMC_BOOT_E_SUCCESS; |
| 761 | } |
| 762 | |
| 763 | /* |
| 764 | * Request any card to send its uniquie card identification (CID) number (CMD2). |
| 765 | */ |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 766 | static unsigned int mmc_boot_all_send_cid(struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 767 | { |
| 768 | struct mmc_boot_command cmd; |
| 769 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 770 | |
| 771 | /* basic check */ |
| 772 | if (card == NULL) { |
| 773 | return MMC_BOOT_E_INVAL; |
| 774 | } |
| 775 | |
| 776 | memset((struct mmc_boot_command *)&cmd, 0, |
| 777 | sizeof(struct mmc_boot_command)); |
| 778 | |
| 779 | /* CMD2 Format: |
| 780 | * [31:0] stuff bits |
| 781 | */ |
| 782 | cmd.cmd_index = CMD2_ALL_SEND_CID; |
| 783 | cmd.argument = 0; |
| 784 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 785 | cmd.resp_type = MMC_BOOT_RESP_R2; |
| 786 | |
| 787 | /* send command */ |
| 788 | mmc_ret = mmc_boot_send_command(&cmd); |
| 789 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 790 | return mmc_ret; |
| 791 | } |
| 792 | |
| 793 | /* Response contains card's 128 bits CID register */ |
| 794 | mmc_ret = mmc_boot_decode_and_save_cid(card, cmd.resp); |
| 795 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 796 | return mmc_ret; |
| 797 | } |
| 798 | return MMC_BOOT_E_SUCCESS; |
| 799 | } |
| 800 | |
| 801 | /* |
| 802 | * Ask any card to send it's relative card address (RCA).This RCA number is |
| 803 | * shorter than CID and is used by the host to address the card in future (CMD3) |
| 804 | */ |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 805 | static unsigned int mmc_boot_send_relative_address(struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 806 | { |
| 807 | struct mmc_boot_command cmd; |
| 808 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 809 | |
| 810 | /* basic check */ |
| 811 | if (card == NULL) { |
| 812 | return MMC_BOOT_E_INVAL; |
| 813 | } |
| 814 | |
| 815 | memset((struct mmc_boot_command *)&cmd, 0, |
| 816 | sizeof(struct mmc_boot_command)); |
| 817 | |
| 818 | /* CMD3 Format: |
| 819 | * [31:0] stuff bits |
| 820 | */ |
| 821 | if (card->type == MMC_BOOT_TYPE_SDHC |
| 822 | || card->type == MMC_BOOT_TYPE_STD_SD) { |
| 823 | cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR; |
| 824 | cmd.argument = 0; |
| 825 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 826 | cmd.resp_type = MMC_BOOT_RESP_R6; |
| 827 | |
| 828 | /* send command */ |
| 829 | mmc_ret = mmc_boot_send_command(&cmd); |
| 830 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 831 | return mmc_ret; |
| 832 | } |
| 833 | /* For sD, card will send RCA. Store it */ |
| 834 | card->rca = (cmd.resp[0] >> 16); |
| 835 | } else { |
| 836 | cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR; |
| 837 | cmd.argument = (MMC_RCA << 16); |
| 838 | card->rca = (cmd.argument >> 16); |
| 839 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 840 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 841 | |
| 842 | /* send command */ |
| 843 | mmc_ret = mmc_boot_send_command(&cmd); |
| 844 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 845 | return mmc_ret; |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | return MMC_BOOT_E_SUCCESS; |
| 850 | } |
| 851 | |
| 852 | /* |
| 853 | * Requests card to send it's CSD register's contents. (CMD9) |
| 854 | */ |
| 855 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 856 | mmc_boot_send_csd(struct mmc_card *card, unsigned int *raw_csd) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 857 | { |
| 858 | struct mmc_boot_command cmd; |
| 859 | unsigned int mmc_arg = 0; |
| 860 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 861 | |
| 862 | /* basic check */ |
| 863 | if (card == NULL) { |
| 864 | return MMC_BOOT_E_INVAL; |
| 865 | } |
| 866 | |
| 867 | memset((struct mmc_boot_command *)&cmd, 0, |
| 868 | sizeof(struct mmc_boot_command)); |
| 869 | |
| 870 | /* CMD9 Format: |
| 871 | * [31:16] RCA |
| 872 | * [15:0] stuff bits |
| 873 | */ |
| 874 | mmc_arg |= card->rca << 16; |
| 875 | |
| 876 | cmd.cmd_index = CMD9_SEND_CSD; |
| 877 | cmd.argument = mmc_arg; |
| 878 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 879 | cmd.resp_type = MMC_BOOT_RESP_R2; |
| 880 | |
| 881 | /* send command */ |
| 882 | mmc_ret = mmc_boot_send_command(&cmd); |
| 883 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 884 | return mmc_ret; |
| 885 | } |
| 886 | |
| 887 | /* response contains the card csd */ |
| 888 | memcpy(raw_csd, cmd.resp, sizeof(cmd.resp)); |
| 889 | |
| 890 | return MMC_BOOT_E_SUCCESS; |
| 891 | } |
| 892 | |
| 893 | /* |
| 894 | * Selects a card by sending CMD7 to the card with its RCA. |
| 895 | * If RCA field is set as 0 ( or any other address ), |
| 896 | * the card will be de-selected. (CMD7) |
| 897 | */ |
| 898 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 899 | mmc_boot_select_card(struct mmc_card *card, unsigned int rca) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 900 | { |
| 901 | struct mmc_boot_command cmd; |
| 902 | unsigned int mmc_arg = 0; |
| 903 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 904 | |
| 905 | /* basic check */ |
| 906 | if (card == NULL) { |
| 907 | return MMC_BOOT_E_INVAL; |
| 908 | } |
| 909 | |
| 910 | memset((struct mmc_boot_command *)&cmd, 0, |
| 911 | sizeof(struct mmc_boot_command)); |
| 912 | |
| 913 | /* CMD7 Format: |
| 914 | * [31:16] RCA |
| 915 | * [15:0] stuff bits |
| 916 | */ |
| 917 | mmc_arg |= rca << 16; |
| 918 | |
| 919 | cmd.cmd_index = CMD7_SELECT_DESELECT_CARD; |
| 920 | cmd.argument = mmc_arg; |
| 921 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 922 | /* If we are deselecting card, we do not get response */ |
| 923 | if (rca == card->rca && rca) { |
| 924 | if (card->type == MMC_BOOT_TYPE_SDHC |
| 925 | || card->type == MMC_BOOT_TYPE_STD_SD) |
| 926 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 927 | else |
| 928 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 929 | } else { |
| 930 | cmd.resp_type = MMC_BOOT_RESP_NONE; |
| 931 | } |
| 932 | |
| 933 | /* send command */ |
| 934 | mmc_ret = mmc_boot_send_command(&cmd); |
| 935 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 936 | return mmc_ret; |
| 937 | } |
| 938 | |
| 939 | /* As of now no need to look into a response. If it's required |
| 940 | * we'll explore later on */ |
| 941 | |
| 942 | return MMC_BOOT_E_SUCCESS; |
| 943 | } |
| 944 | |
| 945 | /* |
| 946 | * Send command to set block length. |
| 947 | */ |
| 948 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 949 | mmc_boot_set_block_len(struct mmc_card *card, unsigned int block_len) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 950 | { |
| 951 | struct mmc_boot_command cmd; |
| 952 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 953 | |
| 954 | /* basic check */ |
| 955 | if (card == NULL) { |
| 956 | return MMC_BOOT_E_INVAL; |
| 957 | } |
| 958 | |
| 959 | memset((struct mmc_boot_command *)&cmd, 0, |
| 960 | sizeof(struct mmc_boot_command)); |
| 961 | |
| 962 | /* CMD16 Format: |
| 963 | * [31:0] block length |
| 964 | */ |
| 965 | |
| 966 | cmd.cmd_index = CMD16_SET_BLOCKLEN; |
| 967 | cmd.argument = block_len; |
| 968 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 969 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 970 | |
| 971 | /* send command */ |
| 972 | mmc_ret = mmc_boot_send_command(&cmd); |
| 973 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 974 | return mmc_ret; |
| 975 | } |
| 976 | |
| 977 | /* If blocklength is larger than 512 bytes, |
| 978 | * the card sets BLOCK_LEN_ERROR bit. */ |
| 979 | if (cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) { |
| 980 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 981 | } |
| 982 | return MMC_BOOT_E_SUCCESS; |
| 983 | } |
| 984 | |
| 985 | /* |
| 986 | * Requests the card to stop transmission of data. |
| 987 | */ |
| 988 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 989 | mmc_boot_send_stop_transmission(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 990 | unsigned int prg_enabled) |
| 991 | { |
| 992 | struct mmc_boot_command cmd; |
| 993 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 994 | |
| 995 | /* basic check */ |
| 996 | if (card == NULL) { |
| 997 | return MMC_BOOT_E_INVAL; |
| 998 | } |
| 999 | |
| 1000 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1001 | sizeof(struct mmc_boot_command)); |
| 1002 | |
| 1003 | /* CMD12 Format: |
| 1004 | * [31:0] stuff bits |
| 1005 | */ |
| 1006 | |
| 1007 | cmd.cmd_index = CMD12_STOP_TRANSMISSION; |
| 1008 | cmd.argument = 0; |
| 1009 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1010 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 1011 | cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK; |
| 1012 | cmd.prg_enabled = prg_enabled; |
| 1013 | |
| 1014 | /* send command */ |
| 1015 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1016 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1017 | return mmc_ret; |
| 1018 | } |
| 1019 | return MMC_BOOT_E_SUCCESS; |
| 1020 | } |
| 1021 | |
| 1022 | /* |
| 1023 | * Get the card's current status |
| 1024 | */ |
| 1025 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1026 | mmc_boot_get_card_status(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1027 | unsigned int prg_enabled, unsigned int *status) |
| 1028 | { |
| 1029 | struct mmc_boot_command cmd; |
| 1030 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1031 | |
| 1032 | /* basic check */ |
| 1033 | if (card == NULL) { |
| 1034 | return MMC_BOOT_E_INVAL; |
| 1035 | } |
| 1036 | |
| 1037 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1038 | sizeof(struct mmc_boot_command)); |
| 1039 | |
| 1040 | /* CMD13 Format: |
| 1041 | * [31:16] RCA |
| 1042 | * [15:0] stuff bits |
| 1043 | */ |
| 1044 | cmd.cmd_index = CMD13_SEND_STATUS; |
| 1045 | cmd.argument = card->rca << 16; |
| 1046 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1047 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1048 | cmd.prg_enabled = prg_enabled; |
| 1049 | |
| 1050 | /* send command */ |
| 1051 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1052 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1053 | return mmc_ret; |
| 1054 | } |
| 1055 | |
| 1056 | /* Checking ADDR_OUT_OF_RANGE error in CMD13 response */ |
| 1057 | if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) { |
| 1058 | return MMC_BOOT_E_FAILURE; |
| 1059 | } |
| 1060 | |
| 1061 | *status = cmd.resp[0]; |
| 1062 | return MMC_BOOT_E_SUCCESS; |
| 1063 | } |
| 1064 | |
| 1065 | /* |
| 1066 | * Decode type of error caused during read and write |
| 1067 | */ |
| 1068 | static unsigned int mmc_boot_status_error(unsigned mmc_status) |
| 1069 | { |
| 1070 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1071 | |
| 1072 | /* If DATA_CRC_FAIL bit is set to 1 then CRC error was detected by |
| 1073 | card/device during the data transfer */ |
| 1074 | if (mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL) { |
| 1075 | mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL; |
| 1076 | } |
| 1077 | /* If DATA_TIMEOUT bit is set to 1 then the data transfer time exceeded |
| 1078 | the data timeout period without completing the transfer */ |
| 1079 | else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT) { |
| 1080 | mmc_ret = MMC_BOOT_E_DATA_TIMEOUT; |
| 1081 | } |
| 1082 | /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to receive data from |
| 1083 | the card before empty storage for new received data was available. |
| 1084 | Verify that bit FLOW_ENA in MCI_CLK is set to 1 during the data xfer. */ |
| 1085 | else if (mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN) { |
| 1086 | /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. so no need to verify |
| 1087 | for now */ |
| 1088 | mmc_ret = MMC_BOOT_E_RX_OVRRUN; |
| 1089 | } |
| 1090 | /* If TX_UNDERRUN bit is set to 1 then SDCC2 tried to send data to |
| 1091 | the card before new data for sending was available. Verify that bit |
| 1092 | FLOW_ENA in MCI_CLK is set to 1 during the data xfer. */ |
| 1093 | else if (mmc_status & MMC_BOOT_MCI_STAT_TX_UNDRUN) { |
| 1094 | /* Note: We've set FLOW_ENA bit in MCI_CLK to 1.so skipping it now */ |
| 1095 | mmc_ret = MMC_BOOT_E_RX_OVRRUN; |
| 1096 | } |
| 1097 | return mmc_ret; |
| 1098 | } |
| 1099 | |
| 1100 | /* |
| 1101 | * Send ext csd command. |
| 1102 | */ |
| 1103 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1104 | mmc_boot_send_ext_cmd(struct mmc_card *card, unsigned char *buf) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1105 | { |
| 1106 | struct mmc_boot_command cmd; |
| 1107 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1108 | unsigned int mmc_reg = 0; |
| 1109 | unsigned int *mmc_ptr = (unsigned int *)buf; |
| 1110 | |
| 1111 | memset(buf, 0, 512); |
| 1112 | |
| 1113 | /* basic check */ |
| 1114 | if (card == NULL) { |
| 1115 | return MMC_BOOT_E_INVAL; |
| 1116 | } |
| 1117 | |
| 1118 | /* set block len */ |
| 1119 | if ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1120 | && (card->type != MMC_BOOT_TYPE_SDHC)) { |
| 1121 | mmc_ret = mmc_boot_set_block_len(card, 512); |
| 1122 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1123 | dprintf(CRITICAL, |
| 1124 | "Error No.%d: Failure setting block length for Card (RCA:%s)\n", |
| 1125 | mmc_ret, (char *)(card->rca)); |
| 1126 | return mmc_ret; |
| 1127 | } |
| 1128 | } |
| 1129 | |
| 1130 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */ |
| 1131 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 1132 | mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 1133 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 1134 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1135 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 1136 | mmc_mclk_reg_wr_delay(); |
| 1137 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1138 | /* Write data timeout period to MCI_DATA_TIMER register. */ |
| 1139 | /* Data timeout period should be in card bus clock periods */ |
| 1140 | mmc_reg = 0xFFFFFFFF; |
| 1141 | writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER); |
| 1142 | writel(512, MMC_BOOT_MCI_DATA_LENGTH); |
| 1143 | |
| 1144 | /* Set appropriate fields and write the MCI_DATA_CTL register. */ |
| 1145 | /* Set ENABLE bit to 1 to enable the data transfer. */ |
| 1146 | mmc_reg = |
| 1147 | MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (512 << |
| 1148 | MMC_BOOT_MCI_BLKSIZE_POS); |
| 1149 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1150 | #if MMC_BOOT_ADM || MMC_BOOT_BAM |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1151 | mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE; |
| 1152 | #endif |
| 1153 | |
| 1154 | writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL); |
| 1155 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1156 | /* Wait for the MMC_BOOT_MCI_DATA_CTL write to go through. */ |
| 1157 | mmc_mclk_reg_wr_delay(); |
| 1158 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1159 | #if MMC_BOOT_BAM |
| 1160 | /* Setup SDCC BAM descriptors for Read operation. */ |
| 1161 | mmc_ret = mmc_boot_bam_setup_desc(mmc_ptr, 512, MMC_BOOT_DATA_READ); |
| 1162 | #endif |
| 1163 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1164 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1165 | sizeof(struct mmc_boot_command)); |
| 1166 | /* CMD8 */ |
| 1167 | cmd.cmd_index = CMD8_SEND_EXT_CSD; |
| 1168 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1169 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1170 | cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK; |
| 1171 | |
| 1172 | /* send command */ |
| 1173 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1174 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1175 | return mmc_ret; |
| 1176 | } |
| 1177 | |
| 1178 | /* Read the transfer data from SDCC FIFO. */ |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1179 | mmc_ret = mmc_boot_data_transfer(mmc_ptr, 512, MMC_BOOT_DATA_READ); |
| 1180 | |
| 1181 | /* Reset DPSM */ |
| 1182 | writel(0, MMC_BOOT_MCI_DATA_CTL); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1183 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1184 | /* Wait for the MMC_BOOT_MCI_DATA_CTL write to go through. */ |
| 1185 | mmc_mclk_reg_wr_delay(); |
| 1186 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1187 | return mmc_ret; |
| 1188 | } |
| 1189 | |
| 1190 | /* |
| 1191 | * Switch command |
| 1192 | */ |
| 1193 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1194 | mmc_boot_switch_cmd(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1195 | unsigned access, unsigned index, unsigned value) |
| 1196 | { |
| 1197 | |
| 1198 | struct mmc_boot_command cmd; |
| 1199 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1200 | uint32_t mmc_status; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1201 | |
| 1202 | /* basic check */ |
| 1203 | if (card == NULL) { |
| 1204 | return MMC_BOOT_E_INVAL; |
| 1205 | } |
| 1206 | |
| 1207 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1208 | sizeof(struct mmc_boot_command)); |
| 1209 | |
| 1210 | /* CMD6 Format: |
| 1211 | * [31:26] set to 0 |
| 1212 | * [25:24] access |
| 1213 | * [23:16] index |
| 1214 | * [15:8] value |
| 1215 | * [7:3] set to 0 |
| 1216 | * [2:0] cmd set |
| 1217 | */ |
| 1218 | cmd.cmd_index = CMD6_SWITCH_FUNC; |
| 1219 | cmd.argument |= (access << 24); |
| 1220 | cmd.argument |= (index << 16); |
| 1221 | cmd.argument |= (value << 8); |
| 1222 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1223 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1224 | cmd.prg_enabled = 1; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1225 | |
| 1226 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1227 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1228 | dprintf(CRITICAL,"Send cmd6 failed\n"); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1229 | return mmc_ret; |
| 1230 | } |
| 1231 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1232 | /* Wait for interrupt or poll on PROG_DONE bit of MCI_STATUS register. |
| 1233 | * If PROG_DONE bit is set to 1 it means that the card finished it programming |
| 1234 | * and stopped driving DAT0 line to 0. |
| 1235 | */ |
| 1236 | do { |
| 1237 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 1238 | if (mmc_status & MMC_BOOT_MCI_STAT_PROG_DONE) { |
| 1239 | break; |
| 1240 | } |
| 1241 | } |
| 1242 | while (1); |
| 1243 | |
| 1244 | /* Check if the card completed the switch command processing */ |
| 1245 | mmc_ret = mmc_boot_get_card_status(card, 0, &mmc_status); |
| 1246 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1247 | dprintf(CRITICAL, "Get card status failed\n"); |
| 1248 | return mmc_ret; |
| 1249 | } |
| 1250 | |
| 1251 | if (MMC_BOOT_CARD_STATUS(mmc_status) != MMC_BOOT_TRAN_STATE) |
| 1252 | { |
| 1253 | dprintf(CRITICAL, "Switch cmd failed. Card not in tran state\n"); |
| 1254 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 1255 | } |
| 1256 | |
| 1257 | if (mmc_status & MMC_BOOT_SWITCH_FUNC_ERR_FLAG) |
| 1258 | { |
| 1259 | dprintf(CRITICAL, "Switch cmd failed. Switch Error.\n"); |
| 1260 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 1261 | } |
| 1262 | |
| 1263 | return mmc_ret; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1264 | } |
| 1265 | |
| 1266 | /* |
| 1267 | * A command to set the data bus width for card. Set width to either |
| 1268 | */ |
| 1269 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1270 | mmc_boot_set_bus_width(struct mmc_card *card, unsigned int width) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1271 | { |
| 1272 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1273 | unsigned int mmc_reg = 0; |
| 1274 | unsigned int mmc_width = 0; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1275 | |
| 1276 | if (width != MMC_BOOT_BUS_WIDTH_1_BIT) { |
| 1277 | mmc_width = width - 1; |
| 1278 | } |
| 1279 | |
| 1280 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, |
| 1281 | MMC_BOOT_EXT_CMMC_BUS_WIDTH, mmc_width); |
| 1282 | |
| 1283 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1284 | dprintf(CRITICAL, "Switch cmd failed\n"); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1285 | return mmc_ret; |
| 1286 | } |
| 1287 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1288 | /* set MCI_CLK accordingly */ |
| 1289 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 1290 | mmc_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE; |
| 1291 | if (width == MMC_BOOT_BUS_WIDTH_1_BIT) { |
| 1292 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT; |
| 1293 | } else if (width == MMC_BOOT_BUS_WIDTH_4_BIT) { |
| 1294 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT; |
| 1295 | } else if (width == MMC_BOOT_BUS_WIDTH_8_BIT) { |
| 1296 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT; |
| 1297 | } |
Channagoud Kadabi | 676c2e3 | 2013-04-02 11:39:01 -0700 | [diff] [blame] | 1298 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1299 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 1300 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1301 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 1302 | mmc_mclk_reg_wr_delay(); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1303 | |
| 1304 | return MMC_BOOT_E_SUCCESS; |
| 1305 | } |
| 1306 | |
| 1307 | /* |
Channagoud Kadabi | 676c2e3 | 2013-04-02 11:39:01 -0700 | [diff] [blame] | 1308 | * Function to enable HS200 mode |
| 1309 | * 1. Set the clock frequency to 100 MHZ |
| 1310 | * 2. Set the bus width to 4/8 bit SDR as supported byt the target & host |
| 1311 | * 3. Set the HS_TIMING on ext_csd 185 for the card |
| 1312 | */ |
| 1313 | static uint32_t mmc_set_hs200_mode(struct mmc_host *host, |
| 1314 | struct mmc_card *card) |
| 1315 | { |
| 1316 | uint32_t mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1317 | |
| 1318 | /* Set Clock @ 100 MHZ */ |
| 1319 | clock_config_mmc(mmc_slot, host->caps.hs_clk_rate); |
| 1320 | host->mclk_rate = host->caps.hs_clk_rate; |
| 1321 | |
| 1322 | /* Set 4/8 bit SDR bus width */ |
| 1323 | mmc_ret = mmc_boot_set_bus_width(card, host->caps.bus_width); |
| 1324 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1325 | dprintf(CRITICAL, |
| 1326 | "Error No.%d: Failure to set wide bus for Card(RCA:%x)\n", |
| 1327 | mmc_ret, card->rca); |
| 1328 | return mmc_ret; |
| 1329 | } |
| 1330 | |
| 1331 | /* Setting HS200 in HS_TIMING using EXT_CSD (CMD6) */ |
| 1332 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, |
| 1333 | MMC_BOOT_EXT_CMMC_HS_TIMING, 2); |
| 1334 | |
| 1335 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1336 | dprintf(CRITICAL, "Switch cmd returned failure %d\n", __LINE__); |
| 1337 | return mmc_ret; |
| 1338 | } |
| 1339 | |
| 1340 | return mmc_ret; |
| 1341 | } |
| 1342 | |
| 1343 | /* |
| 1344 | * Function to enable DDR mode |
| 1345 | * 1. Set the bus width to 8 bit DDR |
| 1346 | * 1. Set the clock frequency to 100 MHZ |
| 1347 | * 3. Set DDR mode in mci clk register |
| 1348 | * 4. Set Widebus enable in mci clock register |
| 1349 | */ |
| 1350 | static uint32_t mmc_set_ddr_mode(struct mmc_host *host, |
| 1351 | struct mmc_card *card) |
| 1352 | { |
| 1353 | uint8_t mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1354 | uint32_t mmc_reg = 0; |
| 1355 | uint32_t width = 0; |
| 1356 | |
| 1357 | switch (host->caps.bus_width) { |
| 1358 | case MMC_BOOT_BUS_WIDTH_4_BIT: |
| 1359 | width = MMC_DDR_BUS_WIDTH_4_BIT; |
| 1360 | break; |
| 1361 | case MMC_BOOT_BUS_WIDTH_8_BIT: |
| 1362 | width = MMC_DDR_BUS_WIDTH_8_BIT; |
| 1363 | break; |
| 1364 | default: |
| 1365 | dprintf(CRITICAL, "Invalid bus width, DDR mode is not enabled\n"); |
| 1366 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 1367 | goto end; |
| 1368 | }; |
| 1369 | |
| 1370 | /* Set width for 4/8 bit DDR bus width */ |
| 1371 | mmc_ret = mmc_boot_set_bus_width(card, width); |
| 1372 | |
| 1373 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1374 | dprintf(CRITICAL, |
| 1375 | "Error No.%d: Failure to set wide bus for Card(RCA:%x)\n", |
| 1376 | mmc_ret, card->rca); |
| 1377 | return mmc_ret; |
| 1378 | } |
| 1379 | |
| 1380 | /* Bump up the clock frequency */ |
| 1381 | clock_config_mmc(mmc_slot, host->caps.hs_clk_rate); |
| 1382 | host->mclk_rate = host->caps.hs_clk_rate; |
| 1383 | |
| 1384 | /* Select DDR mode in mci register */ |
| 1385 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 1386 | mmc_reg |= (MMC_MCI_DDR_MODE_EN << MMC_MCI_MODE_SELECT); |
| 1387 | |
| 1388 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 1389 | |
| 1390 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 1391 | mmc_mclk_reg_wr_delay(); |
| 1392 | |
| 1393 | /* Enable wide bus for DDR */ |
| 1394 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 1395 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_MODE; |
| 1396 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 1397 | |
| 1398 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 1399 | mmc_mclk_reg_wr_delay(); |
| 1400 | |
| 1401 | end: |
| 1402 | return MMC_BOOT_E_SUCCESS; |
| 1403 | } |
| 1404 | |
| 1405 | /* |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1406 | * A command to start data read from card. Either a single block or |
| 1407 | * multiple blocks can be read. Multiple blocks read will continuously |
| 1408 | * transfer data from card to host unless requested to stop by issuing |
| 1409 | * CMD12 - STOP_TRANSMISSION. |
| 1410 | */ |
| 1411 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1412 | mmc_boot_send_read_command(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1413 | unsigned int xfer_type, unsigned int data_addr) |
| 1414 | { |
| 1415 | struct mmc_boot_command cmd; |
| 1416 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1417 | |
| 1418 | /* basic check */ |
| 1419 | if (card == NULL) { |
| 1420 | return MMC_BOOT_E_INVAL; |
| 1421 | } |
| 1422 | |
| 1423 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1424 | sizeof(struct mmc_boot_command)); |
| 1425 | |
| 1426 | /* CMD17/18 Format: |
| 1427 | * [31:0] Data Address |
| 1428 | */ |
| 1429 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) { |
| 1430 | cmd.cmd_index = CMD18_READ_MULTIPLE_BLOCK; |
| 1431 | } else { |
| 1432 | cmd.cmd_index = CMD17_READ_SINGLE_BLOCK; |
| 1433 | } |
| 1434 | |
| 1435 | cmd.argument = data_addr; |
| 1436 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1437 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1438 | |
| 1439 | /* send command */ |
| 1440 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1441 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1442 | return mmc_ret; |
| 1443 | } |
| 1444 | |
| 1445 | /* Response contains 32 bit Card status. Here we'll check |
| 1446 | BLOCK_LEN_ERROR and ADDRESS_ERROR */ |
| 1447 | if (cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) { |
| 1448 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 1449 | } |
| 1450 | /* Misaligned address not matching block length */ |
| 1451 | if (cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR) { |
| 1452 | return MMC_BOOT_E_ADDRESS_ERR; |
| 1453 | } |
| 1454 | |
| 1455 | return MMC_BOOT_E_SUCCESS; |
| 1456 | } |
| 1457 | |
| 1458 | /* |
| 1459 | * A command to start data write to card. Either a single block or |
| 1460 | * multiple blocks can be written. Multiple block write will continuously |
| 1461 | * transfer data from host to card unless requested to stop by issuing |
| 1462 | * CMD12 - STOP_TRANSMISSION. |
| 1463 | */ |
| 1464 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1465 | mmc_boot_send_write_command(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1466 | unsigned int xfer_type, unsigned int data_addr) |
| 1467 | { |
| 1468 | struct mmc_boot_command cmd; |
| 1469 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1470 | |
| 1471 | /* basic check */ |
| 1472 | if (card == NULL) { |
| 1473 | return MMC_BOOT_E_INVAL; |
| 1474 | } |
| 1475 | |
| 1476 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1477 | sizeof(struct mmc_boot_command)); |
| 1478 | |
| 1479 | /* CMD24/25 Format: |
| 1480 | * [31:0] Data Address |
| 1481 | */ |
| 1482 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) { |
| 1483 | cmd.cmd_index = CMD25_WRITE_MULTIPLE_BLOCK; |
| 1484 | } else { |
| 1485 | cmd.cmd_index = CMD24_WRITE_SINGLE_BLOCK; |
| 1486 | } |
| 1487 | |
| 1488 | cmd.argument = data_addr; |
| 1489 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1490 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1491 | |
| 1492 | /* send command */ |
| 1493 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1494 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1495 | return mmc_ret; |
| 1496 | } |
| 1497 | |
| 1498 | /* Response contains 32 bit Card status. Here we'll check |
| 1499 | BLOCK_LEN_ERROR and ADDRESS_ERROR */ |
| 1500 | if (cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) { |
| 1501 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 1502 | } |
| 1503 | /* Misaligned address not matching block length */ |
| 1504 | if (cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR) { |
| 1505 | return MMC_BOOT_E_ADDRESS_ERR; |
| 1506 | } |
| 1507 | |
| 1508 | return MMC_BOOT_E_SUCCESS; |
| 1509 | } |
| 1510 | |
| 1511 | /* |
| 1512 | * Write data_len data to address specified by data_addr. data_len is |
| 1513 | * multiple of blocks for block data transfer. |
| 1514 | */ |
Channagoud Kadabi | 7cf5d04 | 2013-04-19 12:58:15 -0700 | [diff] [blame] | 1515 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1516 | mmc_boot_write_to_card(struct mmc_host *host, |
| 1517 | struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1518 | unsigned long long data_addr, |
| 1519 | unsigned int data_len, unsigned int *in) |
| 1520 | { |
| 1521 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1522 | unsigned int mmc_status = 0; |
| 1523 | unsigned int mmc_reg = 0; |
| 1524 | unsigned int addr; |
| 1525 | unsigned int xfer_type; |
| 1526 | unsigned int status; |
| 1527 | |
| 1528 | if ((host == NULL) || (card == NULL)) { |
| 1529 | return MMC_BOOT_E_INVAL; |
| 1530 | } |
| 1531 | |
| 1532 | /* Set block length. High Capacity MMC/SD card uses fixed 512 bytes block |
| 1533 | length. So no need to send CMD16. */ |
| 1534 | if ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1535 | && (card->type != MMC_BOOT_TYPE_SDHC)) { |
| 1536 | mmc_ret = mmc_boot_set_block_len(card, card->wr_block_len); |
| 1537 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1538 | dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card\ |
| 1539 | (RCA:%s)\n", mmc_ret, |
| 1540 | (char *)(card->rca)); |
| 1541 | return mmc_ret; |
| 1542 | } |
| 1543 | } |
| 1544 | |
| 1545 | /* use multi-block mode to transfer for data larger than a block */ |
| 1546 | xfer_type = |
| 1547 | (data_len > |
| 1548 | card-> |
| 1549 | rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK : |
| 1550 | MMC_BOOT_XFER_SINGLE_BLOCK; |
| 1551 | |
| 1552 | /* For MMCHC/SDHC data address is specified in unit of 512B */ |
| 1553 | addr = ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1554 | && (card->type != |
| 1555 | MMC_BOOT_TYPE_SDHC)) ? (unsigned int)data_addr : (unsigned |
| 1556 | int) |
| 1557 | (data_addr / 512); |
| 1558 | |
| 1559 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */ |
| 1560 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 1561 | mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 1562 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 1563 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1564 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 1565 | mmc_mclk_reg_wr_delay(); |
| 1566 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1567 | /* Write data timeout period to MCI_DATA_TIMER register */ |
| 1568 | /* Data timeout period should be in card bus clock periods */ |
| 1569 | /*TODO: Fix timeout value */ |
| 1570 | mmc_reg = 0xFFFFFFFF; |
| 1571 | writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER); |
| 1572 | |
| 1573 | /* Write the total size of the transfer data to MCI_DATA_LENGTH register */ |
| 1574 | writel(data_len, MMC_BOOT_MCI_DATA_LENGTH); |
| 1575 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1576 | #if MMC_BOOT_BAM |
| 1577 | mmc_boot_bam_setup_desc(in, data_len, MMC_BOOT_DATA_WRITE); |
| 1578 | #endif |
| 1579 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1580 | /* Send command to the card/device in order to start the write data xfer. |
| 1581 | The possible commands are CMD24/25/53/60/61 */ |
| 1582 | mmc_ret = mmc_boot_send_write_command(card, xfer_type, addr); |
| 1583 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1584 | dprintf(CRITICAL, "Error No.%d: Failure sending write command to the\ |
| 1585 | Card(RCA:%x)\n", mmc_ret, |
| 1586 | card->rca); |
| 1587 | return mmc_ret; |
| 1588 | } |
| 1589 | |
| 1590 | /* Set appropriate fields and write the MCI_DATA_CTL register */ |
| 1591 | /* Set ENABLE bit to 1 to enable the data transfer. */ |
| 1592 | mmc_reg = 0; |
| 1593 | mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE; |
| 1594 | /* Clear DIRECTION bit to 0 to enable transfer from host to card */ |
| 1595 | /* Clear MODE bit to 0 to enable block oriented data transfer. For |
| 1596 | MMC cards only, if stream data transfer mode is desired, set |
| 1597 | MODE bit to 1. */ |
| 1598 | |
| 1599 | /* Set DM_ENABLE bit to 1 in order to enable DMA, otherwise set 0 */ |
| 1600 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1601 | #if MMC_BOOT_ADM || MMC_BOOT_BAM |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1602 | mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE; |
| 1603 | #endif |
| 1604 | |
| 1605 | /* Write size of block to be used during the data transfer to |
| 1606 | BLOCKSIZE field */ |
| 1607 | mmc_reg |= card->wr_block_len << MMC_BOOT_MCI_BLKSIZE_POS; |
| 1608 | writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL); |
| 1609 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1610 | /* Wait for the MMC_BOOT_MCI_DATA_CTL write to go through. */ |
| 1611 | mmc_mclk_reg_wr_delay(); |
| 1612 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1613 | /* write data to FIFO */ |
| 1614 | mmc_ret = |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1615 | mmc_boot_data_transfer(in, data_len, MMC_BOOT_DATA_WRITE); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1616 | |
| 1617 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1618 | dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \ |
| 1619 | Card(RCA:%x)\n", mmc_ret, |
| 1620 | card->rca); |
| 1621 | /* In case of any failure happening for multi block transfer */ |
| 1622 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) |
| 1623 | mmc_boot_send_stop_transmission(card, 1); |
| 1624 | return mmc_ret; |
| 1625 | } |
| 1626 | |
| 1627 | /* Send command to the card/device in order to poll the de-assertion of |
| 1628 | card/device BUSY condition. It is important to set PROG_ENA bit in |
| 1629 | MCI_CLK register before sending the command. Possible commands are |
| 1630 | CMD12/13. */ |
| 1631 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) { |
| 1632 | mmc_ret = mmc_boot_send_stop_transmission(card, 1); |
| 1633 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1634 | dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \ |
| 1635 | command to the Card(RCA:%x)\n", mmc_ret, |
| 1636 | card->rca); |
| 1637 | return mmc_ret; |
| 1638 | } |
| 1639 | } else { |
| 1640 | mmc_ret = mmc_boot_get_card_status(card, 1, &status); |
| 1641 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1642 | dprintf(CRITICAL, |
| 1643 | "Error No.%d: Failure getting card status of Card(RCA:%x)\n", |
| 1644 | mmc_ret, card->rca); |
| 1645 | return mmc_ret; |
| 1646 | } |
| 1647 | } |
| 1648 | |
| 1649 | /* Wait for interrupt or poll on PROG_DONE bit of MCI_STATUS register. If |
| 1650 | PROG_DONE bit is set to 1 it means that the card finished it programming |
| 1651 | and stopped driving DAT0 line to 0 */ |
| 1652 | do { |
| 1653 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 1654 | if (mmc_status & MMC_BOOT_MCI_STAT_PROG_DONE) { |
| 1655 | break; |
| 1656 | } |
| 1657 | } |
| 1658 | while (1); |
| 1659 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1660 | #if MMC_BOOT_BAM |
| 1661 | /* Wait for DML trasaction to end */ |
| 1662 | mmc_boot_dml_wait_consumer_idle(); |
| 1663 | #endif |
| 1664 | |
| 1665 | /* Reset DPSM */ |
| 1666 | writel(0, MMC_BOOT_MCI_DATA_CTL); |
| 1667 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1668 | /* Wait for the MMC_BOOT_MCI_DATA_CTL write to go through. */ |
| 1669 | mmc_mclk_reg_wr_delay(); |
| 1670 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1671 | return MMC_BOOT_E_SUCCESS; |
| 1672 | } |
| 1673 | |
| 1674 | /* |
| 1675 | * Adjust the interface speed to optimal speed |
| 1676 | */ |
| 1677 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1678 | mmc_boot_adjust_interface_speed(struct mmc_host *host, |
| 1679 | struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1680 | { |
| 1681 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1682 | |
| 1683 | /* Setting HS_TIMING in EXT_CSD (CMD6) */ |
| 1684 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, |
| 1685 | MMC_BOOT_EXT_CMMC_HS_TIMING, 1); |
| 1686 | |
| 1687 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1688 | dprintf(CRITICAL, "Switch cmd returned failure %d\n", __LINE__); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1689 | return mmc_ret; |
| 1690 | } |
| 1691 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1692 | clock_config_mmc(mmc_slot, MMC_CLK_50MHZ); |
| 1693 | |
| 1694 | host->mclk_rate = MMC_CLK_50MHZ; |
| 1695 | |
| 1696 | return MMC_BOOT_E_SUCCESS; |
| 1697 | } |
| 1698 | |
| 1699 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1700 | mmc_boot_set_block_count(struct mmc_card *card, unsigned int block_count) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1701 | { |
| 1702 | struct mmc_boot_command cmd; |
| 1703 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1704 | |
| 1705 | /* basic check */ |
| 1706 | if (card == NULL) { |
| 1707 | return MMC_BOOT_E_INVAL; |
| 1708 | } |
| 1709 | |
| 1710 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1711 | sizeof(struct mmc_boot_command)); |
| 1712 | |
| 1713 | /* CMD23 Format: |
| 1714 | * [15:0] number of blocks |
| 1715 | */ |
| 1716 | |
| 1717 | cmd.cmd_index = CMD23_SET_BLOCK_COUNT; |
| 1718 | cmd.argument = block_count; |
| 1719 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1720 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1721 | |
| 1722 | /* send command */ |
| 1723 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1724 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1725 | return mmc_ret; |
| 1726 | } |
| 1727 | |
| 1728 | if (cmd.resp[0] & MMC_BOOT_R1_OUT_OF_RANGE) { |
| 1729 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 1730 | } |
| 1731 | |
| 1732 | return MMC_BOOT_E_SUCCESS; |
| 1733 | } |
| 1734 | |
| 1735 | /* |
| 1736 | * Reads a data of data_len from the address specified. data_len |
| 1737 | * should be multiple of block size for block data transfer. |
| 1738 | */ |
Channagoud Kadabi | 7cf5d04 | 2013-04-19 12:58:15 -0700 | [diff] [blame] | 1739 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1740 | mmc_boot_read_from_card(struct mmc_host *host, |
| 1741 | struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1742 | unsigned long long data_addr, |
| 1743 | unsigned int data_len, unsigned int *out) |
| 1744 | { |
| 1745 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1746 | unsigned int mmc_reg = 0; |
| 1747 | unsigned int xfer_type; |
| 1748 | unsigned int addr = 0; |
| 1749 | unsigned char open_ended_read = 1; |
| 1750 | |
| 1751 | if ((host == NULL) || (card == NULL)) { |
| 1752 | return MMC_BOOT_E_INVAL; |
| 1753 | } |
| 1754 | |
| 1755 | /* Set block length. High Capacity MMC/SD card uses fixed 512 bytes block |
| 1756 | length. So no need to send CMD16. */ |
| 1757 | if ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1758 | && (card->type != MMC_BOOT_TYPE_SDHC)) { |
| 1759 | mmc_ret = mmc_boot_set_block_len(card, card->rd_block_len); |
| 1760 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1761 | dprintf(CRITICAL, |
| 1762 | "Error No.%d: Failure setting block length for Card (RCA:%s)\n", |
| 1763 | mmc_ret, (char *)(card->rca)); |
| 1764 | return mmc_ret; |
| 1765 | } |
| 1766 | } |
| 1767 | |
| 1768 | /* use multi-block mode to transfer for data larger than a block */ |
| 1769 | xfer_type = |
| 1770 | (data_len > |
| 1771 | card-> |
| 1772 | rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK : |
| 1773 | MMC_BOOT_XFER_SINGLE_BLOCK; |
| 1774 | |
| 1775 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) { |
| 1776 | if ((card->type == MMC_BOOT_TYPE_MMCHC) |
| 1777 | || (card->type == MMC_BOOT_TYPE_STD_MMC)) { |
| 1778 | /* Virtio model does not support open-ended multi-block reads. |
| 1779 | * So, block count must be set before sending read command. |
| 1780 | * All SD cards do not support this command. Restrict this to MMC. |
| 1781 | */ |
| 1782 | mmc_ret = |
| 1783 | mmc_boot_set_block_count(card, |
| 1784 | data_len / |
| 1785 | (card->rd_block_len)); |
| 1786 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1787 | dprintf(CRITICAL, |
| 1788 | "Error No.%d: Failure setting read block count for Card (RCA:%s)\n", |
| 1789 | mmc_ret, (char *)(card->rca)); |
| 1790 | return mmc_ret; |
| 1791 | } |
| 1792 | |
| 1793 | open_ended_read = 0; |
| 1794 | } |
| 1795 | } |
| 1796 | |
| 1797 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */ |
| 1798 | /* Note: It's already enabled */ |
| 1799 | |
| 1800 | /* If Data Mover is used for data transfer then prepare Command |
| 1801 | List Entry and enable the Data mover to work with SDCC2 */ |
| 1802 | |
| 1803 | /* Write data timeout period to MCI_DATA_TIMER register. */ |
| 1804 | /* Data timeout period should be in card bus clock periods */ |
| 1805 | mmc_reg = (unsigned long)(card->rd_timeout_ns / 1000000) * |
| 1806 | (host->mclk_rate / 1000); |
| 1807 | mmc_reg += 1000; // add some extra clock cycles to be safe |
| 1808 | mmc_reg = mmc_reg / 2; |
| 1809 | writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER); |
| 1810 | |
| 1811 | /* Write the total size of the transfer data to MCI_DATA_LENGTH |
| 1812 | register. For block xfer it must be multiple of the block |
| 1813 | size. */ |
| 1814 | writel(data_len, MMC_BOOT_MCI_DATA_LENGTH); |
| 1815 | |
| 1816 | /* For MMCHC/SDHC data address is specified in unit of 512B */ |
| 1817 | addr = ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1818 | && (card->type != |
| 1819 | MMC_BOOT_TYPE_SDHC)) ? (unsigned int)data_addr : (unsigned |
| 1820 | int) |
| 1821 | (data_addr / 512); |
| 1822 | |
| 1823 | /* Set appropriate fields and write the MCI_DATA_CTL register. */ |
| 1824 | /* Set ENABLE bit to 1 to enable the data transfer. */ |
| 1825 | mmc_reg = 0; |
| 1826 | mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE; |
| 1827 | /* Clear DIRECTION bit to 1 to enable transfer from card to host */ |
| 1828 | mmc_reg |= MMC_BOOT_MCI_DATA_DIR; |
| 1829 | /* Clear MODE bit to 0 to enable block oriented data transfer. For |
| 1830 | MMC cards only, if stream data transfer mode is desired, set |
| 1831 | MODE bit to 1. */ |
| 1832 | |
| 1833 | /* If DMA is to be used, Set DM_ENABLE bit to 1 */ |
| 1834 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1835 | #if MMC_BOOT_ADM || MMC_BOOT_BAM |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1836 | mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE; |
| 1837 | #endif |
| 1838 | |
| 1839 | /* Write size of block to be used during the data transfer to |
| 1840 | BLOCKSIZE field */ |
| 1841 | mmc_reg |= (card->rd_block_len << MMC_BOOT_MCI_BLKSIZE_POS); |
| 1842 | writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL); |
| 1843 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1844 | /* Wait for the MMC_BOOT_MCI_DATA_CTL write to go through. */ |
| 1845 | mmc_mclk_reg_wr_delay(); |
| 1846 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1847 | #if MMC_BOOT_BAM |
| 1848 | /* Setup SDCC FIFO descriptors for Read operation. */ |
| 1849 | mmc_ret = mmc_boot_bam_setup_desc(out, data_len, MMC_BOOT_DATA_READ); |
| 1850 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1851 | /* Send command to the card/device in order to start the read data |
| 1852 | transfer. Possible commands: CMD17/18/53/60/61. */ |
| 1853 | mmc_ret = mmc_boot_send_read_command(card, xfer_type, addr); |
| 1854 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1855 | dprintf(CRITICAL, |
| 1856 | "Error No.%d: Failure sending read command to the Card(RCA:%x)\n", |
| 1857 | mmc_ret, card->rca); |
| 1858 | return mmc_ret; |
| 1859 | } |
| 1860 | |
| 1861 | /* Read the transfer data from SDCC FIFO. */ |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1862 | mmc_ret = mmc_boot_data_transfer(out, data_len, MMC_BOOT_DATA_READ); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1863 | |
| 1864 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1865 | dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \ |
| 1866 | Card(RCA:%x)\n", mmc_ret, |
| 1867 | card->rca); |
| 1868 | return mmc_ret; |
| 1869 | } |
| 1870 | |
| 1871 | /* In case a multiple block transfer was performed, send CMD12 to the |
| 1872 | card/device in order to indicate the end of read data transfer */ |
| 1873 | if ((xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) && open_ended_read) { |
| 1874 | mmc_ret = mmc_boot_send_stop_transmission(card, 0); |
| 1875 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1876 | dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \ |
| 1877 | command to the Card(RCA:%x)\n", mmc_ret, |
| 1878 | card->rca); |
| 1879 | return mmc_ret; |
| 1880 | } |
| 1881 | } |
| 1882 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 1883 | /* Reset DPSM */ |
| 1884 | writel(0, MMC_BOOT_MCI_DATA_CTL); |
| 1885 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1886 | /* Wait for the MMC_BOOT_MCI_DATA_CTL write to go through. */ |
| 1887 | mmc_mclk_reg_wr_delay(); |
| 1888 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1889 | return MMC_BOOT_E_SUCCESS; |
| 1890 | } |
| 1891 | |
| 1892 | /* |
| 1893 | * Initialize host structure, set and enable clock-rate and power mode. |
| 1894 | */ |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1895 | unsigned int mmc_boot_init(struct mmc_host *host) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1896 | { |
| 1897 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1898 | unsigned int mmc_pwr = 0; |
| 1899 | |
| 1900 | host->ocr = MMC_BOOT_OCR_27_36 | MMC_BOOT_OCR_SEC_MODE; |
| 1901 | host->cmd_retry = MMC_BOOT_MAX_COMMAND_RETRY; |
| 1902 | |
| 1903 | /* Initialize any clocks needed for SDC controller */ |
| 1904 | clock_init_mmc(mmc_slot); |
| 1905 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1906 | /* Save the verison on the mmc controller. */ |
| 1907 | host->mmc_cont_version = readl(MMC_BOOT_MCI_VERSION); |
| 1908 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1909 | /* Setup initial freq to 400KHz */ |
| 1910 | clock_config_mmc(mmc_slot, MMC_CLK_400KHZ); |
| 1911 | |
| 1912 | host->mclk_rate = MMC_CLK_400KHZ; |
| 1913 | |
| 1914 | /* set power mode */ |
| 1915 | /* give some time to reach minimum voltate */ |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1916 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1917 | mmc_pwr &= ~MMC_BOOT_MCI_PWR_UP; |
| 1918 | mmc_pwr |= MMC_BOOT_MCI_PWR_ON; |
| 1919 | mmc_pwr |= MMC_BOOT_MCI_PWR_UP; |
| 1920 | writel(mmc_pwr, MMC_BOOT_MCI_POWER); |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1921 | |
| 1922 | /* Wait for the MMC_BOOT_MCI_POWER write to go through. */ |
| 1923 | mmc_mclk_reg_wr_delay(); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1924 | |
| 1925 | return MMC_BOOT_E_SUCCESS; |
| 1926 | } |
| 1927 | |
| 1928 | /* |
| 1929 | * Performs card identification process: |
| 1930 | * - get card's unique identification number (CID) |
| 1931 | * - get(for sd)/set (for mmc) relative card address (RCA) |
| 1932 | * - get CSD |
| 1933 | * - select the card, thus transitioning it to Transfer State |
| 1934 | * - get Extended CSD (for mmc) |
| 1935 | */ |
| 1936 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 1937 | mmc_boot_identify_card(struct mmc_host *host, struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1938 | { |
| 1939 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS; |
| 1940 | unsigned int raw_csd[4]; |
| 1941 | |
| 1942 | /* basic check */ |
| 1943 | if ((host == NULL) || (card == NULL)) { |
| 1944 | return MMC_BOOT_E_INVAL; |
| 1945 | } |
| 1946 | |
| 1947 | /* Ask card to send its unique card identification (CID) number (CMD2) */ |
| 1948 | mmc_return = mmc_boot_all_send_cid(card); |
| 1949 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1950 | dprintf(CRITICAL, |
| 1951 | "Error No. %d: Failure getting card's CID number!\n", |
| 1952 | mmc_return); |
| 1953 | return mmc_return; |
| 1954 | } |
| 1955 | |
| 1956 | /* Ask card to send a relative card address (RCA) (CMD3) */ |
| 1957 | mmc_return = mmc_boot_send_relative_address(card); |
| 1958 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1959 | dprintf(CRITICAL, "Error No. %d: Failure getting card's RCA!\n", |
| 1960 | mmc_return); |
| 1961 | return mmc_return; |
| 1962 | } |
| 1963 | |
| 1964 | /* Get card's CSD register (CMD9) */ |
| 1965 | mmc_return = mmc_boot_send_csd(card, raw_csd); |
| 1966 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1967 | dprintf(CRITICAL, |
| 1968 | "Error No.%d: Failure getting card's CSD information!\n", |
| 1969 | mmc_return); |
| 1970 | return mmc_return; |
| 1971 | } |
| 1972 | |
| 1973 | /* Select the card (CMD7) */ |
| 1974 | mmc_return = mmc_boot_select_card(card, card->rca); |
| 1975 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1976 | dprintf(CRITICAL, |
| 1977 | "Error No.%d: Failure selecting the Card with RCA: %x\n", |
| 1978 | mmc_return, card->rca); |
| 1979 | return mmc_return; |
| 1980 | } |
| 1981 | |
| 1982 | /* Set the card status as active */ |
| 1983 | card->status = MMC_BOOT_STATUS_ACTIVE; |
| 1984 | |
| 1985 | if ((card->type == MMC_BOOT_TYPE_STD_MMC) |
| 1986 | || (card->type == MMC_BOOT_TYPE_MMCHC)) { |
| 1987 | /* For MMC cards, also get the extended csd */ |
| 1988 | mmc_return = mmc_boot_send_ext_cmd(card, ext_csd_buf); |
| 1989 | |
| 1990 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1991 | dprintf(CRITICAL, |
| 1992 | "Error No.%d: Failure getting card's ExtCSD information!\n", |
| 1993 | mmc_return); |
| 1994 | |
| 1995 | return mmc_return; |
| 1996 | } |
| 1997 | |
| 1998 | } |
| 1999 | |
| 2000 | /* Decode and save the CSD register */ |
| 2001 | mmc_return = mmc_boot_decode_and_save_csd(card, raw_csd); |
| 2002 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2003 | dprintf(CRITICAL, |
| 2004 | "Error No.%d: Failure decoding card's CSD information!\n", |
| 2005 | mmc_return); |
| 2006 | return mmc_return; |
| 2007 | } |
| 2008 | |
| 2009 | /* Once CSD is received, set read and write timeout value now itself */ |
| 2010 | mmc_return = mmc_boot_set_read_timeout(host, card); |
| 2011 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2012 | dprintf(CRITICAL, |
| 2013 | "Error No.%d: Failure setting Read Timeout value!\n", |
| 2014 | mmc_return); |
| 2015 | return mmc_return; |
| 2016 | } |
| 2017 | |
| 2018 | mmc_return = mmc_boot_set_write_timeout(host, card); |
| 2019 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2020 | dprintf(CRITICAL, |
| 2021 | "Error No.%d: Failure setting Write Timeout value!\n", |
| 2022 | mmc_return); |
| 2023 | return mmc_return; |
| 2024 | } |
| 2025 | |
| 2026 | return MMC_BOOT_E_SUCCESS; |
| 2027 | } |
| 2028 | |
| 2029 | static unsigned int mmc_boot_send_app_cmd(unsigned int rca) |
| 2030 | { |
| 2031 | struct mmc_boot_command cmd; |
| 2032 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2033 | |
| 2034 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2035 | sizeof(struct mmc_boot_command)); |
| 2036 | |
| 2037 | cmd.cmd_index = CMD55_APP_CMD; |
| 2038 | cmd.argument = (rca << 16); |
| 2039 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2040 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 2041 | |
| 2042 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2043 | |
| 2044 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2045 | return mmc_ret; |
| 2046 | } |
| 2047 | |
| 2048 | return MMC_BOOT_E_SUCCESS; |
| 2049 | } |
| 2050 | |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2051 | static unsigned int mmc_boot_sd_init_card(struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2052 | { |
| 2053 | unsigned int i, mmc_ret; |
| 2054 | unsigned int ocr_cmd_arg; |
| 2055 | struct mmc_boot_command cmd; |
| 2056 | |
| 2057 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2058 | sizeof(struct mmc_boot_command)); |
| 2059 | |
| 2060 | /* Send CMD8 to set interface condition */ |
| 2061 | for (i = 0; i < 3; i++) { |
| 2062 | cmd.cmd_index = CMD8_SEND_IF_COND; |
| 2063 | cmd.argument = MMC_BOOT_SD_HC_VOLT_SUPPLIED; |
| 2064 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 2065 | cmd.resp_type = MMC_BOOT_RESP_R7; |
| 2066 | |
| 2067 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2068 | if (mmc_ret == MMC_BOOT_E_SUCCESS) { |
| 2069 | if (cmd.resp[0] != MMC_BOOT_SD_HC_VOLT_SUPPLIED) |
| 2070 | return MMC_BOOT_E_FAILURE; |
| 2071 | /* Set argument for ACMD41 */ |
| 2072 | ocr_cmd_arg = MMC_BOOT_SD_NEG_OCR | MMC_BOOT_SD_HC_HCS; |
| 2073 | break; |
| 2074 | } |
| 2075 | mdelay(1); |
| 2076 | } |
| 2077 | |
| 2078 | /* Send ACMD41 to set operating condition */ |
| 2079 | /* Try for a max of 1 sec as per spec */ |
| 2080 | for (i = 0; i < 20; i++) { |
| 2081 | mmc_ret = mmc_boot_send_app_cmd(0); |
| 2082 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2083 | return mmc_ret; |
| 2084 | } |
| 2085 | |
| 2086 | cmd.cmd_index = ACMD41_SEND_OP_COND; |
| 2087 | cmd.argument = ocr_cmd_arg; |
| 2088 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 2089 | cmd.resp_type = MMC_BOOT_RESP_R3; |
| 2090 | |
| 2091 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2092 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2093 | return mmc_ret; |
| 2094 | } else if (cmd.resp[0] & MMC_BOOT_SD_DEV_READY) { |
| 2095 | /* Check for HC */ |
| 2096 | if (cmd.resp[0] & (1 << 30)) { |
| 2097 | card->type = MMC_BOOT_TYPE_SDHC; |
| 2098 | } else { |
| 2099 | card->type = MMC_BOOT_TYPE_STD_SD; |
| 2100 | } |
| 2101 | break; |
| 2102 | } |
| 2103 | mdelay(50); |
| 2104 | } |
| 2105 | return MMC_BOOT_E_SUCCESS; |
| 2106 | } |
| 2107 | |
| 2108 | /* |
| 2109 | * Routine to initialize MMC card. It resets a card to idle state, verify operating |
| 2110 | * voltage and set the card inready state. |
| 2111 | */ |
| 2112 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2113 | mmc_boot_init_card(struct mmc_host *host, struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2114 | { |
| 2115 | unsigned int mmc_retry = 0; |
| 2116 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS; |
| 2117 | |
| 2118 | /* basic check */ |
| 2119 | if ((host == NULL) || (card == NULL)) { |
| 2120 | return MMC_BOOT_E_INVAL; |
| 2121 | } |
| 2122 | |
| 2123 | /* 1. Card Reset - CMD0 */ |
| 2124 | mmc_return = mmc_boot_reset_cards(); |
| 2125 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2126 | dprintf(CRITICAL, |
| 2127 | "Error No.:%d: Failure resetting MMC cards!\n", |
| 2128 | mmc_return); |
| 2129 | return mmc_return; |
| 2130 | } |
| 2131 | |
| 2132 | /* 2. Card Initialization process */ |
| 2133 | |
| 2134 | /* Send CMD1 to identify and reject cards that do not match host's VDD range |
| 2135 | profile. Cards sends its OCR register in response. |
| 2136 | */ |
| 2137 | mmc_retry = 0; |
| 2138 | do { |
| 2139 | mmc_return = mmc_boot_send_op_cond(host, card); |
| 2140 | /* Card returns busy status. We'll retry again! */ |
| 2141 | if (mmc_return == MMC_BOOT_E_CARD_BUSY) { |
| 2142 | mmc_retry++; |
| 2143 | mdelay(1); |
| 2144 | continue; |
| 2145 | } else if (mmc_return == MMC_BOOT_E_SUCCESS) { |
| 2146 | break; |
| 2147 | } else { |
| 2148 | dprintf(CRITICAL, |
| 2149 | "Error No. %d: Failure Initializing MMC Card!\n", |
| 2150 | mmc_return); |
| 2151 | |
| 2152 | /* Check for sD card */ |
| 2153 | mmc_return = mmc_boot_sd_init_card(card); |
| 2154 | return mmc_return; |
| 2155 | } |
| 2156 | } |
| 2157 | while (mmc_retry < host->cmd_retry); |
| 2158 | |
| 2159 | /* If card still returned busy status we are out of luck. |
| 2160 | * Card cannot be initialized */ |
| 2161 | if (mmc_return == MMC_BOOT_E_CARD_BUSY) { |
| 2162 | dprintf(CRITICAL, "Error No. %d: Card has busy status set. \ |
| 2163 | Initialization not completed\n", mmc_return); |
| 2164 | return MMC_BOOT_E_CARD_BUSY; |
| 2165 | } |
Channagoud Kadabi | 57eb630 | 2013-09-10 14:21:30 -0700 | [diff] [blame] | 2166 | |
| 2167 | card->block_size = BLOCK_SIZE; |
| 2168 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2169 | return MMC_BOOT_E_SUCCESS; |
| 2170 | } |
| 2171 | |
| 2172 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2173 | mmc_boot_set_sd_bus_width(struct mmc_card *card, unsigned int width) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2174 | { |
| 2175 | struct mmc_boot_command cmd; |
| 2176 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2177 | unsigned int sd_reg; |
| 2178 | |
| 2179 | mmc_ret = mmc_boot_send_app_cmd(card->rca); |
| 2180 | |
| 2181 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2182 | return mmc_ret; |
| 2183 | } |
| 2184 | |
| 2185 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2186 | sizeof(struct mmc_boot_command)); |
| 2187 | |
| 2188 | /* Send ACMD6 to set bus width */ |
| 2189 | cmd.cmd_index = ACMD6_SET_BUS_WIDTH; |
| 2190 | /* 10 => 4 bit wide */ |
| 2191 | if (width == MMC_BOOT_BUS_WIDTH_1_BIT) { |
| 2192 | cmd.argument = 0; |
| 2193 | } else if (width == MMC_BOOT_BUS_WIDTH_4_BIT) { |
| 2194 | cmd.argument = (1 << 1); |
| 2195 | } |
| 2196 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2197 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 2198 | |
| 2199 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2200 | |
| 2201 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2202 | return mmc_ret; |
| 2203 | } |
| 2204 | |
| 2205 | /* set MCI_CLK accordingly */ |
| 2206 | sd_reg = readl(MMC_BOOT_MCI_CLK); |
| 2207 | sd_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE; |
| 2208 | if (width == MMC_BOOT_BUS_WIDTH_1_BIT) { |
| 2209 | sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT; |
| 2210 | } else if (width == MMC_BOOT_BUS_WIDTH_4_BIT) { |
| 2211 | sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT; |
| 2212 | } else if (width == MMC_BOOT_BUS_WIDTH_8_BIT) { |
| 2213 | sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT; |
| 2214 | } |
| 2215 | writel(sd_reg, MMC_BOOT_MCI_CLK); |
| 2216 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 2217 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 2218 | mmc_mclk_reg_wr_delay(); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2219 | |
| 2220 | return MMC_BOOT_E_SUCCESS; |
| 2221 | } |
| 2222 | |
| 2223 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2224 | mmc_boot_set_sd_hs(struct mmc_host *host, struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2225 | { |
| 2226 | unsigned char sw_buf[64]; |
| 2227 | unsigned int mmc_ret; |
| 2228 | |
| 2229 | /* CMD6 is a data transfer command. sD card returns 512 bits of data */ |
| 2230 | /* Refer 4.3.10 of sD card specification 3.0 */ |
| 2231 | mmc_ret = |
| 2232 | mmc_boot_read_reg(card, 64, CMD6_SWITCH_FUNC, MMC_BOOT_SD_SWITCH_HS, |
| 2233 | (unsigned int *)&sw_buf); |
| 2234 | |
| 2235 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2236 | return mmc_ret; |
| 2237 | } |
| 2238 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2239 | clock_config_mmc(mmc_slot, MMC_CLK_50MHZ); |
| 2240 | |
| 2241 | host->mclk_rate = MMC_CLK_50MHZ; |
| 2242 | |
| 2243 | return MMC_BOOT_E_SUCCESS; |
| 2244 | } |
| 2245 | |
| 2246 | /* |
| 2247 | * Performs initialization and identification of all the MMC cards connected |
| 2248 | * to the host. |
| 2249 | */ |
| 2250 | |
| 2251 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2252 | mmc_boot_init_and_identify_cards(struct mmc_host *host, |
| 2253 | struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2254 | { |
| 2255 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS; |
| 2256 | unsigned int status; |
Channagoud Kadabi | 7d84dd6 | 2012-08-24 21:20:56 +0530 | [diff] [blame] | 2257 | uint8_t mmc_bus_width = 0; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2258 | |
| 2259 | /* Basic check */ |
| 2260 | if (host == NULL) { |
| 2261 | return MMC_BOOT_E_INVAL; |
| 2262 | } |
| 2263 | |
| 2264 | /* Initialize MMC card structure */ |
| 2265 | card->status = MMC_BOOT_STATUS_INACTIVE; |
| 2266 | card->rd_block_len = MMC_BOOT_RD_BLOCK_LEN; |
| 2267 | card->wr_block_len = MMC_BOOT_WR_BLOCK_LEN; |
| 2268 | |
| 2269 | /* Start initialization process (CMD0 & CMD1) */ |
| 2270 | mmc_return = mmc_boot_init_card(host, card); |
| 2271 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2272 | return mmc_return; |
| 2273 | } |
| 2274 | |
| 2275 | /* Identify (CMD2, CMD3 & CMD9) and select the card (CMD7) */ |
| 2276 | mmc_return = mmc_boot_identify_card(host, card); |
| 2277 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2278 | return mmc_return; |
| 2279 | } |
| 2280 | |
| 2281 | if (card->type == MMC_BOOT_TYPE_SDHC |
| 2282 | || card->type == MMC_BOOT_TYPE_STD_SD) { |
| 2283 | /* Setting sD card to high speed without checking card's capability. |
| 2284 | Cards that do not support high speed may fail to boot */ |
| 2285 | mmc_return = mmc_boot_set_sd_hs(host, card); |
| 2286 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2287 | return mmc_return; |
| 2288 | } |
| 2289 | |
| 2290 | mmc_return = |
| 2291 | mmc_boot_set_sd_bus_width(card, MMC_BOOT_BUS_WIDTH_4_BIT); |
| 2292 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2293 | dprintf(CRITICAL, |
| 2294 | "Couldn't set 4bit mode for sD card\n"); |
| 2295 | mmc_return = |
| 2296 | mmc_boot_set_sd_bus_width(card, |
| 2297 | MMC_BOOT_BUS_WIDTH_1_BIT); |
| 2298 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2299 | dprintf(CRITICAL, |
| 2300 | "Error No.%d: Failed in setting bus width!\n", |
| 2301 | mmc_return); |
| 2302 | return mmc_return; |
| 2303 | } |
| 2304 | } |
| 2305 | } else { |
| 2306 | /* set interface speed */ |
| 2307 | mmc_return = mmc_boot_adjust_interface_speed(host, card); |
| 2308 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2309 | dprintf(CRITICAL, |
| 2310 | "Error No.%d: Error adjusting interface speed!\n", |
| 2311 | mmc_return); |
| 2312 | return mmc_return; |
| 2313 | } |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2314 | |
Channagoud Kadabi | 676c2e3 | 2013-04-02 11:39:01 -0700 | [diff] [blame] | 2315 | /* Enable HS200 mode by default if supported, |
| 2316 | * else if DDR mode is supported enable it. |
| 2317 | * else use default 4/8 bit mode |
| 2318 | */ |
| 2319 | if (card_supports_hs200_mode() && host->caps.hs200_mode) { |
| 2320 | mmc_return = mmc_set_hs200_mode(host, card); |
| 2321 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2322 | dprintf(CRITICAL, |
| 2323 | "Error No.%d: Failure to set HS200 mode for Card(RCA:%x)\n", |
| 2324 | mmc_return, card->rca); |
| 2325 | return mmc_return; |
| 2326 | } |
| 2327 | } else if (card_supports_ddr_mode() && host->caps.ddr_mode) { |
| 2328 | mmc_return = mmc_set_ddr_mode(host, card); |
| 2329 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2330 | dprintf(CRITICAL, |
| 2331 | "Error No.%d: Failure to set DDR mode for Card(RCA:%x)\n", |
| 2332 | mmc_return, card->rca); |
| 2333 | return mmc_return; |
| 2334 | } |
| 2335 | } else { |
| 2336 | mmc_return = |
| 2337 | mmc_boot_set_bus_width(card, host->caps.bus_width); |
| 2338 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2339 | dprintf(CRITICAL, |
| 2340 | "Error No.%d: Failure to set wide bus for Card(RCA:%x)\n", |
| 2341 | mmc_return, card->rca); |
| 2342 | return mmc_return; |
| 2343 | } |
| 2344 | } |
Channagoud Kadabi | 4f8fdb5 | 2013-05-30 13:10:41 -0700 | [diff] [blame] | 2345 | } |
Channagoud Kadabi | 676c2e3 | 2013-04-02 11:39:01 -0700 | [diff] [blame] | 2346 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2347 | /* Just checking whether we're in TRAN state after changing speed and bus width */ |
| 2348 | mmc_return = mmc_boot_get_card_status(card, 0, &status); |
| 2349 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2350 | return mmc_return; |
| 2351 | } |
| 2352 | |
| 2353 | if (MMC_BOOT_CARD_STATUS(status) != MMC_BOOT_TRAN_STATE) |
| 2354 | return MMC_BOOT_E_FAILURE; |
| 2355 | |
| 2356 | return MMC_BOOT_E_SUCCESS; |
| 2357 | } |
| 2358 | |
| 2359 | void mmc_display_ext_csd(void) |
| 2360 | { |
| 2361 | dprintf(SPEW, "part_config: %x\n", ext_csd_buf[179]); |
| 2362 | dprintf(SPEW, "erase_group_def: %x\n", ext_csd_buf[175]); |
| 2363 | dprintf(SPEW, "user_wp: %x\n", ext_csd_buf[171]); |
| 2364 | } |
| 2365 | |
| 2366 | void mmc_display_csd(void) |
| 2367 | { |
| 2368 | dprintf(SPEW, "erase_grpsize: %d\n", mmc_card.csd.erase_grp_size); |
| 2369 | dprintf(SPEW, "erase_grpmult: %d\n", mmc_card.csd.erase_grp_mult); |
| 2370 | dprintf(SPEW, "wp_grpsize: %d\n", mmc_card.csd.wp_grp_size); |
| 2371 | dprintf(SPEW, "wp_grpen: %d\n", mmc_card.csd.wp_grp_enable); |
| 2372 | dprintf(SPEW, "perm_wp: %d\n", mmc_card.csd.perm_wp); |
| 2373 | dprintf(SPEW, "temp_wp: %d\n", mmc_card.csd.temp_wp); |
| 2374 | } |
| 2375 | |
| 2376 | /* |
| 2377 | * Entry point to MMC boot process |
| 2378 | */ |
| 2379 | unsigned int mmc_boot_main(unsigned char slot, unsigned int base) |
| 2380 | { |
| 2381 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2382 | |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2383 | memset((struct mmc_host *)&mmc_host, 0, |
| 2384 | sizeof(struct mmc_host)); |
| 2385 | memset((struct mmc_card *)&mmc_card, 0, |
| 2386 | sizeof(struct mmc_card)); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2387 | |
| 2388 | mmc_slot = slot; |
| 2389 | mmc_boot_mci_base = base; |
| 2390 | |
Channagoud Kadabi | 676c2e3 | 2013-04-02 11:39:01 -0700 | [diff] [blame] | 2391 | /* Get the capabilities for the host/target */ |
| 2392 | target_mmc_caps(&mmc_host); |
| 2393 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2394 | /* Initialize necessary data structure and enable/set clock and power */ |
| 2395 | dprintf(SPEW, " Initializing MMC host data structure and clock!\n"); |
| 2396 | mmc_ret = mmc_boot_init(&mmc_host); |
| 2397 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2398 | dprintf(CRITICAL, "MMC Boot: Error Initializing MMC Card!!!\n"); |
| 2399 | return MMC_BOOT_E_FAILURE; |
| 2400 | } |
| 2401 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 2402 | #if MMC_BOOT_BAM |
| 2403 | |
| 2404 | mmc_ret = mmc_bam_init(mmc_sdc_bam_base[slot - 1]); |
| 2405 | dml_base = mmc_sdc_dml_base[slot - 1]; |
| 2406 | #endif |
| 2407 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2408 | /* Initialize and identify cards connected to host */ |
| 2409 | mmc_ret = mmc_boot_init_and_identify_cards(&mmc_host, &mmc_card); |
| 2410 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2411 | dprintf(CRITICAL, |
| 2412 | "MMC Boot: Failed detecting MMC/SDC @ slot%d\n", slot); |
| 2413 | return MMC_BOOT_E_FAILURE; |
| 2414 | } |
| 2415 | |
| 2416 | mmc_display_csd(); |
| 2417 | mmc_display_ext_csd(); |
| 2418 | |
Channagoud Kadabi | 7cf5d04 | 2013-04-19 12:58:15 -0700 | [diff] [blame] | 2419 | mmc_ret = partition_read_table(); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2420 | return mmc_ret; |
| 2421 | } |
| 2422 | |
| 2423 | /* |
| 2424 | * MMC write function |
| 2425 | */ |
| 2426 | unsigned int |
| 2427 | mmc_write(unsigned long long data_addr, unsigned int data_len, unsigned int *in) |
| 2428 | { |
| 2429 | int val = 0; |
| 2430 | unsigned int write_size = ((unsigned)(0xFFFFFF / 512)) * 512; |
| 2431 | unsigned offset = 0; |
| 2432 | unsigned int *sptr = in; |
| 2433 | |
| 2434 | if (data_len % 512) |
| 2435 | data_len = ROUND_TO_PAGE(data_len, 511); |
| 2436 | |
| 2437 | while (data_len > write_size) { |
| 2438 | val = mmc_boot_write_to_card(&mmc_host, &mmc_card, |
| 2439 | data_addr + offset, write_size, |
| 2440 | sptr); |
| 2441 | if (val) { |
| 2442 | return val; |
| 2443 | } |
| 2444 | |
| 2445 | sptr += (write_size / sizeof(unsigned)); |
| 2446 | offset += write_size; |
| 2447 | data_len -= write_size; |
| 2448 | } |
| 2449 | if (data_len) { |
| 2450 | val = mmc_boot_write_to_card(&mmc_host, &mmc_card, |
| 2451 | data_addr + offset, data_len, |
| 2452 | sptr); |
| 2453 | } |
| 2454 | return val; |
| 2455 | } |
| 2456 | |
| 2457 | /* |
| 2458 | * MMC read function |
| 2459 | */ |
| 2460 | |
| 2461 | unsigned int |
| 2462 | mmc_read(unsigned long long data_addr, unsigned int *out, unsigned int data_len) |
| 2463 | { |
| 2464 | int val = 0; |
| 2465 | val = |
| 2466 | mmc_boot_read_from_card(&mmc_host, &mmc_card, data_addr, data_len, |
| 2467 | out); |
| 2468 | return val; |
| 2469 | } |
| 2470 | |
| 2471 | /* |
| 2472 | * Function to read registers from MMC or SD card |
| 2473 | */ |
| 2474 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2475 | mmc_boot_read_reg(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2476 | unsigned int data_len, |
| 2477 | unsigned int command, unsigned int addr, unsigned int *out) |
| 2478 | { |
| 2479 | struct mmc_boot_command cmd; |
| 2480 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2481 | unsigned int mmc_reg = 0; |
| 2482 | |
| 2483 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */ |
| 2484 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 2485 | mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 2486 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 2487 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 2488 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 2489 | mmc_mclk_reg_wr_delay(); |
| 2490 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2491 | /* Write data timeout period to MCI_DATA_TIMER register. */ |
| 2492 | /* Data timeout period should be in card bus clock periods */ |
| 2493 | mmc_reg = 0xFFFFFFFF; |
| 2494 | writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER); |
| 2495 | writel(data_len, MMC_BOOT_MCI_DATA_LENGTH); |
| 2496 | |
| 2497 | /* Set appropriate fields and write the MCI_DATA_CTL register. */ |
| 2498 | /* Set ENABLE bit to 1 to enable the data transfer. */ |
| 2499 | mmc_reg = |
| 2500 | MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (data_len << |
| 2501 | MMC_BOOT_MCI_BLKSIZE_POS); |
| 2502 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 2503 | #if MMC_BOOT_ADM || MMC_BOOT_BAM |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2504 | mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE; |
| 2505 | #endif |
| 2506 | |
| 2507 | writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL); |
| 2508 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 2509 | /* Wait for the MMC_BOOT_MCI_DATA_CTL write to go through. */ |
| 2510 | mmc_mclk_reg_wr_delay(); |
| 2511 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2512 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2513 | sizeof(struct mmc_boot_command)); |
| 2514 | |
| 2515 | cmd.cmd_index = command; |
| 2516 | cmd.argument = addr; |
| 2517 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2518 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 2519 | |
| 2520 | /* send command */ |
| 2521 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2522 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2523 | return mmc_ret; |
| 2524 | } |
| 2525 | |
| 2526 | /* Read the transfer data from SDCC FIFO. */ |
| 2527 | mmc_ret = |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 2528 | mmc_boot_data_transfer(out, data_len, MMC_BOOT_DATA_READ); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2529 | |
| 2530 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2531 | dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \ |
| 2532 | Card(RCA:%x)\n", mmc_ret, |
| 2533 | card->rca); |
| 2534 | return mmc_ret; |
| 2535 | } |
| 2536 | |
| 2537 | return MMC_BOOT_E_SUCCESS; |
| 2538 | } |
| 2539 | |
| 2540 | /* |
| 2541 | * Function to set/clear power-on write protection for the user area partitions |
| 2542 | */ |
| 2543 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2544 | mmc_boot_set_clr_power_on_wp_user(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2545 | unsigned int addr, |
| 2546 | unsigned int size, unsigned char set_clear_wp) |
| 2547 | { |
| 2548 | struct mmc_boot_command cmd; |
| 2549 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2550 | unsigned int wp_group_size, loop_count; |
| 2551 | unsigned int status; |
| 2552 | |
| 2553 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2554 | sizeof(struct mmc_boot_command)); |
| 2555 | |
| 2556 | /* Disabling PERM_WP for USER AREA (CMD6) */ |
Channagoud Kadabi | 8416283 | 2013-11-22 14:57:56 -0800 | [diff] [blame] | 2557 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_SET_BIT, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2558 | MMC_BOOT_EXT_USER_WP, |
| 2559 | MMC_BOOT_US_PERM_WP_DIS); |
| 2560 | |
| 2561 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2562 | return mmc_ret; |
| 2563 | } |
| 2564 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2565 | mmc_ret = mmc_boot_send_ext_cmd(card, ext_csd_buf); |
| 2566 | |
| 2567 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2568 | return mmc_ret; |
| 2569 | } |
| 2570 | |
| 2571 | /* Make sure power-on write protection for user area is not disabled |
| 2572 | and permanent write protection for user area is not enabled */ |
| 2573 | |
| 2574 | if ((IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PERM_WP_EN)) |
| 2575 | || |
| 2576 | (IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PWR_WP_DIS))) |
| 2577 | { |
| 2578 | return MMC_BOOT_E_FAILURE; |
| 2579 | } |
| 2580 | |
| 2581 | if (ext_csd_buf[MMC_BOOT_EXT_ERASE_GROUP_DEF]) { |
| 2582 | /* wp_group_size = 512KB * HC_WP_GRP_SIZE * HC_ERASE_GRP_SIZE. |
| 2583 | Getting write protect group size in sectors here. */ |
| 2584 | |
| 2585 | wp_group_size = |
| 2586 | (512 * 1024) * ext_csd_buf[MMC_BOOT_EXT_HC_WP_GRP_SIZE] * |
| 2587 | ext_csd_buf[MMC_BOOT_EXT_HC_ERASE_GRP_SIZE] / |
| 2588 | MMC_BOOT_WR_BLOCK_LEN; |
| 2589 | } else { |
| 2590 | /* wp_group_size = (WP_GRP_SIZE + 1) * (ERASE_GRP_SIZE + 1) |
| 2591 | * (ERASE_GRP_MULT + 1). |
| 2592 | This is defined as the number of write blocks directly */ |
| 2593 | |
| 2594 | wp_group_size = (card->csd.erase_grp_size + 1) * |
| 2595 | (card->csd.erase_grp_mult + 1) * (card->csd.wp_grp_size + |
| 2596 | 1); |
| 2597 | } |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 2598 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2599 | if (wp_group_size == 0) { |
| 2600 | return MMC_BOOT_E_FAILURE; |
| 2601 | } |
| 2602 | |
| 2603 | /* Setting POWER_ON_WP for USER AREA (CMD6) */ |
Channagoud Kadabi | 8416283 | 2013-11-22 14:57:56 -0800 | [diff] [blame] | 2604 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_SET_BIT, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2605 | MMC_BOOT_EXT_USER_WP, |
| 2606 | MMC_BOOT_US_PWR_WP_EN); |
| 2607 | |
| 2608 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2609 | return mmc_ret; |
| 2610 | } |
| 2611 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2612 | /* Calculating the loop count for sending SET_WRITE_PROTECT (CMD28) |
| 2613 | or CLEAR_WRITE_PROTECT (CMD29). |
| 2614 | We are write protecting the partitions in blocks of write protect |
| 2615 | group sizes only */ |
| 2616 | |
| 2617 | if (size % wp_group_size) { |
| 2618 | loop_count = (size / wp_group_size) + 1; |
| 2619 | } else { |
| 2620 | loop_count = (size / wp_group_size); |
| 2621 | } |
| 2622 | |
| 2623 | if (set_clear_wp) |
| 2624 | cmd.cmd_index = CMD28_SET_WRITE_PROTECT; |
| 2625 | else |
| 2626 | cmd.cmd_index = CMD29_CLEAR_WRITE_PROTECT; |
| 2627 | |
| 2628 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2629 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 2630 | |
| 2631 | for (unsigned int i = 0; i < loop_count; i++) { |
| 2632 | /* Sending CMD28 for each WP group size |
| 2633 | address is in sectors already */ |
| 2634 | cmd.argument = (addr + (i * wp_group_size)); |
| 2635 | |
| 2636 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2637 | |
| 2638 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2639 | return mmc_ret; |
| 2640 | } |
| 2641 | |
| 2642 | /* Checking ADDR_OUT_OF_RANGE error in CMD28 response */ |
| 2643 | if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) { |
| 2644 | return MMC_BOOT_E_FAILURE; |
| 2645 | } |
| 2646 | |
| 2647 | /* Sending CMD13 to check card status */ |
| 2648 | do { |
| 2649 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 2650 | if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE) |
| 2651 | break; |
| 2652 | } |
| 2653 | while ((mmc_ret == MMC_BOOT_E_SUCCESS) && |
| 2654 | (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE)); |
| 2655 | |
| 2656 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2657 | return mmc_ret; |
| 2658 | } |
| 2659 | } |
| 2660 | |
| 2661 | return MMC_BOOT_E_SUCCESS; |
| 2662 | } |
| 2663 | |
| 2664 | /* |
| 2665 | * Function to get Write Protect status of the given sector |
| 2666 | */ |
| 2667 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2668 | mmc_boot_get_wp_status(struct mmc_card *card, unsigned int sector) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2669 | { |
| 2670 | unsigned int rc = MMC_BOOT_E_SUCCESS; |
| 2671 | memset(wp_status_buf, 0, 8); |
| 2672 | |
| 2673 | rc = mmc_boot_read_reg(card, 8, CMD31_SEND_WRITE_PROT_TYPE, sector, |
| 2674 | (unsigned int *)wp_status_buf); |
| 2675 | return rc; |
| 2676 | } |
| 2677 | |
| 2678 | /* |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 2679 | * Test Function for setting Write protect for given sector |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2680 | */ |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 2681 | static unsigned int |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2682 | mmc_wp(unsigned int sector, unsigned int size, unsigned char set_clear_wp) |
| 2683 | { |
| 2684 | unsigned int rc = MMC_BOOT_E_SUCCESS; |
| 2685 | |
| 2686 | /* Checking whether group write protection feature is available */ |
Channagoud Kadabi | 8416283 | 2013-11-22 14:57:56 -0800 | [diff] [blame] | 2687 | if (mmc_card.csd.wp_grp_enable) |
| 2688 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2689 | rc = mmc_boot_get_wp_status(&mmc_card, sector); |
Channagoud Kadabi | 8416283 | 2013-11-22 14:57:56 -0800 | [diff] [blame] | 2690 | if (rc != MMC_BOOT_E_SUCCESS) |
| 2691 | { |
| 2692 | dprintf(CRITICAL, "Failure in getting wp_status (%u):%s:%u\n", rc, __FILE__, __LINE__); |
| 2693 | return rc; |
| 2694 | } |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2695 | rc = mmc_boot_set_clr_power_on_wp_user(&mmc_card, sector, size, |
| 2696 | set_clear_wp); |
Channagoud Kadabi | 8416283 | 2013-11-22 14:57:56 -0800 | [diff] [blame] | 2697 | if (rc != MMC_BOOT_E_SUCCESS) |
| 2698 | { |
| 2699 | dprintf(CRITICAL, "Failure in setting power on wp user (%u):%s:%u\n", rc, __FILE__, __LINE__); |
| 2700 | return rc; |
| 2701 | } |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2702 | rc = mmc_boot_get_wp_status(&mmc_card, sector); |
Channagoud Kadabi | 8416283 | 2013-11-22 14:57:56 -0800 | [diff] [blame] | 2703 | if (rc != MMC_BOOT_E_SUCCESS) |
| 2704 | { |
| 2705 | dprintf(CRITICAL, "Failure in getting wp_status (%u)%s:%u\n", rc, __FILE__, __LINE__); |
| 2706 | return rc; |
| 2707 | } |
| 2708 | } |
| 2709 | else |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2710 | return MMC_BOOT_E_FAILURE; |
| 2711 | } |
| 2712 | |
| 2713 | void mmc_wp_test(void) |
| 2714 | { |
| 2715 | unsigned int mmc_ret = 0; |
| 2716 | mmc_ret = mmc_wp(0xE06000, 0x5000, 1); |
| 2717 | } |
| 2718 | |
| 2719 | unsigned mmc_get_psn(void) |
| 2720 | { |
| 2721 | return mmc_card.cid.psn; |
| 2722 | } |
| 2723 | |
| 2724 | /* |
| 2725 | * Read/write data from/to SDC FIFO. |
| 2726 | */ |
| 2727 | static unsigned int |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 2728 | mmc_boot_data_transfer(unsigned int *data_ptr, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2729 | unsigned int data_len, unsigned char direction) |
| 2730 | { |
| 2731 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2732 | |
| 2733 | #if MMC_BOOT_ADM |
| 2734 | adm_result_t ret; |
| 2735 | adm_dir_t adm_dir; |
| 2736 | |
| 2737 | if (direction == MMC_BOOT_DATA_READ) { |
| 2738 | adm_dir = ADM_MMC_READ; |
| 2739 | } else { |
| 2740 | adm_dir = ADM_MMC_WRITE; |
| 2741 | } |
| 2742 | |
| 2743 | ret = adm_transfer_mmc_data(mmc_slot, |
| 2744 | (unsigned char *)data_ptr, data_len, |
| 2745 | adm_dir); |
| 2746 | |
| 2747 | if (ret != ADM_RESULT_SUCCESS) { |
| 2748 | dprintf(CRITICAL, "MMC ADM transfer error: %d\n", ret); |
| 2749 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 2750 | } |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 2751 | |
| 2752 | #elif MMC_BOOT_BAM |
| 2753 | mmc_ret = mmc_bam_transfer_data(data_ptr, data_len, direction); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2754 | #else |
| 2755 | |
| 2756 | if (direction == MMC_BOOT_DATA_READ) { |
| 2757 | mmc_ret = mmc_boot_fifo_read(data_ptr, data_len); |
| 2758 | } else { |
| 2759 | mmc_ret = mmc_boot_fifo_write(data_ptr, data_len); |
| 2760 | } |
| 2761 | #endif |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 2762 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2763 | return mmc_ret; |
| 2764 | } |
| 2765 | |
| 2766 | /* |
| 2767 | * Read data to SDC FIFO. |
| 2768 | */ |
| 2769 | static unsigned int |
| 2770 | mmc_boot_fifo_read(unsigned int *mmc_ptr, unsigned int data_len) |
| 2771 | { |
| 2772 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2773 | unsigned int mmc_status = 0; |
| 2774 | unsigned int mmc_count = 0; |
| 2775 | unsigned int read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | |
| 2776 | MMC_BOOT_MCI_STAT_DATA_TIMEOUT | MMC_BOOT_MCI_STAT_RX_OVRRUN; |
| 2777 | |
| 2778 | /* Read the data from the MCI_FIFO register as long as RXDATA_AVLBL |
| 2779 | bit of MCI_STATUS register is set to 1 and bits DATA_CRC_FAIL, |
| 2780 | DATA_TIMEOUT, RX_OVERRUN of MCI_STATUS register are cleared to 0. |
| 2781 | Continue the reads until the whole transfer data is received */ |
| 2782 | |
| 2783 | do { |
| 2784 | mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2785 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 2786 | |
| 2787 | if (mmc_status & read_error) { |
| 2788 | mmc_ret = mmc_boot_status_error(mmc_status); |
| 2789 | break; |
| 2790 | } |
| 2791 | |
| 2792 | if (mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL) { |
| 2793 | unsigned read_count = 1; |
| 2794 | if (mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL) { |
| 2795 | read_count = MMC_BOOT_MCI_HFIFO_COUNT; |
| 2796 | } |
| 2797 | |
| 2798 | for (unsigned int i = 0; i < read_count; i++) { |
| 2799 | /* FIFO contains 16 32-bit data buffer on 16 sequential addresses */ |
| 2800 | *mmc_ptr = readl(MMC_BOOT_MCI_FIFO + |
| 2801 | (mmc_count % |
| 2802 | MMC_BOOT_MCI_FIFO_SIZE)); |
| 2803 | mmc_ptr++; |
| 2804 | /* increase mmc_count by word size */ |
| 2805 | mmc_count += sizeof(unsigned int); |
| 2806 | } |
| 2807 | /* quit if we have read enough of data */ |
| 2808 | if (mmc_count == data_len) |
| 2809 | break; |
| 2810 | } else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_END) { |
| 2811 | break; |
| 2812 | } |
| 2813 | } |
| 2814 | while (1); |
| 2815 | |
| 2816 | return mmc_ret; |
| 2817 | } |
| 2818 | |
| 2819 | /* |
| 2820 | * Write data to SDC FIFO. |
| 2821 | */ |
| 2822 | static unsigned int |
| 2823 | mmc_boot_fifo_write(unsigned int *mmc_ptr, unsigned int data_len) |
| 2824 | { |
| 2825 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2826 | unsigned int mmc_status = 0; |
| 2827 | unsigned int mmc_count = 0; |
| 2828 | unsigned int write_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | |
| 2829 | MMC_BOOT_MCI_STAT_DATA_TIMEOUT | MMC_BOOT_MCI_STAT_TX_UNDRUN; |
Shashank Mittal | 5d19111 | 2012-09-19 17:02:21 -0700 | [diff] [blame] | 2830 | unsigned int count = 0; |
| 2831 | unsigned int sz = 0; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2832 | |
| 2833 | /* Write the transfer data to SDCC3 FIFO */ |
| 2834 | do { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2835 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 2836 | |
Shashank Mittal | 5d19111 | 2012-09-19 17:02:21 -0700 | [diff] [blame] | 2837 | /* Bytes left to write */ |
| 2838 | count = data_len - mmc_count; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2839 | |
Shashank Mittal | 5d19111 | 2012-09-19 17:02:21 -0700 | [diff] [blame] | 2840 | /* Break if whole data is transferred */ |
| 2841 | if (!count) |
| 2842 | break; |
| 2843 | |
| 2844 | /* Write half FIFO or less (remaining) words in MCI_FIFO as long as either |
| 2845 | TX_FIFO_EMPTY or TX_FIFO_HFULL bits of MCI_STATUS register are set. */ |
| 2846 | if ((mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_EMPTY) || |
| 2847 | (mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_HFULL)) { |
| 2848 | |
| 2849 | /* Write minimum of half FIFO and remaining words */ |
| 2850 | sz = ((count >> 2) > MMC_BOOT_MCI_HFIFO_COUNT) \ |
| 2851 | ? MMC_BOOT_MCI_HFIFO_COUNT : (count >> 2); |
| 2852 | |
| 2853 | for (int i = 0; i < sz; i++) { |
| 2854 | writel(*mmc_ptr, MMC_BOOT_MCI_FIFO); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2855 | mmc_ptr++; |
| 2856 | /* increase mmc_count by word size */ |
| 2857 | mmc_count += sizeof(unsigned int); |
| 2858 | } |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2859 | } |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2860 | } |
| 2861 | while (1); |
Shashank Mittal | 5d19111 | 2012-09-19 17:02:21 -0700 | [diff] [blame] | 2862 | |
| 2863 | do |
| 2864 | { |
| 2865 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 2866 | if (mmc_status & write_error) { |
| 2867 | mmc_ret = mmc_boot_status_error(mmc_status); |
| 2868 | break; |
| 2869 | } |
| 2870 | } |
| 2871 | while (!(mmc_status & MMC_BOOT_MCI_STAT_DATA_END)); |
| 2872 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2873 | return mmc_ret; |
| 2874 | } |
| 2875 | |
| 2876 | /* |
| 2877 | * CMD35_ERASE_GROUP_START |
| 2878 | */ |
| 2879 | |
| 2880 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2881 | mmc_boot_send_erase_group_start(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2882 | unsigned long long data_addr) |
| 2883 | { |
| 2884 | struct mmc_boot_command cmd; |
| 2885 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2886 | |
| 2887 | if (card == NULL) |
| 2888 | return MMC_BOOT_E_INVAL; |
| 2889 | |
| 2890 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2891 | sizeof(struct mmc_boot_command)); |
| 2892 | |
| 2893 | cmd.cmd_index = CMD35_ERASE_GROUP_START; |
| 2894 | cmd.argument = data_addr; |
| 2895 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2896 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 2897 | |
| 2898 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2899 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2900 | return mmc_ret; |
| 2901 | } |
| 2902 | |
| 2903 | /* Checking for address error */ |
| 2904 | if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) { |
| 2905 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 2906 | } |
| 2907 | |
| 2908 | return MMC_BOOT_E_SUCCESS; |
| 2909 | |
| 2910 | } |
| 2911 | |
| 2912 | /* |
| 2913 | * CMD36 ERASE GROUP END |
| 2914 | */ |
| 2915 | static unsigned int |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2916 | mmc_boot_send_erase_group_end(struct mmc_card *card, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2917 | unsigned long long data_addr) |
| 2918 | { |
| 2919 | struct mmc_boot_command cmd; |
| 2920 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2921 | |
| 2922 | if (card == NULL) |
| 2923 | return MMC_BOOT_E_INVAL; |
| 2924 | |
| 2925 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2926 | sizeof(struct mmc_boot_command)); |
| 2927 | |
| 2928 | cmd.cmd_index = CMD36_ERASE_GROUP_END; |
| 2929 | cmd.argument = data_addr; |
| 2930 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2931 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 2932 | |
| 2933 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2934 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2935 | return mmc_ret; |
| 2936 | } |
| 2937 | |
| 2938 | /* Checking for address error */ |
| 2939 | if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) { |
| 2940 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 2941 | } |
| 2942 | |
| 2943 | return MMC_BOOT_E_SUCCESS; |
| 2944 | } |
| 2945 | |
| 2946 | /* |
| 2947 | * CMD38 ERASE |
| 2948 | */ |
Channagoud Kadabi | 398e1a2 | 2013-03-18 12:06:11 -0700 | [diff] [blame] | 2949 | static unsigned int mmc_boot_send_erase(struct mmc_card *card) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2950 | { |
| 2951 | |
| 2952 | struct mmc_boot_command cmd; |
| 2953 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2954 | unsigned int status; |
| 2955 | |
| 2956 | if (card == NULL) |
| 2957 | return MMC_BOOT_E_INVAL; |
| 2958 | |
| 2959 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2960 | sizeof(struct mmc_boot_command)); |
| 2961 | |
| 2962 | cmd.cmd_index = CMD38_ERASE; |
| 2963 | cmd.argument = 0x00000000; |
| 2964 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2965 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 2966 | |
| 2967 | /* Checking if the card is in the transfer state */ |
| 2968 | do { |
| 2969 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 2970 | if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE) |
| 2971 | break; |
| 2972 | } |
| 2973 | while ((mmc_ret == MMC_BOOT_E_SUCCESS) && |
| 2974 | (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE)); |
| 2975 | |
| 2976 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2977 | return mmc_ret; |
| 2978 | } |
| 2979 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2980 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2981 | return mmc_ret; |
| 2982 | } |
| 2983 | |
| 2984 | /* Checking for write protect */ |
| 2985 | if (cmd.resp[0] & MMC_BOOT_R1_WP_ERASE_SKIP) { |
| 2986 | dprintf(CRITICAL, "Write protect enabled for sector \n"); |
| 2987 | return; |
| 2988 | } |
| 2989 | |
| 2990 | /* Checking if the erase operation for the card is compelete */ |
| 2991 | do { |
| 2992 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 2993 | if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE) |
| 2994 | break; |
| 2995 | } |
| 2996 | while ((mmc_ret == MMC_BOOT_E_SUCCESS) && |
| 2997 | (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE)); |
| 2998 | |
| 2999 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 3000 | return mmc_ret; |
| 3001 | } |
| 3002 | |
| 3003 | return MMC_BOOT_E_SUCCESS; |
| 3004 | } |
| 3005 | |
| 3006 | /* |
| 3007 | * Function to erase data on the eMMC card |
| 3008 | */ |
| 3009 | unsigned int |
| 3010 | mmc_erase_card(unsigned long long data_addr, unsigned long long size) |
| 3011 | { |
| 3012 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 3013 | unsigned long long erase_grp_size; |
| 3014 | unsigned long long data_end = 0x00000000; |
| 3015 | unsigned long long loop_count; |
| 3016 | unsigned int out[512] = { 0 }; |
| 3017 | |
| 3018 | /* Converting size to sectors */ |
| 3019 | size = size / 512; |
| 3020 | |
| 3021 | if (ext_csd_buf[MMC_BOOT_EXT_ERASE_GROUP_DEF]) { |
| 3022 | erase_grp_size = |
| 3023 | (512 * ext_csd_buf[MMC_BOOT_EXT_HC_ERASE_GRP_SIZE] * 1024); |
| 3024 | erase_grp_size = erase_grp_size / 512; |
| 3025 | } else { |
| 3026 | erase_grp_size = (mmc_card.csd.erase_grp_size + 1) * |
| 3027 | (mmc_card.csd.erase_grp_mult + 1); |
| 3028 | } |
| 3029 | |
| 3030 | if (erase_grp_size == 0) { |
| 3031 | return MMC_BOOT_E_FAILURE; |
| 3032 | } |
| 3033 | |
| 3034 | if (size % erase_grp_size) { |
| 3035 | dprintf(CRITICAL, "Overflow beyond ERASE_GROUP_SIZE:%llu\n", |
| 3036 | (size % erase_grp_size)); |
| 3037 | |
| 3038 | } |
| 3039 | loop_count = (size / erase_grp_size); |
| 3040 | /* |
| 3041 | *In case the partition size is less than the erase_grp_size |
| 3042 | 0 is written to the first block of the partition. |
| 3043 | */ |
| 3044 | if (loop_count < 1) { |
| 3045 | mmc_ret = mmc_write(data_addr, 512, (unsigned int *)out); |
| 3046 | if (mmc_ret != MMC_BOOT_E_SUCCESS) |
| 3047 | return mmc_ret; |
| 3048 | else |
| 3049 | return MMC_BOOT_E_SUCCESS; |
| 3050 | } else { |
| 3051 | data_addr = ((mmc_card.type != MMC_BOOT_TYPE_MMCHC) && |
| 3052 | (mmc_card.type != MMC_BOOT_TYPE_SDHC)) |
| 3053 | ? (unsigned int)data_addr : (unsigned int)(data_addr / 512); |
| 3054 | data_end = data_addr + erase_grp_size * (loop_count - 1); |
| 3055 | } |
| 3056 | |
| 3057 | /* Sending CMD35 */ |
| 3058 | mmc_ret = mmc_boot_send_erase_group_start(&mmc_card, data_addr); |
| 3059 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 3060 | dprintf(CRITICAL, "Error %d: Failure sending erase group start " |
| 3061 | "command to the card (RCA:%x)\n", mmc_ret, |
| 3062 | mmc_card.rca); |
| 3063 | return mmc_ret; |
| 3064 | } |
| 3065 | |
| 3066 | /* Sending CMD36 */ |
Neeti Desai | e8bd43d | 2012-04-11 17:12:31 -0700 | [diff] [blame] | 3067 | mmc_ret = mmc_boot_send_erase_group_end(&mmc_card, data_end); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 3068 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 3069 | dprintf(CRITICAL, "Error %d: Failure sending erase group end " |
| 3070 | "command to the card (RCA:%x)\n", mmc_ret, |
| 3071 | mmc_card.rca); |
| 3072 | return mmc_ret; |
| 3073 | } |
| 3074 | |
Neeti Desai | e8bd43d | 2012-04-11 17:12:31 -0700 | [diff] [blame] | 3075 | /* Sending CMD38 */ |
| 3076 | mmc_ret = mmc_boot_send_erase(&mmc_card); |
| 3077 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 3078 | dprintf(CRITICAL, |
| 3079 | "Error %d: Failure sending erase command " |
| 3080 | "to the card (RCA:%x)\n", mmc_ret, mmc_card.rca); |
| 3081 | return mmc_ret; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 3082 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 3083 | } |
Neeti Desai | e8bd43d | 2012-04-11 17:12:31 -0700 | [diff] [blame] | 3084 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 3085 | dprintf(CRITICAL, "ERASE SUCCESSFULLY COMPLETED\n"); |
| 3086 | return MMC_BOOT_E_SUCCESS; |
| 3087 | } |
| 3088 | |
Channagoud Kadabi | e2ec5a4 | 2013-03-14 16:30:42 -0700 | [diff] [blame] | 3089 | /* |
| 3090 | * Disable MCI clk |
| 3091 | */ |
| 3092 | void mmc_boot_mci_clk_disable() |
| 3093 | { |
| 3094 | uint32_t reg = 0; |
| 3095 | |
| 3096 | reg |= MMC_BOOT_MCI_CLK_DISABLE; |
| 3097 | writel(reg, MMC_BOOT_MCI_CLK); |
| 3098 | |
| 3099 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 3100 | mmc_mclk_reg_wr_delay(); |
| 3101 | } |
| 3102 | |
| 3103 | /* |
| 3104 | * Enable MCI CLK |
| 3105 | */ |
| 3106 | void mmc_boot_mci_clk_enable() |
| 3107 | { |
| 3108 | uint32_t reg = 0; |
| 3109 | |
| 3110 | reg |= MMC_BOOT_MCI_CLK_ENABLE; |
| 3111 | reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 3112 | reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; |
| 3113 | writel(reg, MMC_BOOT_MCI_CLK); |
| 3114 | |
| 3115 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 3116 | mmc_mclk_reg_wr_delay(); |
Channagoud Kadabi | e2ec5a4 | 2013-03-14 16:30:42 -0700 | [diff] [blame] | 3117 | } |
| 3118 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 3119 | #if MMC_BOOT_BAM |
| 3120 | |
| 3121 | void mmc_boot_dml_init() |
| 3122 | { |
| 3123 | uint32_t val = 0; |
| 3124 | |
| 3125 | /* Initialize s/w reset for DML core */ |
| 3126 | mmc_boot_dml_reset(); |
| 3127 | |
| 3128 | /* Program DML config: |
| 3129 | * 1. Disable producer and consumer CRCI. |
| 3130 | * 2. Set Bypass mode for the DML for Direct access. |
| 3131 | */ |
| 3132 | val = 0; |
| 3133 | val |= 1 >> SDCC_BYPASS_SHIFT; |
| 3134 | writel(val, SDCC_DML_CONFIG(dml_base)); |
| 3135 | |
| 3136 | /* Program consumer logic size: |
| 3137 | * This is for handshaking between the BAM and the DML blocks. |
| 3138 | */ |
| 3139 | writel(4096, SDCC_DML_CONSUMER_PIPE_LOGICAL_SIZE(dml_base)); |
| 3140 | |
| 3141 | /* Program producer logic size |
| 3142 | * This is for handshaking between the BAM and the DML blocks. |
| 3143 | */ |
| 3144 | writel(4096, SDCC_DML_PRODUCER_PIPE_LOGICAL_SIZE(dml_base)); |
| 3145 | |
| 3146 | |
| 3147 | /* Write the pipe id numbers. */ |
| 3148 | val = 0; |
| 3149 | val |= bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].pipe_num << SDCC_PRODUCER_PIPE_ID_SHIFT; |
| 3150 | val |= bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].pipe_num << SDCC_CONSUMER_PIPE_ID_SHIFT; |
| 3151 | |
| 3152 | writel(val, SDCC_DML_PIPE_ID(dml_base)); |
| 3153 | |
| 3154 | } |
| 3155 | |
| 3156 | /* Function to set up SDCC dml for System producer transaction. */ |
| 3157 | static void mmc_boot_dml_consumer_trans_init() |
| 3158 | { |
| 3159 | uint32_t val = 0; |
| 3160 | |
| 3161 | val = 0 << SDCC_PRODUCER_CRCI_SEL_SHIFT; |
| 3162 | val |= 1 << SDCC_CONSUMER_CRCI_SEL_SHIFT; |
| 3163 | writel(val, SDCC_DML_CONFIG(dml_base)); |
| 3164 | |
| 3165 | |
| 3166 | /* Start the consumer transaction */ |
| 3167 | writel(1, SDCC_DML_CONSUMER_START(dml_base)); |
| 3168 | |
| 3169 | } |
| 3170 | |
| 3171 | /* Function to set up SDCC dml for System consumer transaction. |
| 3172 | * trans_end: 1: Assert DML trasaction signal |
| 3173 | * at the end of transaction. |
| 3174 | * 0: Do not assert DML transaction signal. |
| 3175 | * size: Transaction size |
| 3176 | */ |
| 3177 | static void mmc_boot_dml_producer_trans_init(unsigned trans_end, |
| 3178 | unsigned size) |
| 3179 | { |
| 3180 | uint32_t val = 0; |
| 3181 | |
| 3182 | val = 1 << SDCC_PRODUCER_CRCI_SEL_SHIFT; |
| 3183 | val |= 0 << SDCC_CONSUMER_CRCI_SEL_SHIFT; |
| 3184 | val |= trans_end << SDCC_PRODUCER_TRANS_END_EN_SHIFT; |
| 3185 | writel(val, SDCC_DML_CONFIG(dml_base)); |
| 3186 | |
| 3187 | /* Set block size */ |
| 3188 | writel(BLOCK_SIZE, SDCC_DML_PRODUCER_BAM_BLOCK_SIZE(dml_base)); |
| 3189 | |
| 3190 | /* Write transaction size */ |
| 3191 | writel(size, SDCC_DML_PRODUCER_BAM_TRANS_SIZE(dml_base)); |
| 3192 | |
| 3193 | /* Start the producer transaction */ |
| 3194 | writel(1, SDCC_DML_PRODUCER_START(dml_base)); |
| 3195 | } |
| 3196 | |
| 3197 | /* Function to check producer idle status of the DML. |
| 3198 | * return value: 1: Producer is idle |
| 3199 | * 0: Producer is busy |
| 3200 | */ |
| 3201 | static uint32_t mmc_boot_dml_chk_producer_idle() |
| 3202 | { |
| 3203 | uint32_t val = 0; |
| 3204 | |
| 3205 | val = readl(SDCC_DML_STATUS(dml_base)); |
| 3206 | |
| 3207 | /* Read only the producer idle status */ |
| 3208 | val &= (1 << SDCC_DML_PRODUCER_IDLE_SHIFT); |
| 3209 | |
| 3210 | return val; |
| 3211 | } |
| 3212 | |
| 3213 | /* Function to clear transaction complete flag */ |
| 3214 | static void mmc_boot_dml_clr_trans_complete() |
| 3215 | { |
| 3216 | uint32_t val; |
| 3217 | |
| 3218 | val = readl(SDCC_DML_CONFIG(dml_base)); |
| 3219 | |
| 3220 | val &= ~(1 << SDCC_PRODUCER_TRANS_END_EN_SHIFT); |
| 3221 | writel(val, SDCC_DML_CONFIG(dml_base)); |
| 3222 | } |
| 3223 | |
| 3224 | /* Blocking function to wait until DML is idle. */ |
| 3225 | static void mmc_boot_dml_wait_producer_idle() |
| 3226 | { |
| 3227 | while(!(readl(SDCC_DML_STATUS(dml_base)) & 1)); |
| 3228 | } |
| 3229 | |
| 3230 | /* Blocking function to wait until DML is idle. */ |
| 3231 | static void mmc_boot_dml_wait_consumer_idle() |
| 3232 | { |
| 3233 | while(!(readl(SDCC_DML_STATUS(dml_base)) & (1 << SDCC_DML_CONSUMER_IDLE_SHIFT))); |
| 3234 | } |
| 3235 | |
| 3236 | /* Initialize S/W reset */ |
| 3237 | static void mmc_boot_dml_reset() |
| 3238 | { |
| 3239 | /* Initialize s/w reset for DML core */ |
| 3240 | writel(1, SDCC_DML_SW_RESET(dml_base)); |
| 3241 | |
| 3242 | } |
| 3243 | |
| 3244 | static int mmc_bam_init(uint32_t bam_base) |
| 3245 | { |
| 3246 | |
| 3247 | uint32_t mmc_ret = MMC_BOOT_E_SUCCESS; |
| 3248 | |
| 3249 | bam.base = bam_base; |
| 3250 | /* Read pipe parameter initializations. */ |
| 3251 | bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].pipe_num = MMC_BOOT_BAM_READ_PIPE; |
| 3252 | /* System consumer */ |
| 3253 | bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].trans_type = BAM2SYS; |
| 3254 | /* Set the descriptor FIFO start ptr */ |
| 3255 | bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].fifo.head = desc_fifo; |
| 3256 | /* Set the descriptor FIFO lengths */ |
| 3257 | bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].fifo.size = MMC_BOOT_BAM_FIFO_SIZE; |
| 3258 | |
| 3259 | /* Write pipe parameter initializations.*/ |
| 3260 | bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].pipe_num = MMC_BOOT_BAM_WRITE_PIPE; |
| 3261 | /* System producer */ |
| 3262 | bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].trans_type = SYS2BAM; |
| 3263 | /* Write fifo uses the same fifo as read */ |
| 3264 | bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].fifo.head = desc_fifo; |
| 3265 | /* Set the descriptor FIFO lengths */ |
| 3266 | bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].fifo.size = MMC_BOOT_BAM_FIFO_SIZE; |
| 3267 | |
| 3268 | /* Programs the minimum threshold for BAM transfer*/ |
| 3269 | bam.threshold = BLOCK_SIZE; |
| 3270 | |
| 3271 | /* Initialize MMC BAM */ |
| 3272 | bam_init(&bam); |
| 3273 | |
| 3274 | /* Initialize BAM MMC read pipe */ |
| 3275 | bam_sys_pipe_init(&bam, MMC_BOOT_BAM_READ_PIPE_INDEX); |
| 3276 | |
| 3277 | mmc_ret = bam_pipe_fifo_init(&bam, bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].pipe_num); |
| 3278 | |
| 3279 | if (mmc_ret) |
| 3280 | { |
| 3281 | dprintf(CRITICAL, "MMC: BAM Read pipe fifo init error\n"); |
| 3282 | goto mmc_bam_init_error; |
| 3283 | } |
| 3284 | |
| 3285 | /* Initialize BAM MMC write pipe */ |
| 3286 | bam_sys_pipe_init(&bam, MMC_BOOT_BAM_WRITE_PIPE_INDEX); |
| 3287 | |
| 3288 | mmc_ret = bam_pipe_fifo_init(&bam, bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].pipe_num); |
| 3289 | |
| 3290 | if (mmc_ret) |
| 3291 | { |
| 3292 | dprintf(CRITICAL, "MMC: BAM Write pipe fifo init error\n"); |
| 3293 | goto mmc_bam_init_error; |
| 3294 | } |
| 3295 | |
| 3296 | mmc_boot_dml_init(); |
| 3297 | |
| 3298 | mmc_bam_init_error: |
| 3299 | |
| 3300 | return mmc_ret; |
| 3301 | } |
| 3302 | |
| 3303 | static int mmc_bam_transfer_data(unsigned int *data_ptr, |
| 3304 | unsigned int data_len, |
| 3305 | unsigned int dir) |
| 3306 | { |
| 3307 | uint32_t mmc_ret; |
| 3308 | uint32_t offset; |
| 3309 | |
| 3310 | mmc_ret = MMC_BOOT_E_SUCCESS; |
| 3311 | |
| 3312 | if(dir == MMC_BOOT_DATA_READ) |
| 3313 | { |
| 3314 | /* Check BAM IRQ status reg to verify the desc has been processed */ |
| 3315 | mmc_ret = bam_wait_for_interrupt(&bam, |
| 3316 | MMC_BOOT_BAM_READ_PIPE_INDEX, P_PRCSD_DESC_EN_MASK); |
| 3317 | |
| 3318 | if (mmc_ret != BAM_RESULT_SUCCESS) |
| 3319 | { |
| 3320 | dprintf(CRITICAL, "BAM transfer error \n"); |
| 3321 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 3322 | goto mmc_bam_transfer_err; |
| 3323 | } |
| 3324 | |
| 3325 | mmc_boot_dml_wait_producer_idle(); |
| 3326 | |
| 3327 | /* Update BAM pipe fifo offsets */ |
| 3328 | offset = bam_read_offset_update(&bam, MMC_BOOT_BAM_READ_PIPE_INDEX); |
| 3329 | |
| 3330 | /* Reset DPSM */ |
| 3331 | writel(0, MMC_BOOT_MCI_DATA_CTL); |
| 3332 | |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 3333 | /* Wait for the MMC_BOOT_MCI_DATA_CTL write to go through. */ |
| 3334 | mmc_mclk_reg_wr_delay(); |
| 3335 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 3336 | dprintf(SPEW, "Offset value is %d \n", offset); |
| 3337 | } |
| 3338 | else |
| 3339 | { |
| 3340 | /* Check BAM IRQ status reg to verify the desc has been processed */ |
| 3341 | mmc_ret = bam_wait_for_interrupt(&bam, |
| 3342 | MMC_BOOT_BAM_WRITE_PIPE_INDEX, P_TRNSFR_END_EN_MASK); |
| 3343 | |
| 3344 | if (mmc_ret != BAM_RESULT_SUCCESS) |
| 3345 | { |
| 3346 | dprintf(CRITICAL, "BAM transfer error \n"); |
| 3347 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 3348 | goto mmc_bam_transfer_err; |
| 3349 | } |
| 3350 | |
| 3351 | /* Update BAM pipe fifo offsets */ |
| 3352 | offset = bam_read_offset_update(&bam, MMC_BOOT_BAM_WRITE_PIPE_INDEX); |
| 3353 | |
| 3354 | dprintf(SPEW, "Offset value is %d \n", offset); |
| 3355 | } |
| 3356 | |
| 3357 | mmc_bam_transfer_err: |
| 3358 | |
| 3359 | return mmc_ret; |
| 3360 | } |
| 3361 | |
| 3362 | static unsigned int |
| 3363 | mmc_boot_bam_setup_desc(unsigned int *data_ptr, |
| 3364 | unsigned int data_len, |
| 3365 | unsigned char direction) |
| 3366 | { |
| 3367 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 3368 | |
| 3369 | if (direction == MMC_BOOT_DATA_READ) |
| 3370 | { |
| 3371 | mmc_boot_dml_producer_trans_init(1, data_len); |
| 3372 | mmc_ret = bam_add_desc(&bam, MMC_BOOT_BAM_READ_PIPE_INDEX, |
| 3373 | (unsigned char *)data_ptr, data_len); |
| 3374 | } |
| 3375 | else |
| 3376 | { |
| 3377 | mmc_boot_dml_consumer_trans_init(); |
| 3378 | mmc_ret = bam_add_desc(&bam, MMC_BOOT_BAM_WRITE_PIPE_INDEX, |
| 3379 | (unsigned char *)data_ptr, data_len); |
| 3380 | } |
| 3381 | |
| 3382 | /* Update return value enums */ |
| 3383 | if (mmc_ret != BAM_RESULT_SUCCESS) |
| 3384 | { |
| 3385 | dprintf(CRITICAL, "MMC BAM transfer error: %d\n", mmc_ret); |
| 3386 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 3387 | } |
| 3388 | } |
| 3389 | |
| 3390 | #endif |
Channagoud Kadabi | 676c2e3 | 2013-04-02 11:39:01 -0700 | [diff] [blame] | 3391 | |
| 3392 | /* |
| 3393 | * Check if card supports DDR mode |
| 3394 | */ |
| 3395 | uint8_t card_supports_ddr_mode() |
| 3396 | { |
| 3397 | if (IS_BIT_SET_EXT_CSD(MMC_DEVICE_TYPE, 2) || |
| 3398 | IS_BIT_SET_EXT_CSD(MMC_DEVICE_TYPE, 3)) |
| 3399 | return 1; |
| 3400 | else |
| 3401 | return 0; |
| 3402 | } |
| 3403 | |
| 3404 | /* |
| 3405 | * Check if card suppports HS200 mode |
| 3406 | */ |
| 3407 | uint8_t card_supports_hs200_mode() |
| 3408 | { |
| 3409 | if (IS_BIT_SET_EXT_CSD(MMC_DEVICE_TYPE, 4) || |
| 3410 | IS_BIT_SET_EXT_CSD(MMC_DEVICE_TYPE, 5)) |
| 3411 | return 1; |
| 3412 | else |
| 3413 | return 0; |
| 3414 | } |
Channagoud Kadabi | 7cf5d04 | 2013-04-19 12:58:15 -0700 | [diff] [blame] | 3415 | |
| 3416 | /* Return the density of the mmc device */ |
| 3417 | uint64_t mmc_get_device_capacity() |
| 3418 | { |
| 3419 | return mmc_card.capacity; |
| 3420 | } |
Channagoud Kadabi | 54dd531 | 2013-06-18 18:31:44 -0700 | [diff] [blame] | 3421 | |
Channagoud Kadabi | 57eb630 | 2013-09-10 14:21:30 -0700 | [diff] [blame] | 3422 | /* Return the block size of the mmc device */ |
| 3423 | uint32_t mmc_get_device_blocksize() |
| 3424 | { |
| 3425 | return mmc_card.block_size; |
| 3426 | } |
| 3427 | |
Channagoud Kadabi | 54dd531 | 2013-06-18 18:31:44 -0700 | [diff] [blame] | 3428 | void mmc_put_card_to_sleep(void) |
| 3429 | { |
| 3430 | uint32_t mmc_ret; |
| 3431 | struct mmc_boot_command cmd = {0}; |
| 3432 | |
| 3433 | cmd.cmd_index = CMD7_SELECT_DESELECT_CARD; |
| 3434 | cmd.argument = 0x00000000; |
| 3435 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 3436 | cmd.resp_type = MMC_BOOT_RESP_NONE; |
| 3437 | |
| 3438 | /* send command */ |
| 3439 | mmc_ret = mmc_boot_send_command(&cmd); |
| 3440 | if (mmc_ret != MMC_BOOT_E_SUCCESS) |
| 3441 | { |
| 3442 | dprintf(CRITICAL, "card deselect error: %d\n", mmc_ret); |
| 3443 | return; |
| 3444 | } |
| 3445 | |
| 3446 | cmd.cmd_index = CMD5_SLEEP_AWAKE; |
| 3447 | cmd.argument = (mmc_card.rca << MMC_CARD_RCA_BIT) | MMC_CARD_SLEEP; |
| 3448 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 3449 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 3450 | |
| 3451 | /* send command */ |
| 3452 | mmc_ret = mmc_boot_send_command(&cmd); |
| 3453 | if (mmc_ret != MMC_BOOT_E_SUCCESS) |
| 3454 | dprintf(CRITICAL, "card sleep error: %d\n", mmc_ret); |
| 3455 | } |