blob: 82a7f09803d35878f79daee2d90d1247e4a5888c [file] [log] [blame]
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of The Linux Foundation nor
11 * the names of its contributors may be used to endorse or promote
12 * products derived from this software without specific prior written
13 * permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
19 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <mdp5.h>
29#include <debug.h>
30#include <reg.h>
31#include <target/display.h>
32#include <platform/timer.h>
33#include <platform/iomap.h>
34#include <dev/lcdc.h>
35#include <dev/fbcon.h>
36#include <bits.h>
37#include <msm_panel.h>
38#include <mipi_dsi.h>
39#include <err.h>
40#include <clock.h>
Siddhartha Agrawal8d690822013-01-28 12:18:58 -080041#include <scm.h>
42
43int restore_secure_cfg(uint32_t id);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -080044
45static int mdp_rev;
46
47void mdp_set_revision(int rev)
48{
49 mdp_rev = rev;
50}
51
52int mdp_get_revision()
53{
54 return mdp_rev;
55}
56
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -080057uint32_t mdss_mdp_intf_offset()
58{
59 uint32_t mdss_mdp_intf_off;
60 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
61
Chandan Uddarajuaab58512013-06-25 17:47:39 -070062 if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102)
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -080063 mdss_mdp_intf_off = 0;
Aravind Venkateswarand78d1592013-06-19 15:39:54 -070064 else
Chandan Uddarajuaab58512013-06-25 17:47:39 -070065 mdss_mdp_intf_off = 0xEC00;
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -080066
67 return mdss_mdp_intf_off;
68}
69
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -080070void mdp_clk_gating_ctrl(void)
71{
72 writel(0x40000000, MDP_CLK_CTRL0);
73 udelay(20);
74 writel(0x40000040, MDP_CLK_CTRL0);
75 writel(0x40000000, MDP_CLK_CTRL1);
76 writel(0x00400000, MDP_CLK_CTRL3);
77 udelay(20);
78 writel(0x00404000, MDP_CLK_CTRL3);
79 writel(0x40000000, MDP_CLK_CTRL4);
80}
81
Siddhartha Agrawald3893392013-06-11 15:32:19 -070082static void mdss_rgb_pipe_config(struct fbcon_config *fb, struct msm_panel_info
83 *pinfo, uint32_t pipe_base)
84{
85 uint32_t src_size, out_size, stride;
Siddhartha Agrawal6ef1e222013-06-12 18:24:58 -070086 uint32_t fb_off = 0;
Siddhartha Agrawald3893392013-06-11 15:32:19 -070087
88 /* write active region size*/
89 src_size = (fb->height << 16) + fb->width;
90 out_size = src_size;
91
92 if (pinfo->lcdc.dual_pipe) {
93 out_size = (fb->height << 16) + (fb->width / 2);
Siddhartha Agrawal6ef1e222013-06-12 18:24:58 -070094 if ((pinfo->lcdc.pipe_swap == TRUE) && (pipe_base ==
95 MDP_VP_0_RGB_0_BASE))
96 fb_off = (pinfo->xres / 2);
97 else if ((pinfo->lcdc.pipe_swap != TRUE) && (pipe_base ==
98 MDP_VP_0_RGB_1_BASE))
99 fb_off = (pinfo->xres / 2);
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700100 }
101
102 stride = (fb->stride * fb->bpp/8);
103
104 writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR);
105 writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE);
106 writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE);
107 writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE);
108 writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE);
Siddhartha Agrawal6ef1e222013-06-12 18:24:58 -0700109 writel(fb_off, pipe_base + PIPE_SSPP_SRC_XY);
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700110 writel(0x00, pipe_base + PIPE_SSPP_OUT_XY);
111
112 /* Tight Packing 3bpp 0-Alpha 8-bit R B G */
113 writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT);
114 writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN);
115 writel(0x00, pipe_base + PIPE_SSPP_SRC_OP_MODE);
116}
117
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700118static void mdss_vbif_setup()
119{
120 int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS);
Aravind Venkateswarand78d1592013-06-19 15:39:54 -0700121 uint32_t mdp_hw_rev = readl(MDP_HW_REV);
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700122
123 /* TZ returns an errornous ret val even if the VBIF registers were
124 * successfully unlocked. Ignore TZ return value till it's fixed */
125 if (!access_secure || 1) {
126 dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n");
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700127
Ujwal Patel00e19852013-12-18 20:40:38 -0800128 /* Force VBIF Clocks on */
129 if (mdp_hw_rev < MDSS_MDP_HW_REV_103)
130 writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
131
132 /*
133 * Following configuration is needed because on some versions,
134 * recommended reset values are not stored.
135 */
136 if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
137 MDSS_MDP_HW_REV_100)) {
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700138 writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
139 writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL );
140 writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
141 writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN);
142 writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO);
143 writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0);
144 writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1);
Ujwal Patel00e19852013-12-18 20:40:38 -0800145 } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
146 MDSS_MDP_HW_REV_101)) {
Aravind Venkateswarand78d1592013-06-19 15:39:54 -0700147 writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
148 writel(0x00000003, VBIF_VBIF_DDR_ARB_CTRL);
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700149 }
150 }
151}
152
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800153static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt,
154 uint32_t fixed_smp_cnt, uint32_t free_smp_offset)
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700155{
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800156 uint32_t i, j;
157 uint32_t reg_val = 0;
Aravind Venkateswarand78d1592013-06-19 15:39:54 -0700158 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700159
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800160 for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) {
161 /* max 3 MMB per register */
162 reg_val |= client_id << (((j++) % 3) * 8);
163 if ((j % 3) == 0) {
164 writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE +
165 free_smp_offset);
166 writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE +
167 free_smp_offset);
168 reg_val = 0;
169 free_smp_offset += 4;
170 }
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700171 }
172
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800173 if (j % 3) {
174 writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset);
175 writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset);
176 free_smp_offset += 4;
177 }
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700178
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800179 return free_smp_offset;
180}
181
182void mdss_smp_setup(struct msm_panel_info *pinfo)
183{
184 uint32_t rgb0_client_id, rgb1_client_id;
185 uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH;
186 uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0;
187 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
188
189 if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) &&
190 (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) {
191 smp_size = 8192;
192 fixed_smp_cnt = 2;
193 free_smp_offset = 0xC;
194 }
195
196 rgb1_client_id = 0x11; /* 17 */
197 if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101))
198 rgb0_client_id = 0x7;
199 else
200 rgb0_client_id = 0x10; /* 16 */
201
202 /* Each pipe driving half the screen */
203 if (pinfo->lcdc.dual_pipe)
204 xres /= 2;
205
206 /* bpp = bytes per pixel of input image */
207 smp_cnt = (xres * bpp * 2) + smp_size - 1;
208 smp_cnt /= smp_size;
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700209
210 if (smp_cnt > 4) {
211 dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__,
212 smp_cnt);
213 ASSERT(0); /* Max 4 SMPs can be allocated per client */
214 }
215
Dhaval Patel142daad2013-10-18 18:58:09 -0700216 writel(smp_cnt * 0x40, MDP_VP_0_RGB_0_BASE + REQPRIORITY_FIFO_WATERMARK0);
217 writel(smp_cnt * 0x80, MDP_VP_0_RGB_0_BASE + REQPRIORITY_FIFO_WATERMARK1);
218 writel(smp_cnt * 0xc0, MDP_VP_0_RGB_0_BASE + REQPRIORITY_FIFO_WATERMARK2);
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700219
220 if (pinfo->lcdc.dual_pipe) {
Dhaval Patel142daad2013-10-18 18:58:09 -0700221 writel(smp_cnt * 0x40, MDP_VP_0_RGB_1_BASE + REQPRIORITY_FIFO_WATERMARK0);
222 writel(smp_cnt * 0x80, MDP_VP_0_RGB_1_BASE + REQPRIORITY_FIFO_WATERMARK1);
223 writel(smp_cnt * 0xc0, MDP_VP_0_RGB_1_BASE + REQPRIORITY_FIFO_WATERMARK2);
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700224 }
225
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800226 free_smp_offset = mdss_smp_alloc(rgb0_client_id, smp_cnt,
227 fixed_smp_cnt, free_smp_offset);
228 if (pinfo->lcdc.dual_pipe)
229 mdss_smp_alloc(rgb1_client_id, smp_cnt, fixed_smp_cnt,
230 free_smp_offset);
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700231}
232
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700233void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800234{
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800235 uint32_t hsync_period, vsync_period;
236 uint32_t hsync_start_x, hsync_end_x;
237 uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend;
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700238 uint32_t mdss_mdp_intf_off;
Siddhartha Agrawald359f142013-06-12 19:16:08 -0700239 uint32_t adjust_xres = 0;
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700240
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800241 struct lcdc_panel_info *lcdc = NULL;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800242
243 if (pinfo == NULL)
244 return ERR_INVALID_ARGS;
245
246 lcdc = &(pinfo->lcdc);
247 if (lcdc == NULL)
248 return ERR_INVALID_ARGS;
249
Siddhartha Agrawald359f142013-06-12 19:16:08 -0700250 adjust_xres = pinfo->xres;
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700251 if (pinfo->lcdc.split_display) {
Siddhartha Agrawald359f142013-06-12 19:16:08 -0700252 adjust_xres /= 2;
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700253 if (intf_base == MDP_INTF_1_BASE) {
254 writel(BIT(8), MDP_TG_SINK);
255 writel(0x0, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
256 writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
257 }
258 }
259
260 mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
261
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800262 hsync_period = lcdc->h_pulse_width +
263 lcdc->h_back_porch +
Siddhartha Agrawald359f142013-06-12 19:16:08 -0700264 adjust_xres + lcdc->xres_pad + lcdc->h_front_porch;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800265 vsync_period = (lcdc->v_pulse_width +
266 lcdc->v_back_porch +
267 pinfo->yres + lcdc->yres_pad +
268 lcdc->v_front_porch);
269
270 hsync_start_x =
271 lcdc->h_pulse_width +
272 lcdc->h_back_porch;
273 hsync_end_x =
274 hsync_period - lcdc->h_front_porch - 1;
275
276 display_vstart = (lcdc->v_pulse_width +
277 lcdc->v_back_porch)
278 * hsync_period + lcdc->hsync_skew;
279 display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period)
280 +lcdc->hsync_skew - 1;
281
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300282 if (intf_base == MDP_INTF_0_BASE) { /* eDP */
283 display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch;
284 display_vend -= lcdc->h_front_porch;
285 }
286
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800287 hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
288 display_hctl = (hsync_end_x << 16) | hsync_start_x;
289
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700290 writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off);
291 writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
292 mdss_mdp_intf_off);
293 writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
294 writel(lcdc->v_pulse_width*hsync_period,
295 MDP_VSYNC_PULSE_WIDTH_F0 +
296 mdss_mdp_intf_off);
297 writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
298 writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off);
299 writel(display_vstart, MDP_DISPLAY_V_START_F0 +
300 mdss_mdp_intf_off);
301 writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off);
302 writel(display_vend, MDP_DISPLAY_V_END_F0 +
303 mdss_mdp_intf_off);
304 writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off);
305 writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off);
306 writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off);
307 writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off);
308 writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off);
309 writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off);
310 writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off);
311
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300312 if (intf_base == MDP_INTF_0_BASE) /* eDP */
313 writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
314 else
315 writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700316}
317
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700318void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
319 *pinfo)
320{
321 uint32_t mdp_rgb_size, height, width;
322
Dhaval Patel0a9ab812013-10-25 10:25:06 -0700323 height = fb->height;
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700324 width = fb->width;
325
326 if (pinfo->lcdc.dual_pipe)
327 width /= 2;
328
329 /* write active region size*/
330 mdp_rgb_size = (height << 16) | width;
331
332 writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE);
333 writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE);
334 writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP);
335 writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA);
336 writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP);
337 writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA);
338 writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP);
339 writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA);
340 writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP);
341 writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA);
342
343 /* Baselayer for layer mixer 0 */
344 writel(0x0000200, MDP_CTL_0_BASE + CTL_LAYER_0);
345
346 if (pinfo->lcdc.dual_pipe) {
347 writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE);
348 writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE);
349 writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP);
350 writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA);
351 writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP);
352 writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA);
353 writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP);
354 writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA);
355 writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP);
356 writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA);
357
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700358 /* Baselayer for layer mixer 1 */
359 if (pinfo->lcdc.split_display)
Dhaval Patel0a9ab812013-10-25 10:25:06 -0700360 writel(0x1000, MDP_CTL_1_BASE + CTL_LAYER_1);
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700361 else
362 writel(0x01000, MDP_CTL_0_BASE + CTL_LAYER_1);
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700363 }
364}
365
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700366int mdp_dsi_video_config(struct msm_panel_info *pinfo,
367 struct fbcon_config *fb)
368{
369 int ret = NO_ERROR;
370 struct lcdc_panel_info *lcdc = NULL;
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700371 uint32_t intf_sel = 0x100;
372
373 mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE);
374
375 if (pinfo->mipi.dual_dsi)
376 mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE);
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -0800377
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800378 mdp_clk_gating_ctrl();
379
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700380 mdss_vbif_setup();
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700381 mdss_smp_setup(pinfo);
Siddhartha Agrawalb1b5a1f2013-04-17 19:53:41 -0700382
383 writel(0x0E9, MDP_QOS_REMAPPER_CLASS_0);
384
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700385 mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE);
386 if (pinfo->lcdc.dual_pipe)
387 mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_1_BASE);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800388
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700389 mdss_layer_mixer_setup(fb, pinfo);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800390
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700391 writel(0x1F20, MDP_CTL_0_BASE + CTL_TOP);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800392
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700393 if (pinfo->mipi.dual_dsi) {
394 writel(0x1F30, MDP_CTL_1_BASE + CTL_TOP);
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700395 intf_sel |= BIT(16); /* INTF 2 enable */
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700396 }
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700397
398 writel(intf_sel, MDP_DISP_INTF_SEL);
399
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800400 writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
401 writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
402 writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
403
404 return 0;
405}
406
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300407int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
408{
409 int ret = NO_ERROR;
410 struct lcdc_panel_info *lcdc = NULL;
411
412 mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE);
413
414 mdp_clk_gating_ctrl();
415
416 mdss_vbif_setup();
417 mdss_smp_setup(pinfo);
418
419 writel(0x0E9, MDP_QOS_REMAPPER_CLASS_0);
420
421 mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE);
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700422 if (pinfo->lcdc.dual_pipe)
423 mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_1_BASE);
424
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300425
426 mdss_layer_mixer_setup(fb, pinfo);
427
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700428
429 if (pinfo->lcdc.dual_pipe)
430 writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP);
431 else
432 writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP);
433
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300434 writel(0x9, MDP_DISP_INTF_SEL);
435 writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
436 writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
437 writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
438
439 return 0;
440}
441
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800442int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
443 struct fbcon_config *fb)
444{
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700445 int ret = NO_ERROR;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800446
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700447 struct lcdc_panel_info *lcdc = NULL;
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700448 uint32_t mdss_mdp_intf_off = 0;
449
450 if (pinfo == NULL)
451 return ERR_INVALID_ARGS;
452
453 lcdc = &(pinfo->lcdc);
454 if (lcdc == NULL)
455 return ERR_INVALID_ARGS;
456
457 mdss_mdp_intf_off = mdss_mdp_intf_offset();
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700458
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700459 mdp_clk_gating_ctrl();
460
461 writel(0x0100, MDP_DISP_INTF_SEL);
462
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700463 mdss_vbif_setup();
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700464 mdss_smp_setup(pinfo);
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700465 mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE);
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700466
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700467 mdss_layer_mixer_setup(fb, pinfo);
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700468
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700469 writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700470
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700471 writel(0x20020, MDP_CTL_0_BASE + CTL_TOP);
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700472
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800473 return ret;
474}
475
476int mdp_dsi_video_on(void)
477{
478 int ret = NO_ERROR;
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700479 writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
480 writel(0x32090, MDP_CTL_1_BASE + CTL_FLUSH);
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -0800481 writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800482 return ret;
483}
484
485int mdp_dsi_video_off()
486{
487 if(!target_cont_splash_screen())
488 {
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -0800489 writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN +
490 mdss_mdp_intf_offset());
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800491 mdelay(60);
492 /* Ping-Pong done Tear Check Read/Write */
493 /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
494 writel(0xFF777713, MDP_INTR_CLEAR);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800495 }
496
Siddhartha Agrawal6a598222013-02-17 18:33:27 -0800497 writel(0x00000000, MDP_INTR_EN);
498
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800499 return NO_ERROR;
500}
501
502int mdp_dsi_cmd_off()
503{
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -0700504 if(!target_cont_splash_screen())
505 {
506 /* Ping-Pong done Tear Check Read/Write */
507 /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
508 writel(0xFF777713, MDP_INTR_CLEAR);
509 }
510 writel(0x00000000, MDP_INTR_EN);
511
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800512 return NO_ERROR;
513}
514
515int mdp_dma_on(void)
516{
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700517 writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
518 writel(0x01, MDP_CTL_0_BASE + CTL_START);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800519 return NO_ERROR;
520}
521
522void mdp_disable(void)
523{
524
525}
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300526
527int mdp_edp_on(void)
528{
529 writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
530 writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
531 return NO_ERROR;
532}
533
534int mdp_edp_off(void)
535{
536 if (!target_cont_splash_screen()) {
537
538 writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN +
539 mdss_mdp_intf_offset());
540 mdelay(60);
541 /* Ping-Pong done Tear Check Read/Write */
542 /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
543 writel(0xFF777713, MDP_INTR_CLEAR);
544 writel(0x00000000, MDP_INTR_EN);
545 }
546
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700547 writel(0x00000000, MDP_INTR_EN);
548
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300549 return NO_ERROR;
550}