Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <mmc.h> |
| 33 | #include <clock.h> |
| 34 | #include <platform/clock.h> |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 35 | #include <platform/iomap.h> |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 36 | |
| 37 | void hsusb_clock_init(void) |
| 38 | { |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 39 | int ret; |
| 40 | struct clk *iclk, *cclk; |
| 41 | |
| 42 | ret = clk_get_set_enable("usb_iface_clk", 0, 1); |
| 43 | if(ret) |
| 44 | { |
| 45 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 46 | ASSERT(0); |
| 47 | } |
| 48 | |
| 49 | ret = clk_get_set_enable("usb_core_clk", 75000000, 1); |
| 50 | if(ret) |
| 51 | { |
| 52 | dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret); |
| 53 | ASSERT(0); |
| 54 | } |
| 55 | |
| 56 | /* Wait for the clocks to be stable since we are disabling soon after. */ |
| 57 | mdelay(1); |
| 58 | |
| 59 | iclk = clk_get("usb_iface_clk"); |
| 60 | cclk = clk_get("usb_core_clk"); |
| 61 | |
| 62 | clk_disable(iclk); |
| 63 | clk_disable(cclk); |
| 64 | |
| 65 | /* Wait for the clock disable to complete. */ |
| 66 | mdelay(1); |
| 67 | |
| 68 | /* Start the block reset for usb */ |
| 69 | writel(1, USB_HS_BCR); |
| 70 | |
| 71 | /* Wait for reset to complete. */ |
| 72 | mdelay(1); |
| 73 | |
| 74 | /* Take usb block out of reset */ |
| 75 | writel(0, USB_HS_BCR); |
| 76 | |
| 77 | /* Wait for the block to be brought out of reset. */ |
| 78 | mdelay(1); |
| 79 | |
| 80 | ret = clk_enable(iclk); |
| 81 | |
| 82 | if(ret) |
| 83 | { |
| 84 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 85 | ASSERT(0); |
| 86 | } |
| 87 | |
| 88 | ret = clk_enable(cclk); |
| 89 | |
| 90 | if(ret) |
| 91 | { |
| 92 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 93 | ASSERT(0); |
| 94 | } |
| 95 | |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | void clock_init_mmc(uint32_t interface) |
| 99 | { |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 100 | char clk_name[64]; |
| 101 | int ret; |
| 102 | |
| 103 | snprintf(clk_name, 64, "sdc%u_iface_clk", interface); |
| 104 | |
| 105 | /* enable interface clock */ |
| 106 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 107 | if(ret) |
| 108 | { |
| 109 | dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret); |
| 110 | ASSERT(0); |
| 111 | } |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | /* Configure MMC clock */ |
| 115 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 116 | { |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 117 | int ret; |
| 118 | uint32_t reg; |
| 119 | char clk_name[64]; |
| 120 | |
| 121 | snprintf(clk_name, 64, "sdc%u_core_clk", interface); |
| 122 | |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 123 | if(freq == MMC_CLK_400KHZ) |
| 124 | { |
| 125 | ret = clk_get_set_enable(clk_name, 400000, 1); |
| 126 | } |
Channagoud Kadabi | 908353c | 2013-09-23 11:38:48 -0700 | [diff] [blame] | 127 | else if(freq == MMC_CLK_25MHZ) |
| 128 | { |
| 129 | ret = clk_get_set_enable(clk_name, 25000000, 1); |
| 130 | } |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 131 | else if(freq == MMC_CLK_50MHZ) |
| 132 | { |
| 133 | ret = clk_get_set_enable(clk_name, 50000000, 1); |
| 134 | } |
| 135 | else if(freq == MMC_CLK_96MHZ) |
| 136 | { |
| 137 | ret = clk_get_set_enable(clk_name, 100000000, 1); |
| 138 | } |
Channagoud Kadabi | de9b2d3 | 2013-11-08 13:24:47 -0800 | [diff] [blame] | 139 | else if(freq == MMC_CLK_192MHZ) |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 140 | { |
Channagoud Kadabi | 908353c | 2013-09-23 11:38:48 -0700 | [diff] [blame] | 141 | ret = clk_get_set_enable(clk_name, 192000000, 1); |
| 142 | } |
Channagoud Kadabi | de9b2d3 | 2013-11-08 13:24:47 -0800 | [diff] [blame] | 143 | else if(freq == MMC_CLK_200MHZ) |
| 144 | { |
| 145 | ret = clk_get_set_enable(clk_name, 200000000, 1); |
| 146 | } |
Channagoud Kadabi | 908353c | 2013-09-23 11:38:48 -0700 | [diff] [blame] | 147 | else if(freq == MMC_CLK_400MHZ) |
| 148 | { |
| 149 | ret = clk_get_set_enable(clk_name, 384000000, 1); |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 150 | } |
| 151 | else |
| 152 | { |
| 153 | dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq); |
| 154 | ASSERT(0); |
| 155 | } |
| 156 | |
| 157 | |
| 158 | if(ret) |
| 159 | { |
| 160 | dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret); |
| 161 | ASSERT(0); |
| 162 | } |
| 163 | |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 164 | } |
| 165 | |
Channagoud Kadabi | 908353c | 2013-09-23 11:38:48 -0700 | [diff] [blame] | 166 | /* Configure clocks for SDCC Calibration circuit */ |
| 167 | void clock_config_cdc(uint32_t interface) |
| 168 | { |
| 169 | int ret = 0; |
| 170 | char clk_name[64]; |
| 171 | |
| 172 | snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_sleep_clk", interface); |
| 173 | |
| 174 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 175 | if (ret) |
| 176 | { |
| 177 | dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name); |
| 178 | ASSERT(0); |
| 179 | } |
| 180 | |
| 181 | snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_ff_clk", interface); |
| 182 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 183 | if (ret) |
| 184 | { |
| 185 | dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name); |
| 186 | ASSERT(0); |
| 187 | } |
| 188 | } |
| 189 | |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 190 | /* Configure UART clock based on the UART block id*/ |
| 191 | void clock_config_uart_dm(uint8_t id) |
| 192 | { |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 193 | int ret; |
| 194 | char iclk[64]; |
| 195 | char cclk[64]; |
| 196 | |
| 197 | snprintf(iclk, 64, "uart%u_iface_clk", id); |
| 198 | snprintf(cclk, 64, "uart%u_core_clk", id); |
| 199 | |
| 200 | ret = clk_get_set_enable(iclk, 0, 1); |
| 201 | if(ret) |
| 202 | { |
| 203 | dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret); |
| 204 | ASSERT(0); |
| 205 | } |
| 206 | |
| 207 | ret = clk_get_set_enable(cclk, 7372800, 1); |
| 208 | if(ret) |
| 209 | { |
| 210 | dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret); |
| 211 | ASSERT(0); |
| 212 | } |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | /* Function to asynchronously reset CE (Crypto Engine). |
| 216 | * Function assumes that all the CE clocks are off. |
| 217 | */ |
| 218 | static void ce_async_reset(uint8_t instance) |
| 219 | { |
Sundarajan Srinivasan | 21263d6 | 2013-11-19 11:49:38 -0800 | [diff] [blame^] | 220 | if (instance == 1) |
| 221 | { |
| 222 | /* Start the block reset for CE */ |
| 223 | writel(1, GCC_CE1_BCR); |
| 224 | |
| 225 | udelay(2); |
| 226 | |
| 227 | /* Take CE block out of reset */ |
| 228 | writel(0, GCC_CE1_BCR); |
| 229 | |
| 230 | udelay(2); |
| 231 | } |
| 232 | else if (instance == 2) |
| 233 | { |
| 234 | /* Start the block reset for CE */ |
| 235 | writel(1, GCC_CE2_BCR); |
| 236 | |
| 237 | udelay(2); |
| 238 | |
| 239 | /* Take CE block out of reset */ |
| 240 | writel(0, GCC_CE2_BCR); |
| 241 | |
| 242 | udelay(2); |
| 243 | } |
| 244 | else |
| 245 | { |
| 246 | dprintf(CRITICAL, "CE instance not supported instance = %d", instance); |
| 247 | ASSERT(0); |
| 248 | } |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | void clock_ce_enable(uint8_t instance) |
| 252 | { |
Sundarajan Srinivasan | 21263d6 | 2013-11-19 11:49:38 -0800 | [diff] [blame^] | 253 | int ret; |
| 254 | char clk_name[64]; |
| 255 | |
| 256 | snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance); |
| 257 | ret = clk_get_set_enable(clk_name, 100000000, 1); |
| 258 | if(ret) |
| 259 | { |
| 260 | dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret); |
| 261 | ASSERT(0); |
| 262 | } |
| 263 | |
| 264 | snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance); |
| 265 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 266 | if(ret) |
| 267 | { |
| 268 | dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret); |
| 269 | ASSERT(0); |
| 270 | } |
| 271 | |
| 272 | snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance); |
| 273 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 274 | if(ret) |
| 275 | { |
| 276 | dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret); |
| 277 | ASSERT(0); |
| 278 | } |
| 279 | |
| 280 | snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance); |
| 281 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 282 | if(ret) |
| 283 | { |
| 284 | dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret); |
| 285 | ASSERT(0); |
| 286 | } |
| 287 | |
| 288 | /* Wait for 48 * #pipes cycles. |
| 289 | * This is necessary as immediately after an access control reset (boot up) |
| 290 | * or a debug re-enable, the Crypto core sequentially clears its internal |
| 291 | * pipe key storage memory. If pipe key initialization writes are attempted |
| 292 | * during this time, they may be overwritten by the internal clearing logic. |
| 293 | */ |
| 294 | udelay(1); |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | void clock_ce_disable(uint8_t instance) |
| 298 | { |
Sundarajan Srinivasan | 21263d6 | 2013-11-19 11:49:38 -0800 | [diff] [blame^] | 299 | struct clk *ahb_clk; |
| 300 | struct clk *cclk; |
| 301 | struct clk *axi_clk; |
| 302 | struct clk *src_clk; |
| 303 | char clk_name[64]; |
| 304 | |
| 305 | snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance); |
| 306 | src_clk = clk_get(clk_name); |
| 307 | |
| 308 | snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance); |
| 309 | ahb_clk = clk_get(clk_name); |
| 310 | |
| 311 | snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance); |
| 312 | axi_clk = clk_get(clk_name); |
| 313 | |
| 314 | snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance); |
| 315 | cclk = clk_get(clk_name); |
| 316 | |
| 317 | clk_disable(ahb_clk); |
| 318 | clk_disable(axi_clk); |
| 319 | clk_disable(cclk); |
| 320 | clk_disable(src_clk); |
| 321 | |
| 322 | /* Some delay for the clocks to stabalize. */ |
| 323 | udelay(1); |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | void clock_config_ce(uint8_t instance) |
| 327 | { |
| 328 | /* Need to enable the clock before disabling since the clk_disable() |
| 329 | * has a check to default to nop when the clk_enable() is not called |
| 330 | * on that particular clock. |
| 331 | */ |
| 332 | clock_ce_enable(instance); |
| 333 | |
| 334 | clock_ce_disable(instance); |
| 335 | |
| 336 | ce_async_reset(instance); |
| 337 | |
| 338 | clock_ce_enable(instance); |
| 339 | |
| 340 | } |
Amol Jadi | 0a4c9b4 | 2013-10-11 14:22:11 -0700 | [diff] [blame] | 341 | |
| 342 | void clock_usb30_gdsc_enable(void) |
| 343 | { |
| 344 | uint32_t reg = readl(GCC_USB30_GDSCR); |
| 345 | |
| 346 | reg &= ~(0x1); |
| 347 | |
| 348 | writel(reg, GCC_USB30_GDSCR); |
| 349 | } |
| 350 | |
| 351 | /* enables usb30 interface and master clocks */ |
| 352 | void clock_usb30_init(void) |
| 353 | { |
| 354 | int ret; |
| 355 | |
| 356 | /* interface clock */ |
| 357 | ret = clk_get_set_enable("usb30_iface_clk", 0, 1); |
| 358 | if(ret) |
| 359 | { |
| 360 | dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret); |
| 361 | ASSERT(0); |
| 362 | } |
| 363 | |
| 364 | clock_usb30_gdsc_enable(); |
| 365 | |
| 366 | /* master clock */ |
| 367 | ret = clk_get_set_enable("usb30_master_clk", 125000000, 1); |
| 368 | if(ret) |
| 369 | { |
| 370 | dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret); |
| 371 | ASSERT(0); |
| 372 | } |
| 373 | } |
Dhaval Patel | 4a87d52 | 2013-10-18 19:02:37 -0700 | [diff] [blame] | 374 | |
| 375 | void mdp_gdsc_ctrl(uint8_t enable) |
| 376 | { |
| 377 | uint32_t reg = 0; |
| 378 | reg = readl(MDP_GDSCR); |
| 379 | if (enable) { |
| 380 | if (!(reg & GDSC_POWER_ON_BIT)) { |
| 381 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 382 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 383 | writel(reg, MDP_GDSCR); |
| 384 | while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 385 | } else { |
| 386 | dprintf(INFO, "MDP GDSC already enabled\n"); |
| 387 | } |
| 388 | } else { |
| 389 | reg |= BIT(0); |
| 390 | writel(reg, MDP_GDSCR); |
| 391 | while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)); |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | /* Configure MDP clock */ |
| 396 | void mdp_clock_enable(void) |
| 397 | { |
| 398 | int ret; |
| 399 | |
| 400 | /* Set MDP clock to 240MHz */ |
| 401 | ret = clk_get_set_enable("mdp_ahb_clk", 0, 1); |
| 402 | if(ret) |
| 403 | { |
| 404 | dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret); |
| 405 | ASSERT(0); |
| 406 | } |
| 407 | |
| 408 | ret = clk_get_set_enable("mdss_mdp_clk_src", 240000000, 1); |
| 409 | if(ret) |
| 410 | { |
| 411 | dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret); |
| 412 | ASSERT(0); |
| 413 | } |
| 414 | |
| 415 | ret = clk_get_set_enable("mdss_vsync_clk", 0, 1); |
| 416 | if(ret) |
| 417 | { |
| 418 | dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret); |
| 419 | ASSERT(0); |
| 420 | } |
| 421 | |
| 422 | ret = clk_get_set_enable("mdss_mdp_clk", 0, 1); |
| 423 | if(ret) |
| 424 | { |
| 425 | dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret); |
| 426 | ASSERT(0); |
| 427 | } |
| 428 | |
| 429 | ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1); |
| 430 | if(ret) |
| 431 | { |
| 432 | dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret); |
| 433 | ASSERT(0); |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | void mdp_clock_disable() |
| 438 | { |
| 439 | clk_disable(clk_get("mdss_vsync_clk")); |
| 440 | clk_disable(clk_get("mdss_mdp_clk")); |
| 441 | clk_disable(clk_get("mdss_mdp_lut_clk")); |
| 442 | clk_disable(clk_get("mdss_mdp_clk_src")); |
| 443 | clk_disable(clk_get("mdp_ahb_clk")); |
| 444 | |
| 445 | } |
| 446 | |
| 447 | void mmss_bus_clock_enable(void) |
| 448 | { |
| 449 | int ret; |
| 450 | /* Configure MMSSNOC AXI clock */ |
| 451 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1); |
| 452 | if(ret) |
| 453 | { |
| 454 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 455 | ASSERT(0); |
| 456 | } |
| 457 | |
| 458 | /* Configure S0 AXI clock */ |
| 459 | ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1); |
| 460 | if(ret) |
| 461 | { |
| 462 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 463 | ASSERT(0); |
| 464 | } |
| 465 | |
| 466 | /* Configure AXI clock */ |
| 467 | ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1); |
| 468 | if(ret) |
| 469 | { |
| 470 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 471 | ASSERT(0); |
| 472 | } |
| 473 | } |
| 474 | |
| 475 | void mmss_bus_clock_disable(void) |
| 476 | { |
| 477 | /* Disable MDSS AXI clock */ |
| 478 | clk_disable(clk_get("mdss_axi_clk")); |
| 479 | |
| 480 | /* Disable MMSSNOC S0AXI clock */ |
| 481 | clk_disable(clk_get("mmss_s0_axi_clk")); |
| 482 | |
| 483 | /* Disable MMSSNOC AXI clock */ |
| 484 | clk_disable(clk_get("mmss_mmssnoc_axi_clk")); |
| 485 | } |
| 486 | |
| 487 | void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi, |
| 488 | uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d) |
| 489 | { |
| 490 | int ret; |
| 491 | |
| 492 | /* Configure Byte clock -autopll- This will not change because |
| 493 | byte clock does not need any divider*/ |
| 494 | writel(0x100, DSI_BYTE0_CFG_RCGR); |
| 495 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
| 496 | writel(0x1, DSI_BYTE0_CBCR); |
| 497 | |
| 498 | /* Configure Pixel clock */ |
| 499 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR); |
| 500 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 501 | writel(0x1, DSI_PIXEL0_CBCR); |
| 502 | |
| 503 | writel(pclk0_m, DSI_PIXEL0_M); |
| 504 | writel(pclk0_n, DSI_PIXEL0_N); |
| 505 | writel(pclk0_d, DSI_PIXEL0_D); |
| 506 | |
| 507 | /* Configure ESC clock */ |
| 508 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 509 | if(ret) |
| 510 | { |
| 511 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 512 | ASSERT(0); |
| 513 | } |
| 514 | |
| 515 | if (dual_dsi) { |
| 516 | /* Configure Byte 1 clock */ |
| 517 | writel(0x100, DSI_BYTE1_CFG_RCGR); |
| 518 | writel(0x1, DSI_BYTE1_CMD_RCGR); |
| 519 | writel(0x1, DSI_BYTE1_CBCR); |
| 520 | |
| 521 | /* Configure Pixel clock */ |
| 522 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR); |
| 523 | writel(0x1, DSI_PIXEL1_CMD_RCGR); |
| 524 | writel(0x1, DSI_PIXEL1_CBCR); |
| 525 | |
Dhaval Patel | 3980fc0 | 2013-10-25 12:16:52 -0700 | [diff] [blame] | 526 | writel(pclk0_m, DSI_PIXEL1_M); |
| 527 | writel(pclk0_n, DSI_PIXEL1_N); |
| 528 | writel(pclk0_d, DSI_PIXEL1_D); |
Dhaval Patel | 4a87d52 | 2013-10-18 19:02:37 -0700 | [diff] [blame] | 529 | |
| 530 | /* Configure ESC clock */ |
| 531 | ret = clk_get_set_enable("mdss_esc1_clk", 0, 1); |
| 532 | if(ret) |
| 533 | { |
| 534 | dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret); |
| 535 | ASSERT(0); |
| 536 | } |
| 537 | } |
| 538 | } |
| 539 | |
| 540 | void mmss_dsi_clock_disable(uint32_t dual_dsi) |
| 541 | { |
| 542 | /* Disable ESC clock */ |
| 543 | clk_disable(clk_get("mdss_esc0_clk")); |
| 544 | writel(0x0, DSI_BYTE0_CBCR); |
| 545 | writel(0x0, DSI_PIXEL0_CBCR); |
| 546 | |
| 547 | if (dual_dsi) { |
| 548 | /* Disable ESC clock */ |
| 549 | clk_disable(clk_get("mdss_esc1_clk")); |
| 550 | writel(0x0, DSI_BYTE1_CBCR); |
| 551 | writel(0x0, DSI_PIXEL1_CBCR); |
| 552 | } |
| 553 | } |