Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <debug.h> |
| 30 | #include <platform/iomap.h> |
| 31 | #include <platform/irqs.h> |
| 32 | #include <platform/gpio.h> |
| 33 | #include <reg.h> |
| 34 | #include <target.h> |
| 35 | #include <platform.h> |
| 36 | #include <dload_util.h> |
| 37 | #include <uart_dm.h> |
| 38 | #include <mmc.h> |
| 39 | #include <spmi.h> |
| 40 | #include <board.h> |
| 41 | #include <smem.h> |
| 42 | #include <baseband.h> |
| 43 | #include <dev/keys.h> |
| 44 | #include <pm8x41.h> |
| 45 | #include <crypto5_wrapper.h> |
| 46 | #include <hsusb.h> |
| 47 | #include <clock.h> |
| 48 | #include <partition_parser.h> |
| 49 | #include <scm.h> |
| 50 | #include <platform/clock.h> |
| 51 | #include <platform/gpio.h> |
| 52 | #include <platform/timer.h> |
| 53 | #include <stdlib.h> |
| 54 | #include <ufs.h> |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 55 | #include <boot_device.h> |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 56 | #include <qmp_phy.h> |
Joonwoo Park | 8b30997 | 2014-06-09 16:58:38 -0700 | [diff] [blame] | 57 | #include <qusb2_phy.h> |
Sundarajan Srinivasan | 19b95c7 | 2014-07-24 16:37:04 -0700 | [diff] [blame] | 58 | #include <rpm-smd.h> |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 59 | |
Channagoud Kadabi | 27ff934 | 2014-06-16 11:19:29 -0700 | [diff] [blame] | 60 | #define CE_INSTANCE 2 |
Channagoud Kadabi | 4b93fd3 | 2014-06-04 17:28:03 -0700 | [diff] [blame] | 61 | #define CE_EE 1 |
| 62 | #define CE_FIFO_SIZE 64 |
| 63 | #define CE_READ_PIPE 3 |
| 64 | #define CE_WRITE_PIPE 2 |
| 65 | #define CE_READ_PIPE_LOCK_GRP 0 |
| 66 | #define CE_WRITE_PIPE_LOCK_GRP 0 |
| 67 | #define CE_ARRAY_SIZE 20 |
| 68 | |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 69 | #define PMIC_ARB_CHANNEL_NUM 0 |
| 70 | #define PMIC_ARB_OWNER_ID 0 |
| 71 | |
| 72 | #define FASTBOOT_MODE 0x77665500 |
| 73 | |
| 74 | #define BOOT_DEVICE_MASK(val) ((val & 0x3E) >>1) |
Aparna Mallavarapu | 965fac9 | 2014-08-04 22:45:01 +0530 | [diff] [blame] | 75 | #define PMIC_WLED_SLAVE_ID 3 |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 76 | |
| 77 | static void set_sdc_power_ctrl(void); |
| 78 | static uint32_t mmc_pwrctl_base[] = |
| 79 | { MSM_SDC1_BASE, MSM_SDC2_BASE }; |
| 80 | |
| 81 | static uint32_t mmc_sdhci_base[] = |
| 82 | { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE }; |
| 83 | |
| 84 | static uint32_t mmc_sdc_pwrctl_irq[] = |
| 85 | { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ }; |
| 86 | |
| 87 | struct mmc_device *dev; |
| 88 | struct ufs_dev ufs_device; |
| 89 | |
| 90 | extern void ulpi_write(unsigned val, unsigned reg); |
| 91 | |
| 92 | void target_early_init(void) |
| 93 | { |
| 94 | #if WITH_DEBUG_UART |
| 95 | uart_dm_init(2, 0, BLSP1_UART1_BASE); |
| 96 | #endif |
| 97 | } |
| 98 | |
| 99 | /* Return 1 if vol_up pressed */ |
| 100 | static int target_volume_up() |
| 101 | { |
| 102 | uint8_t status = 0; |
| 103 | struct pm8x41_gpio gpio; |
| 104 | |
| 105 | /* Configure the GPIO */ |
| 106 | gpio.direction = PM_GPIO_DIR_IN; |
| 107 | gpio.function = 0; |
| 108 | gpio.pull = PM_GPIO_PULL_UP_30; |
| 109 | gpio.vin_sel = 2; |
| 110 | |
| 111 | pm8x41_gpio_config(3, &gpio); |
| 112 | |
| 113 | /* Wait for the pmic gpio config to take effect */ |
| 114 | thread_sleep(1); |
| 115 | |
| 116 | /* Get status of P_GPIO_5 */ |
| 117 | pm8x41_gpio_get(3, &status); |
| 118 | |
| 119 | return !status; /* active low */ |
| 120 | } |
| 121 | |
| 122 | /* Return 1 if vol_down pressed */ |
| 123 | uint32_t target_volume_down() |
| 124 | { |
| 125 | return pm8x41_resin_status(); |
| 126 | } |
| 127 | |
| 128 | static void target_keystatus() |
| 129 | { |
| 130 | keys_init(); |
| 131 | |
| 132 | if(target_volume_down()) |
| 133 | keys_post_event(KEY_VOLUMEDOWN, 1); |
| 134 | |
| 135 | if(target_volume_up()) |
| 136 | keys_post_event(KEY_VOLUMEUP, 1); |
| 137 | } |
| 138 | |
| 139 | void target_uninit(void) |
| 140 | { |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 141 | if (platform_boot_dev_isemmc()) |
Channagoud Kadabi | d6a45ea | 2014-06-02 21:12:51 -0700 | [diff] [blame] | 142 | { |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 143 | mmc_put_card_to_sleep(dev); |
Channagoud Kadabi | d6a45ea | 2014-06-02 21:12:51 -0700 | [diff] [blame] | 144 | /* Disable HC mode before jumping to kernel */ |
| 145 | sdhci_mode_disable(&dev->host); |
| 146 | } |
Channagoud Kadabi | 4b93fd3 | 2014-06-04 17:28:03 -0700 | [diff] [blame] | 147 | |
| 148 | if (crypto_initialized()) |
| 149 | crypto_eng_cleanup(); |
Sundarajan Srinivasan | 19b95c7 | 2014-07-24 16:37:04 -0700 | [diff] [blame] | 150 | |
| 151 | rpm_smd_uninit(); |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | /* Do target specific usb initialization */ |
| 155 | void target_usb_init(void) |
| 156 | { |
| 157 | uint32_t val; |
| 158 | |
Sundarajan Srinivasan | 0ebf2fc | 2014-04-23 16:45:18 -0700 | [diff] [blame] | 159 | if(board_hardware_id() == HW_PLATFORM_DRAGON) |
| 160 | { |
| 161 | /* Select the QUSB2 PHY */ |
| 162 | writel(0x1, USB2_PHY_SEL); |
| 163 | |
Joonwoo Park | 8b30997 | 2014-06-09 16:58:38 -0700 | [diff] [blame] | 164 | qusb2_phy_reset(); |
Sundarajan Srinivasan | 0ebf2fc | 2014-04-23 16:45:18 -0700 | [diff] [blame] | 165 | } |
| 166 | |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 167 | /* Enable sess_vld */ |
| 168 | val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN; |
| 169 | writel(val, USB_GENCONFIG_2); |
| 170 | |
| 171 | /* Enable external vbus configuration in the LINK */ |
| 172 | val = readl(USB_USBCMD); |
| 173 | val |= SESS_VLD_CTRL; |
| 174 | writel(val, USB_USBCMD); |
| 175 | } |
| 176 | |
| 177 | void target_usb_stop(void) |
| 178 | { |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | static void set_sdc_power_ctrl() |
| 182 | { |
| 183 | /* Drive strength configs for sdc pins */ |
| 184 | struct tlmm_cfgs sdc1_hdrv_cfg[] = |
| 185 | { |
Channagoud Kadabi | 9571715 | 2014-06-04 17:59:29 -0700 | [diff] [blame] | 186 | { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK }, |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 187 | { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK }, |
| 188 | { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK }, |
| 189 | }; |
| 190 | |
| 191 | /* Pull configs for sdc pins */ |
| 192 | struct tlmm_cfgs sdc1_pull_cfg[] = |
| 193 | { |
| 194 | { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK }, |
| 195 | { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK }, |
| 196 | { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK }, |
| 197 | }; |
| 198 | |
Channagoud Kadabi | 9571715 | 2014-06-04 17:59:29 -0700 | [diff] [blame] | 199 | struct tlmm_cfgs sdc1_rclk_cfg[] = |
| 200 | { |
| 201 | { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK }, |
| 202 | }; |
| 203 | |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 204 | /* Set the drive strength & pull control values */ |
| 205 | tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg)); |
| 206 | tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg)); |
Channagoud Kadabi | 9571715 | 2014-06-04 17:59:29 -0700 | [diff] [blame] | 207 | tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg)); |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | void target_sdc_init() |
| 211 | { |
Channagoud Kadabi | a66a6f2 | 2014-05-28 17:19:44 -0700 | [diff] [blame] | 212 | struct mmc_config_data config = {0}; |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 213 | |
| 214 | /* Set drive strength & pull ctrl values */ |
| 215 | set_sdc_power_ctrl(); |
| 216 | |
| 217 | config.bus_width = DATA_BUS_WIDTH_8BIT; |
| 218 | config.max_clk_rate = MMC_CLK_192MHZ; |
| 219 | |
| 220 | /* Try slot 1*/ |
| 221 | config.slot = 1; |
| 222 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 223 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 224 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
Channagoud Kadabi | 6b3a998 | 2014-06-05 12:59:46 -0700 | [diff] [blame] | 225 | config.hs400_support = 1; |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 226 | |
| 227 | if (!(dev = mmc_init(&config))) |
| 228 | { |
| 229 | /* Try slot 2 */ |
| 230 | config.slot = 2; |
| 231 | config.max_clk_rate = MMC_CLK_200MHZ; |
| 232 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 233 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 234 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 235 | |
| 236 | if (!(dev = mmc_init(&config))) |
| 237 | { |
| 238 | dprintf(CRITICAL, "mmc init failed!"); |
| 239 | ASSERT(0); |
| 240 | } |
| 241 | } |
| 242 | } |
| 243 | |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 244 | void *target_mmc_device() |
| 245 | { |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 246 | if (platform_boot_dev_isemmc()) |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 247 | return (void *) dev; |
| 248 | else |
| 249 | return (void *) &ufs_device; |
| 250 | } |
| 251 | |
| 252 | void target_init(void) |
| 253 | { |
| 254 | dprintf(INFO, "target_init()\n"); |
| 255 | |
| 256 | spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID); |
| 257 | |
| 258 | target_keystatus(); |
| 259 | |
Channagoud Kadabi | 4b93fd3 | 2014-06-04 17:28:03 -0700 | [diff] [blame] | 260 | |
| 261 | if (target_use_signed_kernel()) |
| 262 | target_crypto_init_params(); |
| 263 | |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 264 | platform_read_boot_config(); |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 265 | |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 266 | if (platform_boot_dev_isemmc()) |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 267 | { |
| 268 | target_sdc_init(); |
| 269 | } |
| 270 | else |
| 271 | { |
| 272 | ufs_device.base = UFS_BASE; |
| 273 | ufs_init(&ufs_device); |
| 274 | } |
| 275 | |
| 276 | /* Storage initialization is complete, read the partition table info */ |
| 277 | if (partition_read_table()) |
| 278 | { |
| 279 | dprintf(CRITICAL, "Error reading the partition table info\n"); |
| 280 | ASSERT(0); |
| 281 | } |
Sundarajan Srinivasan | 19b95c7 | 2014-07-24 16:37:04 -0700 | [diff] [blame] | 282 | |
| 283 | rpm_smd_init(); |
Aparna Mallavarapu | 965fac9 | 2014-08-04 22:45:01 +0530 | [diff] [blame] | 284 | |
| 285 | /* QPNP WLED init for display backlight */ |
| 286 | pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID); |
| 287 | qpnp_wled_init(); |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | unsigned board_machtype(void) |
| 291 | { |
| 292 | return LINUX_MACHTYPE_UNKNOWN; |
| 293 | } |
| 294 | |
| 295 | /* Detect the target type */ |
| 296 | void target_detect(struct board_data *board) |
| 297 | { |
| 298 | /* This is filled from board.c */ |
| 299 | } |
| 300 | |
Dhaval Patel | 019057a | 2014-08-12 13:52:25 -0700 | [diff] [blame] | 301 | /* Returns 1 if target supports continuous splash screen. */ |
| 302 | int target_cont_splash_screen() |
| 303 | { |
| 304 | switch(board_hardware_id()) |
| 305 | { |
| 306 | case HW_PLATFORM_SURF: |
| 307 | case HW_PLATFORM_MTP: |
| 308 | case HW_PLATFORM_FLUID: |
| 309 | dprintf(SPEW, "Target_cont_splash=1\n"); |
| 310 | return 1; |
| 311 | default: |
| 312 | dprintf(SPEW, "Target_cont_splash=0\n"); |
| 313 | return 0; |
| 314 | } |
| 315 | } |
| 316 | |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 317 | /* Detect the modem type */ |
| 318 | void target_baseband_detect(struct board_data *board) |
| 319 | { |
| 320 | uint32_t platform; |
| 321 | |
| 322 | platform = board->platform; |
| 323 | |
| 324 | switch(platform) { |
Channagoud Kadabi | 44ea30d | 2014-04-14 13:59:42 -0700 | [diff] [blame] | 325 | case MSM8994: |
Channagoud Kadabi | 23c90ab | 2014-08-28 15:49:19 -0700 | [diff] [blame^] | 326 | case MSM8992: |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 327 | board->baseband = BASEBAND_MSM; |
| 328 | break; |
Channagoud Kadabi | 30ef445 | 2014-07-12 13:03:30 -0700 | [diff] [blame] | 329 | case APQ8094: |
Channagoud Kadabi | 23c90ab | 2014-08-28 15:49:19 -0700 | [diff] [blame^] | 330 | case APQ8092: |
Channagoud Kadabi | 30ef445 | 2014-07-12 13:03:30 -0700 | [diff] [blame] | 331 | board->baseband = BASEBAND_APQ; |
| 332 | break; |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 333 | default: |
| 334 | dprintf(CRITICAL, "Platform type: %u is not supported\n",platform); |
| 335 | ASSERT(0); |
| 336 | }; |
| 337 | } |
| 338 | unsigned target_baseband() |
| 339 | { |
| 340 | return board_baseband(); |
| 341 | } |
| 342 | |
| 343 | void target_serialno(unsigned char *buf) |
| 344 | { |
| 345 | unsigned int serialno; |
| 346 | if (target_is_emmc_boot()) { |
| 347 | serialno = mmc_get_psn(); |
| 348 | snprintf((char *)buf, 13, "%x", serialno); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | unsigned check_reboot_mode(void) |
| 353 | { |
| 354 | uint32_t restart_reason = 0; |
| 355 | uint32_t restart_reason_addr; |
| 356 | |
| 357 | restart_reason_addr = RESTART_REASON_ADDR; |
| 358 | |
| 359 | /* Read reboot reason and scrub it */ |
| 360 | restart_reason = readl(restart_reason_addr); |
| 361 | writel(0x00, restart_reason_addr); |
| 362 | |
| 363 | return restart_reason; |
| 364 | } |
| 365 | |
| 366 | void reboot_device(unsigned reboot_reason) |
| 367 | { |
| 368 | uint8_t reset_type = 0; |
| 369 | |
| 370 | /* Write the reboot reason */ |
| 371 | writel(reboot_reason, RESTART_REASON_ADDR); |
| 372 | |
| 373 | if(reboot_reason == FASTBOOT_MODE) |
| 374 | reset_type = PON_PSHOLD_WARM_RESET; |
| 375 | else |
| 376 | reset_type = PON_PSHOLD_HARD_RESET; |
| 377 | |
| 378 | pm8x41_reset_configure(reset_type); |
| 379 | |
| 380 | /* Drop PS_HOLD for MSM */ |
| 381 | writel(0x00, MPM2_MPM_PS_HOLD); |
| 382 | |
| 383 | mdelay(5000); |
| 384 | |
| 385 | dprintf(CRITICAL, "Rebooting failed\n"); |
| 386 | } |
| 387 | |
| 388 | int emmc_recovery_init(void) |
| 389 | { |
| 390 | return _emmc_recovery_init(); |
| 391 | } |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 392 | |
| 393 | target_usb_iface_t* target_usb30_init() |
| 394 | { |
| 395 | target_usb_iface_t *t_usb_iface; |
| 396 | |
| 397 | t_usb_iface = calloc(1, sizeof(target_usb_iface_t)); |
| 398 | ASSERT(t_usb_iface); |
| 399 | |
| 400 | t_usb_iface->mux_config = target_usb_phy_mux_configure; |
| 401 | t_usb_iface->phy_init = usb30_qmp_phy_init; |
| 402 | t_usb_iface->phy_reset = usb30_qmp_phy_reset; |
| 403 | t_usb_iface->clock_init = clock_usb30_init; |
| 404 | t_usb_iface->vbus_override = 1; |
| 405 | |
| 406 | return t_usb_iface; |
| 407 | } |
| 408 | |
| 409 | /* identify the usb controller to be used for the target */ |
| 410 | const char * target_usb_controller() |
| 411 | { |
Tanya Finkel | 90abab7 | 2014-07-30 09:55:23 +0300 | [diff] [blame] | 412 | if(board_hardware_id() == HW_PLATFORM_DRAGON) |
| 413 | return "ci"; |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 414 | return "dwc"; |
| 415 | } |
| 416 | |
| 417 | /* mux hs phy to route to dwc controller */ |
| 418 | static void phy_mux_configure_with_tcsr() |
| 419 | { |
| 420 | /* As per the hardware team, set the mux for snps controller */ |
| 421 | RMWREG32(TCSR_PHSS_USB2_PHY_SEL, 0x0, 0x1, 0x1); |
| 422 | } |
| 423 | |
| 424 | /* configure hs phy mux if using dwc controller */ |
| 425 | void target_usb_phy_mux_configure(void) |
| 426 | { |
| 427 | if(!strcmp(target_usb_controller(), "dwc")) |
| 428 | { |
| 429 | phy_mux_configure_with_tcsr(); |
| 430 | } |
| 431 | } |
Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 432 | |
| 433 | uint32_t target_override_pll() |
| 434 | { |
| 435 | return 1; |
| 436 | } |
Channagoud Kadabi | 4b93fd3 | 2014-06-04 17:28:03 -0700 | [diff] [blame] | 437 | |
| 438 | /* Set up params for h/w CE. */ |
| 439 | void target_crypto_init_params() |
| 440 | { |
| 441 | struct crypto_init_params ce_params; |
| 442 | |
| 443 | /* Set up base addresses and instance. */ |
| 444 | ce_params.crypto_instance = CE_INSTANCE; |
Channagoud Kadabi | 27ff934 | 2014-06-16 11:19:29 -0700 | [diff] [blame] | 445 | ce_params.crypto_base = MSM_CE2_BASE; |
| 446 | ce_params.bam_base = MSM_CE2_BAM_BASE; |
Channagoud Kadabi | 4b93fd3 | 2014-06-04 17:28:03 -0700 | [diff] [blame] | 447 | |
| 448 | /* Set up BAM config. */ |
| 449 | ce_params.bam_ee = CE_EE; |
| 450 | ce_params.pipes.read_pipe = CE_READ_PIPE; |
| 451 | ce_params.pipes.write_pipe = CE_WRITE_PIPE; |
| 452 | ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP; |
| 453 | ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP; |
| 454 | |
| 455 | /* Assign buffer sizes. */ |
| 456 | ce_params.num_ce = CE_ARRAY_SIZE; |
| 457 | ce_params.read_fifo_size = CE_FIFO_SIZE; |
| 458 | ce_params.write_fifo_size = CE_FIFO_SIZE; |
| 459 | |
| 460 | /* BAM is initialized by TZ for this platform. |
| 461 | * Do not do it again as the initialization address space |
| 462 | * is locked. |
| 463 | */ |
| 464 | ce_params.do_bam_init = 0; |
| 465 | |
| 466 | crypto_init_params(&ce_params); |
| 467 | } |
| 468 | |
| 469 | crypto_engine_type board_ce_type(void) |
| 470 | { |
| 471 | return CRYPTO_ENGINE_TYPE_HW; |
| 472 | } |
Channagoud Kadabi | 84f860f | 2014-07-01 15:46:09 -0700 | [diff] [blame] | 473 | |
| 474 | void shutdown_device() |
| 475 | { |
| 476 | dprintf(CRITICAL, "Going down for shutdown.\n"); |
| 477 | |
| 478 | /* Configure PMIC for shutdown. */ |
| 479 | pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN); |
| 480 | |
| 481 | /* Drop PS_HOLD for MSM */ |
| 482 | writel(0x00, MPM2_MPM_PS_HOLD); |
| 483 | |
| 484 | mdelay(5000); |
| 485 | |
| 486 | dprintf(CRITICAL, "Shutdown failed\n"); |
| 487 | |
| 488 | ASSERT(0); |
| 489 | } |
Sundarajan Srinivasan | cd3bb3c | 2014-07-23 12:25:44 -0700 | [diff] [blame] | 490 | |
| 491 | void target_fastboot_init(void) |
| 492 | { |
| 493 | /* We are entering fastboot mode, so read partition table */ |
| 494 | mmc_read_partition_table(1); |
| 495 | } |