Jeevan Shriram | 2d3500b | 2014-12-29 16:25:06 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
| 32 | #include <err.h> |
| 33 | #include <msm_panel.h> |
| 34 | #include <mipi_dsi.h> |
| 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <board.h> |
| 38 | #include <mdp5.h> |
Dhaval Patel | 914e8db | 2014-04-16 12:07:13 -0700 | [diff] [blame] | 39 | #include <scm.h> |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 40 | #include <endian.h> |
| 41 | #include <platform/gpio.h> |
| 42 | #include <platform/clock.h> |
| 43 | #include <platform/iomap.h> |
| 44 | #include <target/display.h> |
| 45 | #include "include/panel.h" |
| 46 | #include "include/display_resource.h" |
Veera Sundaram Sankaran | 87f8813 | 2015-01-28 11:32:44 -0800 | [diff] [blame] | 47 | #include "gcdb_display.h" |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 48 | |
| 49 | #define HFPLL_LDO_ID 12 |
| 50 | |
| 51 | #define GPIO_STATE_LOW 0 |
| 52 | #define GPIO_STATE_HIGH 2 |
| 53 | #define RESET_GPIO_SEQ_LEN 3 |
| 54 | |
Kuogee Hsieh | acc3194 | 2014-06-17 15:12:10 -0700 | [diff] [blame] | 55 | static struct backlight edp_bklt = { |
| 56 | 0, 1, 4095, 100, 1, "PMIC_8941" |
| 57 | }; |
| 58 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 59 | static uint32_t dsi_pll_lock_status(uint32_t pll_base) |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 60 | { |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 61 | uint32_t counter, status; |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 62 | |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 63 | udelay(100); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 64 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 65 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 66 | status = readl(pll_base + 0x00c0) & 0x01; |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 67 | for (counter = 0; counter < 5 && !status; counter++) { |
| 68 | udelay(100); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 69 | status = readl(pll_base + 0x00c0) & 0x01; |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | return status; |
| 73 | } |
| 74 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 75 | static uint32_t dsi_pll_enable_seq_b(uint32_t pll_base) |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 76 | { |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 77 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 78 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 79 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 80 | udelay(1); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 81 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 82 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 83 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 84 | udelay(500); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 85 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 86 | udelay(500); |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 87 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 88 | return dsi_pll_lock_status(pll_base); |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 89 | } |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 90 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 91 | static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base) |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 92 | { |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 93 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 94 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 95 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 96 | udelay(1); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 97 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 98 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 99 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 100 | udelay(250); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 101 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 102 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 103 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 104 | udelay(500); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 105 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 106 | udelay(500); |
| 107 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 108 | return dsi_pll_lock_status(pll_base); |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 109 | } |
| 110 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 111 | static void dsi_pll_enable_seq(uint32_t pll_base) |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 112 | { |
| 113 | uint32_t counter, status; |
| 114 | |
| 115 | for (counter = 0; counter < 3; counter++) { |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 116 | status = dsi_pll_enable_seq_b(pll_base); |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 117 | if (status) |
| 118 | break; |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 119 | status = dsi_pll_enable_seq_d(pll_base); |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 120 | if (status) |
| 121 | break; |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 122 | status = dsi_pll_enable_seq_d(pll_base); |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 123 | if(status) |
| 124 | break; |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 125 | } |
Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 126 | |
| 127 | if (!status) |
| 128 | dprintf(CRITICAL, "Pll lock sequence failed\n"); |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 129 | } |
| 130 | |
Kuogee Hsieh | df96174 | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 131 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 132 | { |
| 133 | struct pm8x41_gpio pwmgpio_param = { |
| 134 | .direction = PM_GPIO_DIR_OUT, |
| 135 | .function = PM_GPIO_FUNC_1, |
| 136 | .vin_sel = 2, /* VIN_2 */ |
| 137 | .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10, |
| 138 | .output_buffer = PM_GPIO_OUT_CMOS, |
| 139 | .out_strength = 0x03, |
| 140 | }; |
Kuogee Hsieh | df96174 | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 141 | |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 142 | if (enable) { |
Dhaval Patel | 499b7d2 | 2014-01-07 21:57:30 -0800 | [diff] [blame] | 143 | pm8x41_gpio_config(pwm_gpio.pin_id, &pwmgpio_param); |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 144 | |
Kuogee Hsieh | acc3194 | 2014-06-17 15:12:10 -0700 | [diff] [blame] | 145 | /* lpg channel 3 */ |
Dhaval Patel | 499b7d2 | 2014-01-07 21:57:30 -0800 | [diff] [blame] | 146 | pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */ |
| 147 | pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */ |
| 148 | pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */ |
| 149 | pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x44, 0xcc); /* LPG_VALUE_LSB */ |
| 150 | pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x45, 0x00); /* LPG_VALUE_MSB */ |
| 151 | pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */ |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 152 | } else { |
Dhaval Patel | 499b7d2 | 2014-01-07 21:57:30 -0800 | [diff] [blame] | 153 | pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0x0); /* LPG_ENABLE_CONTROL */ |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | return NO_ERROR; |
| 157 | } |
| 158 | |
| 159 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 160 | { |
Dhaval Patel | 914e8db | 2014-04-16 12:07:13 -0700 | [diff] [blame] | 161 | uint32_t ret; |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 162 | struct mdss_dsi_pll_config *pll_data; |
| 163 | uint32_t dual_dsi = pinfo->mipi.dual_dsi; |
| 164 | dprintf(SPEW, "target_panel_clock\n"); |
| 165 | |
| 166 | pll_data = pinfo->mipi.dsi_pll_config; |
| 167 | if (enable) { |
| 168 | mdp_gdsc_ctrl(enable); |
| 169 | mmss_bus_clock_enable(); |
| 170 | mdp_clock_enable(); |
Dhaval Patel | 914e8db | 2014-04-16 12:07:13 -0700 | [diff] [blame] | 171 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 172 | if (ret) { |
| 173 | dprintf(CRITICAL, |
| 174 | "%s: Failed to restore MDP security configs", |
| 175 | __func__); |
| 176 | mdp_clock_disable(); |
| 177 | mmss_bus_clock_disable(); |
| 178 | mdp_gdsc_ctrl(0); |
| 179 | return ret; |
| 180 | } |
Padmanabhan Komanduru | c0766c8 | 2015-04-27 16:39:15 -0700 | [diff] [blame] | 181 | mdss_dsi_auto_pll_config(pinfo->mipi.pll_base, |
Jeevan Shriram | 2d3500b | 2014-12-29 16:25:06 -0800 | [diff] [blame] | 182 | pinfo->mipi.ctl_base, pll_data); |
Padmanabhan Komanduru | c0766c8 | 2015-04-27 16:39:15 -0700 | [diff] [blame] | 183 | dsi_pll_enable_seq(pinfo->mipi.pll_base); |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 184 | mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi, |
| 185 | pll_data->pclk_m, |
| 186 | pll_data->pclk_n, |
| 187 | pll_data->pclk_d); |
| 188 | } else if(!target_cont_splash_screen()) { |
| 189 | /* Disable clocks if continuous splash off */ |
Dhaval Patel | f14af12 | 2013-10-29 12:48:41 -0700 | [diff] [blame] | 190 | mmss_dsi_clock_disable(dual_dsi); |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 191 | mdp_clock_disable(); |
| 192 | mmss_bus_clock_disable(); |
| 193 | mdp_gdsc_ctrl(enable); |
| 194 | } |
| 195 | |
| 196 | return NO_ERROR; |
| 197 | } |
| 198 | |
| 199 | /* Pull DISP_RST_N high to get panel out of reset */ |
| 200 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 201 | struct msm_panel_info *pinfo) |
| 202 | { |
| 203 | uint32_t i = 0; |
| 204 | |
| 205 | if (enable) { |
| 206 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 207 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 208 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 209 | |
| 210 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 211 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 212 | enable_gpio.pin_strength, enable_gpio.pin_state); |
| 213 | |
| 214 | gpio_tlmm_config(bkl_gpio.pin_id, 0, |
| 215 | bkl_gpio.pin_direction, bkl_gpio.pin_pull, |
| 216 | bkl_gpio.pin_strength, bkl_gpio.pin_state); |
| 217 | |
| 218 | gpio_set(enable_gpio.pin_id, 2); |
| 219 | gpio_set(bkl_gpio.pin_id, 2); |
| 220 | /* reset */ |
| 221 | for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 222 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 223 | gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 224 | else |
| 225 | gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 226 | mdelay(resetseq->sleep[i]); |
| 227 | } |
| 228 | } else { |
| 229 | gpio_set(reset_gpio.pin_id, 0); |
| 230 | gpio_set(enable_gpio.pin_id, 0); |
| 231 | gpio_set(bkl_gpio.pin_id, 0); |
| 232 | } |
| 233 | |
| 234 | return NO_ERROR; |
| 235 | } |
| 236 | |
Kuogee Hsieh | 93bcff6 | 2014-08-22 14:02:08 -0700 | [diff] [blame] | 237 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 238 | { |
| 239 | uint32_t ldocounter = 0; |
| 240 | uint32_t pm8x41_ldo_base = 0x13F00; |
| 241 | |
| 242 | while (ldocounter < TOTAL_LDO_DEFINED) { |
| 243 | struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base + |
| 244 | 0x100 * ldo_entry_array[ldocounter].ldo_id), |
| 245 | ldo_entry_array[ldocounter].ldo_type); |
| 246 | |
| 247 | dprintf(SPEW, "Setting %s\n", |
| 248 | ldo_entry_array[ldocounter].ldo_id); |
| 249 | |
| 250 | /* Set voltage during power on */ |
| 251 | if (enable) { |
| 252 | pm8x41_ldo_set_voltage(&ldo_entry, |
| 253 | ldo_entry_array[ldocounter].ldo_voltage); |
| 254 | pm8x41_ldo_control(&ldo_entry, enable); |
| 255 | } else if(ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) { |
| 256 | pm8x41_ldo_control(&ldo_entry, enable); |
| 257 | } |
| 258 | ldocounter++; |
| 259 | } |
| 260 | |
| 261 | return NO_ERROR; |
| 262 | } |
| 263 | |
Dhaval Patel | 7709c41 | 2015-05-12 10:09:41 -0700 | [diff] [blame] | 264 | int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db) |
| 265 | { |
| 266 | memcpy(phy_db->regulator, panel_regulator_settings, REGULATOR_SIZE); |
| 267 | memcpy(phy_db->ctrl, panel_physical_ctrl, PHYSICAL_SIZE); |
| 268 | memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE); |
| 269 | memcpy(phy_db->bistCtrl, panel_bist_ctrl, BIST_SIZE); |
| 270 | memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE); |
| 271 | return NO_ERROR; |
| 272 | } |
| 273 | |
Dhaval Patel | ab2de89 | 2013-10-25 10:40:58 -0700 | [diff] [blame] | 274 | int target_display_pre_on() |
| 275 | { |
| 276 | writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0); |
| 277 | writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1); |
| 278 | writel(0xC0000CCD, MDP_CLK_CTRL0); |
| 279 | writel(0xD0000CCC, MDP_CLK_CTRL1); |
| 280 | writel(0x00CCCCCC, MDP_CLK_CTRL2); |
| 281 | writel(0x000000CC, MDP_CLK_CTRL6); |
| 282 | writel(0x0CCCC0C0, MDP_CLK_CTRL3); |
| 283 | writel(0xCCCCC0C0, MDP_CLK_CTRL4); |
| 284 | writel(0xCCCCC0C0, MDP_CLK_CTRL5); |
| 285 | writel(0x00CCC000, MDP_CLK_CTRL7); |
| 286 | |
Dhaval Patel | ab2de89 | 2013-10-25 10:40:58 -0700 | [diff] [blame] | 287 | writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF0); |
| 288 | writel(0x08000808, VBIF_VBIF_IN_RD_LIM_CONF1); |
| 289 | writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF2); |
| 290 | writel(0x00000808, VBIF_VBIF_IN_RD_LIM_CONF3); |
| 291 | writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF0); |
| 292 | writel(0x00100000, VBIF_VBIF_IN_WR_LIM_CONF1); |
| 293 | writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF2); |
| 294 | writel(0x00000000, VBIF_VBIF_IN_WR_LIM_CONF3); |
| 295 | writel(0x00013fff, VBIF_VBIF_ABIT_SHORT); |
| 296 | writel(0x000000A4, VBIF_VBIF_ABIT_SHORT_CONF); |
| 297 | writel(0x00003FFF, VBIF_VBIF_GATE_OFF_WRREQ_EN); |
| 298 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 299 | |
| 300 | return NO_ERROR; |
| 301 | } |
| 302 | |
Ajay Singh Parmar | 60430b9 | 2014-07-23 23:39:01 -0700 | [diff] [blame] | 303 | int target_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 304 | { |
| 305 | uint32_t ret; |
| 306 | |
| 307 | dprintf(SPEW, "%s: target_panel_clock\n", __func__); |
| 308 | |
| 309 | if (enable) { |
| 310 | mdp_gdsc_ctrl(enable); |
| 311 | mmss_bus_clock_enable(); |
| 312 | mdp_clock_enable(); |
| 313 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 314 | if (ret) { |
| 315 | dprintf(CRITICAL, |
| 316 | "%s: Failed to restore MDP security configs", |
| 317 | __func__); |
| 318 | mdp_clock_disable(); |
| 319 | mmss_bus_clock_disable(); |
| 320 | mdp_gdsc_ctrl(0); |
| 321 | return ret; |
| 322 | } |
| 323 | |
| 324 | hdmi_phy_reset(); |
| 325 | hdmi_pll_config(); |
| 326 | hdmi_vco_enable(); |
| 327 | hdmi_clk_enable(); |
| 328 | } else if(!target_cont_splash_screen()) { |
| 329 | /* Disable clocks if continuous splash off */ |
| 330 | hdmi_clk_disable(); |
| 331 | hdmi_vco_disable(); |
| 332 | mdp_clock_disable(); |
| 333 | mmss_bus_clock_disable(); |
| 334 | mdp_gdsc_ctrl(enable); |
| 335 | } |
| 336 | |
| 337 | return NO_ERROR; |
| 338 | } |
| 339 | |
| 340 | static void target_hdmi_mvs_enable(bool enable) |
| 341 | { |
| 342 | struct pm8x41_mvs mvs; |
| 343 | mvs.base = PM8x41_MVS1_BASE; |
| 344 | |
| 345 | if (enable) |
| 346 | pm8x41_enable_mvs(&mvs, MVS_ENABLE); |
| 347 | else |
| 348 | pm8x41_enable_mvs(&mvs, MVS_DISABLE); |
| 349 | } |
| 350 | |
| 351 | static void target_hdmi_vreg_enable(bool enable) |
| 352 | { |
| 353 | struct pm8x41_mpp mpp; |
| 354 | mpp.base = PM8x41_MMP3_BASE; |
| 355 | |
| 356 | if (enable) { |
| 357 | mpp.mode = MPP_HIGH; |
| 358 | mpp.vin = MPP_VIN2; |
| 359 | pm8x41_config_output_mpp(&mpp); |
| 360 | pm8x41_enable_mpp(&mpp, MPP_ENABLE); |
| 361 | } else { |
| 362 | pm8x41_enable_mpp(&mpp, MPP_DISABLE); |
| 363 | } |
| 364 | } |
| 365 | |
| 366 | int target_hdmi_regulator_ctrl(bool enable) |
| 367 | { |
| 368 | target_hdmi_mvs_enable(enable); |
| 369 | target_hdmi_vreg_enable(enable); |
| 370 | |
| 371 | return 0; |
| 372 | } |
| 373 | |
Ajay Singh Parmar | 7f31e0e | 2014-09-03 22:09:46 -0700 | [diff] [blame] | 374 | int target_hdmi_gpio_ctrl(bool enable) |
| 375 | { |
| 376 | gpio_tlmm_config(hdmi_cec_gpio.pin_id, 1, /* gpio 31, CEC */ |
| 377 | hdmi_cec_gpio.pin_direction, hdmi_cec_gpio.pin_pull, |
| 378 | hdmi_cec_gpio.pin_strength, hdmi_cec_gpio.pin_state); |
| 379 | |
| 380 | gpio_tlmm_config(hdmi_ddc_clk_gpio.pin_id, 1, /* gpio 32, DDC CLK */ |
| 381 | hdmi_ddc_clk_gpio.pin_direction, hdmi_ddc_clk_gpio.pin_pull, |
| 382 | hdmi_ddc_clk_gpio.pin_strength, hdmi_ddc_clk_gpio.pin_state); |
| 383 | |
| 384 | |
| 385 | gpio_tlmm_config(hdmi_ddc_data_gpio.pin_id, 1, /* gpio 33, DDC DATA */ |
| 386 | hdmi_ddc_data_gpio.pin_direction, hdmi_ddc_data_gpio.pin_pull, |
| 387 | hdmi_ddc_data_gpio.pin_strength, hdmi_ddc_data_gpio.pin_state); |
| 388 | |
| 389 | gpio_tlmm_config(hdmi_hpd_gpio.pin_id, 1, /* gpio 34, HPD */ |
| 390 | hdmi_hpd_gpio.pin_direction, hdmi_hpd_gpio.pin_pull, |
| 391 | hdmi_hpd_gpio.pin_strength, hdmi_hpd_gpio.pin_state); |
| 392 | |
| 393 | gpio_set(hdmi_cec_gpio.pin_id, hdmi_cec_gpio.pin_direction); |
| 394 | gpio_set(hdmi_ddc_clk_gpio.pin_id, hdmi_ddc_clk_gpio.pin_direction); |
| 395 | gpio_set(hdmi_ddc_data_gpio.pin_id, hdmi_ddc_data_gpio.pin_direction); |
| 396 | gpio_set(hdmi_hpd_gpio.pin_id, hdmi_hpd_gpio.pin_direction); |
| 397 | |
| 398 | /* MUX */ |
| 399 | gpio_tlmm_config(hdmi_mux_lpm_gpio.pin_id, 0, /* gpio 27 MUX LPM */ |
| 400 | hdmi_mux_lpm_gpio.pin_direction, hdmi_mux_lpm_gpio.pin_pull, |
| 401 | hdmi_mux_lpm_gpio.pin_strength, hdmi_mux_lpm_gpio.pin_state); |
| 402 | |
| 403 | gpio_tlmm_config(hdmi_mux_en_gpio.pin_id, 0, /* gpio 83 MUX EN */ |
| 404 | hdmi_mux_en_gpio.pin_direction, hdmi_mux_en_gpio.pin_pull, |
| 405 | hdmi_mux_en_gpio.pin_strength, hdmi_mux_en_gpio.pin_state); |
| 406 | |
| 407 | gpio_tlmm_config(hdmi_mux_sel_gpio.pin_id, 0, /* gpio 85 MUX SEL */ |
| 408 | hdmi_mux_sel_gpio.pin_direction, hdmi_mux_sel_gpio.pin_pull, |
| 409 | hdmi_mux_sel_gpio.pin_strength, hdmi_mux_sel_gpio.pin_state); |
| 410 | |
| 411 | gpio_set(hdmi_mux_lpm_gpio.pin_id, hdmi_mux_lpm_gpio.pin_direction); |
| 412 | gpio_set(hdmi_mux_en_gpio.pin_id, hdmi_mux_en_gpio.pin_direction); |
| 413 | gpio_set(hdmi_mux_sel_gpio.pin_id, hdmi_mux_sel_gpio.pin_direction); |
| 414 | |
| 415 | return NO_ERROR; |
| 416 | } |
| 417 | |
Kuogee Hsieh | acc3194 | 2014-06-17 15:12:10 -0700 | [diff] [blame] | 418 | void target_edp_panel_init(struct msm_panel_info *pinfo) |
| 419 | { |
| 420 | edp_panel_init(pinfo); |
| 421 | } |
| 422 | |
| 423 | int target_edp_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 424 | { |
| 425 | uint32_t ret; |
| 426 | |
| 427 | dprintf(SPEW, "%s: target_panel_clock\n", __func__); |
| 428 | |
| 429 | if (enable) { |
| 430 | mdp_gdsc_ctrl(enable); |
| 431 | mmss_bus_clock_enable(); |
| 432 | mdp_clock_enable(); |
| 433 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 434 | if (ret) { |
| 435 | dprintf(CRITICAL, |
| 436 | "%s: Failed to restore MDP security configs", |
| 437 | __func__); |
| 438 | mdp_clock_disable(); |
| 439 | mmss_bus_clock_disable(); |
| 440 | mdp_gdsc_ctrl(0); |
| 441 | return ret; |
| 442 | } |
| 443 | |
| 444 | edp_clk_enable(); |
| 445 | } else if(!target_cont_splash_screen()) { |
| 446 | /* Disable clocks if continuous splash off */ |
| 447 | edp_clk_disable(); |
| 448 | mdp_clock_disable(); |
| 449 | mmss_bus_clock_disable(); |
| 450 | mdp_gdsc_ctrl(enable); |
| 451 | } |
| 452 | |
| 453 | return NO_ERROR; |
| 454 | } |
| 455 | |
| 456 | int target_edp_panel_enable(void) |
| 457 | { |
| 458 | gpio_tlmm_config(enable_gpio.pin_id, 0, /* gpio 137 */ |
| 459 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 460 | enable_gpio.pin_strength, enable_gpio.pin_state); |
| 461 | |
| 462 | |
| 463 | gpio_tlmm_config(edp_hpd_gpio.pin_id, 0, /* hpd 103 */ |
| 464 | edp_hpd_gpio.pin_direction, edp_hpd_gpio.pin_pull, |
| 465 | edp_hpd_gpio.pin_strength, edp_hpd_gpio.pin_state); |
| 466 | |
| 467 | |
| 468 | gpio_tlmm_config(edp_lvl_en_gpio.pin_id, 0, /* lvl_en 91 */ |
| 469 | edp_lvl_en_gpio.pin_direction, edp_lvl_en_gpio.pin_pull, |
| 470 | edp_lvl_en_gpio.pin_strength, edp_lvl_en_gpio.pin_state); |
| 471 | |
| 472 | gpio_set(enable_gpio.pin_id, 2); |
| 473 | gpio_set(edp_lvl_en_gpio.pin_id, 2); |
| 474 | |
| 475 | return NO_ERROR; |
| 476 | } |
| 477 | |
| 478 | int target_edp_panel_disable(void) |
| 479 | { |
| 480 | gpio_set(edp_lvl_en_gpio.pin_id, 0); |
| 481 | gpio_set(enable_gpio.pin_id, 0); |
| 482 | |
| 483 | return NO_ERROR; |
| 484 | } |
| 485 | |
| 486 | int target_edp_bl_ctrl(int enable) |
| 487 | { |
| 488 | return target_backlight_ctrl(&edp_bklt, enable); |
| 489 | } |
| 490 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 491 | bool target_display_panel_node(char *pbuf, uint16_t buf_size) |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 492 | { |
| 493 | int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX); |
| 494 | bool ret = true; |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 495 | struct oem_panel_data oem = mdss_dsi_get_oem_data(); |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 496 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 497 | if (!strcmp(oem.panel, HDMI_PANEL_NAME)) { |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 498 | if (buf_size < (prefix_string_len + LK_OVERRIDE_PANEL_LEN + |
Ajay Singh Parmar | 3d14bdd | 2014-07-11 14:56:32 -0700 | [diff] [blame] | 499 | strlen(HDMI_CONTROLLER_STRING))) { |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 500 | dprintf(CRITICAL, "command line argument is greater than buffer size\n"); |
| 501 | return false; |
| 502 | } |
| 503 | |
| 504 | strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size); |
| 505 | buf_size -= prefix_string_len; |
| 506 | strlcat(pbuf, LK_OVERRIDE_PANEL, buf_size); |
| 507 | buf_size -= LK_OVERRIDE_PANEL_LEN; |
| 508 | strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size); |
| 509 | } else { |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 510 | ret = gcdb_display_cmdline_arg(pbuf, buf_size); |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 511 | } |
| 512 | |
| 513 | return ret; |
| 514 | } |
| 515 | |
Aravind Venkateswaran | 6385f7e | 2014-02-25 16:45:11 -0800 | [diff] [blame] | 516 | void target_display_init(const char *panel_name) |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 517 | { |
| 518 | uint32_t ret = 0; |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 519 | struct oem_panel_data oem; |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 520 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 521 | set_panel_cmd_string(panel_name); |
| 522 | oem = mdss_dsi_get_oem_data(); |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 523 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 524 | if (!strcmp(oem.panel, NO_PANEL_CONFIG) |
| 525 | || !strcmp(oem.panel, SIM_VIDEO_PANEL) |
| 526 | || !strcmp(oem.panel, SIM_DUALDSI_VIDEO_PANEL) |
| 527 | || !strcmp(oem.panel, SIM_CMD_PANEL) |
| 528 | || !strcmp(oem.panel, SIM_DUALDSI_CMD_PANEL) |
| 529 | || oem.skip) { |
Veera Sundaram Sankaran | c95d675 | 2014-07-31 11:49:52 -0700 | [diff] [blame] | 530 | dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n", |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 531 | oem.panel); |
Jeevan Shriram | b0d523a | 2014-05-30 12:55:17 -0700 | [diff] [blame] | 532 | return; |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 533 | } else if (!strcmp(oem.panel, HDMI_PANEL_NAME)) { |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 534 | dprintf(INFO, "%s: HDMI is primary\n", __func__); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 535 | mdss_hdmi_display_init(MDP_REV_50, HDMI_FB_ADDR); |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 536 | return; |
| 537 | } |
| 538 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 539 | ret = gcdb_display_init(oem.panel, MDP_REV_50, MIPI_FB_ADDR); |
Justin Philip | be9de5c | 2014-09-17 12:26:49 +0530 | [diff] [blame] | 540 | if (ret) { |
| 541 | target_force_cont_splash_disable(true); |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 542 | msm_display_off(); |
Justin Philip | be9de5c | 2014-09-17 12:26:49 +0530 | [diff] [blame] | 543 | } |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 544 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 545 | if (!oem.cont_splash) { |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 546 | dprintf(INFO, "Forcing continuous splash disable\n"); |
| 547 | target_force_cont_splash_disable(true); |
| 548 | } |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 549 | } |
| 550 | |
Aravind Venkateswaran | dd50c1a | 2014-02-25 14:42:43 -0800 | [diff] [blame] | 551 | void target_display_shutdown(void) |
Dhaval Patel | f998627 | 2013-10-18 19:06:05 -0700 | [diff] [blame] | 552 | { |
| 553 | gcdb_display_shutdown(); |
| 554 | } |