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gerrit-public.fairphone.software / kernel / lk / 44979803f30b1927bcad971a404b15340abeaaad / . / platform / msm8996 / include / platform / iomap.h
blob: 50d254273b0dbc31de3654e6872680f1bff8dbfb [file] [log] [blame]
Sridhar Parasurambe12c3d2015-01-16 13:42:26 -0800[diff] [blame]1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_THULIUM_IOMAP_H_
30#define _PLATFORM_THULIUM_IOMAP_H_
31
32#define MSM_SHARED_BASE 0x86000000
33
34#define MSM_IOMAP_HMSS_START 0x09800000
35
36#define MSM_IOMAP_BASE 0x00000000
37#define MSM_IOMAP_END 0x10000000
38
39#define MSM_SHARED_IMEM_BASE 0x066BF000
40#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]41#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + 0x6B0)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]42
43#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
44#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
45
46#define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000)
47#define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE
48
Sridhar Parasurambe12c3d2015-01-16 13:42:26 -0800[diff] [blame]49#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS 0x00068000
50#define RPM_SS_MSG_RAM_START_ADDRESS_BASE RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS
51#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE 0x00006000
52
Sridhar Parasuram103702f2015-01-26 18:07:55 -0800[diff] [blame]53#define APCS_HLOS_IPC_INTERRUPT_0 0x9820010
54
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]55#define PERIPH_SS_BASE 0x07400000
56
57#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000)
58#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
59#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
60#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
61
62#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0016F000)
63#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x00170000)
64#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x00171000)
65#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00172000)
66#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00173000)
67#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00174000)
68
69#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x001B0000)
70
71/* USB3.0 */
72#define MSM_USB30_BASE 0x6A00000
73#define MSM_USB30_QSCRATCH_BASE 0x6AF8800
74/* SS QMP (Qulacomm Multi Protocol) */
75#define QMP_PHY_BASE 0x7410000
76
77/* QUSB2 PHY */
78#define QUSB2_PHY_BASE 0x7411000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]79#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00012038)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]80
Channagoud Kadabi4517eb12015-09-02 18:43:13 -0700[diff] [blame]81#define AHB2_PHY_BASE 0x7416000
82#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
Channagoud Kadabidf6d7ad2015-09-24 15:17:03 -0700[diff] [blame]83#define GCC_RX2_USB2_CLKREF_EN 0x00388014
Channagoud Kadabi4517eb12015-09-02 18:43:13 -0700[diff] [blame]84
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]85/* Clocks */
86#define CLK_CTL_BASE 0x300000
87
c_wufeng78f7a5f2015-09-21 13:02:06 +0800[diff] [blame]88#define PMI_SLAVE_BASE 2
89#define PMI_FIRST_SLAVE_OFFSET 0
90#define PMI_SECOND_SLAVE_OFFSET 1
91
92#define PMI_FIRST_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_FIRST_SLAVE_OFFSET ) << 16)
93#define PMI_SECOND_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_SECOND_SLAVE_OFFSET) << 16)
94
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]95/* GPLL */
96#define GPLL0_MODE (CLK_CTL_BASE + 0x0000)
97#define GPLL4_MODE (CLK_CTL_BASE + 0x77000)
98#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x52000)
99#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
100
101/* UART Clocks */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]102#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x25004)
103#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29004)
Channagoud Kadabi35503c42014-11-14 16:22:43 -0800[diff] [blame]104#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C)
105#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010)
106#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014)
107#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0x29018)
108#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0x2901C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]109
110/* USB3 clocks */
111#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]112#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]113#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]114#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
115#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]116#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014)
117#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018)
118#define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C)
119#define USB30_MASTER_N (CLK_CTL_BASE + 0xF020)
120#define USB30_MASTER_D (CLK_CTL_BASE + 0xF024)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]121#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF028)
122#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF02C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]123#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C)
124
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]125#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C)
126#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010)
127#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000)
128#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004)
129#define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020)
130#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]131#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]132#define GCC_AGGRE2_USB3_AXI_CBCR (CLK_CTL_BASE + 0x83018)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]133
134/* SDCC */
135#define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */
136#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x13004) /* branch control */
137#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x13008)
138#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x13010) /* cmd */
139#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x13014) /* cfg */
140#define SDCC1_M (CLK_CTL_BASE + 0x13018) /* m */
141#define SDCC1_N (CLK_CTL_BASE + 0x1301C) /* n */
142#define SDCC1_D (CLK_CTL_BASE + 0x13020) /* d */
143
144/* SDCC2 */
145#define SDCC2_BCR (CLK_CTL_BASE + 0x14000) /* block reset */
146#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x14004) /* branch control */
147#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x14008)
148#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x14010) /* cmd */
149#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x14014) /* cfg */
150#define SDCC2_M (CLK_CTL_BASE + 0x14018) /* m */
151#define SDCC2_N (CLK_CTL_BASE + 0x1401C) /* n */
152#define SDCC2_D (CLK_CTL_BASE + 0x14020) /* d */
153
154#define UFS_BASE 0x624000
155
156#define SPMI_BASE 0x4000000
157#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
158#define SPMI_PIC_BASE (SPMI_BASE + 0x1800000)
Channagoud Kadabi7b20dea2014-11-11 13:27:33 -0800[diff] [blame]159#define PMIC_ARB_CORE 0x400F000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]160
Channagoud Kadabi037c8b82015-02-05 12:09:32 -0800[diff] [blame]161#define MSM_CE_BAM_BASE 0x644000
162#define MSM_CE_BASE 0x67A000
163#define GCC_CE1_BCR (CLK_CTL_BASE + 0x00041000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]164
165#define TLMM_BASE_ADDR 0x1010000
166#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
167#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x4 + (x)*0x1000)
168
169#define MPM2_MPM_CTRL_BASE 0x4A1000
170#define MPM2_MPM_PS_HOLD 0x4AB000
171#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
172
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]173/* QSEECOM: Secure app region notification */
174#define APP_REGION_ADDR 0x86600000
Zhen Kong327fac52015-06-12 17:04:24 -0700[diff] [blame]175#define APP_REGION_SIZE 0x2200000
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]176
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]177/* DRV strength for sdcc */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]178#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0012C000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]179
180/* SDHCI - power control registers */
181#define SDCC_MCI_HC_MODE (0x00000078)
182#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
183#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
184#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
185#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
186
187/* Boot config */
188#define SEC_CTRL_CORE_BASE 0x70000
189#define BOOT_CONFIG_OFFSET 0x00006044
190#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
191
Channagoud Kadabi652a6f62014-11-17 17:23:23 -0800[diff] [blame]192/* QMP rev registers */
193#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x788)
194#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x78C)
195#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x790)
196#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x794)
197
198/* Dummy macro needed for compilation only */
199#define PLATFORM_QMP_OFFSET 0x0
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]200
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]201/* RPMB send receive buffer needs to be mapped
202 * as device memory, define the start address
203 * and size in MB
204 */
Channagoud Kadabi40039922015-09-29 15:23:03 -0700[diff] [blame]205#define RPMB_SND_RCV_BUF 0x91A00000
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700[diff] [blame]206#define RPMB_SND_RCV_BUF_SZ 0x2
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]207
Channagoud Kadabi23edc0c2015-03-27 18:31:32 -0700[diff] [blame]208#define TCSR_BOOT_MISC_DETECT 0x007B3000
Dhaval Patel0f3cbeb2015-03-17 11:52:12 -0700[diff] [blame]209
210#define MSM_MMSS_CLK_CTL_BASE 0x8C0000
211#define MMSS_MISC_AHB_CBCR (MSM_MMSS_CLK_CTL_BASE + 0x5018)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]212
213#define MIPI_DSI_BASE (0x994000)
214#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
215#define MIPI_DSI1_BASE (0x996000)
216#define DSI0_PHY_BASE (0x994400)
217#define DSI1_PHY_BASE (0x996400)
218#define DSI0_PLL_BASE (0x994800)
219#define DSI1_PLL_BASE (0x996800)
220#define DSI0_REGULATOR_BASE (0x994000)
221#define DSI1_REGULATOR_BASE (0x996000)
222
Jeevan Shriram3c20e632015-08-03 15:21:04 -0700[diff] [blame]223#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0D0
224#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0D4
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]225
226#define MDP_BASE (0x900000)
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]227#define REG_MDP(off) (MDP_BASE + (off))
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]228
229#ifdef MDP_PP_0_BASE
230#undef MDP_PP_0_BASE
231#endif
232#define MDP_PP_0_BASE REG_MDP(0x71000)
233
234#ifdef MDP_PP_1_BASE
235#undef MDP_PP_1_BASE
236#endif
237#define MDP_PP_1_BASE REG_MDP(0x71800)
238
Ujwal Patel41a665a2015-07-17 13:51:30 -0700[diff] [blame]239#ifdef MDP_DSC_0_BASE
240#undef MDP_DSC_0_BASE
241#endif
242#define MDP_DSC_0_BASE REG_MDP(0x81000)
243
244#ifdef MDP_DSC_1_BASE
245#undef MDP_DSC_1_BASE
246#endif
247#define MDP_DSC_1_BASE REG_MDP(0x81400)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]248
249#ifdef MDP_HW_REV
250#undef MDP_HW_REV
251#endif
252#define MDP_HW_REV REG_MDP(0x1000)
253
254#ifdef MDP_INTR_EN
255#undef MDP_INTR_EN
256#endif
257#define MDP_INTR_EN REG_MDP(0x1010)
258
259#ifdef MDP_INTR_CLEAR
260#undef MDP_INTR_CLEAR
261#endif
262#define MDP_INTR_CLEAR REG_MDP(0x1018)
263
264#ifdef MDP_HIST_INTR_EN
265#undef MDP_HIST_INTR_EN
266#endif
267#define MDP_HIST_INTR_EN REG_MDP(0x101C)
268
269#ifdef MDP_DISP_INTF_SEL
270#undef MDP_DISP_INTF_SEL
271#endif
272#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
273
274#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
275#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
276#endif
277#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
278
279#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
280#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
281#endif
282#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
283
284#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
285#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
286#endif
287#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
288
289#ifdef MDP_INTF_0_TIMING_ENGINE_EN
290#undef MDP_INTF_0_TIMING_ENGINE_EN
291#endif
292#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
293
294#ifdef MDP_INTF_1_TIMING_ENGINE_EN
295#undef MDP_INTF_1_TIMING_ENGINE_EN
296#endif
297#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
298
299#ifdef MDP_INTF_2_TIMING_ENGINE_EN
300#undef MDP_INTF_2_TIMING_ENGINE_EN
301#endif
302#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x6C000)
303
304#ifdef MDP_CTL_0_BASE
305#undef MDP_CTL_0_BASE
306#endif
307#define MDP_CTL_0_BASE REG_MDP(0x2000)
308
309#ifdef MDP_CTL_1_BASE
310#undef MDP_CTL_1_BASE
311#endif
312#define MDP_CTL_1_BASE REG_MDP(0x2200)
313
314#ifdef MDP_REG_SPLIT_DISPLAY_EN
315#undef MDP_REG_SPLIT_DISPLAY_EN
316#endif
317#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
318
319#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
320#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
321#endif
322#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
323
324#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
325#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
326#endif
327#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
328
329#ifdef MDP_INTF_0_BASE
330#undef MDP_INTF_0_BASE
331#endif
332#define MDP_INTF_0_BASE REG_MDP(0x6b000)
333
334#ifdef MDP_INTF_1_BASE
335#undef MDP_INTF_1_BASE
336#endif
337#define MDP_INTF_1_BASE REG_MDP(0x6b800)
338
339#ifdef MDP_INTF_2_BASE
340#undef MDP_INTF_2_BASE
341#endif
342#define MDP_INTF_2_BASE REG_MDP(0x6c000)
343
344#ifdef MDP_CLK_CTRL0
345#undef MDP_CLK_CTRL0
346#endif
347#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
348
349#ifdef MDP_CLK_CTRL1
350#undef MDP_CLK_CTRL1
351#endif
352#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
353
354#ifdef MDP_CLK_CTRL2
355#undef MDP_CLK_CTRL2
356#endif
357#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
358
359#ifdef MDP_CLK_CTRL3
360#undef MDP_CLK_CTRL3
361#endif
362#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
363
364#ifdef MDP_CLK_CTRL4
365#undef MDP_CLK_CTRL4
366#endif
367#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
368
369#ifdef MDP_CLK_CTRL5
370#undef MDP_CLK_CTRL5
371#endif
372#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
373
374#ifdef MDP_CLK_CTRL6
375#undef MDP_CLK_CTRL6
376#endif
377#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
378
379#ifdef MDP_CLK_CTRL7
380#undef MDP_CLK_CTRL7
381#endif
382#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
383
384#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
385#undef MMSS_MDP_SMP_ALLOC_W_BASE
386#endif
387#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
388
389#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
390#undef MMSS_MDP_SMP_ALLOC_R_BASE
391#endif
392#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
393
394#ifdef MDP_QOS_REMAPPER_CLASS_0
395#undef MDP_QOS_REMAPPER_CLASS_0
396#endif
397#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
398
399#ifdef MDP_QOS_REMAPPER_CLASS_1
400#undef MDP_QOS_REMAPPER_CLASS_1
401#endif
402#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
403
404#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
405#undef VBIF_VBIF_DDR_FORCE_CLK_ON
406#endif
407#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xb0004)
408
409#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
410#undef VBIF_VBIF_DDR_OUT_MAX_BURST
411#endif
412#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xb00D8)
413
414#ifdef VBIF_VBIF_DDR_ARB_CTRL
415#undef VBIF_VBIF_DDR_ARB_CTRL
416#endif
417#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xb00F0)
418
419#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
420#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
421#endif
422#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xb0124)
423
424#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
425#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
426#endif
427#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xb0160)
428
429#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
430#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
431#endif
432#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xb0164)
433
434#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
435#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
436#endif
437#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xb0178)
438
439#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
440#undef VBIF_VBIF_DDR_OUT_AX_AOOO
441#endif
442#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xb017C)
443
444#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
445#undef VBIF_VBIF_IN_RD_LIM_CONF0
446#endif
447#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xb00B0)
448
449#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
450#undef VBIF_VBIF_IN_RD_LIM_CONF1
451#endif
452#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xb00B4)
453
454#ifdef VBIF_VBIF_IN_RD_LIM_CONF2
455#undef VBIF_VBIF_IN_RD_LIM_CONF2
456#endif
457#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xb00B8)
458
459#ifdef VBIF_VBIF_IN_RD_LIM_CONF3
460#undef VBIF_VBIF_IN_RD_LIM_CONF3
461#endif
462#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xb00BC)
463
464#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
465#undef VBIF_VBIF_IN_WR_LIM_CONF0
466#endif
467#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xb00C0)
468
469#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
470#undef VBIF_VBIF_IN_WR_LIM_CONF1
471#endif
472#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xb00C4)
473
474#ifdef VBIF_VBIF_IN_WR_LIM_CONF2
475#undef VBIF_VBIF_IN_WR_LIM_CONF2
476#endif
477#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xb00C8)
478
479#ifdef VBIF_VBIF_IN_WR_LIM_CONF3
480#undef VBIF_VBIF_IN_WR_LIM_CONF3
481#endif
482#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xb00CC)
483
484#ifdef VBIF_VBIF_ABIT_SHORT
485#undef VBIF_VBIF_ABIT_SHORT
486#endif
487#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xb0070)
488
489#ifdef VBIF_VBIF_ABIT_SHORT_CONF
490#undef VBIF_VBIF_ABIT_SHORT_CONF
491#endif
492#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xb0074)
493
494#ifdef VBIF_VBIF_GATE_OFF_WRREQ_EN
495#undef VBIF_VBIF_GATE_OFF_WRREQ_EN
496#endif
497#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xb00A8)
498
499#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
500#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
501#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
502#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
503#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
504#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
505#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
506#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
507
508#define DMA_CMD_OFFSET 0x048
509#define DMA_CMD_LENGTH 0x04C
510
511#define INT_CTRL 0x110
512#define CMD_MODE_DMA_SW_TRIGGER 0x090
513
514#define EOT_PACKET_CTRL 0x0CC
515#define MISR_CMD_CTRL 0x0A0
516#define MISR_VIDEO_CTRL 0x0A4
517#define VIDEO_MODE_CTRL 0x010
518#define HS_TIMER_CTRL 0x0BC
519
520#define SOFT_RESET 0x118
521#define CLK_CTRL 0x11C
522#define TRIG_CTRL 0x084
523#define CTRL 0x004
524#define COMMAND_MODE_DMA_CTRL 0x03C
525#define COMMAND_MODE_MDP_CTRL 0x040
526#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
527#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
528#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
529#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
530#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
531#define ERR_INT_MASK0 0x10C
532
533#define LANE_CTL 0x0AC
534#define LANE_SWAP_CTL 0x0B0
535#define TIMING_CTL 0x0C4
536
537#define VIDEO_MODE_ACTIVE_H 0x024
538#define VIDEO_MODE_ACTIVE_V 0x028
539#define VIDEO_MODE_TOTAL 0x02C
540#define VIDEO_MODE_HSYNC 0x030
541#define VIDEO_MODE_VSYNC 0x034
542#define VIDEO_MODE_VSYNC_VPOS 0x038
543
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]544#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
545#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
546#define CMD_COMPRESSION_MODE_CTRL 0x2A8
547#define CMD_COMPRESSION_MODE_CTRL_2 0x2Ac
548#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
549
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]550#define QPNP_LED_CTRL_BASE 0xD000
551#define QPNP_BLUE_LPG_CTRL_BASE 0xB100
552#define QPNP_GREEN_LPG_CTRL_BASE 0xB200
553#define QPNP_RED_LPG_CTRL_BASE 0xB300
554
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700[diff] [blame]555#define APSS_WDOG_BASE 0x9830000
556#define APPS_WDOG_BARK_VAL_REG (APSS_WDOG_BASE + 0x10)
557#define APPS_WDOG_BITE_VAL_REG (APSS_WDOG_BASE + 0x14)
558#define APPS_WDOG_RESET_REG (APSS_WDOG_BASE + 0x04)
559#define APPS_WDOG_CTL_REG (APSS_WDOG_BASE + 0x08)
560
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]561#endif