blob: 37e632352bb7d9e825ce8fe50b1f9e64e9c68c72 [file] [log] [blame]
Deepa Dinamani554b0622013-05-16 15:00:30 -07001/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <assert.h>
30#include <reg.h>
31#include <err.h>
32#include <clock.h>
33#include <clock_pll.h>
34#include <clock_lib2.h>
35#include <platform/clock.h>
36#include <platform/iomap.h>
37
38
39/* Mux source select values */
40#define cxo_source_val 0
41#define gpll0_source_val 1
42#define cxo_mm_source_val 0
43#define mmpll0_mm_source_val 1
44#define mmpll1_mm_source_val 2
45#define mmpll3_mm_source_val 3
46#define gpll0_mm_source_val 5
47
48struct clk_freq_tbl rcg_dummy_freq = F_END;
49
50
51/* Clock Operations */
52static struct clk_ops clk_ops_branch =
53{
54 .enable = clock_lib2_branch_clk_enable,
55 .disable = clock_lib2_branch_clk_disable,
56 .set_rate = clock_lib2_branch_set_rate,
57};
58
59static struct clk_ops clk_ops_rcg_mnd =
60{
61 .enable = clock_lib2_rcg_enable,
62 .set_rate = clock_lib2_rcg_set_rate,
63};
64
65static struct clk_ops clk_ops_rcg =
66{
67 .enable = clock_lib2_rcg_enable,
68 .set_rate = clock_lib2_rcg_set_rate,
69};
70
71static struct clk_ops clk_ops_cxo =
72{
73 .enable = cxo_clk_enable,
74 .disable = cxo_clk_disable,
75};
76
77static struct clk_ops clk_ops_pll_vote =
78{
79 .enable = pll_vote_clk_enable,
80 .disable = pll_vote_clk_disable,
81 .auto_off = pll_vote_clk_disable,
82 .is_enabled = pll_vote_clk_is_enabled,
83};
84
85static struct clk_ops clk_ops_vote =
86{
87 .enable = clock_lib2_vote_clk_enable,
88 .disable = clock_lib2_vote_clk_disable,
89};
90
91/* Clock Sources */
92static struct fixed_clk cxo_clk_src =
93{
94 .c = {
95 .rate = 19200000,
96 .dbg_name = "cxo_clk_src",
97 .ops = &clk_ops_cxo,
98 },
99};
100
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -0700101static struct pll_vote_clk gpll0_clk_src =
102{
103 .en_reg = (void *) APCS_GPLL_ENA_VOTE,
104 .en_mask = BIT(0),
105 .status_reg = (void *) GPLL0_STATUS,
106 .status_mask = BIT(17),
107 .parent = &cxo_clk_src.c,
108
109 .c = {
110 .rate = 600000000,
111 .dbg_name = "gpll0_clk_src",
112 .ops = &clk_ops_pll_vote,
113 },
114};
115
116/* UART Clocks */
117static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
118{
119 F( 3686400, gpll0, 1, 96, 15625),
120 F( 7372800, gpll0, 1, 192, 15625),
121 F(14745600, gpll0, 1, 384, 15625),
122 F(16000000, gpll0, 5, 2, 15),
123 F(19200000, cxo, 1, 0, 0),
124 F(24000000, gpll0, 5, 1, 5),
125 F(32000000, gpll0, 1, 4, 75),
126 F(40000000, gpll0, 15, 0, 0),
127 F(46400000, gpll0, 1, 29, 375),
128 F(48000000, gpll0, 12.5, 0, 0),
129 F(51200000, gpll0, 1, 32, 375),
130 F(56000000, gpll0, 1, 7, 75),
131 F(58982400, gpll0, 1, 1536, 15625),
132 F(60000000, gpll0, 10, 0, 0),
133 F_END
134};
135
Sundarajan Srinivasand8b7c6f2013-09-13 16:50:22 -0700136static struct rcg_clk blsp2_uart2_apps_clk_src =
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -0700137{
Sundarajan Srinivasand8b7c6f2013-09-13 16:50:22 -0700138 .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
139 .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
140 .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
141 .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
142 .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -0700143
144 .set_rate = clock_lib2_rcg_set_rate_mnd,
145 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
146 .current_freq = &rcg_dummy_freq,
147
148 .c = {
149 .dbg_name = "blsp1_uart2_apps_clk",
150 .ops = &clk_ops_rcg_mnd,
151 },
152};
153
Sundarajan Srinivasand8b7c6f2013-09-13 16:50:22 -0700154static struct branch_clk gcc_blsp2_uart2_apps_clk =
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -0700155{
Sundarajan Srinivasand8b7c6f2013-09-13 16:50:22 -0700156 .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
157 .parent = &blsp2_uart2_apps_clk_src.c,
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -0700158
159 .c = {
Sundarajan Srinivasand8b7c6f2013-09-13 16:50:22 -0700160 .dbg_name = "gcc_blsp2_uart2_apps_clk",
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -0700161 .ops = &clk_ops_branch,
162 },
163};
164
165static struct vote_clk gcc_blsp1_ahb_clk = {
166 .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
167 .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
168 .en_mask = BIT(17),
169
170 .c = {
171 .dbg_name = "gcc_blsp1_ahb_clk",
172 .ops = &clk_ops_vote,
173 },
174};
175
176static struct vote_clk gcc_blsp2_ahb_clk = {
177 .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
178 .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
179 .en_mask = BIT(15),
180
181 .c = {
182 .dbg_name = "gcc_blsp2_ahb_clk",
183 .ops = &clk_ops_vote,
184 },
185};
186
187/* USB Clocks */
188static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
189{
190 F(75000000, gpll0, 8, 0, 0),
191 F_END
192};
193
194static struct rcg_clk usb_hs_system_clk_src =
195{
196 .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
197 .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
198
199 .set_rate = clock_lib2_rcg_set_rate_hid,
200 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
201 .current_freq = &rcg_dummy_freq,
202
203 .c = {
204 .dbg_name = "usb_hs_system_clk",
205 .ops = &clk_ops_rcg,
206 },
207};
208
209static struct branch_clk gcc_usb_hs_system_clk =
210{
211 .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
212 .parent = &usb_hs_system_clk_src.c,
213
214 .c = {
215 .dbg_name = "gcc_usb_hs_system_clk",
216 .ops = &clk_ops_branch,
217 },
218};
219
220static struct branch_clk gcc_usb_hs_ahb_clk =
221{
222 .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
223 .has_sibling = 1,
224
225 .c = {
226 .dbg_name = "gcc_usb_hs_ahb_clk",
227 .ops = &clk_ops_branch,
228 },
229};
230
231/* SDCC Clocks */
232static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
233{
234 F( 144000, cxo, 16, 3, 25),
235 F( 400000, cxo, 12, 1, 4),
236 F( 20000000, gpll0, 15, 1, 2),
237 F( 25000000, gpll0, 12, 1, 2),
238 F( 50000000, gpll0, 12, 0, 0),
239 F(100000000, gpll0, 6, 0, 0),
240 F(200000000, gpll0, 3, 0, 0),
241 F_END
242};
243
244static struct rcg_clk sdcc1_apps_clk_src =
245{
246 .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
247 .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
248 .m_reg = (uint32_t *) SDCC1_M,
249 .n_reg = (uint32_t *) SDCC1_N,
250 .d_reg = (uint32_t *) SDCC1_D,
251
252 .set_rate = clock_lib2_rcg_set_rate_mnd,
253 .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
254 .current_freq = &rcg_dummy_freq,
255
256 .c = {
257 .dbg_name = "sdc1_clk",
258 .ops = &clk_ops_rcg_mnd,
259 },
260};
261
262static struct branch_clk gcc_sdcc1_apps_clk =
263{
264 .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
265 .parent = &sdcc1_apps_clk_src.c,
266
267 .c = {
268 .dbg_name = "gcc_sdcc1_apps_clk",
269 .ops = &clk_ops_branch,
270 },
271};
272
273static struct branch_clk gcc_sdcc1_ahb_clk =
274{
275 .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
276 .has_sibling = 1,
277
278 .c = {
279 .dbg_name = "gcc_sdcc1_ahb_clk",
280 .ops = &clk_ops_branch,
281 },
282};
283
Amol Jadi0a4c9b42013-10-11 14:22:11 -0700284/* USB 3.0 Clocks */
285static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
286{
287 F(125000000, gpll0, 1, 5, 24),
288 F_END
289};
290
291static struct rcg_clk usb30_master_clk_src =
292{
293 .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR,
294 .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR,
295 .m_reg = (uint32_t *) GCC_USB30_MASTER_M,
296 .n_reg = (uint32_t *) GCC_USB30_MASTER_N,
297 .d_reg = (uint32_t *) GCC_USB30_MASTER_D,
298
299 .set_rate = clock_lib2_rcg_set_rate_mnd,
300 .freq_tbl = ftbl_gcc_usb30_master_clk,
301 .current_freq = &rcg_dummy_freq,
302
303 .c = {
304 .dbg_name = "usb30_master_clk_src",
305 .ops = &clk_ops_rcg,
306 },
307};
308
309
310static struct branch_clk gcc_usb30_master_clk =
311{
312 .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR,
313 .parent = &usb30_master_clk_src.c,
314
315 .c = {
316 .dbg_name = "gcc_usb30_master_clk",
317 .ops = &clk_ops_branch,
318 },
319};
320
321static struct branch_clk gcc_sys_noc_usb30_axi_clk =
322{
323 .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR,
324 .has_sibling = 1,
325
326 .c = {
327 .dbg_name = "gcc_sys_noc_usb3_axi_clk",
328 .ops = &clk_ops_branch,
329 },
330};
331
Dhaval Patel4a87d522013-10-18 19:02:37 -0700332/* Display clocks */
333static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
334 F_MM(19200000, cxo, 1, 0, 0),
335 F_END
336};
337
338static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
339 F_MM(19200000, cxo, 1, 0, 0),
340 F_END
341};
342
343static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
344 F_MM(19200000, cxo, 1, 0, 0),
345 F_MM(100000000, gpll0, 6, 0, 0),
346 F_END
347};
348
349static struct clk_freq_tbl ftbl_mdp_clk[] = {
350 F_MM( 75000000, gpll0, 8, 0, 0),
351 F_MM( 240000000, gpll0, 2.5, 0, 0),
352 F_END
353};
354
355static struct rcg_clk dsi_esc0_clk_src = {
356 .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR,
357 .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR,
358 .set_rate = clock_lib2_rcg_set_rate_hid,
359 .freq_tbl = ftbl_mdss_esc0_1_clk,
360
361 .c = {
362 .dbg_name = "dsi_esc0_clk_src",
363 .ops = &clk_ops_rcg,
364 },
365};
366
367static struct rcg_clk dsi_esc1_clk_src = {
368 .cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR,
369 .cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR,
370 .set_rate = clock_lib2_rcg_set_rate_hid,
371 .freq_tbl = ftbl_mdss_esc1_1_clk,
372
373 .c = {
374 .dbg_name = "dsi_esc1_clk_src",
375 .ops = &clk_ops_rcg,
376 },
377};
378
379static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
380 F_MM(19200000, cxo, 1, 0, 0),
381 F_END
382};
383
384static struct rcg_clk vsync_clk_src = {
385 .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR,
386 .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR,
387 .set_rate = clock_lib2_rcg_set_rate_hid,
388 .freq_tbl = ftbl_mdss_vsync_clk,
389
390 .c = {
391 .dbg_name = "vsync_clk_src",
392 .ops = &clk_ops_rcg,
393 },
394};
395
396static struct rcg_clk mdp_axi_clk_src = {
397 .cmd_reg = (uint32_t *) MDP_AXI_CMD_RCGR,
398 .cfg_reg = (uint32_t *) MDP_AXI_CFG_RCGR,
399 .set_rate = clock_lib2_rcg_set_rate_hid,
400 .freq_tbl = ftbl_mmss_axi_clk,
401
402 .c = {
403 .dbg_name = "mdp_axi_clk_src",
404 .ops = &clk_ops_rcg,
405 },
406};
407
408static struct branch_clk mdss_esc0_clk = {
409 .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR,
410 .parent = &dsi_esc0_clk_src.c,
411 .has_sibling = 0,
412
413 .c = {
414 .dbg_name = "mdss_esc0_clk",
415 .ops = &clk_ops_branch,
416 },
417};
418
419static struct branch_clk mdss_esc1_clk = {
420 .cbcr_reg = (uint32_t *) DSI_ESC1_CBCR,
421 .parent = &dsi_esc1_clk_src.c,
422 .has_sibling = 0,
423
424 .c = {
425 .dbg_name = "mdss_esc1_clk",
426 .ops = &clk_ops_branch,
427 },
428};
429
430static struct branch_clk mdss_axi_clk = {
431 .cbcr_reg = (uint32_t *) MDP_AXI_CBCR,
432 .parent = &mdp_axi_clk_src.c,
433 .has_sibling = 0,
434
435 .c = {
436 .dbg_name = "mdss_axi_clk",
437 .ops = &clk_ops_branch,
438 },
439};
440
441static struct branch_clk mmss_mmssnoc_axi_clk = {
442 .cbcr_reg = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR,
443 .parent = &mdp_axi_clk_src.c,
444 .has_sibling = 0,
445
446 .c = {
447 .dbg_name = "mmss_mmssnoc_axi_clk",
448 .ops = &clk_ops_branch,
449 },
450};
451
452static struct branch_clk mmss_s0_axi_clk = {
453 .cbcr_reg = (uint32_t *) MMSS_S0_AXI_CBCR,
454 .parent = &mdp_axi_clk_src.c,
455 .has_sibling = 0,
456
457 .c = {
458 .dbg_name = "mmss_s0_axi_clk",
459 .ops = &clk_ops_branch,
460 },
461};
462
463static struct branch_clk mdp_ahb_clk = {
464 .cbcr_reg = (uint32_t *) MDP_AHB_CBCR,
465 .has_sibling = 1,
466
467 .c = {
468 .dbg_name = "mdp_ahb_clk",
469 .ops = &clk_ops_branch,
470 },
471};
472
473static struct rcg_clk mdss_mdp_clk_src = {
474 .cmd_reg = (uint32_t *) MDP_CMD_RCGR,
475 .cfg_reg = (uint32_t *) MDP_CFG_RCGR,
476 .set_rate = clock_lib2_rcg_set_rate_hid,
477 .freq_tbl = ftbl_mdp_clk,
478 .current_freq = &rcg_dummy_freq,
479
480 .c = {
481 .dbg_name = "mdss_mdp_clk_src",
482 .ops = &clk_ops_rcg,
483 },
484};
485
486static struct branch_clk mdss_mdp_clk = {
487 .cbcr_reg = (uint32_t *) MDP_CBCR,
488 .parent = &mdss_mdp_clk_src.c,
489 .has_sibling = 1,
490
491 .c = {
492 .dbg_name = "mdss_mdp_clk",
493 .ops = &clk_ops_branch,
494 },
495};
496
497static struct branch_clk mdss_mdp_lut_clk = {
498 .cbcr_reg = MDP_LUT_CBCR,
499 .parent = &mdss_mdp_clk_src.c,
500 .has_sibling = 1,
501
502 .c = {
503 .dbg_name = "mdss_mdp_lut_clk",
504 .ops = &clk_ops_branch,
505 },
506};
507
508static struct branch_clk mdss_vsync_clk = {
509 .cbcr_reg = MDSS_VSYNC_CBCR,
510 .parent = &vsync_clk_src.c,
511 .has_sibling = 0,
512
513 .c = {
514 .dbg_name = "mdss_vsync_clk",
515 .ops = &clk_ops_branch,
516 },
517};
518
519
Deepa Dinamani554b0622013-05-16 15:00:30 -0700520/* Clock lookup table */
521static struct clk_lookup msm_clocks_8084[] =
522{
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -0700523 CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
524 CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
Deepa Dinamani554b0622013-05-16 15:00:30 -0700525
Sundarajan Srinivasand8b7c6f2013-09-13 16:50:22 -0700526 CLK_LOOKUP("uart7_iface_clk", gcc_blsp2_ahb_clk.c),
527 CLK_LOOKUP("uart7_core_clk", gcc_blsp2_uart2_apps_clk.c),
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -0700528
529 CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
530 CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
Amol Jadi0a4c9b42013-10-11 14:22:11 -0700531
532 /* USB 3.0 */
533 CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
534 CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
Dhaval Patel4a87d522013-10-18 19:02:37 -0700535
536 /* mdss clocks */
537 CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
538 CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
539 CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c),
540 CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c),
541 CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c),
542 CLK_LOOKUP("mmss_s0_axi_clk", mmss_s0_axi_clk.c),
543 CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c),
544 CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
545 CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
546 CLK_LOOKUP("mdss_mdp_lut_clk", mdss_mdp_lut_clk.c),
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -0700547};
Deepa Dinamani554b0622013-05-16 15:00:30 -0700548
549void platform_clock_init(void)
550{
551 clk_init(msm_clocks_8084, ARRAY_SIZE(msm_clocks_8084));
552}