Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame^] | 1 | /* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | #include <mdp4.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <target/display.h> |
| 33 | #include <platform/timer.h> |
| 34 | #include <platform/iomap.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame^] | 35 | #include <dev/lcdc.h> |
| 36 | #include <dev/fbcon.h> |
| 37 | #include <bits.h> |
| 38 | #include <msm_panel.h> |
| 39 | #include <mipi_dsi.h> |
| 40 | #include <err.h> |
| 41 | |
| 42 | static int mdp_rev; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 43 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 44 | void |
| 45 | mdp_setup_dma_p_video_config(unsigned short pack_pattern, |
| 46 | unsigned short img_width, |
| 47 | unsigned short img_height, |
| 48 | unsigned long input_img_addr, |
| 49 | unsigned short img_width_full_size, |
| 50 | unsigned char ystride) |
| 51 | { |
| 52 | dprintf(SPEW, "MDP4.2 Setup for DSI Video Mode\n"); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 53 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 54 | // ----- programming MDP_AXI_RDMASTER_CONFIG -------- |
| 55 | /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's |
| 56 | the only port connected */ |
| 57 | //TODO: Seems to still work without this |
| 58 | writel(0x00290000, MDP_AXI_RDMASTER_CONFIG); |
| 59 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 60 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 61 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 62 | /* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */ |
| 63 | writel(0x00000049, MDP_DISP_INTF_SEL); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 64 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 65 | /* DMA P */ |
| 66 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 67 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 68 | /* RGB 888 */ |
| 69 | writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 70 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 71 | writel(0x0, MDP_DMA_P_OUT_XY); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 72 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 73 | writel(img_height << 16 | img_width, MDP_DMA_P_SIZE); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 74 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 75 | writel(input_img_addr, MDP_DMA_P_BUF_ADDR); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 76 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 77 | writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 78 | } |
| 79 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 80 | int |
| 81 | mdp_setup_dma_p_video_mode(unsigned short disp_width, |
| 82 | unsigned short disp_height, |
| 83 | unsigned short img_width, |
| 84 | unsigned short img_height, |
| 85 | unsigned short hsync_porch0_fp, |
| 86 | unsigned short hsync_porch0_bp, |
| 87 | unsigned short vsync_porch0_fp, |
| 88 | unsigned short vsync_porch0_bp, |
| 89 | unsigned short hsync_width, |
| 90 | unsigned short vsync_width, |
| 91 | unsigned long input_img_addr, |
| 92 | unsigned short img_width_full_size, |
| 93 | unsigned short pack_pattern, unsigned char ystride) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 94 | { |
| 95 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 96 | // unsigned long mdp_intr_status; |
| 97 | int status = FAIL; |
| 98 | unsigned long hsync_period; |
| 99 | unsigned long vsync_period; |
| 100 | unsigned long vsync_period_intmd; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 101 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 102 | dprintf(SPEW, "MDP4.1 for DSI Video Mode\n"); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 103 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 104 | hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1; |
| 105 | vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1; |
| 106 | vsync_period = vsync_period_intmd * hsync_period; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 107 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 108 | // ----- programming MDP_AXI_RDMASTER_CONFIG -------- |
| 109 | /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's |
| 110 | the only port connected */ |
| 111 | writel(0x00290000, MDP_AXI_RDMASTER_CONFIG); |
| 112 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 113 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
| 114 | /* sets PRIM_INTF_SEL to 0x1 and SEC_INTF_SEL to 0x2 and DSI_VIDEO_INTF_SEL */ |
| 115 | writel(0x00000049, MDP_DISP_INTF_SEL); |
| 116 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 117 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 118 | // ------------- programming MDP_DMA_P_CONFIG --------------------- |
| 119 | writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); // rgb888 |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 120 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 121 | writel(0x00000000, MDP_DMA_P_OUT_XY); |
| 122 | writel(img_height << 16 | img_width, MDP_DMA_P_SIZE); |
| 123 | writel(input_img_addr, MDP_DMA_P_BUF_ADDR); |
| 124 | writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE); |
| 125 | writel(0x00ff0000, MDP_DMA_P_OP_MODE); |
| 126 | writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL); |
| 127 | writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD); |
| 128 | writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH); |
| 129 | writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp, |
| 130 | MDP_DSI_VIDEO_DISPLAY_HCTL); |
| 131 | writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START); |
| 132 | writel((img_height + vsync_porch0_bp) * hsync_period, |
| 133 | MDP_DSI_VIDEO_DISPLAY_V_END); |
| 134 | writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR); |
| 135 | writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW); |
| 136 | writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY); |
| 137 | // end of cmd mdp |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 138 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 139 | writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 140 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 141 | status = PASS; |
| 142 | return status; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 143 | } |
| 144 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 145 | int |
| 146 | mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 147 | unsigned short num_of_lanes) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 148 | { |
| 149 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 150 | int status = 0; |
| 151 | unsigned long input_img_addr = MIPI_FB_ADDR; |
| 152 | unsigned short image_wd = mipi_fb_cfg.width; |
| 153 | unsigned short image_ht = mipi_fb_cfg.height; |
| 154 | unsigned short pack_pattern = 0x12; |
| 155 | unsigned char ystride = 3; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 156 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 157 | writel(0x03ffffff, MDP_INTR_ENABLE); |
| 158 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 159 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 160 | // ------------- programming MDP_DMA_P_CONFIG --------------------- |
| 161 | writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888 |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 162 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 163 | writel(0x00000000, MDP_DMA_P_OUT_XY); |
| 164 | writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE); |
| 165 | writel(input_img_addr, MDP_DMA_P_BUF_ADDR); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 166 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 167 | writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 168 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 169 | writel(0x00000000, MDP_DMA_P_OP_MODE); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 170 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 171 | writel(0x10, MDP_DSI_CMD_MODE_ID_MAP); |
| 172 | writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 173 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 174 | writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG); |
| 175 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 176 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
| 177 | writel(0x8a, MDP_DISP_INTF_SEL); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 178 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 179 | return status; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | void mdp_disable(void) |
| 183 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 184 | writel(0x00000000, MDP_DSI_VIDEO_EN); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | void mdp_shutdown(void) |
| 188 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 189 | mdp_disable(); |
| 190 | mdelay(60); |
| 191 | writel(0x00000000, MDP_INTR_ENABLE); |
| 192 | writel(0x00000003, MDP_OVERLAYPROC0_CFG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | void mdp_start_dma(void) |
| 196 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 197 | writel(0x00000001, MDP_DMA_P_START); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 198 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame^] | 199 | |
| 200 | int mdp_lcdc_config(struct msm_panel_info *pinfo, |
| 201 | struct fbcon_config *fb) |
| 202 | { |
| 203 | unsigned mdp_rgb_size; |
| 204 | unsigned mdp_rgb_size_src; |
| 205 | int hsync_period, vsync_period; |
| 206 | int hsync_start_x, hsync_end_x; |
| 207 | int display_hctl, display_vstart, display_vend; |
| 208 | unsigned mdp_rgb_format = 0; |
| 209 | |
| 210 | int active_x, active_y; |
| 211 | int active_hstart_x, active_hend_x; |
| 212 | int active_vstart, active_vend; |
| 213 | |
| 214 | struct lcdc_panel_info *lcdc = NULL; |
| 215 | |
| 216 | if (pinfo == NULL) |
| 217 | return; |
| 218 | |
| 219 | lcdc = &(pinfo->lcdc); |
| 220 | if (lcdc == NULL) |
| 221 | return; |
| 222 | |
| 223 | mdp_rgb_size = (pinfo->yres << 16) + pinfo->xres; |
| 224 | mdp_rgb_size_src = (fb->height << 16) + fb->width; |
| 225 | |
| 226 | dprintf(INFO, "Panel is %d x %d\n", |
| 227 | pinfo->xres + lcdc->xres_pad, |
| 228 | pinfo->yres + lcdc->yres_pad); |
| 229 | |
| 230 | /* write fb addr in MDP_DMA_P_BUF_ADDR */ |
| 231 | writel(fb->base, MDP_DMA_P_BUF_ADDR); |
| 232 | |
| 233 | /* write active region size*/ |
| 234 | writel(mdp_rgb_size, MDP_DMA_P_SIZE); |
| 235 | |
| 236 | /* set Y-stride value in bytes */ |
| 237 | /* Y-stride is defined as the number of bytes |
| 238 | in a line. |
| 239 | */ |
| 240 | writel((pinfo->xres * pinfo->bpp/8), MDP_DMA_P_BUF_Y_STRIDE); |
| 241 | |
| 242 | /* Start XY coordinates */ |
| 243 | writel(0, MDP_DMA_P_OUT_XY); |
| 244 | |
| 245 | if (fb->bpp == 16) { |
| 246 | writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB | |
| 247 | DMA_DITHER_EN | DMA_OUT_SEL_LCDC | |
| 248 | DMA_IBUF_FORMAT_RGB565 | DMA_DSTC0G_8BITS | |
| 249 | DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS, |
| 250 | MDP_DMA_P_CONFIG); |
| 251 | mdp_rgb_format = MDP_RGB_565_FORMAT; |
| 252 | } else if (fb->bpp == 24) { |
| 253 | writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB | |
| 254 | DMA_DITHER_EN | DMA_OUT_SEL_LCDC | |
| 255 | DMA_IBUF_FORMAT_RGB888 | DMA_DSTC0G_8BITS | |
| 256 | DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS, |
| 257 | MDP_DMA_P_CONFIG); |
| 258 | mdp_rgb_format = MDP_RGB_888_FORMAT; |
| 259 | } else { |
| 260 | dprintf(CRITICAL, "Unsupported bpp detected!\n"); |
| 261 | return ERR_INVALID_ARGS; |
| 262 | } |
| 263 | |
| 264 | hsync_period = lcdc->h_pulse_width + |
| 265 | lcdc->h_back_porch + |
| 266 | pinfo->xres + lcdc->h_front_porch; |
| 267 | vsync_period = (lcdc->v_pulse_width + |
| 268 | lcdc->v_back_porch + |
| 269 | pinfo->yres + |
| 270 | lcdc->v_front_porch) * |
| 271 | hsync_period; |
| 272 | hsync_start_x = |
| 273 | lcdc->h_pulse_width + |
| 274 | lcdc->h_back_porch; |
| 275 | hsync_end_x = |
| 276 | hsync_period - lcdc->h_front_porch - 1; |
| 277 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 278 | display_vstart = (lcdc->v_pulse_width + |
| 279 | lcdc->v_back_porch) |
| 280 | * hsync_period + lcdc->hsync_skew; |
| 281 | display_vend = vsync_period - |
| 282 | (lcdc->v_front_porch * hsync_period) |
| 283 | +lcdc->hsync_skew - 1; |
| 284 | |
| 285 | active_x = (pinfo->xres - fb->width)/2; |
| 286 | active_y = (pinfo->yres - fb->height)/2; |
| 287 | |
| 288 | active_hstart_x = lcdc->h_pulse_width + lcdc->h_back_porch |
| 289 | + active_x; |
| 290 | active_hend_x = active_hstart_x + fb->width - 1; |
| 291 | |
| 292 | active_vstart = (lcdc->v_pulse_width + lcdc->v_back_porch |
| 293 | + active_y) * hsync_period |
| 294 | + lcdc->hsync_skew; |
| 295 | active_vend = active_vstart + (fb->height * hsync_period) - 1; |
| 296 | |
| 297 | |
| 298 | /* LCDC specific initalizations */ |
| 299 | writel((hsync_period << 16) | lcdc->h_pulse_width, |
| 300 | MDP_LCDC_HSYNC_CTL); |
| 301 | writel(vsync_period, MDP_LCDC_VSYNC_PERIOD); |
| 302 | writel(lcdc->v_pulse_width * hsync_period, |
| 303 | MDP_LCDC_VSYNC_PULSE_WIDTH); |
| 304 | writel(display_hctl, MDP_LCDC_DISPLAY_HCTL); |
| 305 | writel(display_vstart, MDP_LCDC_DISPLAY_V_START); |
| 306 | writel(display_vend, MDP_LCDC_DISPLAY_V_END); |
| 307 | |
| 308 | writel(BIT(31) | (active_hend_x << 16) | active_hstart_x, |
| 309 | MDP_LCDC_ACTIVE_HCTL); |
| 310 | |
| 311 | writel(BIT(31) | active_vstart, MDP_LCDC_ACTIVE_V_START); |
| 312 | writel(active_vend, MDP_LCDC_ACTIVE_V_END); |
| 313 | |
| 314 | writel(0xf, MDP_LCDC_BORDER_CLR); |
| 315 | writel(0xff, MDP_LCDC_UNDERFLOW_CTL); |
| 316 | writel(lcdc->hsync_skew, |
| 317 | MDP_LCDC_HSYNC_SKEW); |
| 318 | writel(0x3, MDP_LCDC_CTL_POLARITY); |
| 319 | writel(0, MDP_LCDC_ACTIVE_HCTL); |
| 320 | writel(0, MDP_LCDC_ACTIVE_V_START); |
| 321 | writel(0, MDP_LCDC_ACTIVE_V_END); |
| 322 | |
| 323 | /* setting for single layer direct out mode for rgb565 source */ |
| 324 | writel(0x100, MDP_LAYERMIXER_IN_CFG); |
| 325 | writel(mdp_rgb_size_src, MDP_RGB1_SRC_SIZE); |
| 326 | writel(mdp_rgb_size, MDP_RGB1_OUT_SIZE); |
| 327 | writel((int)fb->base, MDP_RGB1_SRCP0_ADDR); |
| 328 | writel((fb->stride * fb->bpp / 8), MDP_RGB1_SRC_YSTRIDE1); |
| 329 | writel(0x00, MDP_RGB1_CONSTANT_COLOR); |
| 330 | writel(mdp_rgb_format, MDP_RGB1_SRC_FORMAT); |
| 331 | writel(0x1, MDP_OVERLAYPROC0_CFG); |
| 332 | if (fb->bpp == 16) |
| 333 | writel(0x1, MDP_OVERLAYPROC0_OPMODE); |
| 334 | else if (fb->bpp == 24) |
| 335 | writel(0x0, MDP_OVERLAYPROC0_OPMODE); |
| 336 | |
| 337 | /* register flush and enable LCDC */ |
| 338 | writel(0x11, MDP_OVERLAY_REG_FLUSH); |
| 339 | return NO_ERROR; |
| 340 | } |
| 341 | |
| 342 | int mdp_lcdc_on() |
| 343 | { |
| 344 | writel(0x1, MDP_LCDC_EN); |
| 345 | return NO_ERROR; |
| 346 | } |
| 347 | |
| 348 | int mdp_lcdc_off() |
| 349 | { |
| 350 | writel(0x0, MDP_LCDC_EN); |
| 351 | return NO_ERROR; |
| 352 | } |
| 353 | |
| 354 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 355 | struct fbcon_config *fb) |
| 356 | { |
| 357 | int ret = NO_ERROR; |
| 358 | int hsync_period, vsync_period; |
| 359 | int hsync_start_x, hsync_end_x; |
| 360 | int display_hctl, display_vstart, display_vend; |
| 361 | struct lcdc_panel_info *lcdc = NULL; |
| 362 | unsigned mdp_rgb_size; |
| 363 | |
| 364 | if (pinfo == NULL) |
| 365 | return ERR_INVALID_ARGS; |
| 366 | |
| 367 | lcdc = &(pinfo->lcdc); |
| 368 | if (lcdc == NULL) |
| 369 | return ERR_INVALID_ARGS; |
| 370 | |
| 371 | hsync_period = lcdc->h_pulse_width + |
| 372 | lcdc->h_back_porch + |
| 373 | pinfo->xres + lcdc->xres_pad + lcdc->h_front_porch; |
| 374 | vsync_period = (lcdc->v_pulse_width + |
| 375 | lcdc->v_back_porch + |
| 376 | pinfo->yres + lcdc->yres_pad + |
| 377 | lcdc->v_front_porch) * hsync_period; |
| 378 | hsync_start_x = |
| 379 | lcdc->h_pulse_width + |
| 380 | lcdc->h_back_porch; |
| 381 | hsync_end_x = |
| 382 | hsync_period - lcdc->h_front_porch - 1; |
| 383 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 384 | display_vstart = (lcdc->v_pulse_width + |
| 385 | lcdc->v_back_porch) |
| 386 | * hsync_period + lcdc->hsync_skew; |
| 387 | display_vend = vsync_period - |
| 388 | (lcdc->v_front_porch * hsync_period) |
| 389 | +lcdc->hsync_skew - 1; |
| 390 | |
| 391 | /* MDP_AXI_RDMASTER_CONFIG set all master to read from |
| 392 | AXI port 0, that's the only port connected */ |
| 393 | writel(0x00290000, MDP_AXI_RDMASTER_CONFIG); |
| 394 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 395 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
| 396 | |
| 397 | /* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, |
| 398 | EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */ |
| 399 | writel(0x00000049, MDP_DISP_INTF_SEL); |
| 400 | |
| 401 | /* DMA P */ |
| 402 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
| 403 | |
| 404 | /* write fb addr in MDP_DMA_P_BUF_ADDR */ |
| 405 | writel(fb->base, MDP_DMA_P_BUF_ADDR); |
| 406 | |
| 407 | /* write active region size*/ |
| 408 | mdp_rgb_size = (fb->height << 16) + fb->width; |
| 409 | writel(mdp_rgb_size, MDP_DMA_P_SIZE); |
| 410 | |
| 411 | /* set Y-stride value in bytes */ |
| 412 | /* Y-stride is defined as the number of bytes |
| 413 | in a line. |
| 414 | */ |
| 415 | writel((fb->stride * fb->bpp/8), MDP_DMA_P_BUF_Y_STRIDE); |
| 416 | |
| 417 | /* Start XY coordinates */ |
| 418 | writel(0, MDP_DMA_P_OUT_XY); |
| 419 | |
| 420 | if (fb->bpp == 16) { |
| 421 | writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB | |
| 422 | DMA_DITHER_EN | DMA_OUT_SEL_LCDC | |
| 423 | DMA_IBUF_FORMAT_RGB565 | DMA_DSTC0G_8BITS | |
| 424 | DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS, |
| 425 | MDP_DMA_P_CONFIG); |
| 426 | } else if (fb->bpp == 24) { |
| 427 | writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB | |
| 428 | DMA_DITHER_EN | DMA_OUT_SEL_LCDC | |
| 429 | DMA_IBUF_FORMAT_RGB888 | DMA_DSTC0G_8BITS | |
| 430 | DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS, |
| 431 | MDP_DMA_P_CONFIG); |
| 432 | } else { |
| 433 | dprintf(CRITICAL, "Unsupported bpp detected!\n"); |
| 434 | return ERR_INVALID_ARGS; |
| 435 | } |
| 436 | |
| 437 | writel(hsync_period << 16 | lcdc->h_pulse_width, |
| 438 | MDP_DSI_VIDEO_HSYNC_CTL); |
| 439 | writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD); |
| 440 | writel(lcdc->v_pulse_width * hsync_period, |
| 441 | MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH); |
| 442 | writel(display_hctl, |
| 443 | MDP_DSI_VIDEO_DISPLAY_HCTL); |
| 444 | writel(display_vstart, MDP_DSI_VIDEO_DISPLAY_V_START); |
| 445 | writel(display_vend, MDP_DSI_VIDEO_DISPLAY_V_END); |
| 446 | |
| 447 | if (lcdc->xres_pad) { |
| 448 | writel((1 << 31) | |
| 449 | (lcdc->h_back_porch + lcdc->h_pulse_width + |
| 450 | fb->width - 1) << 16 | lcdc->h_pulse_width + |
| 451 | lcdc->h_back_porch, MDP_DSI_VIDEO_ACTIVE_HCTL); |
| 452 | } |
| 453 | |
| 454 | return ret; |
| 455 | } |
| 456 | |
| 457 | int mdp_dsi_video_on() |
| 458 | { |
| 459 | int ret = NO_ERROR; |
| 460 | |
| 461 | writel(0x00000001, MDP_DSI_VIDEO_EN); |
| 462 | |
| 463 | return ret; |
| 464 | } |
| 465 | |
| 466 | int mdp_dsi_video_off() |
| 467 | { |
| 468 | #if (!CONT_SPLASH_SCREEN) |
| 469 | writel(0x00000000, MDP_DSI_VIDEO_EN); |
| 470 | mdelay(60); |
| 471 | writel(0x00000000, MDP_INTR_ENABLE); |
| 472 | writel(0x00000003, MDP_OVERLAYPROC0_CFG); |
| 473 | #endif |
| 474 | return NO_ERROR; |
| 475 | } |
| 476 | |
| 477 | void mdp_set_revision(int rev) |
| 478 | { |
| 479 | mdp_rev = rev; |
| 480 | } |
| 481 | |
| 482 | int mdp_get_revision() |
| 483 | { |
| 484 | return mdp_rev; |
| 485 | } |