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Brian Swetland9a477532009-01-01 11:40:02 -08001/*
2 * Copyright (c) 2008, Google Inc.
3 * All rights reserved.
4 *
Channagoud Kadabifd473732011-10-19 22:43:41 +05305 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
Shashank Mittal52525ff2010-04-13 11:11:10 -07006 *
Brian Swetland9a477532009-01-01 11:40:02 -08007 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
20 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
21 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
27 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <debug.h>
32#include <reg.h>
Greg Griscod2471ef2011-07-14 13:00:42 -070033#include <dev/gpio.h>
Brian Swetland9a477532009-01-01 11:40:02 -080034
35#include <platform/iomap.h>
Ajay Dudanib01e5062011-12-03 23:23:42 -080036#define ACPU_CLK 0 /* Applications processor clock */
37#define ADM_CLK 1 /* Applications data mover clock */
38#define ADSP_CLK 2 /* ADSP clock */
39#define EBI1_CLK 3 /* External bus interface 1 clock */
40#define EBI2_CLK 4 /* External bus interface 2 clock */
41#define ECODEC_CLK 5 /* External CODEC clock */
42#define EMDH_CLK 6 /* External MDDI host clock */
43#define GP_CLK 7 /* General purpose clock */
44#define GRP_CLK 8 /* Graphics clock */
45#define I2C_CLK 9 /* I2C clock */
46#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
47#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
48#define IMEM_CLK 12 /* Internal graphics memory clock */
49#define MDC_CLK 13 /* MDDI client clock */
50#define MDP_CLK 14 /* Mobile display processor clock */
51#define PBUS_CLK 15 /* Peripheral bus clock */
52#define PCM_CLK 16 /* PCM clock */
53#define PMDH_CLK 17 /* Primary MDDI host clock */
54#define SDAC_CLK 18 /* Stereo DAC clock */
55#define SDC1_CLK 19 /* Secure Digital Card clocks */
Brian Swetland9a477532009-01-01 11:40:02 -080056#define SDC1_PCLK 20
57#define SDC2_CLK 21
58#define SDC2_PCLK 22
Ajay Dudanib01e5062011-12-03 23:23:42 -080059#define SDC3_CLK 23
60#define SDC3_PCLK 24
Brian Swetland9a477532009-01-01 11:40:02 -080061#define SDC4_CLK 25
62#define SDC4_PCLK 26
Ajay Dudanib01e5062011-12-03 23:23:42 -080063#define TSIF_CLK 27 /* Transport Stream Interface clocks */
Brian Swetland9a477532009-01-01 11:40:02 -080064#define TSIF_REF_CLK 28
Ajay Dudanib01e5062011-12-03 23:23:42 -080065#define TV_DAC_CLK 29 /* TV clocks */
Brian Swetland9a477532009-01-01 11:40:02 -080066#define TV_ENC_CLK 30
Ajay Dudanib01e5062011-12-03 23:23:42 -080067#define UART1_CLK 31 /* UART clocks */
Brian Swetland9a477532009-01-01 11:40:02 -080068#define UART2_CLK 32
69#define UART3_CLK 33
70#define UART1DM_CLK 34
71#define UART2DM_CLK 35
Ajay Dudanib01e5062011-12-03 23:23:42 -080072#define USB_HS_CLK 36 /* High speed USB core clock */
73#define USB_HS_PCLK 37 /* High speed USB pbus clock */
74#define USB_OTG_CLK 38 /* Full speed USB clock */
75#define VDC_CLK 39 /* Video controller clock */
76#define VFE_CLK 40 /* Camera / Video Front End clock */
77#define VFE_MDC_CLK 41 /* VFE MDDI client clock */
Brian Swetland9a477532009-01-01 11:40:02 -080078
79/* qsd8k adds... */
80#define MDP_LCDC_PCLK_CLK 42
81#define MDP_LCDC_PAD_PCLK_CLK 43
82#define MDP_VSYNC_CLK 44
83
Ajay Dudanib01e5062011-12-03 23:23:42 -080084#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
Shashank Mittal37040832010-08-24 15:57:57 -070085/* msm7x30 adds... */
Chandan Uddarajuc009e4d2010-09-08 17:06:45 -070086#define PMDH_P_CLK 82
Shashank Mittal37040832010-08-24 15:57:57 -070087#define MDP_P_CLK 86
88
Brian Swetland9a477532009-01-01 11:40:02 -080089enum {
90 PCOM_CMD_IDLE = 0x0,
91 PCOM_CMD_DONE,
92 PCOM_RESET_APPS,
93 PCOM_RESET_CHIP,
94 PCOM_CONFIG_NAND_MPU,
95 PCOM_CONFIG_USB_CLKS,
96 PCOM_GET_POWER_ON_STATUS,
97 PCOM_GET_WAKE_UP_STATUS,
98 PCOM_GET_BATT_LEVEL,
99 PCOM_CHG_IS_CHARGING,
100 PCOM_POWER_DOWN,
101 PCOM_USB_PIN_CONFIG,
102 PCOM_USB_PIN_SEL,
103 PCOM_SET_RTC_ALARM,
104 PCOM_NV_READ,
105 PCOM_NV_WRITE,
106 PCOM_GET_UUID_HIGH,
107 PCOM_GET_UUID_LOW,
108 PCOM_GET_HW_ENTROPY,
109 PCOM_RPC_GPIO_TLMM_CONFIG_REMOTE,
110 PCOM_CLKCTL_RPC_ENABLE,
111 PCOM_CLKCTL_RPC_DISABLE,
112 PCOM_CLKCTL_RPC_RESET,
113 PCOM_CLKCTL_RPC_SET_FLAGS,
114 PCOM_CLKCTL_RPC_SET_RATE,
115 PCOM_CLKCTL_RPC_MIN_RATE,
116 PCOM_CLKCTL_RPC_MAX_RATE,
117 PCOM_CLKCTL_RPC_RATE,
118 PCOM_CLKCTL_RPC_PLL_REQUEST,
119 PCOM_CLKCTL_RPC_ENABLED,
120 PCOM_VREG_SWITCH,
121 PCOM_VREG_SET_LEVEL,
122 PCOM_GPIO_TLMM_CONFIG_GROUP,
123 PCOM_GPIO_TLMM_UNCONFIG_GROUP,
124 PCOM_NV_READ_HIGH_BITS,
125 PCOM_NV_WRITE_HIGH_BITS,
Ajay Dudanib01e5062011-12-03 23:23:42 -0800126 PCOM_RPC_GPIO_TLMM_CONFIG_EX = 0x25,
Brian Swetland9a477532009-01-01 11:40:02 -0800127 PCOM_NUM_CMDS,
Channagoud Kadabi5c86fe32012-02-16 10:58:48 +0530128 PCOM_KERNEL_SEC_BOOT = 0x7A,
Brian Swetland9a477532009-01-01 11:40:02 -0800129};
130
131enum {
Ajay Dudanib01e5062011-12-03 23:23:42 -0800132 PCOM_INVALID_STATUS = 0x0,
133 PCOM_READY,
134 PCOM_CMD_RUNNING,
135 PCOM_CMD_SUCCESS,
136 PCOM_CMD_FAIL,
Brian Swetland9a477532009-01-01 11:40:02 -0800137};
138
Ajay Dudani232ce812009-12-02 00:14:11 -0800139#ifndef PLATFORM_MSM7X30
Brian Swetland9a477532009-01-01 11:40:02 -0800140#define MSM_A2M_INT(n) (MSM_CSR_BASE + 0x400 + (n) * 4)
Ajay Dudani232ce812009-12-02 00:14:11 -0800141#endif
Brian Swetland9a477532009-01-01 11:40:02 -0800142static inline void notify_other_proc_comm(void)
143{
Ajay Dudani232ce812009-12-02 00:14:11 -0800144#ifndef PLATFORM_MSM7X30
Ajay Dudanib01e5062011-12-03 23:23:42 -0800145 writel(1, MSM_A2M_INT(6));
Ajay Dudani232ce812009-12-02 00:14:11 -0800146#else
Ajay Dudanib01e5062011-12-03 23:23:42 -0800147 writel(1 << 6, (MSM_GCC_BASE + 0x8));
Ajay Dudani232ce812009-12-02 00:14:11 -0800148#endif
Brian Swetland9a477532009-01-01 11:40:02 -0800149}
150
151#define APP_COMMAND (MSM_SHARED_BASE + 0x00)
152#define APP_STATUS (MSM_SHARED_BASE + 0x04)
153#define APP_DATA1 (MSM_SHARED_BASE + 0x08)
154#define APP_DATA2 (MSM_SHARED_BASE + 0x0C)
155
156#define MDM_COMMAND (MSM_SHARED_BASE + 0x10)
157#define MDM_STATUS (MSM_SHARED_BASE + 0x14)
158#define MDM_DATA1 (MSM_SHARED_BASE + 0x18)
159#define MDM_DATA2 (MSM_SHARED_BASE + 0x1C)
160
161int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2)
162{
163 int ret = -1;
164 unsigned status;
165
Ajay Dudanib01e5062011-12-03 23:23:42 -0800166// dprintf(INFO, "proc_comm(%d,%d,%d)\n",
167// cmd, data1 ? *data1 : 0, data2 ? *data2 : 0);
Brian Swetland9a477532009-01-01 11:40:02 -0800168 while (readl(MDM_STATUS) != PCOM_READY) {
169 /* XXX check for A9 reset */
170 }
171
Brian Swetland9a477532009-01-01 11:40:02 -0800172 if (data1)
173 writel(*data1, APP_DATA1);
174 if (data2)
175 writel(*data2, APP_DATA2);
176
Channagoud Kadabifd473732011-10-19 22:43:41 +0530177 /*
178 * As per the specs write data, cmd, interrupt for
179 * proc comm processing
180 */
181 writel(cmd, APP_COMMAND);
Ajay Dudanib01e5062011-12-03 23:23:42 -0800182// dprintf(INFO, "proc_comm tx\n");
Brian Swetland9a477532009-01-01 11:40:02 -0800183 notify_other_proc_comm();
184 while (readl(APP_COMMAND) != PCOM_CMD_DONE) {
185 /* XXX check for A9 reset */
186 }
187
188 status = readl(APP_STATUS);
Ajay Dudanib01e5062011-12-03 23:23:42 -0800189// dprintf(INFO, "proc_comm status %d\n", status);
Brian Swetland9a477532009-01-01 11:40:02 -0800190
191 if (status != PCOM_CMD_FAIL) {
192 if (data1)
193 *data1 = readl(APP_DATA1);
194 if (data2)
195 *data2 = readl(APP_DATA2);
196 ret = 0;
Ajay Dudanib01e5062011-12-03 23:23:42 -0800197 /*
198 * Write command idle to indicate non HLOS that
199 * apps has finished reading the status & data
200 * of proc comm command
201 */
Channagoud Kadabifd473732011-10-19 22:43:41 +0530202 writel(PCOM_CMD_IDLE, APP_COMMAND);
Brian Swetland9a477532009-01-01 11:40:02 -0800203 }
204
205 return ret;
206}
207
208static int clock_enable(unsigned id)
209{
210 return msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, 0);
211}
212
213static int clock_disable(unsigned id)
214{
215 return msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, 0);
216}
217
218static int clock_set_rate(unsigned id, unsigned rate)
219{
220 return msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
221}
222
Shashank Mittal52525ff2010-04-13 11:11:10 -0700223static int clock_get_rate(unsigned id)
224{
225 if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, 0)) {
226 return -1;
227 } else {
Ajay Dudanib01e5062011-12-03 23:23:42 -0800228 return (int)id;
Shashank Mittal52525ff2010-04-13 11:11:10 -0700229 }
230}
231
Ajay Dudani7d605522010-10-01 19:52:37 -0700232void usb_clock_init()
233{
234 clock_enable(USB_HS_PCLK);
235 clock_enable(USB_HS_CLK);
Chandan Uddaraju0af34822010-10-07 14:46:58 -0700236 clock_enable(P_USB_HS_CORE_CLK);
Ajay Dudani7d605522010-10-01 19:52:37 -0700237}
238
Brian Swetland9a477532009-01-01 11:40:02 -0800239void lcdc_clock_init(unsigned rate)
240{
Shashank Mittal37040832010-08-24 15:57:57 -0700241 clock_set_rate(MDP_LCDC_PCLK_CLK, rate);
Brian Swetland9a477532009-01-01 11:40:02 -0800242 clock_enable(MDP_LCDC_PCLK_CLK);
243 clock_enable(MDP_LCDC_PAD_PCLK_CLK);
Shashank Mittal37040832010-08-24 15:57:57 -0700244}
Brian Swetland9a477532009-01-01 11:40:02 -0800245
Ajay Dudanib01e5062011-12-03 23:23:42 -0800246void mdp_clock_init(unsigned rate)
Shashank Mittal37040832010-08-24 15:57:57 -0700247{
248 clock_set_rate(MDP_CLK, rate);
Brian Swetland9a477532009-01-01 11:40:02 -0800249 clock_enable(MDP_CLK);
Shashank Mittal37040832010-08-24 15:57:57 -0700250 clock_enable(MDP_P_CLK);
Brian Swetland9a477532009-01-01 11:40:02 -0800251}
252
253void uart3_clock_init(void)
254{
255 clock_enable(UART3_CLK);
256 clock_set_rate(UART3_CLK, 19200000 / 4);
257}
Brian Swetland977224f2009-01-02 01:33:04 -0800258
Shashank Mittal1ddc04c2010-12-21 14:39:07 -0800259void uart2_clock_init(void)
260{
261 clock_enable(UART2_CLK);
262 clock_set_rate(UART2_CLK, 19200000);
263}
264
Shashank Mittal2fad67f2011-04-08 19:45:10 -0700265void uart1_clock_init(void)
266{
267 clock_enable(UART1_CLK);
268 clock_set_rate(UART1_CLK, 19200000 / 4);
269}
270
Dima Zavin36785e32009-01-28 17:26:43 -0800271void mddi_clock_init(unsigned num, unsigned rate)
272{
273 unsigned clock_id;
274
275 if (num == 0)
276 clock_id = PMDH_CLK;
277 else
278 clock_id = EMDH_CLK;
279
280 clock_enable(clock_id);
281 clock_set_rate(clock_id, rate);
Chandan Uddarajuc009e4d2010-09-08 17:06:45 -0700282#ifdef PLATFORM_MSM7X30
Ajay Dudanib01e5062011-12-03 23:23:42 -0800283 clock_enable(PMDH_P_CLK);
Chandan Uddarajuc009e4d2010-09-08 17:06:45 -0700284#endif
Dima Zavin36785e32009-01-28 17:26:43 -0800285}
Chandan Uddaraju94183c02010-01-15 15:13:59 -0800286
287void reboot(unsigned reboot_reason)
288{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800289 msm_proc_comm(PCOM_RESET_CHIP, &reboot_reason, 0);
290 for (;;) ;
Chandan Uddaraju94183c02010-01-15 15:13:59 -0800291}
Chandan Uddaraju7f5b9012010-02-06 16:37:48 -0800292
Ajay Dudanib01e5062011-12-03 23:23:42 -0800293int mmc_clock_enable_disable(unsigned id, unsigned enable)
Shashank Mittal52525ff2010-04-13 11:11:10 -0700294{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800295 if (enable) {
296 return clock_enable(id); //Enable mmc clock rate
297 } else {
298 return clock_disable(id); //Disable mmc clock rate
Shashank Mittal52525ff2010-04-13 11:11:10 -0700299 }
300}
301
302int mmc_clock_set_rate(unsigned id, unsigned rate)
303{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800304 return clock_set_rate(id, rate); //Set mmc clock rate
Shashank Mittal52525ff2010-04-13 11:11:10 -0700305}
306
307int mmc_clock_get_rate(unsigned id)
308{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800309 return clock_get_rate(id); //Get mmc clock rate
Shashank Mittal52525ff2010-04-13 11:11:10 -0700310}
311
Shashank Mittal37040832010-08-24 15:57:57 -0700312int gpio_tlmm_config(unsigned config, unsigned disable)
313{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800314 return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable);
Shashank Mittal37040832010-08-24 15:57:57 -0700315}
316
317int vreg_set_level(unsigned id, unsigned mv)
318{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800319 return msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv);
Shashank Mittal37040832010-08-24 15:57:57 -0700320}
321
322int vreg_enable(unsigned id)
323{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800324 int enable = 1;
325 return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
Shashank Mittal37040832010-08-24 15:57:57 -0700326
327}
328
329int vreg_disable(unsigned id)
330{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800331 int enable = 0;
332 return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
Shashank Mittal37040832010-08-24 15:57:57 -0700333}
Channagoud Kadabi5c86fe32012-02-16 10:58:48 +0530334
335void set_tamper_flag(int tamper)
336{
337 return msm_proc_comm(PCOM_KERNEL_SEC_BOOT, &tamper, 0);
338}