Matthew Qin | 3aa8705 | 2014-02-21 10:32:34 +0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 2 | |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation, Inc. nor the names of its |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 29 | #include <bits.h> |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <spmi.h> |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 33 | #include <string.h> |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 34 | #include <pm8x41_hw.h> |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 35 | #include <pm8x41.h> |
| 36 | #include <platform/timer.h> |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 37 | |
Channagoud Kadabi | d091f70 | 2013-01-07 16:17:37 -0800 | [diff] [blame] | 38 | /* SPMI helper functions */ |
| 39 | uint8_t pm8x41_reg_read(uint32_t addr) |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 40 | { |
| 41 | uint8_t val = 0; |
| 42 | struct pmic_arb_cmd cmd; |
| 43 | struct pmic_arb_param param; |
| 44 | |
| 45 | cmd.address = PERIPH_ID(addr); |
| 46 | cmd.offset = REG_OFFSET(addr); |
| 47 | cmd.slave_id = SLAVE_ID(addr); |
| 48 | cmd.priority = 0; |
| 49 | |
| 50 | param.buffer = &val; |
| 51 | param.size = 1; |
| 52 | |
| 53 | pmic_arb_read_cmd(&cmd, ¶m); |
| 54 | |
| 55 | return val; |
| 56 | } |
| 57 | |
Channagoud Kadabi | d091f70 | 2013-01-07 16:17:37 -0800 | [diff] [blame] | 58 | void pm8x41_reg_write(uint32_t addr, uint8_t val) |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 59 | { |
| 60 | struct pmic_arb_cmd cmd; |
| 61 | struct pmic_arb_param param; |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 62 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 63 | cmd.address = PERIPH_ID(addr); |
| 64 | cmd.offset = REG_OFFSET(addr); |
| 65 | cmd.slave_id = SLAVE_ID(addr); |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 66 | cmd.priority = 0; |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 67 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 68 | param.buffer = &val; |
| 69 | param.size = 1; |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 70 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 71 | pmic_arb_write_cmd(&cmd, ¶m); |
| 72 | } |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 73 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 74 | /* Exported functions */ |
| 75 | |
| 76 | /* Set the boot done flag */ |
| 77 | void pm8x41_set_boot_done() |
| 78 | { |
| 79 | uint8_t val; |
| 80 | |
| 81 | val = REG_READ(SMBB_MISC_BOOT_DONE); |
| 82 | val |= BIT(BOOT_DONE_BIT); |
| 83 | REG_WRITE(SMBB_MISC_BOOT_DONE, val); |
| 84 | } |
| 85 | |
| 86 | /* Configure GPIO */ |
| 87 | int pm8x41_gpio_config(uint8_t gpio, struct pm8x41_gpio *config) |
| 88 | { |
| 89 | uint8_t val; |
| 90 | uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio); |
| 91 | |
| 92 | /* Disable the GPIO */ |
| 93 | val = REG_READ(gpio_base + GPIO_EN_CTL); |
| 94 | val &= ~BIT(PERPH_EN_BIT); |
| 95 | REG_WRITE(gpio_base + GPIO_EN_CTL, val); |
| 96 | |
| 97 | /* Select the mode */ |
| 98 | val = config->function | (config->direction << 4); |
| 99 | REG_WRITE(gpio_base + GPIO_MODE_CTL, val); |
| 100 | |
| 101 | /* Set the right pull */ |
| 102 | val = config->pull; |
| 103 | REG_WRITE(gpio_base + GPIO_DIG_PULL_CTL, val); |
| 104 | |
| 105 | /* Select the VIN */ |
| 106 | val = config->vin_sel; |
| 107 | REG_WRITE(gpio_base + GPIO_DIG_VIN_CTL, val); |
| 108 | |
Siddhartha Agrawal | d61f81e | 2012-12-17 19:20:35 -0800 | [diff] [blame] | 109 | if (config->direction == PM_GPIO_DIR_OUT) { |
| 110 | /* Set the right dig out control */ |
| 111 | val = config->out_strength | (config->output_buffer << 4); |
| 112 | REG_WRITE(gpio_base + GPIO_DIG_OUT_CTL, val); |
| 113 | } |
| 114 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 115 | /* Enable the GPIO */ |
| 116 | val = REG_READ(gpio_base + GPIO_EN_CTL); |
| 117 | val |= BIT(PERPH_EN_BIT); |
| 118 | REG_WRITE(gpio_base + GPIO_EN_CTL, val); |
| 119 | |
Siddhartha Agrawal | d61f81e | 2012-12-17 19:20:35 -0800 | [diff] [blame] | 120 | return 0; |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | /* Reads the status of requested gpio */ |
| 124 | int pm8x41_gpio_get(uint8_t gpio, uint8_t *status) |
| 125 | { |
| 126 | uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio); |
| 127 | |
| 128 | *status = REG_READ(gpio_base + GPIO_STATUS); |
| 129 | |
| 130 | /* Return the value of the GPIO pin */ |
| 131 | *status &= BIT(GPIO_STATUS_VAL_BIT); |
| 132 | |
| 133 | dprintf(SPEW, "GPIO %d status is %d\n", gpio, *status); |
| 134 | |
Siddhartha Agrawal | d61f81e | 2012-12-17 19:20:35 -0800 | [diff] [blame] | 135 | return 0; |
| 136 | } |
| 137 | |
| 138 | /* Write the output value of the requested gpio */ |
| 139 | int pm8x41_gpio_set(uint8_t gpio, uint8_t value) |
| 140 | { |
| 141 | uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio); |
| 142 | uint8_t val; |
| 143 | |
| 144 | /* Set the output value of the gpio */ |
| 145 | val = REG_READ(gpio_base + GPIO_MODE_CTL); |
| 146 | val = (val & ~PM_GPIO_OUTPUT_MASK) | value; |
| 147 | REG_WRITE(gpio_base + GPIO_MODE_CTL, val); |
| 148 | |
| 149 | return 0; |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 150 | } |
| 151 | |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 152 | /* Prepare PON RESIN S2 reset (bite) */ |
| 153 | void pm8x41_resin_s2_reset_enable() |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 154 | { |
| 155 | uint8_t val; |
| 156 | |
| 157 | /* disable s2 reset */ |
| 158 | REG_WRITE(PON_RESIN_N_RESET_S2_CTL, 0x0); |
| 159 | |
Amol Jadi | 7ec52b4 | 2012-08-16 14:12:45 -0700 | [diff] [blame] | 160 | /* Delay needed for disable to kick in. */ |
| 161 | udelay(300); |
| 162 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 163 | /* configure s1 timer to 0 */ |
| 164 | REG_WRITE(PON_RESIN_N_RESET_S1_TIMER, 0x0); |
| 165 | |
| 166 | /* configure s2 timer to 2s */ |
| 167 | REG_WRITE(PON_RESIN_N_RESET_S2_TIMER, PON_RESIN_N_RESET_S2_TIMER_MAX_VALUE); |
| 168 | |
| 169 | /* configure reset type */ |
| 170 | REG_WRITE(PON_RESIN_N_RESET_S2_CTL, S2_RESET_TYPE_WARM); |
| 171 | |
| 172 | val = REG_READ(PON_RESIN_N_RESET_S2_CTL); |
| 173 | |
| 174 | /* enable s2 reset */ |
| 175 | val |= BIT(S2_RESET_EN_BIT); |
| 176 | REG_WRITE(PON_RESIN_N_RESET_S2_CTL, val); |
| 177 | } |
| 178 | |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 179 | /* Disable PON RESIN S2 reset. (bite)*/ |
| 180 | void pm8x41_resin_s2_reset_disable() |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 181 | { |
| 182 | /* disable s2 reset */ |
| 183 | REG_WRITE(PON_RESIN_N_RESET_S2_CTL, 0x0); |
Amol Jadi | 7ec52b4 | 2012-08-16 14:12:45 -0700 | [diff] [blame] | 184 | |
| 185 | /* Delay needed for disable to kick in. */ |
| 186 | udelay(300); |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 187 | } |
| 188 | |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 189 | /* Resin irq status for faulty pmic*/ |
Channagoud Kadabi | 36c19ea | 2013-07-05 16:28:44 -0700 | [diff] [blame] | 190 | uint32_t pm8x41_v2_resin_status() |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 191 | { |
| 192 | uint8_t rt_sts = 0; |
| 193 | |
| 194 | /* Enable S2 reset so we can detect the volume down key press */ |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 195 | pm8x41_resin_s2_reset_enable(); |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 196 | |
| 197 | /* Delay before interrupt triggering. |
| 198 | * See PON_DEBOUNCE_CTL reg. |
| 199 | */ |
| 200 | mdelay(100); |
| 201 | |
| 202 | rt_sts = REG_READ(PON_INT_RT_STS); |
| 203 | |
| 204 | /* Must disable S2 reset otherwise PMIC will reset if key |
| 205 | * is held longer than S2 timer. |
| 206 | */ |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 207 | pm8x41_resin_s2_reset_disable(); |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 208 | |
| 209 | return (rt_sts & BIT(RESIN_BARK_INT_BIT)); |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 210 | } |
Neeti Desai | 120b55d | 2012-08-20 17:15:56 -0700 | [diff] [blame] | 211 | |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 212 | /* Resin pin status */ |
| 213 | uint32_t pm8x41_resin_status() |
| 214 | { |
| 215 | uint8_t rt_sts = 0; |
| 216 | |
| 217 | rt_sts = REG_READ(PON_INT_RT_STS); |
| 218 | |
| 219 | return (rt_sts & BIT(RESIN_ON_INT_BIT)); |
| 220 | } |
| 221 | |
Matthew Qin | 3aa8705 | 2014-02-21 10:32:34 +0800 | [diff] [blame] | 222 | /* Return 1 if power key is pressed */ |
| 223 | uint32_t pm8x41_get_pwrkey_is_pressed() |
| 224 | { |
| 225 | uint8_t pwr_sts = 0; |
| 226 | |
| 227 | pwr_sts = REG_READ(PON_INT_RT_STS); |
| 228 | |
| 229 | if (pwr_sts & BIT(KPDPWR_ON_INT_BIT)) |
| 230 | return 1; |
| 231 | else |
| 232 | return 0; |
| 233 | } |
| 234 | |
Deepa Dinamani | 3c9865d | 2013-03-08 14:03:19 -0800 | [diff] [blame] | 235 | void pm8x41_v2_reset_configure(uint8_t reset_type) |
Neeti Desai | 120b55d | 2012-08-20 17:15:56 -0700 | [diff] [blame] | 236 | { |
| 237 | uint8_t val; |
| 238 | |
| 239 | /* disable PS_HOLD_RESET */ |
| 240 | REG_WRITE(PON_PS_HOLD_RESET_CTL, 0x0); |
| 241 | |
| 242 | /* Delay needed for disable to kick in. */ |
| 243 | udelay(300); |
| 244 | |
| 245 | /* configure reset type */ |
| 246 | REG_WRITE(PON_PS_HOLD_RESET_CTL, reset_type); |
| 247 | |
| 248 | val = REG_READ(PON_PS_HOLD_RESET_CTL); |
| 249 | |
| 250 | /* enable PS_HOLD_RESET */ |
| 251 | val |= BIT(S2_RESET_EN_BIT); |
| 252 | REG_WRITE(PON_PS_HOLD_RESET_CTL, val); |
| 253 | } |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 254 | |
Deepa Dinamani | 3c9865d | 2013-03-08 14:03:19 -0800 | [diff] [blame] | 255 | void pm8x41_reset_configure(uint8_t reset_type) |
| 256 | { |
| 257 | /* disable PS_HOLD_RESET */ |
| 258 | REG_WRITE(PON_PS_HOLD_RESET_CTL2, 0x0); |
| 259 | |
| 260 | /* Delay needed for disable to kick in. */ |
| 261 | udelay(300); |
| 262 | |
| 263 | /* configure reset type */ |
| 264 | REG_WRITE(PON_PS_HOLD_RESET_CTL, reset_type); |
| 265 | |
| 266 | /* enable PS_HOLD_RESET */ |
| 267 | REG_WRITE(PON_PS_HOLD_RESET_CTL2, BIT(S2_RESET_EN_BIT)); |
| 268 | } |
| 269 | |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 270 | /* |
| 271 | * LDO set voltage, takes ldo name & voltage in UV as input |
| 272 | */ |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 273 | int pm8x41_ldo_set_voltage(struct pm8x41_ldo *ldo, uint32_t voltage) |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 274 | { |
| 275 | uint32_t range = 0; |
| 276 | uint32_t step = 0; |
| 277 | uint32_t mult = 0; |
| 278 | uint32_t val = 0; |
| 279 | uint32_t vmin = 0; |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 280 | |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 281 | if (!ldo) |
| 282 | { |
| 283 | dprintf(CRITICAL, "LDO pointer is invalid: %p\n", ldo); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 284 | return 1; |
| 285 | } |
| 286 | |
| 287 | /* Program Normal power mode */ |
| 288 | val = 0x0; |
| 289 | val = (1 << LDO_NORMAL_PWR_BIT); |
| 290 | REG_WRITE((ldo->base + LDO_POWER_MODE), val); |
| 291 | |
| 292 | /* |
| 293 | * Select range, step & vmin based on input voltage & type of LDO |
| 294 | * LDO can operate in low, mid, high power mode |
| 295 | */ |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 296 | if (ldo->type == PLDO_TYPE) |
| 297 | { |
| 298 | if (voltage < PLDO_UV_MIN) |
| 299 | { |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 300 | range = 2; |
| 301 | step = PLDO_UV_STEP_LOW; |
| 302 | vmin = PLDO_UV_VMIN_LOW; |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 303 | } |
| 304 | else if (voltage < PDLO_UV_MID) |
| 305 | { |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 306 | range = 3; |
| 307 | step = PLDO_UV_STEP_MID; |
| 308 | vmin = PLDO_UV_VMIN_MID; |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 309 | } |
| 310 | else |
| 311 | { |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 312 | range = 4; |
| 313 | step = PLDO_UV_STEP_HIGH; |
| 314 | vmin = PLDO_UV_VMIN_HIGH; |
| 315 | } |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 316 | } |
| 317 | else |
| 318 | { |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 319 | range = 2; |
| 320 | step = NLDO_UV_STEP; |
| 321 | vmin = NLDO_UV_VMIN_LOW; |
| 322 | } |
| 323 | |
| 324 | mult = (voltage - vmin) / step; |
| 325 | |
| 326 | /* Set Range in voltage ctrl register */ |
| 327 | val = 0x0; |
| 328 | val = range << LDO_RANGE_SEL_BIT; |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 329 | REG_WRITE((ldo->base + LDO_RANGE_CTRL), val); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 330 | |
| 331 | /* Set multiplier in voltage ctrl register */ |
| 332 | val = 0x0; |
| 333 | val = mult << LDO_VSET_SEL_BIT; |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 334 | REG_WRITE((ldo->base + LDO_STEP_CTRL), val); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 335 | |
| 336 | return 0; |
| 337 | } |
| 338 | |
| 339 | /* |
| 340 | * Enable or Disable LDO |
| 341 | */ |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 342 | int pm8x41_ldo_control(struct pm8x41_ldo *ldo, uint8_t enable) |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 343 | { |
| 344 | uint32_t val = 0; |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 345 | |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 346 | if (!ldo) |
| 347 | { |
| 348 | dprintf(CRITICAL, "LDO pointer is invalid: %p\n", ldo); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 349 | return 1; |
| 350 | } |
| 351 | |
| 352 | /* Enable LDO */ |
| 353 | if (enable) |
| 354 | val = (1 << LDO_VREG_ENABLE_BIT); |
| 355 | else |
| 356 | val = (0 << LDO_VREG_ENABLE_BIT); |
| 357 | |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 358 | REG_WRITE((ldo->base + LDO_EN_CTL_REG), val); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 359 | |
| 360 | return 0; |
| 361 | } |
Deepa Dinamani | 7564f2a | 2013-02-05 17:55:51 -0800 | [diff] [blame] | 362 | |
Kuogee Hsieh | 1183511 | 2013-10-04 15:50:36 -0700 | [diff] [blame] | 363 | /* |
| 364 | * lpg channel register write: |
| 365 | */ |
| 366 | void pm8x41_lpg_write(uint8_t chan, uint8_t off, uint8_t val) |
| 367 | { |
| 368 | uint32_t lpg_base = LPG_N_PERIPHERAL_BASE(chan); |
| 369 | |
| 370 | REG_WRITE(lpg_base + off, val); |
| 371 | } |
| 372 | |
Deepa Dinamani | 7564f2a | 2013-02-05 17:55:51 -0800 | [diff] [blame] | 373 | uint8_t pm8x41_get_pmic_rev() |
| 374 | { |
| 375 | return REG_READ(REVID_REVISION4); |
| 376 | } |
| 377 | |
sundarajan srinivasan | d0f59e8 | 2013-02-12 19:17:02 -0800 | [diff] [blame] | 378 | uint8_t pm8x41_get_pon_reason() |
| 379 | { |
| 380 | return REG_READ(PON_PON_REASON1); |
| 381 | } |
Deepa Dinamani | c342f12 | 2013-06-12 15:41:31 -0700 | [diff] [blame] | 382 | |
Matthew Qin | 5e90d83 | 2014-07-11 11:15:22 +0800 | [diff] [blame^] | 383 | uint8_t pm8x41_get_pon_poff_reason1() |
| 384 | { |
| 385 | return REG_READ(PON_POFF_REASON1); |
| 386 | } |
| 387 | |
| 388 | uint8_t pm8x41_get_pon_poff_reason2() |
| 389 | { |
| 390 | return REG_READ(PON_POFF_REASON2); |
| 391 | } |
| 392 | |
Deepa Dinamani | c342f12 | 2013-06-12 15:41:31 -0700 | [diff] [blame] | 393 | void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable) |
| 394 | { |
| 395 | ASSERT(mpp); |
| 396 | |
| 397 | REG_WRITE(mpp->base + MPP_EN_CTL, enable << MPP_EN_CTL_ENABLE_SHIFT); |
| 398 | } |
| 399 | |
| 400 | void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp) |
| 401 | { |
| 402 | ASSERT(mpp); |
| 403 | |
| 404 | REG_WRITE(mpp->base + MPP_DIG_VIN_CTL, mpp->vin); |
| 405 | |
| 406 | REG_WRITE(mpp->base + MPP_MODE_CTL, mpp->mode | (MPP_DIGITAL_OUTPUT << MPP_MODE_CTL_MODE_SHIFT)); |
| 407 | } |
Ameya Thakur | b0a62ab | 2013-06-25 13:43:10 -0700 | [diff] [blame] | 408 | |
| 409 | uint8_t pm8x41_get_is_cold_boot() |
| 410 | { |
| 411 | if (REG_READ(PON_WARMBOOT_STATUS1) || REG_READ(PON_WARMBOOT_STATUS2)) { |
| 412 | dprintf(INFO,"%s: Warm boot\n", __func__); |
| 413 | return 0; |
| 414 | } |
| 415 | dprintf(INFO,"%s: cold boot\n", __func__); |
| 416 | return 1; |
| 417 | } |
Amol Jadi | c3231ff | 2013-07-23 14:35:31 -0700 | [diff] [blame] | 418 | |
Channagoud Kadabi | 7ec7a08 | 2014-02-04 15:47:13 -0800 | [diff] [blame] | 419 | /* api to control lnbb clock */ |
| 420 | void pm8x41_lnbb_clock_ctrl(uint8_t enable) |
| 421 | { |
| 422 | uint8_t reg; |
| 423 | |
| 424 | reg = REG_READ(LNBB_CLK_EN_CTL); |
| 425 | |
| 426 | if (enable) |
| 427 | { |
| 428 | reg |= BIT(LNBB_CLK_EN_BIT); |
| 429 | } |
| 430 | else |
| 431 | { |
| 432 | reg &= ~BIT(LNBB_CLK_EN_BIT); |
| 433 | } |
| 434 | |
| 435 | REG_WRITE(LNBB_CLK_EN_CTL, reg); |
| 436 | } |
| 437 | |
Amol Jadi | c3231ff | 2013-07-23 14:35:31 -0700 | [diff] [blame] | 438 | /* api to control diff clock */ |
| 439 | void pm8x41_diff_clock_ctrl(uint8_t enable) |
| 440 | { |
| 441 | uint8_t reg; |
| 442 | |
| 443 | reg = REG_READ(DIFF_CLK1_EN_CTL); |
| 444 | |
| 445 | if (enable) |
| 446 | { |
| 447 | reg |= BIT(DIFF_CLK1_EN_BIT); |
| 448 | } |
| 449 | else |
| 450 | { |
| 451 | reg &= ~BIT(DIFF_CLK1_EN_BIT); |
| 452 | } |
| 453 | |
| 454 | REG_WRITE(DIFF_CLK1_EN_CTL, reg); |
| 455 | } |
Xiaocheng Li | 73c5712 | 2013-09-14 17:32:00 +0800 | [diff] [blame] | 456 | |
| 457 | void pm8x41_clear_pmic_watchdog(void) |
| 458 | { |
| 459 | pm8x41_reg_write(PMIC_WD_RESET_S2_CTL2, 0x0); |
| 460 | } |
Channagoud Kadabi | 1372b90 | 2013-10-28 16:20:51 -0700 | [diff] [blame] | 461 | |
| 462 | /* API to check for borken battery */ |
| 463 | int pm8xxx_is_battery_broken() |
| 464 | { |
| 465 | uint8_t trkl_default = 0; |
| 466 | uint8_t vbat_det_default = 0; |
| 467 | int batt_is_broken = 0; |
| 468 | |
| 469 | /* Store original trickle charging current setting */ |
| 470 | trkl_default = pm8x41_reg_read(PM8XXX_IBAT_ATC_A); |
| 471 | /* Store original VBAT_DET_LO setting */ |
| 472 | vbat_det_default = pm8x41_reg_read(PM8XXX_VBAT_DET); |
| 473 | |
| 474 | /*Set trickle charge current to 50mA (IBAT_ATC_A = 0x00) */ |
| 475 | pm8x41_reg_write(PM8XXX_IBAT_ATC_A, 0x00); |
| 476 | /* Set VBAT_DET_LO to 4.3V so that VBAT_DET_HI = 4.52V (VBAT_DET_LO = 0x35) */ |
| 477 | pm8x41_reg_write(PM8XXX_VBAT_DET, VBAT_DET_LO_4_30V); |
| 478 | /* Unlock SMBBP Secured Register */ |
| 479 | pm8x41_reg_write(PM8XXX_SEC_ACCESS, SEC_ACCESS); |
| 480 | /* Disable VTRKL_FAULT comp (SMBBP_CHGR_COMP_OVR0 = 0x08) */ |
| 481 | pm8x41_reg_write(PM8XXX_COMP_OVR0, OVR0_DIS_VTRKL_FAULT); |
| 482 | /* Disable VCP (SMBB_BAT_IF_VCP = 0x00) */ |
| 483 | pm8x41_reg_write(PM8XXX_VCP, 0x00); |
| 484 | /* Unlock SMBBP Secured Register */ |
| 485 | pm8x41_reg_write(PM8XXX_SEC_ACCESS, SEC_ACCESS); |
| 486 | /* Force trickle charging (SMBB_CHGR_TRKL_CHG_TEST = 0x01) */ |
| 487 | pm8x41_reg_write(PM8XXX_TRKL_CHG_TEST, CHG_TRICKLE_FORCED_ON); |
| 488 | /* Wait for vbat to rise */ |
| 489 | mdelay(12); |
| 490 | |
| 491 | /* Check Above VBAT_DET_HIGH status */ |
| 492 | if (pm8x41_reg_read(PM8XXX_VBAT_IN_TSTS) & VBAT_DET_HI_RT_STS) |
| 493 | batt_is_broken = 1; |
| 494 | else |
| 495 | batt_is_broken = 0; |
| 496 | |
| 497 | /* Unlock SMBBP Secured Register */ |
| 498 | pm8x41_reg_write(PM8XXX_SEC_ACCESS, SEC_ACCESS); |
| 499 | |
| 500 | /* Disable force trickle charging */ |
| 501 | pm8x41_reg_write(PM8XXX_TRKL_CHG_TEST, 0x00); |
| 502 | /* re-enable VCP */ |
| 503 | pm8x41_reg_write(PM8XXX_VCP, VCP_ENABLE); |
| 504 | /* restore trickle charging default current */ |
| 505 | pm8x41_reg_write(PM8XXX_IBAT_ATC_A, trkl_default); |
| 506 | /* restore VBAT_DET_LO setting to original value */ |
| 507 | pm8x41_reg_write(PM8XXX_VBAT_DET, vbat_det_default); |
| 508 | |
| 509 | return batt_is_broken; |
| 510 | } |