Shivaraj Shetty | 5cbb746 | 2014-01-13 17:17:39 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _PLATFORM_MSM_SHARED_MIPI_DSI_H_ |
| 31 | #define _PLATFORM_MSM_SHARED_MIPI_DSI_H_ |
| 32 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 33 | #include <msm_panel.h> |
| 34 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 35 | #define PASS 0 |
| 36 | #define FAIL 1 |
| 37 | |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 38 | #define DSI_CLKOUT_TIMING_CTRL REG_DSI(0x0C0) |
| 39 | #define DSI_SOFT_RESET REG_DSI(0x114) |
| 40 | #define DSI_CAL_CTRL REG_DSI(0x0F4) |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 41 | |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 42 | #define DSIPHY_SW_RESET REG_DSI(0x128) |
| 43 | #define DSIPHY_PLL_RDY REG_DSI(0x280) |
| 44 | #define DSIPHY_REGULATOR_CAL_PWR_CFG REG_DSI(0x518) |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 45 | |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 46 | #define DSI_CLK_CTRL REG_DSI(0x118) |
| 47 | #define DSI_TRIG_CTRL REG_DSI(0x080) |
| 48 | #define DSI_CTRL REG_DSI(0x000) |
| 49 | #define DSI_COMMAND_MODE_DMA_CTRL REG_DSI(0x038) |
| 50 | #define DSI_COMMAND_MODE_MDP_CTRL REG_DSI(0x03C) |
| 51 | #define DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL REG_DSI(0x040) |
| 52 | #define DSI_DMA_CMD_OFFSET REG_DSI(0x044) |
| 53 | #define DSI_DMA_CMD_LENGTH REG_DSI(0x048) |
| 54 | #define DSI_COMMAND_MODE_MDP_STREAM0_CTRL REG_DSI(0x054) |
| 55 | #define DSI_COMMAND_MODE_MDP_STREAM0_TOTAL REG_DSI(0x058) |
| 56 | #define DSI_COMMAND_MODE_MDP_STREAM1_CTRL REG_DSI(0x05C) |
| 57 | #define DSI_COMMAND_MODE_MDP_STREAM1_TOTAL REG_DSI(0x060) |
| 58 | #define DSI_ERR_INT_MASK0 REG_DSI(0x108) |
| 59 | #define DSI_INT_CTRL REG_DSI(0x10C) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 60 | |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 61 | #define DSI_VIDEO_MODE_ACTIVE_H REG_DSI(0x020) |
| 62 | #define DSI_VIDEO_MODE_ACTIVE_V REG_DSI(0x024) |
| 63 | #define DSI_VIDEO_MODE_TOTAL REG_DSI(0x028) |
| 64 | #define DSI_VIDEO_MODE_HSYNC REG_DSI(0x02C) |
| 65 | #define DSI_VIDEO_MODE_VSYNC REG_DSI(0x030) |
| 66 | #define DSI_VIDEO_MODE_VSYNC_VPOS REG_DSI(0x034) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 67 | |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 68 | #define DSI_MISR_CMD_CTRL REG_DSI(0x09C) |
| 69 | #define DSI_MISR_VIDEO_CTRL REG_DSI(0x0A0) |
| 70 | #define DSI_EOT_PACKET_CTRL REG_DSI(0x0C8) |
| 71 | #define DSI_VIDEO_MODE_CTRL REG_DSI(0x00C) |
| 72 | #define DSI_CAL_STRENGTH_CTRL REG_DSI(0x100) |
| 73 | #define DSI_CMD_MODE_DMA_SW_TRIGGER REG_DSI(0x08C) |
| 74 | #define DSI_CMD_MODE_MDP_SW_TRIGGER REG_DSI(0x090) |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 75 | #define DSI_HS_TIMER_CTRL REG_DSI(0x0B8) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 76 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 77 | #define DSI_LANE_CTRL REG_DSI(0x0A8) |
| 78 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 79 | #define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */ |
| 80 | #define MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 81 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 82 | #define DTYPE_GEN_WRITE2 0x23 /* 4th Byte is 0x80 */ |
| 83 | #define DTYPE_GEN_LWRITE 0x29 /* 4th Byte is 0xc0 */ |
| 84 | #define DTYPE_DCS_WRITE1 0x15 /* 4th Byte is 0x80 */ |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 85 | |
Shivaraj Shetty | 5cbb746 | 2014-01-13 17:17:39 +0530 | [diff] [blame] | 86 | #define RDBK_DATA0 0x06C |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 87 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 88 | //BEGINNING OF Tochiba Config- video mode |
| 89 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 90 | static const unsigned char toshiba_panel_mcap_off[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 91 | 0x02, 0x00, 0x29, 0xc0, |
| 92 | 0xb2, 0x00, 0xff, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 93 | }; |
| 94 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 95 | static const unsigned char toshiba_panel_ena_test_reg[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 96 | 0x03, 0x00, 0x29, 0xc0, |
| 97 | 0xEF, 0x01, 0x01, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 98 | }; |
| 99 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 100 | static const unsigned char toshiba_panel_ena_test_reg_wvga[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 101 | 0x03, 0x00, 0x29, 0xc0, |
| 102 | 0xEF, 0x01, 0x01, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 103 | }; |
| 104 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 105 | static const unsigned char toshiba_panel_num_of_2lane[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 106 | 0x03, 0x00, 0x29, 0xc0, // 63:2lane |
| 107 | 0xEF, 0x60, 0x63, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 108 | }; |
| 109 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 110 | static const unsigned char toshiba_panel_num_of_1lane[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 111 | 0x03, 0x00, 0x29, 0xc0, // 62:1lane |
| 112 | 0xEF, 0x60, 0x62, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 113 | }; |
| 114 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 115 | static const unsigned char toshiba_panel_non_burst_sync_pulse[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 116 | 0x03, 0x00, 0x29, 0xc0, |
| 117 | 0xef, 0x61, 0x09, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 118 | }; |
| 119 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 120 | static const unsigned char toshiba_panel_set_DMODE_WQVGA[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 121 | 0x02, 0x00, 0x29, 0xc0, |
| 122 | 0xB3, 0x01, 0xFF, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 123 | }; |
| 124 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 125 | static const unsigned char toshiba_panel_set_DMODE_WVGA[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 126 | 0x02, 0x00, 0x29, 0xc0, |
| 127 | 0xB3, 0x00, 0xFF, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 128 | }; |
| 129 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 130 | static const unsigned char toshiba_panel_set_intern_WR_clk1_wvga[8] |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 131 | = { |
| 132 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 133 | 0x03, 0x00, 0x29, 0xC0, // 1 last packet |
| 134 | 0xef, 0x2f, 0xcc, 0xff, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 135 | }; |
| 136 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 137 | static const unsigned char toshiba_panel_set_intern_WR_clk2_wvga[8] |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 138 | = { |
| 139 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 140 | 0x03, 0x00, 0x29, 0xC0, // 1 last packet |
| 141 | 0xef, 0x6e, 0xdd, 0xff, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 142 | }; |
| 143 | |
| 144 | static const unsigned char |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 145 | toshiba_panel_set_intern_WR_clk1_wqvga[8] = { |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 146 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 147 | 0x03, 0x00, 0x29, 0xC0, // 1 last packet |
| 148 | 0xef, 0x2f, 0x22, 0xff, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 149 | }; |
| 150 | |
| 151 | static const unsigned char |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 152 | toshiba_panel_set_intern_WR_clk2_wqvga[8] = { |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 153 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 154 | 0x03, 0x00, 0x29, 0xC0, // 1 last packet |
| 155 | 0xef, 0x6e, 0x33, 0xff, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 156 | }; |
| 157 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 158 | static const unsigned char toshiba_panel_set_hor_addr_2A_wvga[12] = { |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 159 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 160 | 0x05, 0x00, 0x39, 0xC0, // 1 last packet |
| 161 | // 0x2A, 0x00, 0x08, 0x00,//100 = 64h |
| 162 | // 0x6b, 0xFF, 0xFF, 0xFF, |
| 163 | 0x2A, 0x00, 0x00, 0x01, // 0X1DF = 480-1 0X13F = 320-1 |
| 164 | 0xdf, 0xFF, 0xFF, 0xFF, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 165 | }; |
| 166 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 167 | static const unsigned char toshiba_panel_set_hor_addr_2B_wvga[12] = { |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 168 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 169 | 0x05, 0x00, 0x39, 0xC0, // 1 last packet |
| 170 | // 0x2B, 0x00, 0x08, 0x00,//0X355 = 854-1; 0X1DF = 480-1 |
| 171 | // 0x6b, 0xFF, 0xFF, 0xFF, |
| 172 | 0x2B, 0x00, 0x00, 0x03, // 0X355 = 854-1; 0X1DF = 480-1 |
| 173 | 0x55, 0xFF, 0xFF, 0xFF, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 174 | }; |
| 175 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 176 | static const unsigned char toshiba_panel_set_hor_addr_2A_wqvga[12] |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 177 | = { |
| 178 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 179 | 0x05, 0x00, 0x39, 0xC0, // 1 last packet |
| 180 | 0x2A, 0x00, 0x00, 0x00, // 0XEF = 240-1 |
| 181 | 0xef, 0xFF, 0xFF, 0xFF, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 182 | }; |
| 183 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 184 | static const unsigned char toshiba_panel_set_hor_addr_2B_wqvga[12] |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 185 | = { |
| 186 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 187 | 0x05, 0x00, 0x39, 0xC0, // 1 last packet |
| 188 | 0x2B, 0x00, 0x00, 0x01, // 0X1aa = 427-1; |
| 189 | 0xaa, 0xFF, 0xFF, 0xFF, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 190 | }; |
| 191 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 192 | static const unsigned char toshiba_panel_IFSEL[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 193 | 0x02, 0x00, 0x29, 0xc0, |
| 194 | 0x53, 0x01, 0xff, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 195 | }; |
| 196 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 197 | static const unsigned char toshiba_panel_IFSEL_cmd_mode[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 198 | 0x02, 0x00, 0x29, 0xc0, |
| 199 | 0x53, 0x00, 0xff, 0xff |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 200 | }; |
| 201 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 202 | static const unsigned char toshiba_panel_exit_sleep[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 203 | 0x11, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1 |
| 204 | // params |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 205 | }; |
| 206 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 207 | static const unsigned char toshiba_panel_display_on[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 208 | // 0x29, 0x00, 0x05, 0x80,//25 Reg 0x29 < Display On>; generic write 1 |
| 209 | // params |
| 210 | 0x29, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1 |
| 211 | // params |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 212 | }; |
| 213 | |
| 214 | //color mode off |
| 215 | static const unsigned char dsi_display_config_color_mode_off[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 216 | 0x00, 0x00, 0x02, 0x80, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 217 | }; |
| 218 | |
| 219 | //color mode on |
| 220 | static const unsigned char dsi_display_config_color_mode_on[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 221 | 0x00, 0x00, 0x12, 0x80, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 222 | }; |
| 223 | |
| 224 | //the end OF Tochiba Config- video mode |
| 225 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 226 | /* NOVATEK BLUE panel */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 227 | static char novatek_panel_sw_reset[4] = { 0x01, 0x00, 0x05, 0x00 }; /* DTYPE_DCS_WRITE */ |
| 228 | static char novatek_panel_enter_sleep[4] = { 0x10, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */ |
| 229 | static char novatek_panel_exit_sleep[4] = { 0x11, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */ |
| 230 | static char novatek_panel_display_off[4] = { 0x28, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */ |
| 231 | static char novatek_panel_display_on[4] = { 0x29, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */ |
| 232 | static char novatek_panel_max_packet[4] = { 0x04, 0x00, 0x37, 0x80 }; /* DTYPE_SET_MAX_PACKET */ |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 233 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 234 | static char novatek_panel_set_onelane[4] = { 0xae, 0x01, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */ |
| 235 | static char novatek_panel_rgb_888[4] = { 0x3A, 0x77, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */ |
| 236 | static char novatek_panel_set_twolane[4] = { 0xae, 0x03, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */ |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 237 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 238 | static char novatek_panel_manufacture_id[4] = { 0x04, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */ |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 239 | static char read_id_a1h_cmd[4] = { 0xA1, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 240 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 241 | /* commands by Novatke */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 242 | static char novatek_panel_f4[4] = { 0xf4, 0x55, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */ |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 243 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 244 | static char novatek_panel_8c[20] = { /* DTYPE_DCS_LWRITE */ |
| 245 | 0x10, 0x00, 0x39, 0xC0, 0x8C, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 246 | 0x00, 0x08, 0x08, 0x00, 0x30, 0xC0, 0xB7, 0x37 |
| 247 | }; |
| 248 | static char novatek_panel_ff[4] = { 0xff, 0x55, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */ |
| 249 | |
| 250 | static char novatek_panel_set_width[12] = { /* DTYPE_DCS_LWRITE */ |
| 251 | 0x05, 0x00, 0x39, 0xC0, //1 last packet |
| 252 | 0x2A, 0x00, 0x00, 0x02, //clmn:0 - 0x21B=539 |
| 253 | 0x1B, 0xFF, 0xFF, 0xFF |
| 254 | }; /* 540 - 1 */ |
| 255 | |
| 256 | static char novatek_panel_set_height[12] = { /* DTYPE_DCS_LWRITE */ |
| 257 | 0x05, 0x00, 0x39, 0xC0, //1 last packet |
| 258 | 0x2B, 0x00, 0x00, 0x03, //row:0 - 0x3BF=959 |
| 259 | 0xBF, 0xFF, 0xFF, 0xFF, |
| 260 | }; /* 960 - 1 */ |
Chandan Uddaraju | d25b3a4 | 2011-07-14 13:02:32 -0700 | [diff] [blame] | 261 | |
| 262 | /* Commands to control Backlight */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 263 | static char novatek_panel_set_led_pwm1[8] = { /* DTYPE_DCS_LWRITE */ |
| 264 | 0x02, 0x00, 0x39, 0xC0, //1 last packet |
| 265 | 0x51, 0xFA, 0xFF, 0xFF, // Brightness level set to 0xFA -> 250 |
Chandan Uddaraju | d25b3a4 | 2011-07-14 13:02:32 -0700 | [diff] [blame] | 266 | }; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 267 | |
| 268 | static char novatek_panel_set_led_pwm2[8] = { /* DTYPE_DCS_LWRITE */ |
| 269 | 0x02, 0x00, 0x39, 0xC0, |
| 270 | 0x53, 0x24, 0xFF, 0xFF, |
Chandan Uddaraju | d25b3a4 | 2011-07-14 13:02:32 -0700 | [diff] [blame] | 271 | }; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 272 | |
| 273 | static char novatek_panel_set_led_pwm3[8] = { /* DTYPE_DCS_LWRITE */ |
| 274 | 0x02, 0x00, 0x39, 0xC0, |
| 275 | 0x55, 0x00, 0xFF, 0xFF, |
Chandan Uddaraju | d25b3a4 | 2011-07-14 13:02:32 -0700 | [diff] [blame] | 276 | }; |
| 277 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 278 | /* End of Novatek Blue panel commands */ |
| 279 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 280 | /* Toshiba mdt61 panel cmds */ |
| 281 | static const unsigned char toshiba_mdt61_mcap_start[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 282 | 0xB0, 0x04, DTYPE_GEN_WRITE2, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 283 | }; |
| 284 | |
| 285 | static const unsigned char toshiba_mdt61_num_out_pixelform[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 286 | 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 287 | 0xB3, 0x00, 0x87, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 288 | }; |
| 289 | |
| 290 | static const unsigned char toshiba_mdt61_dsi_ctrl[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 291 | 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 292 | 0xB6, 0x30, 0x83, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 293 | }; |
| 294 | |
| 295 | static const unsigned char toshiba_mdt61_panel_driving[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 296 | 0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 297 | 0xC0, 0x01, 0x00, 0x85, |
| 298 | 0x00, 0x00, 0x00, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 299 | }; |
| 300 | |
| 301 | static const unsigned char toshiba_mdt61_dispV_timing[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 302 | 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 303 | 0xC1, 0x00, 0x10, 0x00, |
| 304 | 0x01, 0xFF, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 305 | }; |
| 306 | |
| 307 | static const unsigned char toshiba_mdt61_dispCtrl[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 308 | 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 309 | 0xC3, 0x00, 0x19, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 310 | }; |
| 311 | |
| 312 | static const unsigned char toshiba_mdt61_test_mode_c4[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 313 | 0xC4, 0x03, DTYPE_GEN_WRITE2, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 314 | }; |
| 315 | |
| 316 | static const unsigned char toshiba_mdt61_dispH_timing[20] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 317 | 0x0F, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 318 | 0xC5, 0x00, 0x01, 0x05, |
| 319 | 0x04, 0x5E, 0x00, 0x00, |
| 320 | 0x00, 0x00, 0x0B, 0x17, |
| 321 | 0x05, 0x00, 0x00, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 322 | }; |
| 323 | |
| 324 | static const unsigned char toshiba_mdt61_test_mode_c6[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 325 | 0xC6, 0x00, DTYPE_GEN_WRITE2, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 326 | }; |
| 327 | |
| 328 | static const unsigned char toshiba_mdt61_gamma_setA[20] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 329 | 0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 330 | 0xC8, 0x0A, 0x15, 0x18, |
| 331 | 0x1B, 0x1C, 0x0D, 0x00, |
| 332 | 0x00, 0x00, 0x00, 0x00, |
| 333 | 0x00, 0xFF, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 334 | }; |
| 335 | |
| 336 | static const unsigned char toshiba_mdt61_gamma_setB[20] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 337 | 0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 338 | 0xC9, 0x0D, 0x1D, 0x1F, |
| 339 | 0x1F, 0x1F, 0x10, 0x00, |
| 340 | 0x00, 0x00, 0x00, 0x00, |
| 341 | 0x00, 0xFF, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 342 | }; |
| 343 | |
| 344 | static const unsigned char toshiba_mdt61_gamma_setC[20] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 345 | 0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 346 | 0xCA, 0x1E, 0x1F, 0x1E, |
| 347 | 0x1D, 0x1D, 0x10, 0x00, |
| 348 | 0x00, 0x00, 0x00, 0x00, |
| 349 | 0x00, 0xFF, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 350 | }; |
| 351 | |
| 352 | static const unsigned char toshiba_mdt61_powerSet_ChrgPmp[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 353 | 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 354 | 0xD0, 0x02, 0x00, 0xA3, |
| 355 | 0xB8, 0xFF, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 356 | }; |
| 357 | |
| 358 | static const unsigned char toshiba_mdt61_testMode_d1[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 359 | 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 360 | 0xD1, 0x10, 0x14, 0x53, |
| 361 | 0x64, 0x00, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 362 | }; |
| 363 | |
| 364 | static const unsigned char toshiba_mdt61_powerSet_SrcAmp[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 365 | 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 366 | 0xD2, 0xB3, 0x00, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 367 | }; |
| 368 | |
| 369 | static const unsigned char toshiba_mdt61_powerInt_PS[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 370 | 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 371 | 0xD3, 0x33, 0x03, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 372 | }; |
| 373 | |
| 374 | static const unsigned char toshiba_mdt61_vreg[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 375 | 0xD5, 0x00, DTYPE_GEN_WRITE2, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 376 | }; |
| 377 | |
| 378 | static const unsigned char toshiba_mdt61_test_mode_d6[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 379 | 0xD6, 0x01, DTYPE_GEN_WRITE2, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 380 | }; |
| 381 | |
| 382 | static const unsigned char toshiba_mdt61_timingCtrl_d7[16] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 383 | 0x09, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 384 | 0xD7, 0x09, 0x00, 0x84, |
| 385 | 0x81, 0x61, 0xBC, 0xB5, |
| 386 | 0x05, 0xFF, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 387 | }; |
| 388 | |
| 389 | static const unsigned char toshiba_mdt61_timingCtrl_d8[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 390 | 0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 391 | 0xD8, 0x04, 0x25, 0x90, |
| 392 | 0x4C, 0x92, 0x00, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 393 | }; |
| 394 | |
| 395 | static const unsigned char toshiba_mdt61_timingCtrl_d9[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 396 | 0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 397 | 0xD9, 0x5B, 0x7F, 0x05 |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 398 | }; |
| 399 | |
| 400 | static const unsigned char toshiba_mdt61_white_balance[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 401 | 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 402 | 0xCB, 0x00, 0x00, 0x00, |
| 403 | 0x1C, 0x00, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 404 | }; |
| 405 | |
| 406 | static const unsigned char toshiba_mdt61_vcs_settings[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 407 | 0xDD, 0x53, DTYPE_GEN_WRITE2, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 408 | }; |
| 409 | |
| 410 | static const unsigned char toshiba_mdt61_vcom_dc_settings[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 411 | 0xDE, 0x43, DTYPE_GEN_WRITE2, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 412 | }; |
| 413 | |
| 414 | static const unsigned char toshiba_mdt61_testMode_e3[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 415 | 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 416 | 0xE3, 0x00, 0x00, 0x00, |
| 417 | 0x00, 0xFF, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 418 | }; |
| 419 | |
| 420 | static const unsigned char toshiba_mdt61_testMode_e4[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 421 | 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 422 | 0xE4, 0x00, 0x00, 0x22, |
| 423 | 0xAA, 0x00, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 424 | }; |
| 425 | |
| 426 | static const unsigned char toshiba_mdt61_testMode_e5[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 427 | 0xE5, 0x00, DTYPE_GEN_WRITE2, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 428 | }; |
| 429 | |
| 430 | static const unsigned char toshiba_mdt61_testMode_fa[8] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 431 | 0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 432 | 0xFA, 0x00, 0x00, 0x00 |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 433 | }; |
| 434 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 435 | static const unsigned char toshiba_mdt61_testMode_fd[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 436 | 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 437 | 0xFD, 0x00, 0x00, 0x00, |
| 438 | 0x00, 0xFF, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 439 | }; |
| 440 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 441 | static const unsigned char toshiba_mdt61_testMode_fe[12] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 442 | 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 443 | 0xFE, 0x00, 0x00, 0x00, |
| 444 | 0x00, 0xFF, 0xFF, 0xFF |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 445 | }; |
| 446 | |
| 447 | static const unsigned char toshiba_mdt61_mcap_end[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 448 | 0xB0, 0x03, DTYPE_GEN_WRITE2, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 449 | }; |
| 450 | |
| 451 | static const unsigned char toshiba_mdt61_set_add_mode[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 452 | 0x36, 0x00, DTYPE_DCS_WRITE1, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 453 | }; |
| 454 | |
| 455 | static const unsigned char toshiba_mdt61_set_pixel_format[4] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 456 | 0x3A, 0x70, DTYPE_DCS_WRITE1, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 457 | }; |
| 458 | |
| 459 | /* Done Toshiba MDT61 Panel Commands */ |
| 460 | /* Toshiba MDT61 (R69320) End */ |
| 461 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 462 | /* Toshiba MDV24 panel commands */ |
| 463 | static const unsigned char toshiba_mdv24_mcap[4] = { |
| 464 | 0xB0, 0x00, DTYPE_GEN_WRITE2, 0x80, |
| 465 | }; |
| 466 | |
| 467 | static const unsigned char toshiba_mdv24_acr[4] = { |
| 468 | 0xB2, 0x00, DTYPE_GEN_WRITE2, 0x80, |
| 469 | }; |
| 470 | |
| 471 | static const unsigned char toshiba_mdv24_intf[4] = { |
| 472 | 0xB3, 0x0c, DTYPE_GEN_WRITE2, 0x80, |
| 473 | }; |
| 474 | |
| 475 | static const unsigned char toshiba_mdv24_pixel[4] = { |
| 476 | 0xB4, 0x02, DTYPE_GEN_WRITE2, 0x80, |
| 477 | }; |
| 478 | |
| 479 | static const unsigned char toshiba_mdv24_drive_setting[12] = { |
| 480 | 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 481 | 0xC0, 0x40, 0x02, 0x7F, |
| 482 | 0xC8, 0x08, 0xFF, 0xFF |
| 483 | }; |
| 484 | |
| 485 | static const unsigned char toshiba_mdv24_display_h_timing[20] = { |
| 486 | 0x10, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 487 | 0xC1, 0x00, 0xA8, 0x00, |
| 488 | 0x00, 0x00, 0x00, 0x00, |
Chandan Uddaraju | 2706561 | 2013-02-08 17:05:24 -0800 | [diff] [blame] | 489 | 0x9D, 0x08, 0x27, 0x00, |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 490 | 0x00, 0x00, 0x00, 0x00 |
| 491 | }; |
| 492 | |
| 493 | static const unsigned char toshiba_mdv24_source_output[12] = { |
| 494 | 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 495 | 0xC2, 0x00, 0x00, 0x09, |
| 496 | 0x00, 0x00, 0xFF, 0xFF |
| 497 | }; |
| 498 | |
| 499 | static const unsigned char toshiba_mdv24_gate_control[4] = { |
| 500 | 0xC3, 0x04, DTYPE_GEN_WRITE2, 0x80, |
| 501 | }; |
| 502 | |
| 503 | static const unsigned char toshiba_mdv24_ltps_control_c4[8] = { |
| 504 | 0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 505 | 0xC4, 0x4d, 0x83, 0x00 |
| 506 | }; |
| 507 | |
| 508 | static const unsigned char toshiba_mdv24_source_output_mode[16] = { |
| 509 | 0x0B, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 510 | 0xC6, 0x12, 0x00, 0x08, |
| 511 | 0x71, 0x00, 0x00, 0x00, |
| 512 | 0x80, 0x00, 0x04, 0xFF |
| 513 | }; |
| 514 | |
| 515 | static const unsigned char toshiba_mdv24_ltps_control_c7[4] = { |
| 516 | 0xC7, 0x22, DTYPE_GEN_WRITE2, 0x80, |
| 517 | }; |
| 518 | |
| 519 | static const unsigned char toshiba_mdv24_gamma_ctrl[12] = { |
| 520 | 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 521 | 0xC8, 0x4C, 0x0C, 0x0C, |
| 522 | 0x0C, 0xFF, 0xFF, 0xFF |
| 523 | }; |
| 524 | |
| 525 | static const unsigned char toshiba_mdv24_gamma_ctrl_a_pos[20] = { |
| 526 | 0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 527 | 0xC9, 0x00, 0x40, 0x00, |
| 528 | 0x16, 0x32, 0x2E, 0x3A, |
| 529 | 0x43, 0x3E, 0x3C, 0x45, |
| 530 | 0x79, 0x3F, 0xFF, 0xFF |
| 531 | }; |
| 532 | |
| 533 | static const unsigned char toshiba_mdv24_gamma_ctrl_a_neg[20] = { |
| 534 | 0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 535 | 0xCA, 0x00, 0x46, 0x1A, |
| 536 | 0x23, 0x21, 0x1C, 0x25, |
| 537 | 0x31, 0x2D, 0x49, 0x5F, |
| 538 | 0x7F, 0x3F, 0xFF, 0xFF |
| 539 | }; |
| 540 | |
| 541 | static const unsigned char toshiba_mdv24_gamma_ctrl_b_pos[20] = { |
| 542 | 0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 543 | 0xCb, 0x00, 0x4c, 0x20, |
| 544 | 0x3A, 0x42, 0x40, 0x47, |
| 545 | 0x4B, 0x42, 0x3E, 0x46, |
| 546 | 0x7E, 0x3F, 0xFF, 0xFF |
| 547 | }; |
| 548 | |
| 549 | static const unsigned char toshiba_mdv24_gamma_ctrl_b_neg[20] = { |
| 550 | 0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 551 | 0xCC, 0x00, 0x41, 0x19, |
| 552 | 0x21, 0x1D, 0x14, 0x18, |
| 553 | 0x1F, 0x1D, 0x25, 0x3F, |
| 554 | 0x73, 0x3F, 0xFF, 0xFF |
| 555 | }; |
| 556 | |
| 557 | static const unsigned char toshiba_mdv24_gamma_ctrl_c_pos[20] = { |
| 558 | 0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 559 | 0xCD, 0x23, 0x79, 0x5A, |
| 560 | 0x5F, 0x57, 0x4C, 0x51, |
| 561 | 0x51, 0x45, 0x3F, 0x4B, |
| 562 | 0x7F, 0x3F, 0xFF, 0xFF |
| 563 | }; |
| 564 | |
| 565 | static const unsigned char toshiba_mdv24_gamma_ctrl_c_neg[20] = { |
| 566 | 0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 567 | 0xCE, 0x00, 0x40, 0x14, |
| 568 | 0x20, 0x1A, 0x0E, 0x0E, |
| 569 | 0x13, 0x08, 0x00, 0x05, |
| 570 | 0x46, 0x1C, 0xFF, 0xFF |
| 571 | }; |
| 572 | |
| 573 | static const unsigned char toshiba_mdv24_pwr_setting1[8] = { |
| 574 | 0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 575 | 0xD0, 0x6A, 0x64, 0x01 |
| 576 | }; |
| 577 | |
| 578 | static const unsigned char toshiba_mdv24_pwr_setting2[8] = { |
| 579 | 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 580 | 0xD1, 0x77, 0xd4, 0xFF |
| 581 | }; |
| 582 | |
| 583 | static const unsigned char toshiba_mdv24_pwr_setting_internal[4] = { |
| 584 | 0xD3, 0x33, DTYPE_GEN_WRITE2, 0x80, |
| 585 | }; |
| 586 | |
| 587 | static const unsigned char toshiba_mdv24_lvl_setting[8] = { |
| 588 | 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 589 | 0xD5, 0x0F, 0x0F, 0xFF |
| 590 | }; |
| 591 | |
| 592 | static const unsigned char toshiba_mdv24_vcomdc_setting1[12] = { |
| 593 | 0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 594 | 0xD8, 0x34, 0x64, 0x23, |
| 595 | 0x25, 0x62, 0x32, 0xFF |
| 596 | }; |
| 597 | |
| 598 | static const unsigned char toshiba_mdv24_vcomdc_setting2[16] = { |
| 599 | 0x0C, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 600 | 0xDE, 0x10, 0x7B, 0x11, |
| 601 | 0x0A, 0x00, 0x00, 0x00, |
| 602 | 0x00, 0x00, 0x00, 0x00 |
| 603 | }; |
| 604 | |
| 605 | static const unsigned char toshiba_mdv24_init_fd[16] = { |
| 606 | 0x09, 0x00, DTYPE_GEN_LWRITE, 0xC0, |
| 607 | 0xFD, 0x04, 0x55, 0x53, |
| 608 | 0x00, 0x70, 0xFF, 0x10, |
| 609 | 0x73, 0xFF, 0xFF, 0xFF |
| 610 | }; |
| 611 | |
| 612 | static const unsigned char toshiba_mdv24_nvm_load_ctrl[4] = { |
| 613 | 0xE2, 0x00, DTYPE_GEN_WRITE2, 0x80, |
| 614 | }; |
| 615 | |
| 616 | /* End of Toshiba MDV24 commands */ |
| 617 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 618 | static const unsigned char dsi_display_exit_sleep[4] = { |
| 619 | 0x11, 0x00, 0x15, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 620 | }; |
| 621 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 622 | static const unsigned char dsi_display_display_on[4] = { |
| 623 | 0x29, 0x00, 0x15, 0x80, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 624 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 625 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 626 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 627 | #define MIPI_VIDEO_MODE 1 |
| 628 | #define MIPI_CMD_MODE 2 |
| 629 | |
| 630 | struct mipi_dsi_phy_ctrl { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 631 | uint32_t regulator[5]; |
| 632 | uint32_t timing[12]; |
| 633 | uint32_t ctrl[4]; |
| 634 | uint32_t strength[4]; |
| 635 | uint32_t pll[21]; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 636 | }; |
| 637 | |
Mao Flynn | 5f137ed | 2014-04-18 14:59:47 +0800 | [diff] [blame] | 638 | enum dsi_reg_mode { |
| 639 | DSI_PHY_REGULATOR_DCDC_MODE, |
| 640 | DSI_PHY_REGULATOR_LDO_MODE, |
| 641 | }; |
| 642 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 643 | struct mdss_dsi_phy_ctrl { |
| 644 | uint32_t regulator[7]; |
| 645 | uint32_t timing[12]; |
| 646 | uint32_t ctrl[4]; |
| 647 | uint32_t strength[2]; |
| 648 | char bistCtrl[6]; |
| 649 | char laneCfg[45]; |
Mao Flynn | 5f137ed | 2014-04-18 14:59:47 +0800 | [diff] [blame] | 650 | enum dsi_reg_mode regulator_mode; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 651 | }; |
| 652 | |
Arpita Banerjee | 2522bc6 | 2013-05-24 16:03:53 -0700 | [diff] [blame] | 653 | typedef struct mdss_dsi_pll_config { |
| 654 | uint32_t pixel_clock; |
| 655 | uint32_t pixel_clock_mhz; |
| 656 | uint32_t byte_clock; |
| 657 | uint32_t bit_clock; |
| 658 | uint32_t halfbit_clock; |
| 659 | uint32_t vco_clock; |
| 660 | uint8_t directpath; |
| 661 | uint8_t posdiv1; |
| 662 | uint8_t posdiv3; |
| 663 | uint8_t pclk_m; |
| 664 | uint8_t pclk_n; |
| 665 | uint8_t pclk_d; |
| 666 | }; |
| 667 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 668 | struct mipi_dsi_cmd { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 669 | int size; |
| 670 | char *payload; |
Sangani Suryanarayana Raju | 769f9ac | 2013-04-30 19:05:06 +0530 | [diff] [blame] | 671 | int wait; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 672 | }; |
| 673 | |
| 674 | struct mipi_dsi_panel_config { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 675 | char mode; |
| 676 | char num_of_lanes; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 677 | char lane_swap; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 678 | char pack; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 679 | uint8_t t_clk_pre; |
| 680 | uint8_t t_clk_post; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 681 | struct mipi_dsi_phy_ctrl *dsi_phy_config; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 682 | struct mdss_dsi_phy_ctrl *mdss_dsi_phy_config; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 683 | struct mipi_dsi_cmd *panel_cmds; |
| 684 | int num_of_panel_cmds; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 685 | uint32_t signature; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 686 | }; |
| 687 | |
| 688 | static struct mipi_dsi_cmd toshiba_panel_video_mode_cmds[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 689 | {sizeof(toshiba_panel_mcap_off), (char *)toshiba_panel_mcap_off}, |
| 690 | {sizeof(toshiba_panel_ena_test_reg), |
| 691 | (char *)toshiba_panel_ena_test_reg}, |
| 692 | {sizeof(toshiba_panel_num_of_1lane), |
| 693 | (char *)toshiba_panel_num_of_1lane}, |
| 694 | {sizeof(toshiba_panel_non_burst_sync_pulse), |
| 695 | (char *)toshiba_panel_non_burst_sync_pulse}, |
| 696 | {sizeof(toshiba_panel_set_DMODE_WVGA), |
| 697 | (char *)toshiba_panel_set_DMODE_WVGA}, |
| 698 | {sizeof(toshiba_panel_set_intern_WR_clk1_wvga), |
| 699 | (char *)toshiba_panel_set_intern_WR_clk1_wvga}, |
| 700 | {sizeof(toshiba_panel_set_intern_WR_clk2_wvga), |
| 701 | (char *)toshiba_panel_set_intern_WR_clk2_wvga}, |
| 702 | {sizeof(toshiba_panel_set_hor_addr_2A_wvga), |
| 703 | (char *)toshiba_panel_set_hor_addr_2A_wvga}, |
| 704 | {sizeof(toshiba_panel_set_hor_addr_2B_wvga), |
| 705 | (char *)toshiba_panel_set_hor_addr_2B_wvga}, |
| 706 | {sizeof(toshiba_panel_IFSEL), (char *)toshiba_panel_IFSEL}, |
| 707 | {sizeof(toshiba_panel_exit_sleep), (char *)toshiba_panel_exit_sleep}, |
| 708 | {sizeof(toshiba_panel_display_on), (char *)toshiba_panel_display_on}, |
| 709 | {sizeof(dsi_display_config_color_mode_on), |
| 710 | (char *)dsi_display_config_color_mode_on}, |
| 711 | {sizeof(dsi_display_config_color_mode_off), |
| 712 | (char *)dsi_display_config_color_mode_off}, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 713 | }; |
| 714 | |
| 715 | static struct mipi_dsi_phy_ctrl mipi_dsi_toshiba_panel_phy_ctrl = { |
| 716 | /* 480*854, RGB888, 1 Lane 60 fps video mode */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 717 | {0x03, 0x01, 0x01, 0x00}, /* regulator */ |
| 718 | /* timing */ |
| 719 | {0x50, 0x0f, 0x14, 0x19, 0x23, 0x0e, 0x12, 0x16, |
| 720 | 0x1b, 0x1c, 0x04}, |
| 721 | {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */ |
| 722 | {0xee, 0x03, 0x86, 0x03}, /* strength */ |
| 723 | /* pll control */ |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 724 | |
| 725 | #if defined(DSI_BIT_CLK_366MHZ) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 726 | {0x41, 0xdb, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63, |
| 727 | 0x31, 0x0f, 0x07, |
| 728 | 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03}, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 729 | #elif defined(DSI_BIT_CLK_380MHZ) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 730 | {0x41, 0xf7, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63, |
| 731 | 0x31, 0x0f, 0x07, |
| 732 | 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03}, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 733 | #elif defined(DSI_BIT_CLK_400MHZ) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 734 | {0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63, |
| 735 | 0x31, 0x0f, 0x07, |
| 736 | 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03}, |
| 737 | #else /* 200 mhz */ |
| 738 | {0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63, |
| 739 | 0x33, 0x1f, 0x1f /* for 1 lane ; 0x0f for 2 lanes */ , |
| 740 | 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03}, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 741 | #endif |
| 742 | }; |
| 743 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 744 | static struct mipi_dsi_cmd toshiba_mdt61_video_mode_cmds[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 745 | {sizeof(toshiba_mdt61_mcap_start), (char *)toshiba_mdt61_mcap_start}, |
| 746 | {sizeof(toshiba_mdt61_num_out_pixelform), |
| 747 | (char *)toshiba_mdt61_num_out_pixelform}, |
| 748 | {sizeof(toshiba_mdt61_dsi_ctrl), (char *)toshiba_mdt61_dsi_ctrl}, |
| 749 | {sizeof(toshiba_mdt61_panel_driving), |
| 750 | (char *)toshiba_mdt61_panel_driving}, |
| 751 | {sizeof(toshiba_mdt61_dispV_timing), |
| 752 | (char *)toshiba_mdt61_dispV_timing}, |
| 753 | {sizeof(toshiba_mdt61_dispCtrl), (char *)toshiba_mdt61_dispCtrl}, |
| 754 | {sizeof(toshiba_mdt61_test_mode_c4), |
| 755 | (char *)toshiba_mdt61_test_mode_c4}, |
| 756 | {sizeof(toshiba_mdt61_dispH_timing), |
| 757 | (char *)toshiba_mdt61_dispH_timing}, |
| 758 | {sizeof(toshiba_mdt61_test_mode_c6), |
| 759 | (char *)toshiba_mdt61_test_mode_c6}, |
| 760 | {sizeof(toshiba_mdt61_gamma_setA), (char *)toshiba_mdt61_gamma_setA}, |
| 761 | {sizeof(toshiba_mdt61_gamma_setB), (char *)toshiba_mdt61_gamma_setB}, |
| 762 | {sizeof(toshiba_mdt61_gamma_setC), (char *)toshiba_mdt61_gamma_setC}, |
| 763 | {sizeof(toshiba_mdt61_powerSet_ChrgPmp), |
| 764 | (char *)toshiba_mdt61_powerSet_ChrgPmp}, |
| 765 | {sizeof(toshiba_mdt61_testMode_d1), (char *)toshiba_mdt61_testMode_d1}, |
| 766 | {sizeof(toshiba_mdt61_powerSet_SrcAmp), |
| 767 | (char *)toshiba_mdt61_powerSet_SrcAmp}, |
| 768 | {sizeof(toshiba_mdt61_powerInt_PS), (char *)toshiba_mdt61_powerInt_PS}, |
| 769 | {sizeof(toshiba_mdt61_vreg), (char *)toshiba_mdt61_vreg}, |
| 770 | {sizeof(toshiba_mdt61_test_mode_d6), |
| 771 | (char *)toshiba_mdt61_test_mode_d6}, |
| 772 | {sizeof(toshiba_mdt61_timingCtrl_d7), |
| 773 | (char *)toshiba_mdt61_timingCtrl_d7}, |
| 774 | {sizeof(toshiba_mdt61_timingCtrl_d8), |
| 775 | (char *)toshiba_mdt61_timingCtrl_d8}, |
| 776 | {sizeof(toshiba_mdt61_timingCtrl_d9), |
| 777 | (char *)toshiba_mdt61_timingCtrl_d9}, |
| 778 | {sizeof(toshiba_mdt61_white_balance), |
| 779 | (char *)toshiba_mdt61_white_balance}, |
| 780 | {sizeof(toshiba_mdt61_vcs_settings), |
| 781 | (char *)toshiba_mdt61_vcs_settings}, |
| 782 | {sizeof(toshiba_mdt61_vcom_dc_settings), |
| 783 | (char *)toshiba_mdt61_vcom_dc_settings}, |
| 784 | {sizeof(toshiba_mdt61_testMode_e3), (char *)toshiba_mdt61_testMode_e3}, |
| 785 | {sizeof(toshiba_mdt61_testMode_e4), (char *)toshiba_mdt61_testMode_e4}, |
| 786 | {sizeof(toshiba_mdt61_testMode_e5), (char *)toshiba_mdt61_testMode_e5}, |
| 787 | {sizeof(toshiba_mdt61_testMode_fa), (char *)toshiba_mdt61_testMode_fa}, |
| 788 | {sizeof(toshiba_mdt61_testMode_fd), (char *)toshiba_mdt61_testMode_fd}, |
| 789 | {sizeof(toshiba_mdt61_testMode_fe), (char *)toshiba_mdt61_testMode_fe}, |
| 790 | {sizeof(toshiba_mdt61_mcap_end), (char *)toshiba_mdt61_mcap_end}, |
| 791 | {sizeof(toshiba_mdt61_set_add_mode), |
| 792 | (char *)toshiba_mdt61_set_add_mode}, |
| 793 | {sizeof(toshiba_mdt61_set_pixel_format), |
| 794 | (char *)toshiba_mdt61_set_pixel_format}, |
| 795 | {sizeof(dsi_display_exit_sleep), (char *)dsi_display_exit_sleep}, |
| 796 | {sizeof(dsi_display_display_on), (char *)dsi_display_display_on}, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 797 | }; |
| 798 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 799 | static struct mipi_dsi_cmd toshiba_mdv24_video_mode_cmds[] = { |
| 800 | {sizeof(toshiba_mdv24_mcap), (char *)toshiba_mdv24_mcap}, |
| 801 | {sizeof(toshiba_mdv24_acr), |
| 802 | (char *)toshiba_mdv24_acr}, |
| 803 | {sizeof(toshiba_mdv24_intf), (char *)toshiba_mdv24_intf}, |
| 804 | {sizeof(toshiba_mdv24_pixel), (char *)toshiba_mdv24_pixel}, |
| 805 | {sizeof(toshiba_mdv24_drive_setting), |
| 806 | (char *)toshiba_mdv24_drive_setting}, |
| 807 | {sizeof(toshiba_mdv24_display_h_timing), |
| 808 | (char *)toshiba_mdv24_display_h_timing}, |
| 809 | {sizeof(toshiba_mdv24_source_output), |
| 810 | (char *)toshiba_mdv24_source_output}, |
| 811 | {sizeof(toshiba_mdv24_gate_control), |
| 812 | (char *)toshiba_mdv24_gate_control}, |
| 813 | {sizeof(toshiba_mdv24_ltps_control_c4), |
| 814 | (char *)toshiba_mdv24_ltps_control_c4}, |
| 815 | {sizeof(toshiba_mdv24_source_output_mode), |
| 816 | (char *)toshiba_mdv24_source_output_mode}, |
| 817 | {sizeof(toshiba_mdv24_ltps_control_c7), |
| 818 | (char *)toshiba_mdv24_ltps_control_c7}, |
| 819 | {sizeof(toshiba_mdv24_gamma_ctrl), |
| 820 | (char *)toshiba_mdv24_gamma_ctrl}, |
| 821 | {sizeof(toshiba_mdv24_gamma_ctrl_a_pos), |
| 822 | (char *)toshiba_mdv24_gamma_ctrl_a_pos}, |
| 823 | {sizeof(toshiba_mdv24_gamma_ctrl_a_neg), |
| 824 | (char *)toshiba_mdv24_gamma_ctrl_a_neg}, |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 825 | {sizeof(toshiba_mdv24_gamma_ctrl_b_pos), |
| 826 | (char *)toshiba_mdv24_gamma_ctrl_b_pos}, |
Chandan Uddaraju | 2706561 | 2013-02-08 17:05:24 -0800 | [diff] [blame] | 827 | {sizeof(toshiba_mdv24_gamma_ctrl_b_neg), |
| 828 | (char *)toshiba_mdv24_gamma_ctrl_b_neg}, |
| 829 | {sizeof(toshiba_mdv24_gamma_ctrl_c_pos), |
| 830 | (char *)toshiba_mdv24_gamma_ctrl_c_pos}, |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 831 | {sizeof(toshiba_mdv24_gamma_ctrl_c_neg), |
| 832 | (char *)toshiba_mdv24_gamma_ctrl_c_neg}, |
| 833 | {sizeof(toshiba_mdv24_pwr_setting1), |
| 834 | (char *)toshiba_mdv24_pwr_setting1}, |
| 835 | {sizeof(toshiba_mdv24_pwr_setting2), |
| 836 | (char *)toshiba_mdv24_pwr_setting2}, |
| 837 | {sizeof(toshiba_mdv24_pwr_setting_internal), |
| 838 | (char *)toshiba_mdv24_pwr_setting_internal}, |
| 839 | {sizeof(toshiba_mdv24_lvl_setting), |
| 840 | (char *)toshiba_mdv24_lvl_setting}, |
| 841 | {sizeof(toshiba_mdv24_vcomdc_setting1), |
| 842 | (char *)toshiba_mdv24_vcomdc_setting1}, |
| 843 | {sizeof(toshiba_mdv24_vcomdc_setting2), |
| 844 | (char *)toshiba_mdv24_vcomdc_setting2}, |
| 845 | {sizeof(toshiba_mdv24_init_fd), |
| 846 | (char *)toshiba_mdv24_init_fd}, |
| 847 | {sizeof(toshiba_mdv24_nvm_load_ctrl), |
| 848 | (char *)toshiba_mdv24_nvm_load_ctrl}, |
| 849 | {sizeof(dsi_display_exit_sleep), (char *)dsi_display_exit_sleep}, |
| 850 | {sizeof(dsi_display_display_on), (char *)dsi_display_display_on}, |
| 851 | }; |
| 852 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 853 | static struct mipi_dsi_phy_ctrl mipi_dsi_toshiba_mdt61_panel_phy_ctrl = { |
| 854 | /* 600*1024, RGB888, 3 Lane 55 fps video mode */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 855 | {0x03, 0x0a, 0x04, 0x00, 0x20}, |
| 856 | /* timing */ |
| 857 | {0xab, 0x8a, 0x18, 0x00, 0x92, 0x97, 0x1b, 0x8c, |
| 858 | 0x0c, 0x03, 0x04, 0xa0}, |
| 859 | {0x5f, 0x00, 0x00, 0x10}, /* phy ctrl */ |
| 860 | {0xff, 0x00, 0x06, 0x00}, /* strength */ |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 861 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 862 | /* pll control 1- 19 */ |
| 863 | {0x01, 0x7f, 0x31, 0xda, 0x00, 0x40, 0x03, 0x62, |
| 864 | 0x41, 0x0f, 0x01, |
| 865 | 0x00, 0x1a, 0x00, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01, 0x00}, |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 866 | }; |
| 867 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 868 | static struct mipi_dsi_cmd novatek_panel_manufacture_id_cmd = |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 869 | { sizeof(novatek_panel_manufacture_id), novatek_panel_manufacture_id }; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 870 | |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 871 | static struct mipi_dsi_cmd read_ddb_start_cmd = |
| 872 | {sizeof(read_id_a1h_cmd), read_id_a1h_cmd}; |
| 873 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 874 | static struct mipi_dsi_cmd novatek_panel_cmd_mode_cmds[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 875 | {sizeof(novatek_panel_sw_reset), novatek_panel_sw_reset} |
| 876 | , |
| 877 | {sizeof(novatek_panel_exit_sleep), novatek_panel_exit_sleep} |
| 878 | , |
| 879 | {sizeof(novatek_panel_display_on), novatek_panel_display_on} |
| 880 | , |
| 881 | {sizeof(novatek_panel_max_packet), novatek_panel_max_packet} |
| 882 | , |
| 883 | {sizeof(novatek_panel_f4), novatek_panel_f4} |
| 884 | , |
| 885 | {sizeof(novatek_panel_8c), novatek_panel_8c} |
| 886 | , |
| 887 | {sizeof(novatek_panel_ff), novatek_panel_ff} |
| 888 | , |
| 889 | {sizeof(novatek_panel_set_twolane), novatek_panel_set_twolane} |
| 890 | , |
| 891 | {sizeof(novatek_panel_set_width), novatek_panel_set_width} |
| 892 | , |
| 893 | {sizeof(novatek_panel_set_height), novatek_panel_set_height} |
| 894 | , |
| 895 | {sizeof(novatek_panel_rgb_888), novatek_panel_rgb_888} |
| 896 | , |
| 897 | {sizeof(novatek_panel_set_led_pwm1), novatek_panel_set_led_pwm1} |
| 898 | , |
| 899 | {sizeof(novatek_panel_set_led_pwm2), novatek_panel_set_led_pwm2} |
| 900 | , |
| 901 | {sizeof(novatek_panel_set_led_pwm3), novatek_panel_set_led_pwm3} |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 902 | }; |
| 903 | |
Asaf Penso | 2a5acb3 | 2013-05-02 22:20:20 +0300 | [diff] [blame] | 904 | static struct mipi_dsi_cmd sharp_qhd_video_mode_cmds[] = { |
| 905 | {sizeof(novatek_panel_sw_reset), novatek_panel_sw_reset} |
| 906 | , |
| 907 | {sizeof(novatek_panel_exit_sleep), novatek_panel_exit_sleep} |
| 908 | , |
| 909 | {sizeof(novatek_panel_display_on), novatek_panel_display_on} |
| 910 | , |
| 911 | {sizeof(novatek_panel_set_twolane), novatek_panel_set_twolane} |
| 912 | , |
| 913 | {sizeof(novatek_panel_rgb_888), novatek_panel_rgb_888} |
| 914 | , |
| 915 | {sizeof(novatek_panel_set_led_pwm1), novatek_panel_set_led_pwm1} |
| 916 | , |
| 917 | {sizeof(novatek_panel_set_led_pwm2), novatek_panel_set_led_pwm2} |
| 918 | , |
| 919 | {sizeof(novatek_panel_set_led_pwm3), novatek_panel_set_led_pwm3} |
| 920 | }; |
| 921 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 922 | static struct mipi_dsi_phy_ctrl mipi_dsi_novatek_panel_phy_ctrl = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 923 | /* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */ |
| 924 | {0x03, 0x01, 0x01, 0x00}, /* regulator */ |
| 925 | /* timing */ |
| 926 | {0x96, 0x26, 0x23, 0x00, 0x50, 0x4B, 0x1e, |
| 927 | 0x28, 0x28, 0x03, 0x04}, |
| 928 | {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */ |
| 929 | {0xee, 0x02, 0x86, 0x00}, /* strength */ |
| 930 | /* pll control */ |
| 931 | {0x40, 0xf9, 0xb0, 0xda, 0x00, 0x50, 0x48, 0x63, |
| 932 | /* 0x30, 0x07, 0x07, --> One lane configuration */ |
| 933 | 0x30, 0x07, 0x03, /* --> Two lane configuration */ |
| 934 | 0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0}, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 935 | }; |
| 936 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 937 | enum { /* mipi dsi panel */ |
| 938 | DSI_VIDEO_MODE, |
| 939 | DSI_CMD_MODE, |
| 940 | }; |
| 941 | #define DSI_NON_BURST_SYNCH_PULSE 0 |
| 942 | #define DSI_NON_BURST_SYNCH_EVENT 1 |
| 943 | #define DSI_BURST_MODE 2 |
| 944 | |
| 945 | #define DSI_RGB_SWAP_RGB 0 |
| 946 | #define DSI_RGB_SWAP_RBG 1 |
| 947 | #define DSI_RGB_SWAP_BGR 2 |
| 948 | #define DSI_RGB_SWAP_BRG 3 |
| 949 | #define DSI_RGB_SWAP_GRB 4 |
| 950 | #define DSI_RGB_SWAP_GBR 5 |
| 951 | |
| 952 | #define DSI_VIDEO_DST_FORMAT_RGB565 0 |
| 953 | #define DSI_VIDEO_DST_FORMAT_RGB666 1 |
| 954 | #define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2 |
| 955 | #define DSI_VIDEO_DST_FORMAT_RGB888 3 |
| 956 | |
| 957 | #define DSI_CMD_DST_FORMAT_RGB111 0 |
| 958 | #define DSI_CMD_DST_FORMAT_RGB332 3 |
| 959 | #define DSI_CMD_DST_FORMAT_RGB444 4 |
| 960 | #define DSI_CMD_DST_FORMAT_RGB565 6 |
| 961 | #define DSI_CMD_DST_FORMAT_RGB666 7 |
| 962 | #define DSI_CMD_DST_FORMAT_RGB888 8 |
| 963 | |
| 964 | #define DSI_CMD_TRIGGER_NONE 0x0 /* mdp trigger */ |
| 965 | #define DSI_CMD_TRIGGER_TE 0x02 |
| 966 | #define DSI_CMD_TRIGGER_SW 0x04 |
| 967 | #define DSI_CMD_TRIGGER_SW_SEOF 0x05 /* cmd dma only */ |
| 968 | #define DSI_CMD_TRIGGER_SW_TE 0x06 |
| 969 | |
Arpita Banerjee | f1a8ac9 | 2013-05-21 10:09:35 -0700 | [diff] [blame] | 970 | #define DSI_DATALANE_SWAP_0123 0 |
| 971 | #define DSI_DATALANE_SWAP_3012 1 |
| 972 | #define DSI_DATALANE_SWAP_2301 2 |
| 973 | #define DSI_DATALANE_SWAP_1230 3 |
| 974 | #define DSI_DATALANE_SWAP_0321 4 |
| 975 | #define DSI_DATALANE_SWAP_1032 5 |
| 976 | #define DSI_DATALANE_SWAP_2103 6 |
| 977 | #define DSI_DATALANE_SWAP_3210 7 |
| 978 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 979 | int mipi_config(struct msm_fb_panel_data *panel); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 980 | int mdss_dsi_config(struct msm_fb_panel_data *panel); |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 981 | int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, |
| 982 | uint32_t ctl_base, uint32_t phy_base); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 983 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 984 | int mdss_dsi_video_mode_config(uint16_t disp_width, |
| 985 | uint16_t disp_height, |
| 986 | uint16_t img_width, |
| 987 | uint16_t img_height, |
| 988 | uint16_t hsync_porch0_fp, |
| 989 | uint16_t hsync_porch0_bp, |
| 990 | uint16_t vsync_porch0_fp, |
| 991 | uint16_t vsync_porch0_bp, |
| 992 | uint16_t hsync_width, |
| 993 | uint16_t vsync_width, |
| 994 | uint16_t dst_format, |
| 995 | uint16_t traffic_mode, |
| 996 | uint8_t lane_en, |
| 997 | uint16_t low_pwr_stop_mode, |
| 998 | uint8_t eof_bllp_pwr, |
| 999 | uint8_t interleav, |
| 1000 | uint32_t ctl_base); |
| 1001 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1002 | int mipi_dsi_video_mode_config(unsigned short disp_width, |
| 1003 | unsigned short disp_height, |
| 1004 | unsigned short img_width, |
| 1005 | unsigned short img_height, |
| 1006 | unsigned short hsync_porch0_fp, |
| 1007 | unsigned short hsync_porch0_bp, |
| 1008 | unsigned short vsync_porch0_fp, |
| 1009 | unsigned short vsync_porch0_bp, |
| 1010 | unsigned short hsync_width, |
| 1011 | unsigned short vsync_width, |
| 1012 | unsigned short dst_format, |
| 1013 | unsigned short traffic_mode, |
| 1014 | unsigned char lane_en, |
| 1015 | unsigned low_pwr_stop_mode, |
| 1016 | unsigned char eof_bllp_pwr, |
| 1017 | unsigned char interleav); |
| 1018 | int mipi_dsi_on(); |
Siddhartha Agrawal | 24d81b5 | 2013-07-01 11:13:32 -0700 | [diff] [blame] | 1019 | int mipi_dsi_off(struct msm_panel_info *pinfo); |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 1020 | int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count); |
| 1021 | int mipi_dsi_cmds_rx(char **rp, int len); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 1022 | #endif |