Ajay Singh Parmar | 392f07a | 2014-11-19 15:06:19 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | #include <err.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 32 | #include <malloc.h> |
| 33 | #include <string.h> |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 34 | #include <msm_panel.h> |
| 35 | #include <platform/timer.h> |
| 36 | #include <platform/clock.h> |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 37 | #include "mdp5.h" |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 38 | #include <platform/iomap.h> |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 39 | #include "mdss_hdmi.h" |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame^] | 40 | #include <target/display.h> |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 41 | |
| 42 | static struct msm_fb_panel_data panel; |
| 43 | |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 44 | extern int msm_display_init(struct msm_fb_panel_data *pdata); |
| 45 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 46 | /* AVI INFOFRAME DATA */ |
| 47 | #define NUM_MODES_AVI 20 |
| 48 | #define AVI_MAX_DATA_BYTES 13 |
| 49 | |
| 50 | enum { |
| 51 | DATA_BYTE_1, |
| 52 | DATA_BYTE_2, |
| 53 | DATA_BYTE_3, |
| 54 | DATA_BYTE_4, |
| 55 | DATA_BYTE_5, |
| 56 | DATA_BYTE_6, |
| 57 | DATA_BYTE_7, |
| 58 | DATA_BYTE_8, |
| 59 | DATA_BYTE_9, |
| 60 | DATA_BYTE_10, |
| 61 | DATA_BYTE_11, |
| 62 | DATA_BYTE_12, |
| 63 | DATA_BYTE_13, |
| 64 | }; |
| 65 | |
| 66 | #define IFRAME_PACKET_OFFSET 0x80 |
| 67 | /* |
| 68 | * InfoFrame Type Code: |
| 69 | * 0x0 - Reserved |
| 70 | * 0x1 - Vendor Specific |
| 71 | * 0x2 - Auxiliary Video Information |
| 72 | * 0x3 - Source Product Description |
| 73 | * 0x4 - AUDIO |
| 74 | * 0x5 - MPEG Source |
| 75 | * 0x6 - NTSC VBI |
| 76 | * 0x7 - 0xFF - Reserved |
| 77 | */ |
| 78 | #define AVI_IFRAME_TYPE 0x2 |
| 79 | #define AVI_IFRAME_VERSION 0x2 |
| 80 | #define LEFT_SHIFT_BYTE(x) ((x) << 8) |
| 81 | #define LEFT_SHIFT_WORD(x) ((x) << 16) |
| 82 | #define LEFT_SHIFT_24BITS(x) ((x) << 24) |
| 83 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 84 | #define DBC_START_OFFSET 4 |
| 85 | #define VIC_INDEX 3 |
| 86 | #define HDMI_VIC_STR_MAX 3 |
| 87 | |
| 88 | enum edid_data_block_type { |
| 89 | RESERVED_DATA_BLOCK1 = 0, |
| 90 | AUDIO_DATA_BLOCK, |
| 91 | VIDEO_DATA_BLOCK, |
| 92 | VENDOR_SPECIFIC_DATA_BLOCK, |
| 93 | SPEAKER_ALLOCATION_DATA_BLOCK, |
| 94 | VESA_DTC_DATA_BLOCK, |
| 95 | RESERVED_DATA_BLOCK2, |
| 96 | USE_EXTENDED_TAG |
| 97 | }; |
| 98 | |
| 99 | /* video formats defined by CEA 861D */ |
| 100 | #define HDMI_VFRMT_UNKNOWN 0 |
| 101 | #define HDMI_VFRMT_640x480p60_4_3 1 |
| 102 | #define HDMI_VFRMT_1280x720p60_16_9 4 |
| 103 | #define HDMI_VFRMT_1920x1080p60_16_9 16 |
| 104 | #define HDMI_VFRMT_MAX 3 |
| 105 | |
| 106 | #define DEFAULT_RESOLUTION HDMI_VFRMT_1920x1080p60_16_9 |
| 107 | static uint8_t mdss_hdmi_video_fmt = HDMI_VFRMT_UNKNOWN; |
| 108 | static uint8_t mdss_hdmi_pref_fmt = HDMI_VFRMT_UNKNOWN; |
| 109 | static uint8_t pt_scan_info; |
| 110 | static uint8_t it_scan_info; |
| 111 | static uint8_t ce_scan_info; |
| 112 | |
| 113 | static uint8_t mdss_hdmi_edid_buf[0x80]; |
| 114 | |
| 115 | enum aspect_ratio { |
| 116 | HDMI_RES_AR_INVALID, |
| 117 | HDMI_RES_AR_4_3, |
| 118 | HDMI_RES_AR_5_4, |
| 119 | HDMI_RES_AR_16_9, |
| 120 | HDMI_RES_AR_16_10, |
| 121 | HDMI_RES_AR_MAX, |
| 122 | }; |
| 123 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 124 | struct mdss_hdmi_timing_info { |
| 125 | uint32_t video_format; |
| 126 | uint32_t active_h; |
| 127 | uint32_t front_porch_h; |
| 128 | uint32_t pulse_width_h; |
| 129 | uint32_t back_porch_h; |
| 130 | uint32_t active_low_h; |
| 131 | uint32_t active_v; |
| 132 | uint32_t front_porch_v; |
| 133 | uint32_t pulse_width_v; |
| 134 | uint32_t back_porch_v; |
| 135 | uint32_t active_low_v; |
| 136 | /* Must divide by 1000 to get the actual frequency in MHZ */ |
| 137 | uint32_t pixel_freq; |
| 138 | /* Must divide by 1000 to get the actual frequency in HZ */ |
| 139 | uint32_t refresh_rate; |
| 140 | uint32_t interlaced; |
| 141 | uint32_t supported; |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 142 | enum aspect_ratio ar; |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 143 | }; |
| 144 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 145 | #define HDMI_VFRMT_640x480p60_4_3_TIMING \ |
| 146 | {HDMI_VFRMT_640x480p60_4_3, 640, 16, 96, 48, true, \ |
| 147 | 480, 10, 2, 33, true, 25200, 60000, false, true, HDMI_RES_AR_4_3} |
Ajay Singh Parmar | 392f07a | 2014-11-19 15:06:19 -0800 | [diff] [blame] | 148 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 149 | #define HDMI_VFRMT_1280x720p60_16_9_TIMING \ |
| 150 | {HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, \ |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 151 | 720, 5, 5, 20, false, 74250, 60000, false, true, HDMI_RES_AR_16_9} |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 152 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 153 | #define HDMI_VFRMT_1920x1080p60_16_9_TIMING \ |
| 154 | {HDMI_VFRMT_1920x1080p60_16_9, 1920, 88, 44, 148, false, \ |
| 155 | 1080, 4, 5, 36, false, 148500, 60000, false, true, HDMI_RES_AR_16_9} |
| 156 | |
| 157 | #define MSM_HDMI_MODES_GET_DETAILS(mode, MODE) do { \ |
| 158 | struct mdss_hdmi_timing_info info = MODE##_TIMING; \ |
| 159 | *mode = info; \ |
| 160 | } while (0) |
| 161 | |
| 162 | static inline int mdss_hdmi_get_timing_info( |
| 163 | struct mdss_hdmi_timing_info *mode, int id) |
| 164 | { |
| 165 | int ret = 0; |
| 166 | |
| 167 | switch (id) { |
| 168 | case HDMI_VFRMT_640x480p60_4_3: |
| 169 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_640x480p60_4_3); |
| 170 | break; |
| 171 | |
| 172 | case HDMI_VFRMT_1280x720p60_16_9: |
| 173 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1280x720p60_16_9); |
| 174 | break; |
| 175 | |
| 176 | case HDMI_VFRMT_1920x1080p60_16_9: |
| 177 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1920x1080p60_16_9); |
| 178 | break; |
| 179 | |
| 180 | default: |
| 181 | ret = ERROR; |
| 182 | } |
| 183 | |
| 184 | return ret; |
| 185 | } |
| 186 | |
| 187 | |
| 188 | /* |
| 189 | * 13 Bytes of AVI infoframe data wrt each resolution |
| 190 | * Data Byte 01: 0 Y1 Y0 A0 B1 B0 S1 S0 |
| 191 | * Data Byte 02: C1 C0 M1 M0 R3 R2 R1 R0 |
| 192 | * Data Byte 03: ITC EC2 EC1 EC0 Q1 Q0 SC1 SC0 |
| 193 | * Data Byte 04: 0 VIC6 VIC5 VIC4 VIC3 VIC2 VIC1 VIC0 |
| 194 | * Data Byte 05: 0 0 0 0 PR3 PR2 PR1 PR0 |
| 195 | * Data Byte 06: LSB Line No of End of Top Bar |
| 196 | * Data Byte 07: MSB Line No of End of Top Bar |
| 197 | * Data Byte 08: LSB Line No of Start of Bottom Bar |
| 198 | * Data Byte 09: MSB Line No of Start of Bottom Bar |
| 199 | * Data Byte 10: LSB Pixel Number of End of Left Bar |
| 200 | * Data Byte 11: MSB Pixel Number of End of Left Bar |
| 201 | * Data Byte 12: LSB Pixel Number of Start of Right Bar |
| 202 | * Data Byte 13: MSB Pixel Number of Start of Right Bar |
| 203 | */ |
| 204 | static uint8_t mdss_hdmi_avi_info_db[HDMI_VFRMT_MAX][AVI_MAX_DATA_BYTES] = { |
| 205 | /* 480p */ |
| 206 | {0x10, 0x18, 0x00, 0x01, 0x00, 0x00, 0x00, |
| 207 | 0xE1, 0x01, 0x00, 0x00, 0x81, 0x02}, |
| 208 | /* 720p */ |
| 209 | {0x10, 0x28, 0x00, 0x04, 0x00, 0x00, 0x00, |
| 210 | 0xD1, 0x02, 0x00, 0x00, 0x01, 0x05}, |
| 211 | /* 1080p */ |
| 212 | {0x10, 0x28, 0x00, 0x10, 0x00, 0x00, 0x00, |
| 213 | 0x39, 0x04, 0x00, 0x00, 0x81, 0x07}, |
| 214 | }; |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 215 | |
Ajay Singh Parmar | a1771a1 | 2014-08-13 15:56:11 -0700 | [diff] [blame] | 216 | static void mdss_hdmi_audio_acr_setup(void) |
| 217 | { |
| 218 | int n, cts, layout, multiplier; |
| 219 | uint32_t aud_pck_ctrl_2_reg = 0, acr_pck_ctrl_reg = 0; |
| 220 | |
| 221 | /* 74.25MHz ACR settings */ |
| 222 | n = 4096; |
| 223 | cts = 74250; |
| 224 | layout = 0; |
| 225 | multiplier = 1; |
| 226 | |
| 227 | /* AUDIO_PRIORITY | SOURCE */ |
| 228 | acr_pck_ctrl_reg |= 0x80000100; |
| 229 | |
| 230 | /* N_MULTIPLE(multiplier) */ |
| 231 | acr_pck_ctrl_reg |= (multiplier & 7) << 16; |
| 232 | |
| 233 | /* SELECT(3) */ |
| 234 | acr_pck_ctrl_reg |= 3 << 4; |
| 235 | |
| 236 | /* CTS_48 */ |
| 237 | cts <<= 12; |
| 238 | |
| 239 | /* CTS: need to determine how many fractional bits */ |
| 240 | writel(cts, HDMI_ACR_48_0); |
| 241 | |
| 242 | /* N */ |
| 243 | /* HDMI_ACR_48_1 */ |
| 244 | writel(n, HDMI_ACR_48_1); |
| 245 | |
| 246 | /* Payload layout depends on number of audio channels */ |
| 247 | aud_pck_ctrl_2_reg = 1 | (layout << 1); |
| 248 | |
| 249 | /* override | layout */ |
| 250 | writel(aud_pck_ctrl_2_reg, HDMI_AUDIO_PKT_CTRL2); |
| 251 | |
| 252 | /* SEND | CONT */ |
| 253 | acr_pck_ctrl_reg |= 0x3; |
| 254 | |
| 255 | writel(acr_pck_ctrl_reg, HDMI_ACR_PKT_CTRL); |
| 256 | } |
| 257 | |
| 258 | static int mdss_hdmi_audio_info_setup(void) |
| 259 | { |
| 260 | uint32_t channel_count = 1; /* Default to 2 channels |
| 261 | -> See Table 17 in CEA-D spec */ |
| 262 | uint32_t channel_allocation = 0; |
| 263 | uint32_t level_shift = 0; |
| 264 | uint32_t down_mix = 0; |
| 265 | uint32_t check_sum, audio_info_0_reg, audio_info_1_reg; |
| 266 | uint32_t audio_info_ctrl_reg; |
| 267 | uint32_t aud_pck_ctrl_2_reg; |
| 268 | uint32_t layout; |
| 269 | |
| 270 | layout = 0; |
| 271 | aud_pck_ctrl_2_reg = 1 | (layout << 1); |
| 272 | writel(aud_pck_ctrl_2_reg, HDMI_AUDIO_PKT_CTRL2); |
| 273 | |
| 274 | /* Read first then write because it is bundled with other controls */ |
| 275 | audio_info_ctrl_reg = readl(HDMI_INFOFRAME_CTRL0); |
| 276 | |
| 277 | channel_allocation = 0; /* Default to FR,FL */ |
| 278 | |
| 279 | /* Program the Channel-Speaker allocation */ |
| 280 | audio_info_1_reg = 0; |
| 281 | |
| 282 | /* CA(channel_allocation) */ |
| 283 | audio_info_1_reg |= channel_allocation & 0xff; |
| 284 | |
| 285 | /* Program the Level shifter */ |
| 286 | /* LSV(level_shift) */ |
| 287 | audio_info_1_reg |= (level_shift << 11) & 0x00007800; |
| 288 | |
| 289 | /* Program the Down-mix Inhibit Flag */ |
| 290 | /* DM_INH(down_mix) */ |
| 291 | audio_info_1_reg |= (down_mix << 15) & 0x00008000; |
| 292 | |
| 293 | writel(audio_info_1_reg, HDMI_AUDIO_INFO1); |
| 294 | |
| 295 | check_sum = 0; |
| 296 | /* HDMI_AUDIO_INFO_FRAME_PACKET_HEADER_TYPE[0x84] */ |
| 297 | check_sum += 0x84; |
| 298 | /* HDMI_AUDIO_INFO_FRAME_PACKET_HEADER_VERSION[0x01] */ |
| 299 | check_sum += 1; |
| 300 | /* HDMI_AUDIO_INFO_FRAME_PACKET_LENGTH[0x0A] */ |
| 301 | check_sum += 0x0A; |
| 302 | check_sum += channel_count; |
| 303 | check_sum += channel_allocation; |
| 304 | /* See Table 8.5 in HDMI spec */ |
| 305 | check_sum += (level_shift & 0xF) << 3 | (down_mix & 0x1) << 7; |
| 306 | check_sum &= 0xFF; |
| 307 | check_sum = (256 - check_sum); |
| 308 | |
| 309 | audio_info_0_reg = 0; |
| 310 | /* CHECKSUM(check_sum) */ |
| 311 | audio_info_0_reg |= check_sum & 0xff; |
| 312 | /* CC(channel_count) */ |
| 313 | audio_info_0_reg |= (channel_count << 8) & 0x00000700; |
| 314 | |
| 315 | writel(audio_info_0_reg, HDMI_AUDIO_INFO0); |
| 316 | |
| 317 | /* Set these flags */ |
| 318 | /* AUDIO_INFO_UPDATE | AUDIO_INFO_SOURCE | AUDIO_INFO_CONT |
| 319 | | AUDIO_INFO_SEND */ |
| 320 | audio_info_ctrl_reg |= 0xF0; |
| 321 | |
| 322 | /* HDMI_INFOFRAME_CTRL0[0x002C] */ |
| 323 | writel(audio_info_ctrl_reg, HDMI_INFOFRAME_CTRL0); |
| 324 | |
| 325 | return 0; |
| 326 | } |
| 327 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 328 | static uint8_t* hdmi_edid_find_block(uint32_t start_offset, |
| 329 | uint8_t type, uint8_t *len) |
| 330 | { |
| 331 | /* the start of data block collection, start of Video Data Block */ |
| 332 | uint8_t *in_buf = mdss_hdmi_edid_buf; |
| 333 | uint32_t offset = start_offset; |
| 334 | uint32_t end_dbc_offset = in_buf[2]; |
| 335 | |
| 336 | *len = 0; |
| 337 | |
| 338 | /* |
| 339 | * edid buffer 1, byte 2 being 4 means no non-DTD/Data block collection |
| 340 | * present. |
| 341 | * edid buffer 1, byte 2 being 0 means no non-DTD/DATA block collection |
| 342 | * present and no DTD data present. |
| 343 | */ |
| 344 | if ((end_dbc_offset == 0) || (end_dbc_offset == 4)) |
| 345 | return NULL; |
| 346 | |
| 347 | while (offset < end_dbc_offset) { |
| 348 | uint8_t block_len = in_buf[offset] & 0x1F; |
| 349 | if ((in_buf[offset] >> 5) == type) { |
| 350 | *len = block_len; |
| 351 | dprintf(SPEW, |
| 352 | "EDID: block=%d found @ %d with length=%d\n", |
| 353 | type, offset, block_len); |
| 354 | return in_buf + offset; |
| 355 | } |
| 356 | offset += 1 + block_len; |
| 357 | } |
| 358 | |
| 359 | return NULL; |
| 360 | } |
| 361 | |
Ajay Singh Parmar | a1771a1 | 2014-08-13 15:56:11 -0700 | [diff] [blame] | 362 | static void mdss_hdmi_audio_playback(void) |
| 363 | { |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 364 | char *base_addr; |
Ajay Singh Parmar | a1771a1 | 2014-08-13 15:56:11 -0700 | [diff] [blame] | 365 | |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 366 | base_addr = (char *) memalign(4096, 0x1000); |
Ajay Singh Parmar | a1771a1 | 2014-08-13 15:56:11 -0700 | [diff] [blame] | 367 | if (base_addr == NULL) { |
| 368 | dprintf(CRITICAL, "%s: Error audio buffer alloc\n", __func__); |
| 369 | return; |
| 370 | } |
| 371 | |
| 372 | memset(base_addr, 0, 0x1000); |
| 373 | |
| 374 | writel(0x00000010, HDMI_AUDIO_PKT_CTRL); |
| 375 | writel(0x00000080, HDMI_AUDIO_CFG); |
| 376 | |
| 377 | writel(0x0000096E, LPASS_LPAIF_RDDMA_CTL0); |
| 378 | writel(0x00000A6E, LPASS_LPAIF_RDDMA_CTL0); |
| 379 | writel(0x00002000, HDMI_VBI_PKT_CTRL); |
| 380 | writel(0x00000000, HDMI_GEN_PKT_CTRL); |
| 381 | writel(0x0000096E, LPASS_LPAIF_RDDMA_CTL0); |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 382 | writel((uint32_t) base_addr, LPASS_LPAIF_RDDMA_BASE0); |
Ajay Singh Parmar | a1771a1 | 2014-08-13 15:56:11 -0700 | [diff] [blame] | 383 | writel(0x000005FF, LPASS_LPAIF_RDDMA_BUFF_LEN0); |
| 384 | writel(0x000005FF, LPASS_LPAIF_RDDMA_PER_LEN0); |
| 385 | writel(0x0000096F, LPASS_LPAIF_RDDMA_CTL0); |
| 386 | writel(0x00000010, LPASS_LPAIF_DEBUG_CTL); |
| 387 | writel(0x00000000, HDMI_GC); |
| 388 | writel(0x00002030, HDMI_VBI_PKT_CTRL); |
| 389 | writel(0x00002030, HDMI_VBI_PKT_CTRL); |
| 390 | writel(0x00002030, HDMI_VBI_PKT_CTRL); |
| 391 | |
| 392 | mdss_hdmi_audio_acr_setup(); |
| 393 | mdss_hdmi_audio_info_setup(); |
| 394 | |
| 395 | writel(0x00000010, HDMI_AUDIO_PKT_CTRL); |
| 396 | writel(0x00000080, HDMI_AUDIO_CFG); |
| 397 | writel(0x00000011, HDMI_AUDIO_PKT_CTRL); |
| 398 | writel(0x00000081, HDMI_AUDIO_CFG); |
| 399 | } |
| 400 | |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 401 | static uint32_t mdss_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 402 | { |
| 403 | return target_hdmi_panel_clock(enable, pinfo); |
| 404 | } |
| 405 | |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame^] | 406 | static uint32_t mdss_hdmi_pll_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 407 | { |
| 408 | return target_hdmi_pll_clock(enable, pinfo); |
| 409 | } |
| 410 | |
Ajay Singh Parmar | 9d2ba15 | 2014-08-14 00:42:24 -0700 | [diff] [blame] | 411 | static int mdss_hdmi_enable_power(uint8_t enable, struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 412 | { |
| 413 | int ret = NO_ERROR; |
| 414 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 415 | ret = target_hdmi_regulator_ctrl(enable); |
| 416 | if (ret) { |
Ajay Singh Parmar | 9d2ba15 | 2014-08-14 00:42:24 -0700 | [diff] [blame] | 417 | dprintf(CRITICAL, "hdmi regulator control enable failed\n"); |
| 418 | goto bail_regulator_fail; |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 419 | } |
| 420 | |
Ajay Singh Parmar | 9d2ba15 | 2014-08-14 00:42:24 -0700 | [diff] [blame] | 421 | ret = target_hdmi_gpio_ctrl(enable); |
| 422 | if (ret) { |
| 423 | dprintf(CRITICAL, "hdmi gpio control enable failed\n"); |
| 424 | goto bail_gpio_fail; |
| 425 | } |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 426 | |
Ajay Singh Parmar | 9d2ba15 | 2014-08-14 00:42:24 -0700 | [diff] [blame] | 427 | dprintf(SPEW, "HDMI Panel power %s done\n", enable ? "on" : "off"); |
| 428 | |
| 429 | return ret; |
| 430 | |
| 431 | bail_gpio_fail: |
| 432 | target_hdmi_regulator_ctrl(0); |
| 433 | |
| 434 | bail_regulator_fail: |
Ajay Singh Parmar | 9d2ba15 | 2014-08-14 00:42:24 -0700 | [diff] [blame] | 435 | return ret; |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 436 | } |
| 437 | |
| 438 | static void mdss_hdmi_set_mode(bool on) |
| 439 | { |
| 440 | uint32_t val = 0; |
| 441 | |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame^] | 442 | if (on) |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 443 | val = 0x3; |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame^] | 444 | |
| 445 | writel(val, HDMI_CTRL); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 446 | } |
| 447 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 448 | |
| 449 | static int mdss_hdmi_read_edid(void) |
| 450 | { |
| 451 | uint8_t ndx; |
| 452 | uint32_t reg_val; |
| 453 | uint32_t dev_addr = 0xA0; |
| 454 | uint32_t len = 0x80; |
| 455 | uint32_t offset = 0x80; |
| 456 | uint32_t time_out; |
| 457 | uint32_t retry = 5; |
| 458 | |
| 459 | dev_addr &= 0xFE; |
| 460 | |
| 461 | again: |
| 462 | time_out = 10; |
| 463 | writel(readl(HDMI_DDC_ARBITRATION) & ~BIT(4), HDMI_DDC_ARBITRATION); |
| 464 | |
| 465 | /* Enable DDC Interrupts */ |
| 466 | writel(BIT(1) | BIT(2), HDMI_DDC_INT_CTRL); |
| 467 | |
| 468 | /* config DDC to read CEA block */ |
| 469 | writel((10 << 16) | (2 << 0), HDMI_DDC_SPEED); |
| 470 | writel(0xFF000000, HDMI_DDC_SETUP); |
| 471 | writel((1 << 16) | (19 << 0), HDMI_DDC_REF); |
| 472 | writel(BIT(31) | (dev_addr << 8), HDMI_DDC_DATA); |
| 473 | writel(offset << 8, HDMI_DDC_DATA); |
| 474 | writel((dev_addr | BIT(0)) << 8, HDMI_DDC_DATA); |
| 475 | writel(BIT(12) | BIT(16), HDMI_DDC_TRANS0); |
| 476 | writel(BIT(0) | BIT(12) | BIT(13) | (len << 16), HDMI_DDC_TRANS1); |
| 477 | writel(BIT(0) | BIT(20), HDMI_DDC_CTRL); |
| 478 | |
| 479 | /* poll for 100ms for read to complete */ |
| 480 | reg_val = readl(HDMI_DDC_INT_CTRL); |
| 481 | while (!(reg_val & BIT(0)) && time_out) { |
| 482 | reg_val = readl(HDMI_DDC_INT_CTRL); |
| 483 | time_out--; |
| 484 | mdelay(10); |
| 485 | } |
| 486 | |
| 487 | if (!time_out) { |
| 488 | dprintf(CRITICAL, "%s: Timeout reading EDID\n", __func__); |
| 489 | if (retry--) |
| 490 | goto again; |
| 491 | else |
| 492 | return ERROR; |
| 493 | } |
| 494 | |
| 495 | /* clear interrupts */ |
| 496 | writel(BIT(1), HDMI_DDC_INT_CTRL); |
| 497 | |
| 498 | reg_val = readl(HDMI_DDC_SW_STATUS); |
| 499 | reg_val &= BIT(12) | BIT(13) | BIT(14) | BIT(15); |
| 500 | |
| 501 | /* Check if any NACK occurred */ |
| 502 | if (reg_val) { |
| 503 | /* SW_STATUS_RESET */ |
| 504 | writel(BIT(3), HDMI_DDC_CTRL); |
| 505 | |
| 506 | /* SOFT_RESET */ |
| 507 | writel(BIT(1), HDMI_DDC_CTRL); |
| 508 | |
| 509 | dprintf(CRITICAL, "%s: NACK reading EDID\n", __func__); |
| 510 | |
| 511 | if (retry--) |
| 512 | goto again; |
| 513 | else |
| 514 | return ERROR; |
| 515 | } |
| 516 | |
| 517 | /* Write this data to DDC buffer */ |
| 518 | writel(BIT(0) | (3 << 16) | BIT(31), HDMI_DDC_DATA); |
| 519 | |
| 520 | /* Discard first byte */ |
| 521 | readl(HDMI_DDC_DATA); |
| 522 | |
| 523 | for (ndx = 0; ndx < 0x80; ndx++) { |
| 524 | reg_val = readl(HDMI_DDC_DATA); |
| 525 | mdss_hdmi_edid_buf[ndx] = (uint8_t)((reg_val & 0x0000FF00) >> 8); |
| 526 | } |
| 527 | |
| 528 | dprintf(INFO, "%s: EDID read successful\n", __func__); |
| 529 | |
| 530 | return NO_ERROR; |
| 531 | } |
| 532 | |
| 533 | static void mdss_hdmi_parse_res(void) |
| 534 | { |
| 535 | uint8_t len, i; |
| 536 | uint32_t video_format; |
| 537 | struct mdss_hdmi_timing_info tinfo_fmt = {0}; |
| 538 | |
| 539 | uint8_t *svd = hdmi_edid_find_block(DBC_START_OFFSET, |
| 540 | VIDEO_DATA_BLOCK, &len); |
| 541 | |
| 542 | mdss_hdmi_video_fmt = HDMI_VFRMT_UNKNOWN; |
| 543 | |
| 544 | if (!svd) { |
| 545 | mdss_hdmi_video_fmt = DEFAULT_RESOLUTION; |
Ajay Singh Parmar | 392f07a | 2014-11-19 15:06:19 -0800 | [diff] [blame] | 546 | return; |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 547 | } |
Ajay Singh Parmar | 392f07a | 2014-11-19 15:06:19 -0800 | [diff] [blame] | 548 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 549 | ++svd; |
| 550 | |
| 551 | for (i = 0; i < len; ++i, ++svd) { |
| 552 | struct mdss_hdmi_timing_info tinfo = {0}; |
| 553 | uint32_t ret = 0; |
| 554 | |
| 555 | video_format = (*svd & 0x7F); |
| 556 | |
| 557 | if (i == 0) |
| 558 | mdss_hdmi_pref_fmt = video_format; |
| 559 | |
| 560 | ret = mdss_hdmi_get_timing_info(&tinfo, video_format); |
| 561 | |
| 562 | if (ret || !tinfo.supported) |
| 563 | continue; |
| 564 | |
| 565 | if (!tinfo_fmt.video_format) { |
| 566 | memcpy(&tinfo_fmt, &tinfo, sizeof(tinfo)); |
| 567 | mdss_hdmi_video_fmt = video_format; |
| 568 | continue; |
| 569 | } |
| 570 | |
| 571 | if (tinfo.active_v > tinfo_fmt.active_v) { |
| 572 | memcpy(&tinfo_fmt, &tinfo, sizeof(tinfo)); |
| 573 | mdss_hdmi_video_fmt = video_format; |
| 574 | } |
| 575 | } |
| 576 | |
| 577 | if (mdss_hdmi_video_fmt == HDMI_VFRMT_UNKNOWN) |
| 578 | mdss_hdmi_video_fmt = DEFAULT_RESOLUTION; |
Ajay Singh Parmar | 392f07a | 2014-11-19 15:06:19 -0800 | [diff] [blame] | 579 | } |
| 580 | |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame^] | 581 | void mdss_hdmi_get_vic(char *buf) |
| 582 | { |
| 583 | struct mdss_hdmi_timing_info tinfo = {0}; |
| 584 | uint32_t ret = mdss_hdmi_get_timing_info(&tinfo, mdss_hdmi_video_fmt); |
| 585 | |
| 586 | if (ret) |
| 587 | snprintf(buf, HDMI_VIC_STR_MAX, "%d", HDMI_VFRMT_UNKNOWN); |
| 588 | else |
| 589 | snprintf(buf, HDMI_VIC_STR_MAX, "%d", tinfo.video_format); |
| 590 | |
| 591 | } |
| 592 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 593 | static void mdss_hdmi_panel_init(struct msm_panel_info *pinfo) |
| 594 | { |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 595 | struct mdss_hdmi_timing_info tinfo = {0}; |
| 596 | uint32_t ret = mdss_hdmi_get_timing_info(&tinfo, mdss_hdmi_video_fmt); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 597 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 598 | if (!pinfo || ret) |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 599 | return; |
| 600 | |
| 601 | pinfo->xres = tinfo.active_h; |
| 602 | pinfo->yres = tinfo.active_v; |
| 603 | pinfo->bpp = 24; |
| 604 | pinfo->type = HDMI_PANEL; |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 605 | pinfo->clk_rate = tinfo.pixel_freq * 1000; |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 606 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 607 | pinfo->lcdc.h_back_porch = tinfo.back_porch_h; |
| 608 | pinfo->lcdc.h_front_porch = tinfo.front_porch_h; |
| 609 | pinfo->lcdc.h_pulse_width = tinfo.pulse_width_h; |
| 610 | pinfo->lcdc.v_back_porch = tinfo.back_porch_v; |
| 611 | pinfo->lcdc.v_front_porch = tinfo.front_porch_v; |
| 612 | pinfo->lcdc.v_pulse_width = tinfo.pulse_width_v; |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 613 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 614 | pinfo->lcdc.hsync_skew = 0; |
| 615 | pinfo->lcdc.xres_pad = 0; |
| 616 | pinfo->lcdc.yres_pad = 0; |
| 617 | pinfo->lcdc.dual_pipe = 0; |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 618 | } |
| 619 | |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame^] | 620 | static int mdss_hdmi_update_panel_info(void) |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 621 | { |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame^] | 622 | mdss_hdmi_set_mode(true); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 623 | |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame^] | 624 | if (!mdss_hdmi_read_edid()) |
| 625 | mdss_hdmi_parse_res(); |
| 626 | else |
| 627 | mdss_hdmi_video_fmt = DEFAULT_RESOLUTION; |
| 628 | |
| 629 | mdss_hdmi_set_mode(false); |
| 630 | |
| 631 | mdss_hdmi_panel_init(&(panel.panel_info)); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 632 | |
| 633 | panel.fb.width = panel.panel_info.xres; |
| 634 | panel.fb.height = panel.panel_info.yres; |
| 635 | panel.fb.stride = panel.panel_info.xres; |
| 636 | panel.fb.bpp = panel.panel_info.bpp; |
| 637 | panel.fb.format = FB_FORMAT_RGB888; |
| 638 | |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame^] | 639 | return NO_ERROR; |
| 640 | } |
| 641 | |
| 642 | void mdss_hdmi_display_init(uint32_t rev, void *base) |
| 643 | { |
| 644 | panel.power_func = mdss_hdmi_enable_power; |
| 645 | panel.clk_func = mdss_hdmi_panel_clock; |
| 646 | panel.update_panel_info = mdss_hdmi_update_panel_info; |
| 647 | panel.pll_clk_func = mdss_hdmi_pll_clock; |
| 648 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 649 | panel.fb.base = base; |
| 650 | panel.mdp_rev = rev; |
| 651 | |
| 652 | msm_display_init(&panel); |
| 653 | } |
| 654 | |
| 655 | static int mdss_hdmi_video_setup(void) |
| 656 | { |
| 657 | uint32_t total_v = 0; |
| 658 | uint32_t total_h = 0; |
| 659 | uint32_t start_h = 0; |
| 660 | uint32_t end_h = 0; |
| 661 | uint32_t start_v = 0; |
| 662 | uint32_t end_v = 0; |
| 663 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 664 | struct mdss_hdmi_timing_info tinfo = {0}; |
| 665 | uint32_t ret = mdss_hdmi_get_timing_info(&tinfo, mdss_hdmi_video_fmt); |
| 666 | |
| 667 | if (ret) |
| 668 | return ERROR; |
| 669 | |
| 670 | dprintf(INFO, "hdmi resolution %dx%d@p%dHz (%d)\n", |
| 671 | tinfo.active_h, tinfo.active_v, tinfo.refresh_rate/1000, |
| 672 | mdss_hdmi_video_fmt); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 673 | |
| 674 | total_h = tinfo.active_h + tinfo.front_porch_h + |
| 675 | tinfo.back_porch_h + tinfo.pulse_width_h - 1; |
| 676 | total_v = tinfo.active_v + tinfo.front_porch_v + |
| 677 | tinfo.back_porch_v + tinfo.pulse_width_v - 1; |
| 678 | if (((total_v << 16) & 0xE0000000) || (total_h & 0xFFFFE000)) { |
| 679 | dprintf(CRITICAL, |
| 680 | "%s: total v=%d or h=%d is larger than supported\n", |
| 681 | __func__, total_v, total_h); |
| 682 | return ERROR; |
| 683 | } |
| 684 | writel((total_v << 16) | (total_h << 0), HDMI_TOTAL); |
| 685 | |
| 686 | start_h = tinfo.back_porch_h + tinfo.pulse_width_h; |
| 687 | end_h = (total_h + 1) - tinfo.front_porch_h; |
| 688 | if (((end_h << 16) & 0xE0000000) || (start_h & 0xFFFFE000)) { |
| 689 | dprintf(CRITICAL, |
| 690 | "%s: end_h=%d or start_h=%d is larger than supported\n", |
| 691 | __func__, end_h, start_h); |
| 692 | return ERROR; |
| 693 | } |
| 694 | writel((end_h << 16) | (start_h << 0), HDMI_ACTIVE_H); |
| 695 | |
| 696 | start_v = tinfo.back_porch_v + tinfo.pulse_width_v - 1; |
| 697 | end_v = total_v - tinfo.front_porch_v; |
| 698 | if (((end_v << 16) & 0xE0000000) || (start_v & 0xFFFFE000)) { |
| 699 | dprintf(CRITICAL, |
| 700 | "%s: end_v=%d or start_v=%d is larger than supported\n", |
| 701 | __func__, end_v, start_v); |
| 702 | return ERROR; |
| 703 | } |
| 704 | writel((end_v << 16) | (start_v << 0), HDMI_ACTIVE_V); |
| 705 | |
| 706 | if (tinfo.interlaced) { |
| 707 | writel((total_v + 1) << 0, HDMI_V_TOTAL_F2); |
| 708 | writel(((end_v + 1) << 16) | ((start_v + 1) << 0), |
| 709 | HDMI_ACTIVE_V_F2); |
| 710 | } else { |
| 711 | writel(0, HDMI_V_TOTAL_F2); |
| 712 | writel(0, HDMI_ACTIVE_V_F2); |
| 713 | } |
| 714 | |
| 715 | writel(((tinfo.interlaced << 31) & 0x80000000) | |
| 716 | ((tinfo.active_low_h << 29) & 0x20000000) | |
| 717 | ((tinfo.active_low_v << 28) & 0x10000000), HDMI_FRAME_CTRL); |
| 718 | |
| 719 | return 0; |
| 720 | } |
| 721 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 722 | static void mdss_hdmi_extract_extended_data_blocks(void) |
| 723 | { |
| 724 | uint8_t len = 0; |
| 725 | uint32_t start_offset = DBC_START_OFFSET; |
| 726 | uint8_t const *etag = NULL; |
| 727 | uint8_t *in_buf = mdss_hdmi_edid_buf; |
| 728 | |
| 729 | do { |
| 730 | /* A Tage code of 7 identifies extended data blocks */ |
| 731 | etag = hdmi_edid_find_block(start_offset, |
| 732 | USE_EXTENDED_TAG, &len); |
| 733 | |
| 734 | start_offset = etag - in_buf + len + 1; |
| 735 | |
| 736 | /* The extended data block should at least be 2 bytes long */ |
| 737 | if (len < 2) { |
| 738 | dprintf(SPEW, "%s: data block of len < 2 bytes\n", |
| 739 | __func__); |
| 740 | continue; |
| 741 | } |
| 742 | |
| 743 | /* |
| 744 | * The second byte of the extended data block has the |
| 745 | * extended tag code |
| 746 | */ |
| 747 | switch (etag[1]) { |
| 748 | case 0: |
| 749 | /* |
| 750 | * Check if the sink specifies underscan |
| 751 | * support for: |
| 752 | * BIT 5: preferred video format |
| 753 | * BIT 3: IT video format |
| 754 | * BIT 1: CE video format |
| 755 | */ |
| 756 | pt_scan_info = (etag[2] & (BIT(4) | BIT(5))) >> 4; |
| 757 | it_scan_info = (etag[2] & (BIT(3) | BIT(2))) >> 2; |
| 758 | ce_scan_info = etag[2] & (BIT(1) | BIT(0)); |
| 759 | |
| 760 | dprintf(INFO, "scan Info (pt|it|ce): (%d|%d|%d)\n", |
| 761 | pt_scan_info, it_scan_info, ce_scan_info); |
| 762 | break; |
| 763 | default: |
| 764 | dprintf(SPEW, "%s: Tag Code %d not supported\n", |
| 765 | __func__, etag[1]); |
| 766 | break; |
| 767 | } |
| 768 | } while (etag != NULL); |
| 769 | } |
| 770 | |
| 771 | /* |
| 772 | * If the sink specified support for both underscan/overscan then, by default, |
| 773 | * set the underscan bit. Only checking underscan support for preferred |
| 774 | * format and cea formats. |
| 775 | */ |
| 776 | uint8_t mdss_hdmi_get_scan_info(void) |
| 777 | { |
| 778 | uint8_t scaninfo = 0; |
| 779 | bool use_ce_scan_info = true; |
| 780 | |
| 781 | mdss_hdmi_extract_extended_data_blocks(); |
| 782 | |
| 783 | if (mdss_hdmi_video_fmt == mdss_hdmi_pref_fmt) { |
| 784 | use_ce_scan_info = false; |
| 785 | |
| 786 | switch (pt_scan_info) { |
| 787 | case 0: |
| 788 | use_ce_scan_info = true; |
| 789 | break; |
| 790 | case 3: |
| 791 | scaninfo = BIT(1); |
| 792 | break; |
| 793 | default: |
| 794 | break; |
| 795 | } |
| 796 | } |
| 797 | |
| 798 | if (use_ce_scan_info) { |
| 799 | if (3 == ce_scan_info) |
| 800 | scaninfo |= BIT(1); |
| 801 | } |
| 802 | |
| 803 | return scaninfo; |
| 804 | } |
| 805 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 806 | void mdss_hdmi_avi_info_frame(void) |
| 807 | { |
| 808 | uint32_t sum; |
| 809 | uint32_t reg_val; |
| 810 | uint8_t checksum; |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 811 | uint8_t scaninfo; |
| 812 | uint32_t i, index; |
| 813 | |
| 814 | scaninfo = mdss_hdmi_get_scan_info(); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 815 | |
| 816 | sum = IFRAME_PACKET_OFFSET + AVI_IFRAME_TYPE + |
| 817 | AVI_IFRAME_VERSION + AVI_MAX_DATA_BYTES; |
| 818 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 819 | for (index = 0; index < HDMI_VFRMT_MAX; index++) { |
| 820 | if (mdss_hdmi_avi_info_db[index][VIC_INDEX] == mdss_hdmi_video_fmt) |
| 821 | break; |
| 822 | } |
| 823 | |
| 824 | if (index == VIC_INDEX) |
| 825 | return; |
| 826 | |
| 827 | mdss_hdmi_avi_info_db[index][DATA_BYTE_1] |= |
| 828 | scaninfo & (BIT(1) | BIT(0)); |
| 829 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 830 | for (i = 0; i < AVI_MAX_DATA_BYTES; i++) |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 831 | sum += mdss_hdmi_avi_info_db[index][i]; |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 832 | |
| 833 | sum &= 0xFF; |
| 834 | sum = 256 - sum; |
| 835 | checksum = (uint8_t) sum; |
| 836 | |
| 837 | reg_val = checksum | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 838 | LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[index][DATA_BYTE_1]) | |
| 839 | LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[index][DATA_BYTE_2]) | |
| 840 | LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[index][DATA_BYTE_3]); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 841 | writel(reg_val, HDMI_AVI_INFO0); |
| 842 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 843 | reg_val = mdss_hdmi_avi_info_db[index][DATA_BYTE_4] | |
| 844 | LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[index][DATA_BYTE_5]) | |
| 845 | LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[index][DATA_BYTE_6]) | |
| 846 | LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[index][DATA_BYTE_7]); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 847 | writel(reg_val, HDMI_AVI_INFO1); |
| 848 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 849 | reg_val = mdss_hdmi_avi_info_db[index][DATA_BYTE_8] | |
| 850 | LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[index][DATA_BYTE_9]) | |
| 851 | LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[index][DATA_BYTE_10]) | |
| 852 | LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[index][DATA_BYTE_11]); |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 853 | writel(reg_val, HDMI_AVI_INFO2); |
| 854 | |
Casey Piper | 97d2527 | 2015-03-17 15:10:34 -0700 | [diff] [blame] | 855 | reg_val = mdss_hdmi_avi_info_db[index][DATA_BYTE_12] | |
| 856 | LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[index][DATA_BYTE_13]) | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 857 | LEFT_SHIFT_24BITS(AVI_IFRAME_VERSION); |
| 858 | writel(reg_val, HDMI_AVI_INFO3); |
| 859 | |
| 860 | /* AVI InfFrame enable (every frame) */ |
| 861 | writel(readl(HDMI_INFOFRAME_CTRL0) | BIT(1) | BIT(0), |
| 862 | HDMI_INFOFRAME_CTRL0); |
| 863 | } |
| 864 | |
| 865 | int mdss_hdmi_init(void) |
| 866 | { |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 867 | mdss_hdmi_set_mode(false); |
| 868 | |
Ajay Singh Parmar | a1771a1 | 2014-08-13 15:56:11 -0700 | [diff] [blame] | 869 | /* Audio settings */ |
| 870 | mdss_hdmi_audio_playback(); |
| 871 | |
| 872 | /* Video settings */ |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 873 | mdss_hdmi_video_setup(); |
| 874 | |
Ajay Singh Parmar | a1771a1 | 2014-08-13 15:56:11 -0700 | [diff] [blame] | 875 | /* AVI info settings */ |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 876 | mdss_hdmi_avi_info_frame(); |
| 877 | |
Ajay Singh Parmar | a1771a1 | 2014-08-13 15:56:11 -0700 | [diff] [blame] | 878 | /* Enable HDMI */ |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 879 | mdss_hdmi_set_mode(true); |
| 880 | |
| 881 | return 0; |
| 882 | } |