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gerrit-public.fairphone.software / kernel / lk / 6c945a414fb776256b26c3b13a514b9ad6593902 / . / platform / msm8953 / include / platform / iomap.h
blob: b1626441708c3d4a9b15e9c2ef12b1cdbd5b0ac2 [file] [log] [blame]
Jayant Shekharcbe5ed92016-01-14 11:12:20 +0530[diff] [blame]1/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
Gaurav Nebhwani6c945a42016-02-16 17:26:51 +0530[diff] [blame^]29#ifndef _PLATFORM_MSM8953_IOMAP_H_
30#define _PLATFORM_MSM8953_IOMAP_H_
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]31
32#define MSM_IOMAP_BASE 0x00000000
33#define MSM_IOMAP_END 0x08000000
34
35#define SDRAM_START_ADDR 0x80000000
36
37#define MSM_SHARED_BASE 0x86300000
38#define MSM_SHARED_IMEM_BASE 0x08600000
39
40#define BS_INFO_OFFSET (0x6B0)
41#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
42
43#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
44
45#define APPS_SS_BASE 0x0B000000
P.V. Phani Kumara053a322015-08-13 18:36:05 +0530[diff] [blame]46#define APPS_SS_END 0x0B200000
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]47
48#define MSM_GIC_DIST_BASE APPS_SS_BASE
49#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
50#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
51#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
52#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
53#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00111008)
54
55#define PERIPH_SS_BASE 0x07800000
56
57#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
58#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000)
59
60#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
61#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
62#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
63
64#define CLK_CTL_BASE 0x1800000
65
66#define SPMI_BASE 0x02000000
67#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
68#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
69#define PMIC_ARB_CORE 0x200F000
70
71#define TLMM_BASE_ADDR 0x1000000
72#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
73#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
74
75#define MPM2_MPM_CTRL_BASE 0x004A0000
76#define MPM2_MPM_PS_HOLD 0x004AB000
77#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
78
c_wufeng79c06462016-01-14 17:51:40 +0800[diff] [blame]79#define PMI_SLAVE_BASE 2
80#define PMI_FIRST_SLAVE_OFFSET 0
81#define PMI_SECOND_SLAVE_OFFSET 1
82#define PMI_FIRST_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_FIRST_SLAVE_OFFSET ) << 16)
83#define PMI_SECOND_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_SECOND_SLAVE_OFFSET) << 16)
84
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]85/* CRYPTO ENGINE */
86#define MSM_CE1_BASE 0x073A000
87#define MSM_CE1_BAM_BASE 0x0704000
P.V. Phani Kumar40fa1352015-08-13 18:15:03 +0530[diff] [blame]88#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
89#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
90#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
91#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
92#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
93#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]94
95
96/* GPLL */
P.V. Phani Kumard017bb92015-11-26 18:31:03 +0530[diff] [blame]97#define GPLL0_MODE (CLK_CTL_BASE + 0x21000)
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]98#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
99#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
P.V. Phani Kumar40fa1352015-08-13 18:15:03 +0530[diff] [blame]100#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
101#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
P.V. Phani Kumar9451ebe2015-12-26 16:31:18 +0530[diff] [blame]102#define GPLL6_STATUS (CLK_CTL_BASE + 0x37024)
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]103
104/* SDCC */
105#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
106#define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/
107#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */
108#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
109#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */
110#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */
111#define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */
112#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
113#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
114
P.V. Phani Kumar40fa1352015-08-13 18:15:03 +0530[diff] [blame]115/* SDHCI */
116#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
117#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
118
119#define SDCC_MCI_HC_MODE (0x00000078)
120#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
121#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
122#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
123#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
124
125#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
126#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
127#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
128#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
129#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
130#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
131#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
132#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
133
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]134/* UART */
135#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
P.V. Phani Kumar9451ebe2015-12-26 16:31:18 +0530[diff] [blame]136#define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x203C)
137#define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2044)
138#define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x2048)
139#define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x204C)
140#define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x2050)
141#define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x2054)
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]142#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
143#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
144#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
145#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
146#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
147#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
148
149/* USB */
150#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
151#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
152#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
153#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
154#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
P.V. Phani Kumar9451ebe2015-12-26 16:31:18 +0530[diff] [blame]155#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x4103C)
156#define MSM_USB30_QSCRATCH_BASE 0x070F8800
157#define MSM_USB30_BASE 0x7000000
158#define USB2_PHY_SEL 0x01937000
159#define QUSB2_PHY_BASE 0X79000
160
161/* SS QMP (Qulacomm Multi Protocol) */
162#define QMP_PHY_BASE 0x78000
163
164#define AHB2_PHY_BASE 0x0007e000
165#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
166
167 /* USB3 clocks */
168#define USB_30_BCR (CLK_CTL_BASE + 0x3F070)
169#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x3F078)
170#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0x3F000)
171#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x3F004)
172#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x3F008)
173#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x3F00C)
174#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x3F010)
175#define USB30_MASTER_M (CLK_CTL_BASE + 0x3F014)
176#define USB30_MASTER_N (CLK_CTL_BASE + 0x3F018)
177#define USB30_MASTER_D (CLK_CTL_BASE + 0x3F01C)
178#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x3F020)
179#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x3F024)
180#define PC_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x3F038)
181
182#define USB3_AUX_CMD_RCGR (CLK_CTL_BASE + 0x3F05C)
183#define USB3_AUX_CFG_RCGR (CLK_CTL_BASE + 0x3F060)
184#define USB3_AUX_CBCR (CLK_CTL_BASE + 0x3F044)
185#define USB3_AUX_M (CLK_CTL_BASE + 0x3F064)
186#define USB3_AUX_N (CLK_CTL_BASE + 0x3F068)
187#define USB3_AUX_D (CLK_CTL_BASE + 0x3F06C)
188#define USB3_PIPE_CBCR (CLK_CTL_BASE + 0x3F040)
189#define USB3_PHY_BCR (CLK_CTL_BASE + 0x3F034)
190#define USB3PHY_PHY_BCR (CLK_CTL_BASE + 0x3F03C)
191#define USB_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x3F080)
192
193/* QMP rev registers */
194#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x988)
195#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x98C)
196#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x990)
197#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x994)
198
199/* Dummy macro needed for compilation only */
200#define PLATFORM_QMP_OFFSET 0x0
201
202#define USB3_PHY_STATUS 0x78974
203/* Register for finding out if single ended or differential clock enablement */
204#define TCSR_PHY_CLK_SCHEME_SEL 0x0193F044
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]205
P.V. Phani Kumara843c9f2015-09-08 11:19:34 +0530[diff] [blame]206/* RPMB send receive buffer needs to be mapped
207 * as device memory, define the start address
208 * and size in MB
209 */
Parth Dixit0b195a42016-02-01 14:11:38 +0530[diff] [blame]210#define RPMB_SND_RCV_BUF 0xA0000000
P.V. Phani Kumara843c9f2015-09-08 11:19:34 +0530[diff] [blame]211#define RPMB_SND_RCV_BUF_SZ 0x1
212
213/* QSEECOM: Secure app region notification */
Gaurav Nebhwani35138f02016-01-19 14:32:26 +0530[diff] [blame]214#define APP_REGION_ADDR 0x85B00000
215#define APP_REGION_SIZE 0x800000
P.V. Phani Kumara843c9f2015-09-08 11:19:34 +0530[diff] [blame]216
Jayant Shekharcbe5ed92016-01-14 11:12:20 +0530[diff] [blame]217/* MDSS */
218#define MIPI_DSI_BASE (0x1A94000)
219#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
220#define MIPI_DSI1_BASE (0x1A96000)
221#define DSI0_PHY_BASE (0x1A94400)
222#define DSI1_PHY_BASE (0x1A96400)
223#define DSI0_PLL_BASE (0x1A94800)
224#define DSI1_PLL_BASE (0x1A96800)
225#define DSI0_REGULATOR_BASE (0x1A94000)
226#define DSI1_REGULATOR_BASE (0x1A96000)
227
228#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0D0
229#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0D4
230
231#define MDP_BASE (0x1A00000)
232#define REG_MDP(off) (MDP_BASE + (off))
233
234#ifdef MDP_HW_REV
235#undef MDP_HW_REV
236#endif
237#define MDP_HW_REV REG_MDP(0x1000)
238
239#ifdef MDP_INTR_EN
240#undef MDP_INTR_EN
241#endif
242#define MDP_INTR_EN REG_MDP(0x1010)
243
244#ifdef MDP_INTR_CLEAR
245#undef MDP_INTR_CLEAR
246#endif
247#define MDP_INTR_CLEAR REG_MDP(0x1018)
248
249#ifdef MDP_HIST_INTR_EN
250#undef MDP_HIST_INTR_EN
251#endif
252#define MDP_HIST_INTR_EN REG_MDP(0x101C)
253
254#ifdef MDP_VP_0_VIG_0_BASE
255#undef MDP_VP_0_VIG_0_BASE
256#endif
257#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
258
259#ifdef MDP_VP_0_VIG_1_BASE
260#undef MDP_VP_0_VIG_1_BASE
261#endif
262#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
263
264#ifdef MDP_VP_0_RGB_0_BASE
265#undef MDP_VP_0_RGB_0_BASE
266#endif
267#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
268
269#ifdef MDP_VP_0_RGB_1_BASE
270#undef MDP_VP_0_RGB_1_BASE
271#endif
272#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
273
274#ifdef MDP_VP_0_DMA_0_BASE
275#undef MDP_VP_0_DMA_0_BASE
276#endif
277#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
278
279#ifdef MDP_VP_0_DMA_1_BASE
280#undef MDP_VP_0_DMA_1_BASE
281#endif
282#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
283
284#ifdef MDP_VP_0_MIXER_0_BASE
285#undef MDP_VP_0_MIXER_0_BASE
286#endif
287#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
288
289#ifdef MDP_VP_0_MIXER_1_BASE
290#undef MDP_VP_0_MIXER_1_BASE
291#endif
292#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
293
294#ifdef MDP_DISP_INTF_SEL
295#undef MDP_DISP_INTF_SEL
296#endif
297#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
298
299#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
300#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
301#endif
302#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
303
304#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
305#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
306#endif
307#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
308
309#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
310#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
311#endif
312#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
313
314#ifdef MDP_CTL_0_BASE
315#undef MDP_CTL_0_BASE
316#endif
317#define MDP_CTL_0_BASE REG_MDP(0x2000)
318
319#ifdef MDP_CTL_1_BASE
320#undef MDP_CTL_1_BASE
321#endif
322#define MDP_CTL_1_BASE REG_MDP(0x2200)
323
324#ifdef MDP_CLK_CTRL0
325#undef MDP_CLK_CTRL0
326#endif
327#define MDP_CLK_CTRL0 REG_MDP(0x012AC)
328
329#ifdef MDP_CLK_CTRL1
330#undef MDP_CLK_CTRL1
331#endif
332#define MDP_CLK_CTRL1 REG_MDP(0x012B4)
333
334#ifdef MDP_CLK_CTRL2
335#undef MDP_CLK_CTRL2
336#endif
337#define MDP_CLK_CTRL2 REG_MDP(0x012BC)
338
339#ifdef MDP_CLK_CTRL3
340#undef MDP_CLK_CTRL3
341#endif
342#define MDP_CLK_CTRL3 REG_MDP(0x013A8)
343
344#ifdef MDP_CLK_CTRL4
345#undef MDP_CLK_CTRL4
346#endif
347#define MDP_CLK_CTRL4 REG_MDP(0x013B0)
348
349#ifdef MDP_CLK_CTRL5
350#undef MDP_CLK_CTRL5
351#endif
352#define MDP_CLK_CTRL5 REG_MDP(0x013B8)
353
354#ifdef MDP_INTF_1_BASE
355#undef MDP_INTF_1_BASE
356#endif
357#define MDP_INTF_1_BASE REG_MDP(0x12700)
358
359#ifdef MDP_INTF_2_BASE
360#undef MDP_INTF_2_BASE
361#endif
362#define MDP_INTF_2_BASE REG_MDP(0x12F00)
363
364#ifdef MDP_REG_SPLIT_DISPLAY_EN
365#undef MDP_REG_SPLIT_DISPLAY_EN
366#endif
367#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
368
369#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
370#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
371#endif
372#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
373
374#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
375#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
376#endif
377#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
378
379#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
380#undef MMSS_MDP_SMP_ALLOC_W_BASE
381#endif
382#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
383
384#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
385#undef MMSS_MDP_SMP_ALLOC_R_BASE
386#endif
387#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
388
389#ifdef MDP_QOS_REMAPPER_CLASS_0
390#undef MDP_QOS_REMAPPER_CLASS_0
391#endif
392#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
393
394#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
395#undef VBIF_VBIF_DDR_FORCE_CLK_ON
396#endif
397#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
398
399#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
400#undef VBIF_VBIF_DDR_OUT_MAX_BURST
401#endif
402#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
403
404#ifdef VBIF_VBIF_DDR_ARB_CTRL
405#undef VBIF_VBIF_DDR_ARB_CTRL
406#endif
407#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
408
409#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
410#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
411#endif
412#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
413
414#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
415#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
416#endif
417#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
418
419#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
420#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
421#endif
422#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
423
424#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
425#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
426#endif
427#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
428
429#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
430#undef VBIF_VBIF_DDR_OUT_AX_AOOO
431#endif
432#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
433
434#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
435#undef VBIF_VBIF_IN_RD_LIM_CONF0
436#endif
437#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
438
439#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
440#undef VBIF_VBIF_IN_RD_LIM_CONF1
441#endif
442#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
443
444#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
445#undef VBIF_VBIF_IN_WR_LIM_CONF0
446#endif
447#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
448
449#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
450#undef VBIF_VBIF_IN_WR_LIM_CONF1
451#endif
452#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
453
454#ifdef MDP_INTF_2_TIMING_ENGINE_EN
455#undef MDP_INTF_2_TIMING_ENGINE_EN
456#endif
457#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x12F00)
458
459#ifdef MDP_PP_0_BASE
460#undef MDP_PP_0_BASE
461#endif
462#define MDP_PP_0_BASE REG_MDP(0x71000)
463
464#ifdef MDP_PP_1_BASE
465#undef MDP_PP_1_BASE
466#endif
467#define MDP_PP_1_BASE REG_MDP(0x71800)
468
469#ifdef MDSS_MDP_REG_DCE_SEL
470#undef MDSS_MDP_REG_DCE_SEL
471#endif
472#define MDSS_MDP_REG_DCE_SEL REG_MDP(0x1428)
473
474#ifdef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
475#undef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
476#endif
477#define MDSS_MDP_PP_DCE_DATA_OUT_SWAP 0x0CC
478
479#ifdef MDP_DSC_0_BASE
480#undef MDP_DSC_0_BASE
481#endif
482#define MDP_DSC_0_BASE REG_MDP(0x81000)
483
484#ifdef MDP_DSC_1_BASE
485#undef MDP_DSC_1_BASE
486#endif
487#define MDP_DSC_1_BASE REG_MDP(0x81400)
488
489#define SOFT_RESET 0x118
490#define CLK_CTRL 0x11C
491#define TRIG_CTRL 0x084
492#define CTRL 0x004
493#define COMMAND_MODE_DMA_CTRL 0x03C
494#define COMMAND_MODE_MDP_CTRL 0x040
495#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
496#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
497#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
498#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
499#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
500#define ERR_INT_MASK0 0x10C
501
502#define LANE_CTL 0x0AC
503#define LANE_SWAP_CTL 0x0B0
504#define TIMING_CTL 0x0C4
505
506#define VIDEO_MODE_ACTIVE_H 0x024
507#define VIDEO_MODE_ACTIVE_V 0x028
508#define VIDEO_MODE_TOTAL 0x02C
509#define VIDEO_MODE_HSYNC 0x030
510#define VIDEO_MODE_VSYNC 0x034
511#define VIDEO_MODE_VSYNC_VPOS 0x038
512
513#define DMA_CMD_OFFSET 0x048
514#define DMA_CMD_LENGTH 0x04C
515
516#define INT_CTRL 0x110
517#define CMD_MODE_DMA_SW_TRIGGER 0x090
518
519#define EOT_PACKET_CTRL 0x0CC
520#define MISR_CMD_CTRL 0x0A0
521#define MISR_VIDEO_CTRL 0x0A4
522#define VIDEO_MODE_CTRL 0x010
523#define HS_TIMER_CTRL 0x0BC
524
525#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
526#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
527#define CMD_COMPRESSION_MODE_CTRL 0x2A8
528#define CMD_COMPRESSION_MODE_CTRL_2 0x2AC
529#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
530
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]531#define TCSR_TZ_WONCE 0x193D000
532#define TCSR_BOOT_MISC_DETECT 0x193D100
533
lijuang6e6aec52016-01-14 15:37:55 +0800[diff] [blame]534#define DDR_START get_ddr_start()
P.V. Phani Kumar05793c72016-01-22 12:08:11 +0530[diff] [blame]535#define ABOOT_FORCE_KERNEL_ADDR (DDR_START + 0x8000)
536#define ABOOT_FORCE_KERNEL64_ADDR (DDR_START + 0x80000)
537#define ABOOT_FORCE_RAMDISK_ADDR (DDR_START + 0x3600000)
538#define ABOOT_FORCE_TAGS_ADDR (DDR_START + 0x3400000)
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530[diff] [blame]539#endif