blob: 765a9eb66e81b6109dcb101b6a368f606f9c7b09 [file] [log] [blame]
Veera Sundaram Sankaran7868d542015-01-02 14:48:47 -08001/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
Ray Zhang743e5032013-05-25 23:25:39 +08002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions
5 * are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in
10 * the documentation and/or other materials provided with the
11 * distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
19 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
20 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <debug.h>
31#include <smem.h>
Arpita Banerjeec5f78df2013-05-24 15:43:40 -070032#include <err.h>
Ray Zhang743e5032013-05-25 23:25:39 +080033#include <msm_panel.h>
Arpita Banerjee0906ffd2013-05-24 16:25:38 -070034#include <mipi_dsi.h>
Ray Zhang743e5032013-05-25 23:25:39 +080035#include <pm8x41.h>
36#include <pm8x41_wled.h>
37#include <board.h>
38#include <mdp5.h>
Aravind Venkateswaranfada7f32013-09-19 15:23:34 -070039#include <scm.h>
Ray Zhang743e5032013-05-25 23:25:39 +080040#include <platform/gpio.h>
41#include <platform/iomap.h>
42#include <target/display.h>
43
Casey Pipercbdfbd22013-08-14 17:22:16 -070044#include "include/panel.h"
Arpita Banerjeec5f78df2013-05-24 15:43:40 -070045#include "include/display_resource.h"
Ray Zhang743e5032013-05-25 23:25:39 +080046
Dhaval Patel815567c2013-07-31 11:13:25 -070047#define HFPLL_LDO_ID 8
48
Ray Zhang743e5032013-05-25 23:25:39 +080049static struct pm8x41_wled_data wled_ctrl = {
rayzhanga3667cd2013-07-01 12:22:54 +080050 .mod_scheme = 0x00,
Ray Zhang743e5032013-05-25 23:25:39 +080051 .led1_brightness = (0x0F << 8) | 0xEF,
Ray Zhang743e5032013-05-25 23:25:39 +080052 .max_duty_cycle = 0x01,
rayzhanga3667cd2013-07-01 12:22:54 +080053 .ovp = 0x0,
Zhenhua Huangd5355cb2013-09-04 16:03:01 +080054 .full_current_scale = 0x19,
55 .fdbck = 0x1
Ray Zhang743e5032013-05-25 23:25:39 +080056};
57
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053058static uint32_t dsi_pll_enable_seq_m(uint32_t pll_base)
Casey Piperaee81202013-08-26 11:14:02 -070059{
60 uint32_t i = 0;
61 uint32_t pll_locked = 0;
62
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053063 mdss_dsi_uniphy_pll_sw_reset(pll_base);
Casey Piperaee81202013-08-26 11:14:02 -070064
65 /*
66 * Add hardware recommended delays between register writes for
67 * the updates to take effect. These delays are necessary for the
68 * PLL to successfully lock
69 */
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053070 writel(0x01, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -070071 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053072 writel(0x05, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -070073 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053074 writel(0x0f, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -070075 udelay(1000);
76
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053077 mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
78 pll_locked = readl(pll_base + 0x00c0) & 0x01;
Casey Piperaee81202013-08-26 11:14:02 -070079 for (i = 0; (i < 4) && !pll_locked; i++) {
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053080 writel(0x07, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -070081 if (i != 0)
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053082 writel(0x34, pll_base + 0x00070); /* CAL CFG1*/
Casey Piperaee81202013-08-26 11:14:02 -070083 udelay(1);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053084 writel(0x0f, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -070085 udelay(1000);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053086 mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
87 pll_locked = readl(pll_base + 0x00c0) & 0x01;
Casey Piperaee81202013-08-26 11:14:02 -070088 }
89
90 return pll_locked;
91}
92
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053093static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base)
Casey Piperaee81202013-08-26 11:14:02 -070094{
95 uint32_t pll_locked = 0;
96
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +053097 mdss_dsi_uniphy_pll_sw_reset(pll_base);
Casey Piperaee81202013-08-26 11:14:02 -070098
99 /*
100 * Add hardware recommended delays between register writes for
101 * the updates to take effect. These delays are necessary for the
102 * PLL to successfully lock
103 */
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530104 writel(0x01, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700105 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530106 writel(0x05, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700107 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530108 writel(0x07, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700109 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530110 writel(0x05, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700111 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530112 writel(0x07, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700113 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530114 writel(0x0f, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700115 udelay(1000);
116
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530117 mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
118 pll_locked = readl(pll_base + 0x00c0) & 0x01;
Casey Piperaee81202013-08-26 11:14:02 -0700119
120 return pll_locked;
121}
122
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530123static uint32_t dsi_pll_enable_seq_f1(uint32_t pll_base)
Casey Piperaee81202013-08-26 11:14:02 -0700124{
125 uint32_t pll_locked = 0;
126
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530127 mdss_dsi_uniphy_pll_sw_reset(pll_base);
Casey Piperaee81202013-08-26 11:14:02 -0700128
129 /*
130 * Add hardware recommended delays between register writes for
131 * the updates to take effect. These delays are necessary for the
132 * PLL to successfully lock
133 */
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530134 writel(0x01, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700135 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530136 writel(0x05, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700137 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530138 writel(0x0f, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700139 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530140 writel(0x0d, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700141 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530142 writel(0x0f, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700143 udelay(1000);
144
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530145 mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
146 pll_locked = readl(pll_base + 0x00c0) & 0x01;
Casey Piperaee81202013-08-26 11:14:02 -0700147
148 return pll_locked;
149}
150
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530151static uint32_t dsi_pll_enable_seq_c(uint32_t pll_base)
Casey Piperaee81202013-08-26 11:14:02 -0700152{
153 uint32_t pll_locked = 0;
154
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530155 mdss_dsi_uniphy_pll_sw_reset(pll_base);
Casey Piperaee81202013-08-26 11:14:02 -0700156
157 /*
158 * Add hardware recommended delays between register writes for
159 * the updates to take effect. These delays are necessary for the
160 * PLL to successfully lock
161 */
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530162 writel(0x01, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700163 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530164 writel(0x05, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700165 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530166 writel(0x0f, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700167 udelay(1000);
168
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530169 mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
170 pll_locked = readl(pll_base + 0x00c0) & 0x01;
Casey Piperaee81202013-08-26 11:14:02 -0700171
172 return pll_locked;
173}
174
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530175static uint32_t dsi_pll_enable_seq_e(uint32_t pll_base)
Casey Piperaee81202013-08-26 11:14:02 -0700176{
177 uint32_t pll_locked = 0;
178
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530179 mdss_dsi_uniphy_pll_sw_reset(pll_base);
Casey Piperaee81202013-08-26 11:14:02 -0700180
181 /*
182 * Add hardware recommended delays between register writes for
183 * the updates to take effect. These delays are necessary for the
184 * PLL to successfully lock
185 */
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530186 writel(0x01, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700187 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530188 writel(0x05, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700189 udelay(200);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530190 writel(0x0d, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700191 udelay(1);
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530192 writel(0x0f, pll_base + 0x0020); /* GLB CFG */
Casey Piperaee81202013-08-26 11:14:02 -0700193 udelay(1000);
194
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530195 mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
196 pll_locked = readl(pll_base + 0x00c0) & 0x01;
Casey Piperaee81202013-08-26 11:14:02 -0700197
198 return pll_locked;
199}
200
Vineet Bajajbb14cb02014-04-25 00:38:09 +0530201static int msm8226_wled_backlight_ctrl(uint8_t enable)
202{
203 if (enable) {
204 pm8x41_wled_config(&wled_ctrl);
205 pm8x41_wled_sink_control(enable);
206 pm8x41_wled_iled_sync_control(enable);
207 pm8x41_wled_led_mod_enable(enable);
208 }
209 pm8x41_wled_enable(enable);
210
211 return NO_ERROR;
212}
213
214static int msm8226_pwm_backlight_ctrl(int gpio_num, int lpg_chan, int enable)
215{
216 struct pm8x41_gpio gpio_param = {
217 .direction = PM_GPIO_DIR_OUT,
218 .function = PM_GPIO_FUNC_2,
219 .vin_sel = 2, /* VIN_2 */
220 .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
221 .output_buffer = PM_GPIO_OUT_CMOS,
222 .out_strength = PM_GPIO_OUT_DRIVE_HIGH,
223 };
224
225 dprintf(SPEW, "%s: gpio=%d lpg=%d enable=%d\n", __func__,
226 gpio_num, lpg_chan, enable);
227
228 if (enable) {
229 pm8x41_gpio_config(gpio_num, &gpio_param);
230 pm8x41_lpg_write(lpg_chan, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
231 pm8x41_lpg_write(lpg_chan, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
232 pm8x41_lpg_write(lpg_chan, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
233 pm8x41_lpg_write(lpg_chan, 0x44, 0xb2); /* LPG_VALUE_LSB */
234 pm8x41_lpg_write(lpg_chan, 0x45, 0x01); /* LPG_VALUE_MSB */
235 pm8x41_lpg_write(lpg_chan, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
236 } else {
237 pm8x41_lpg_write(lpg_chan, 0x46, 0x00);
238 }
239
240 return NO_ERROR;
241}
242
243
Kuogee Hsiehdf961742013-12-18 14:13:45 -0800244int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
Ray Zhang743e5032013-05-25 23:25:39 +0800245{
Vineet Bajajbb14cb02014-04-25 00:38:09 +0530246 uint32_t ret = NO_ERROR;
247
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700248 dprintf(SPEW, "target_backlight_ctrl\n");
249
Kuogee Hsiehdf961742013-12-18 14:13:45 -0800250 if (!bl) {
251 dprintf(CRITICAL, "backlight structure is not available\n");
252 return ERR_INVALID_ARGS;
253 }
254
Vineet Bajajbb14cb02014-04-25 00:38:09 +0530255 switch (bl->bl_interface_type) {
256 case BL_WLED:
257 ret = msm8226_wled_backlight_ctrl(enable);
258 break;
259 case BL_PWM:
260 ret = msm8226_pwm_backlight_ctrl(pwm_gpio.pin_id,
261 PWM_BL_LPG_CHAN_ID,
262 enable);
263 break;
264 default:
265 dprintf(CRITICAL, "backlight type:%d not supported\n",
Kuogee Hsiehdf961742013-12-18 14:13:45 -0800266 bl->bl_interface_type);
Vineet Bajajbb14cb02014-04-25 00:38:09 +0530267 return ERR_NOT_SUPPORTED;
Kuogee Hsiehdf961742013-12-18 14:13:45 -0800268 }
269
Vineet Bajajbb14cb02014-04-25 00:38:09 +0530270 return ret;
Ray Zhang743e5032013-05-25 23:25:39 +0800271}
272
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530273static void dsi_pll_enable_seq(uint32_t pll_base)
Casey Piperaee81202013-08-26 11:14:02 -0700274{
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530275 if (dsi_pll_enable_seq_m(pll_base)) {
276 } else if (dsi_pll_enable_seq_d(pll_base)) {
277 } else if (dsi_pll_enable_seq_d(pll_base)) {
278 } else if (dsi_pll_enable_seq_f1(pll_base)) {
279 } else if (dsi_pll_enable_seq_c(pll_base)) {
280 } else if (dsi_pll_enable_seq_e(pll_base)) {
Casey Piperaee81202013-08-26 11:14:02 -0700281 } else {
282 dprintf(CRITICAL, "Not able to enable the pll\n");
283 }
284}
285
Arpita Banerjee0906ffd2013-05-24 16:25:38 -0700286int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
Ray Zhang743e5032013-05-25 23:25:39 +0800287{
Aravind Venkateswaranfada7f32013-09-19 15:23:34 -0700288 int32_t ret;
Arpita Banerjee0906ffd2013-05-24 16:25:38 -0700289 struct mdss_dsi_pll_config *pll_data;
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700290 dprintf(SPEW, "target_panel_clock\n");
Ray Zhang743e5032013-05-25 23:25:39 +0800291
Arpita Banerjee0906ffd2013-05-24 16:25:38 -0700292 pll_data = pinfo->mipi.dsi_pll_config;
293
Ray Zhang743e5032013-05-25 23:25:39 +0800294 if (enable) {
295 mdp_gdsc_ctrl(enable);
Aravind Venkateswaran5f546922013-09-19 15:13:43 -0700296 mmss_bus_clocks_enable();
297 mdp_clock_enable();
Aravind Venkateswaranfada7f32013-09-19 15:23:34 -0700298 ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
299 if (ret) {
300 dprintf(CRITICAL,
301 "%s: Failed to restore MDP security configs",
302 __func__);
303 mdp_clock_disable();
304 mmss_bus_clocks_disable();
305 mdp_gdsc_ctrl(0);
306 return ret;
307 }
Padmanabhan Komanduru703bd6d2014-03-25 19:57:01 +0530308 mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
309 MIPI_DSI0_BASE, pll_data);
310 dsi_pll_enable_seq(DSI0_PLL_BASE);
Aravind Venkateswaran5f546922013-09-19 15:13:43 -0700311 mmss_dsi_clocks_enable(pll_data->pclk_m,
Arpita Banerjee0906ffd2013-05-24 16:25:38 -0700312 pll_data->pclk_n,
313 pll_data->pclk_d);
Ray Zhang743e5032013-05-25 23:25:39 +0800314 } else if(!target_cont_splash_screen()) {
Aravind Venkateswaran5f546922013-09-19 15:13:43 -0700315 mmss_dsi_clocks_disable();
316 mdp_clock_disable();
317 mmss_bus_clocks_disable();
318 mdp_gdsc_ctrl(enable);
Ray Zhang743e5032013-05-25 23:25:39 +0800319 }
320
321 return 0;
322}
323
Dhaval Patel7a349562013-08-08 20:43:52 -0700324int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
325 struct msm_panel_info *pinfo)
Ray Zhang743e5032013-05-25 23:25:39 +0800326{
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700327 int ret = NO_ERROR;
Ray Zhang743e5032013-05-25 23:25:39 +0800328 if (enable) {
Aravind Venkateswaranaf241212013-11-04 16:46:46 -0800329 if (pinfo->mipi.use_enable_gpio) {
330 gpio_tlmm_config(enable_gpio.pin_id, 0,
331 enable_gpio.pin_direction, enable_gpio.pin_pull,
332 enable_gpio.pin_strength,
333 enable_gpio.pin_state);
334
335 gpio_set_dir(enable_gpio.pin_id, 2);
336 }
337
Dhaval Patel7a349562013-08-08 20:43:52 -0700338 gpio_tlmm_config(reset_gpio.pin_id, 0,
339 reset_gpio.pin_direction, reset_gpio.pin_pull,
340 reset_gpio.pin_strength, reset_gpio.pin_state);
Ray Zhang743e5032013-05-25 23:25:39 +0800341
Dhaval Patel7a349562013-08-08 20:43:52 -0700342 gpio_set_dir(reset_gpio.pin_id, 2);
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700343
Dhaval Patel7a349562013-08-08 20:43:52 -0700344 gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[0]);
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700345 mdelay(resetseq->sleep[0]);
Dhaval Patel7a349562013-08-08 20:43:52 -0700346 gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[1]);
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700347 mdelay(resetseq->sleep[1]);
Dhaval Patel7a349562013-08-08 20:43:52 -0700348 gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[2]);
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700349 mdelay(resetseq->sleep[2]);
Ray Zhang743e5032013-05-25 23:25:39 +0800350 } else if(!target_cont_splash_screen()) {
Dhaval Patel7a349562013-08-08 20:43:52 -0700351 gpio_set_value(reset_gpio.pin_id, 0);
Aravind Venkateswaranaf241212013-11-04 16:46:46 -0800352 if (pinfo->mipi.use_enable_gpio)
353 gpio_set_value(enable_gpio.pin_id, 0);
Ray Zhang743e5032013-05-25 23:25:39 +0800354 }
355
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700356 return ret;
Ray Zhang743e5032013-05-25 23:25:39 +0800357}
358
Kuogee Hsieh93bcff62014-08-22 14:02:08 -0700359int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
Ray Zhang743e5032013-05-25 23:25:39 +0800360{
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700361 uint32_t ret = NO_ERROR;
362 uint32_t ldocounter = 0;
363 uint32_t pm8x41_ldo_base = 0x13F00;
Ray Zhang743e5032013-05-25 23:25:39 +0800364
Dhaval Patel7a349562013-08-08 20:43:52 -0700365 while (ldocounter < TOTAL_LDO_DEFINED) {
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700366 struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
367 0x100 * ldo_entry_array[ldocounter].ldo_id),
368 ldo_entry_array[ldocounter].ldo_type);
Ray Zhang743e5032013-05-25 23:25:39 +0800369
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700370 dprintf(SPEW, "Setting %s\n",
371 ldo_entry_array[ldocounter].ldo_id);
Ray Zhang743e5032013-05-25 23:25:39 +0800372
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700373 /* Set voltage during power on */
Dhaval Patel815567c2013-07-31 11:13:25 -0700374 if (enable) {
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700375 pm8x41_ldo_set_voltage(&ldo_entry,
376 ldo_entry_array[ldocounter].ldo_voltage);
Dhaval Patel815567c2013-07-31 11:13:25 -0700377
378 pm8x41_ldo_control(&ldo_entry, enable);
379
380 } else if(!target_cont_splash_screen() &&
381 ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
382 pm8x41_ldo_control(&ldo_entry, enable);
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700383 }
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700384 ldocounter++;
Ray Zhang743e5032013-05-25 23:25:39 +0800385 }
386
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700387 return ret;
Ray Zhang743e5032013-05-25 23:25:39 +0800388}
389
Ajay Singh Parmareef1d602014-03-15 17:41:52 -0700390bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
391{
Veera Sundaram Sankaranc95d6752014-07-31 11:49:52 -0700392 return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
Ajay Singh Parmareef1d602014-03-15 17:41:52 -0700393}
394
Aravind Venkateswaran6385f7e2014-02-25 16:45:11 -0800395void target_display_init(const char *panel_name)
Ray Zhang743e5032013-05-25 23:25:39 +0800396{
Pradeep Jilagamfeb15982013-10-29 13:08:51 +0530397 uint32_t panel_loop = 0;
398 uint32_t ret = 0;
Aravind Venkateswaran148e0df2014-03-28 16:26:05 -0700399 uint32_t fb_addr = MIPI_FB_ADDR;
Veera Sundaram Sankaran7868d542015-01-02 14:48:47 -0800400 char cont_splash = '\0';
401
402 set_panel_cmd_string(panel_name, &cont_splash);
Aravind Venkateswaran148e0df2014-03-28 16:26:05 -0700403
Veera Sundaram Sankaran3b758822014-10-17 12:15:39 -0700404 if (!strcmp(panel_name, NO_PANEL_CONFIG)
405 || !strcmp(panel_name, SIM_VIDEO_PANEL)
406 || !strcmp(panel_name, SIM_CMD_PANEL)) {
Veera Sundaram Sankaranc95d6752014-07-31 11:49:52 -0700407 dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
Veera Sundaram Sankaran3b758822014-10-17 12:15:39 -0700408 panel_name);
Jeevan Shriramb0d523a2014-05-30 12:55:17 -0700409 return;
410 }
411
Aravind Venkateswaran148e0df2014-03-28 16:26:05 -0700412 if (board_hardware_subtype() == HW_PLATFORM_SUBTYPE_QVGA)
413 fb_addr = MIPI_FB_ADDR_QVGA;
Pradeep Jilagamfeb15982013-10-29 13:08:51 +0530414
415 do {
Justin Philipbe9de5c2014-09-17 12:26:49 +0530416 target_force_cont_splash_disable(false);
Aravind Venkateswaran148e0df2014-03-28 16:26:05 -0700417 ret = gcdb_display_init(panel_name, MDP_REV_50, fb_addr);
Pradeep Jilagamfeb15982013-10-29 13:08:51 +0530418 if (!ret || ret == ERR_NOT_SUPPORTED) {
419 break;
420 } else {
421 target_force_cont_splash_disable(true);
422 msm_display_off();
Pradeep Jilagamfeb15982013-10-29 13:08:51 +0530423 }
424 } while (++panel_loop <= oem_panel_max_auto_detect_panels());
425
Veera Sundaram Sankaran7868d542015-01-02 14:48:47 -0800426 if (cont_splash == '0') {
427 dprintf(INFO, "Forcing continuous splash disable\n");
428 target_force_cont_splash_disable(true);
429 }
Ray Zhang743e5032013-05-25 23:25:39 +0800430}
431
Aravind Venkateswarandd50c1a2014-02-25 14:42:43 -0800432void target_display_shutdown(void)
Ray Zhang743e5032013-05-25 23:25:39 +0800433{
Arpita Banerjeec5f78df2013-05-24 15:43:40 -0700434 gcdb_display_shutdown();
Ray Zhang743e5032013-05-25 23:25:39 +0800435}