Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame^] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 32 | #include <err.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 33 | #include <msm_panel.h> |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 34 | #include <mipi_dsi.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <board.h> |
| 38 | #include <mdp5.h> |
Aravind Venkateswaran | fada7f3 | 2013-09-19 15:23:34 -0700 | [diff] [blame] | 39 | #include <scm.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 40 | #include <platform/gpio.h> |
| 41 | #include <platform/iomap.h> |
| 42 | #include <target/display.h> |
| 43 | |
Casey Piper | cbdfbd2 | 2013-08-14 17:22:16 -0700 | [diff] [blame] | 44 | #include "include/panel.h" |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 45 | #include "include/display_resource.h" |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 46 | |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 47 | #define HFPLL_LDO_ID 8 |
| 48 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 49 | static struct pm8x41_wled_data wled_ctrl = { |
rayzhang | a3667cd | 2013-07-01 12:22:54 +0800 | [diff] [blame] | 50 | .mod_scheme = 0x00, |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 51 | .led1_brightness = (0x0F << 8) | 0xEF, |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 52 | .max_duty_cycle = 0x01, |
rayzhang | a3667cd | 2013-07-01 12:22:54 +0800 | [diff] [blame] | 53 | .ovp = 0x0, |
Zhenhua Huang | d5355cb | 2013-09-04 16:03:01 +0800 | [diff] [blame] | 54 | .full_current_scale = 0x19, |
| 55 | .fdbck = 0x1 |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 56 | }; |
| 57 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 58 | static uint32_t dsi_pll_enable_seq_m(uint32_t pll_base) |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 59 | { |
| 60 | uint32_t i = 0; |
| 61 | uint32_t pll_locked = 0; |
| 62 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 63 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 64 | |
| 65 | /* |
| 66 | * Add hardware recommended delays between register writes for |
| 67 | * the updates to take effect. These delays are necessary for the |
| 68 | * PLL to successfully lock |
| 69 | */ |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 70 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 71 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 72 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 73 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 74 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 75 | udelay(1000); |
| 76 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 77 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 78 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 79 | for (i = 0; (i < 4) && !pll_locked; i++) { |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 80 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 81 | if (i != 0) |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 82 | writel(0x34, pll_base + 0x00070); /* CAL CFG1*/ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 83 | udelay(1); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 84 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 85 | udelay(1000); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 86 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 87 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | return pll_locked; |
| 91 | } |
| 92 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 93 | static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base) |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 94 | { |
| 95 | uint32_t pll_locked = 0; |
| 96 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 97 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 98 | |
| 99 | /* |
| 100 | * Add hardware recommended delays between register writes for |
| 101 | * the updates to take effect. These delays are necessary for the |
| 102 | * PLL to successfully lock |
| 103 | */ |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 104 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 105 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 106 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 107 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 108 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 109 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 110 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 111 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 112 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 113 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 114 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 115 | udelay(1000); |
| 116 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 117 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 118 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 119 | |
| 120 | return pll_locked; |
| 121 | } |
| 122 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 123 | static uint32_t dsi_pll_enable_seq_f1(uint32_t pll_base) |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 124 | { |
| 125 | uint32_t pll_locked = 0; |
| 126 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 127 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 128 | |
| 129 | /* |
| 130 | * Add hardware recommended delays between register writes for |
| 131 | * the updates to take effect. These delays are necessary for the |
| 132 | * PLL to successfully lock |
| 133 | */ |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 134 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 135 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 136 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 137 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 138 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 139 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 140 | writel(0x0d, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 141 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 142 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 143 | udelay(1000); |
| 144 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 145 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 146 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 147 | |
| 148 | return pll_locked; |
| 149 | } |
| 150 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 151 | static uint32_t dsi_pll_enable_seq_c(uint32_t pll_base) |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 152 | { |
| 153 | uint32_t pll_locked = 0; |
| 154 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 155 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 156 | |
| 157 | /* |
| 158 | * Add hardware recommended delays between register writes for |
| 159 | * the updates to take effect. These delays are necessary for the |
| 160 | * PLL to successfully lock |
| 161 | */ |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 162 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 163 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 164 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 165 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 166 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 167 | udelay(1000); |
| 168 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 169 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 170 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 171 | |
| 172 | return pll_locked; |
| 173 | } |
| 174 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 175 | static uint32_t dsi_pll_enable_seq_e(uint32_t pll_base) |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 176 | { |
| 177 | uint32_t pll_locked = 0; |
| 178 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 179 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 180 | |
| 181 | /* |
| 182 | * Add hardware recommended delays between register writes for |
| 183 | * the updates to take effect. These delays are necessary for the |
| 184 | * PLL to successfully lock |
| 185 | */ |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 186 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 187 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 188 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 189 | udelay(200); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 190 | writel(0x0d, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 191 | udelay(1); |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 192 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 193 | udelay(1000); |
| 194 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 195 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 196 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 197 | |
| 198 | return pll_locked; |
| 199 | } |
| 200 | |
Vineet Bajaj | bb14cb0 | 2014-04-25 00:38:09 +0530 | [diff] [blame] | 201 | static int msm8226_wled_backlight_ctrl(uint8_t enable) |
| 202 | { |
| 203 | if (enable) { |
| 204 | pm8x41_wled_config(&wled_ctrl); |
| 205 | pm8x41_wled_sink_control(enable); |
| 206 | pm8x41_wled_iled_sync_control(enable); |
| 207 | pm8x41_wled_led_mod_enable(enable); |
| 208 | } |
| 209 | pm8x41_wled_enable(enable); |
| 210 | |
| 211 | return NO_ERROR; |
| 212 | } |
| 213 | |
| 214 | static int msm8226_pwm_backlight_ctrl(int gpio_num, int lpg_chan, int enable) |
| 215 | { |
| 216 | struct pm8x41_gpio gpio_param = { |
| 217 | .direction = PM_GPIO_DIR_OUT, |
| 218 | .function = PM_GPIO_FUNC_2, |
| 219 | .vin_sel = 2, /* VIN_2 */ |
| 220 | .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10, |
| 221 | .output_buffer = PM_GPIO_OUT_CMOS, |
| 222 | .out_strength = PM_GPIO_OUT_DRIVE_HIGH, |
| 223 | }; |
| 224 | |
| 225 | dprintf(SPEW, "%s: gpio=%d lpg=%d enable=%d\n", __func__, |
| 226 | gpio_num, lpg_chan, enable); |
| 227 | |
| 228 | if (enable) { |
| 229 | pm8x41_gpio_config(gpio_num, &gpio_param); |
| 230 | pm8x41_lpg_write(lpg_chan, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */ |
| 231 | pm8x41_lpg_write(lpg_chan, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */ |
| 232 | pm8x41_lpg_write(lpg_chan, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */ |
| 233 | pm8x41_lpg_write(lpg_chan, 0x44, 0xb2); /* LPG_VALUE_LSB */ |
| 234 | pm8x41_lpg_write(lpg_chan, 0x45, 0x01); /* LPG_VALUE_MSB */ |
| 235 | pm8x41_lpg_write(lpg_chan, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */ |
| 236 | } else { |
| 237 | pm8x41_lpg_write(lpg_chan, 0x46, 0x00); |
| 238 | } |
| 239 | |
| 240 | return NO_ERROR; |
| 241 | } |
| 242 | |
| 243 | |
Kuogee Hsieh | df96174 | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 244 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 245 | { |
Vineet Bajaj | bb14cb0 | 2014-04-25 00:38:09 +0530 | [diff] [blame] | 246 | uint32_t ret = NO_ERROR; |
| 247 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 248 | dprintf(SPEW, "target_backlight_ctrl\n"); |
| 249 | |
Kuogee Hsieh | df96174 | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 250 | if (!bl) { |
| 251 | dprintf(CRITICAL, "backlight structure is not available\n"); |
| 252 | return ERR_INVALID_ARGS; |
| 253 | } |
| 254 | |
Vineet Bajaj | bb14cb0 | 2014-04-25 00:38:09 +0530 | [diff] [blame] | 255 | switch (bl->bl_interface_type) { |
| 256 | case BL_WLED: |
| 257 | ret = msm8226_wled_backlight_ctrl(enable); |
| 258 | break; |
| 259 | case BL_PWM: |
| 260 | ret = msm8226_pwm_backlight_ctrl(pwm_gpio.pin_id, |
| 261 | PWM_BL_LPG_CHAN_ID, |
| 262 | enable); |
| 263 | break; |
| 264 | default: |
| 265 | dprintf(CRITICAL, "backlight type:%d not supported\n", |
Kuogee Hsieh | df96174 | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 266 | bl->bl_interface_type); |
Vineet Bajaj | bb14cb0 | 2014-04-25 00:38:09 +0530 | [diff] [blame] | 267 | return ERR_NOT_SUPPORTED; |
Kuogee Hsieh | df96174 | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 268 | } |
| 269 | |
Vineet Bajaj | bb14cb0 | 2014-04-25 00:38:09 +0530 | [diff] [blame] | 270 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 271 | } |
| 272 | |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 273 | static void dsi_pll_enable_seq(uint32_t pll_base) |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 274 | { |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 275 | if (dsi_pll_enable_seq_m(pll_base)) { |
| 276 | } else if (dsi_pll_enable_seq_d(pll_base)) { |
| 277 | } else if (dsi_pll_enable_seq_d(pll_base)) { |
| 278 | } else if (dsi_pll_enable_seq_f1(pll_base)) { |
| 279 | } else if (dsi_pll_enable_seq_c(pll_base)) { |
| 280 | } else if (dsi_pll_enable_seq_e(pll_base)) { |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 281 | } else { |
| 282 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
| 283 | } |
| 284 | } |
| 285 | |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 286 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 287 | { |
Aravind Venkateswaran | fada7f3 | 2013-09-19 15:23:34 -0700 | [diff] [blame] | 288 | int32_t ret; |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 289 | struct mdss_dsi_pll_config *pll_data; |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 290 | dprintf(SPEW, "target_panel_clock\n"); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 291 | |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 292 | pll_data = pinfo->mipi.dsi_pll_config; |
| 293 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 294 | if (enable) { |
| 295 | mdp_gdsc_ctrl(enable); |
Aravind Venkateswaran | 5f54692 | 2013-09-19 15:13:43 -0700 | [diff] [blame] | 296 | mmss_bus_clocks_enable(); |
| 297 | mdp_clock_enable(); |
Aravind Venkateswaran | fada7f3 | 2013-09-19 15:23:34 -0700 | [diff] [blame] | 298 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 299 | if (ret) { |
| 300 | dprintf(CRITICAL, |
| 301 | "%s: Failed to restore MDP security configs", |
| 302 | __func__); |
| 303 | mdp_clock_disable(); |
| 304 | mmss_bus_clocks_disable(); |
| 305 | mdp_gdsc_ctrl(0); |
| 306 | return ret; |
| 307 | } |
Padmanabhan Komanduru | 703bd6d | 2014-03-25 19:57:01 +0530 | [diff] [blame] | 308 | mdss_dsi_auto_pll_config(DSI0_PLL_BASE, |
| 309 | MIPI_DSI0_BASE, pll_data); |
| 310 | dsi_pll_enable_seq(DSI0_PLL_BASE); |
Aravind Venkateswaran | 5f54692 | 2013-09-19 15:13:43 -0700 | [diff] [blame] | 311 | mmss_dsi_clocks_enable(pll_data->pclk_m, |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 312 | pll_data->pclk_n, |
| 313 | pll_data->pclk_d); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 314 | } else if(!target_cont_splash_screen()) { |
Aravind Venkateswaran | 5f54692 | 2013-09-19 15:13:43 -0700 | [diff] [blame] | 315 | mmss_dsi_clocks_disable(); |
| 316 | mdp_clock_disable(); |
| 317 | mmss_bus_clocks_disable(); |
| 318 | mdp_gdsc_ctrl(enable); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | return 0; |
| 322 | } |
| 323 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 324 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 325 | struct msm_panel_info *pinfo) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 326 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 327 | int ret = NO_ERROR; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 328 | if (enable) { |
Aravind Venkateswaran | af24121 | 2013-11-04 16:46:46 -0800 | [diff] [blame] | 329 | if (pinfo->mipi.use_enable_gpio) { |
| 330 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 331 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 332 | enable_gpio.pin_strength, |
| 333 | enable_gpio.pin_state); |
| 334 | |
| 335 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 336 | } |
| 337 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 338 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 339 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 340 | reset_gpio.pin_strength, reset_gpio.pin_state); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 341 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 342 | gpio_set_dir(reset_gpio.pin_id, 2); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 343 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 344 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[0]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 345 | mdelay(resetseq->sleep[0]); |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 346 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[1]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 347 | mdelay(resetseq->sleep[1]); |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 348 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[2]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 349 | mdelay(resetseq->sleep[2]); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 350 | } else if(!target_cont_splash_screen()) { |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 351 | gpio_set_value(reset_gpio.pin_id, 0); |
Aravind Venkateswaran | af24121 | 2013-11-04 16:46:46 -0800 | [diff] [blame] | 352 | if (pinfo->mipi.use_enable_gpio) |
| 353 | gpio_set_value(enable_gpio.pin_id, 0); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 354 | } |
| 355 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 356 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 357 | } |
| 358 | |
Kuogee Hsieh | 93bcff6 | 2014-08-22 14:02:08 -0700 | [diff] [blame] | 359 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 360 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 361 | uint32_t ret = NO_ERROR; |
| 362 | uint32_t ldocounter = 0; |
| 363 | uint32_t pm8x41_ldo_base = 0x13F00; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 364 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 365 | while (ldocounter < TOTAL_LDO_DEFINED) { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 366 | struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base + |
| 367 | 0x100 * ldo_entry_array[ldocounter].ldo_id), |
| 368 | ldo_entry_array[ldocounter].ldo_type); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 369 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 370 | dprintf(SPEW, "Setting %s\n", |
| 371 | ldo_entry_array[ldocounter].ldo_id); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 372 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 373 | /* Set voltage during power on */ |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 374 | if (enable) { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 375 | pm8x41_ldo_set_voltage(&ldo_entry, |
| 376 | ldo_entry_array[ldocounter].ldo_voltage); |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 377 | |
| 378 | pm8x41_ldo_control(&ldo_entry, enable); |
| 379 | |
| 380 | } else if(!target_cont_splash_screen() && |
| 381 | ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) { |
| 382 | pm8x41_ldo_control(&ldo_entry, enable); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 383 | } |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 384 | ldocounter++; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 385 | } |
| 386 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 387 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 388 | } |
| 389 | |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 390 | bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size) |
| 391 | { |
Veera Sundaram Sankaran | c95d675 | 2014-07-31 11:49:52 -0700 | [diff] [blame] | 392 | return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size); |
Ajay Singh Parmar | eef1d60 | 2014-03-15 17:41:52 -0700 | [diff] [blame] | 393 | } |
| 394 | |
Aravind Venkateswaran | 6385f7e | 2014-02-25 16:45:11 -0800 | [diff] [blame] | 395 | void target_display_init(const char *panel_name) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 396 | { |
Pradeep Jilagam | feb1598 | 2013-10-29 13:08:51 +0530 | [diff] [blame] | 397 | uint32_t panel_loop = 0; |
| 398 | uint32_t ret = 0; |
Aravind Venkateswaran | 148e0df | 2014-03-28 16:26:05 -0700 | [diff] [blame] | 399 | uint32_t fb_addr = MIPI_FB_ADDR; |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame^] | 400 | char cont_splash = '\0'; |
| 401 | |
| 402 | set_panel_cmd_string(panel_name, &cont_splash); |
Aravind Venkateswaran | 148e0df | 2014-03-28 16:26:05 -0700 | [diff] [blame] | 403 | |
Veera Sundaram Sankaran | 3b75882 | 2014-10-17 12:15:39 -0700 | [diff] [blame] | 404 | if (!strcmp(panel_name, NO_PANEL_CONFIG) |
| 405 | || !strcmp(panel_name, SIM_VIDEO_PANEL) |
| 406 | || !strcmp(panel_name, SIM_CMD_PANEL)) { |
Veera Sundaram Sankaran | c95d675 | 2014-07-31 11:49:52 -0700 | [diff] [blame] | 407 | dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n", |
Veera Sundaram Sankaran | 3b75882 | 2014-10-17 12:15:39 -0700 | [diff] [blame] | 408 | panel_name); |
Jeevan Shriram | b0d523a | 2014-05-30 12:55:17 -0700 | [diff] [blame] | 409 | return; |
| 410 | } |
| 411 | |
Aravind Venkateswaran | 148e0df | 2014-03-28 16:26:05 -0700 | [diff] [blame] | 412 | if (board_hardware_subtype() == HW_PLATFORM_SUBTYPE_QVGA) |
| 413 | fb_addr = MIPI_FB_ADDR_QVGA; |
Pradeep Jilagam | feb1598 | 2013-10-29 13:08:51 +0530 | [diff] [blame] | 414 | |
| 415 | do { |
Justin Philip | be9de5c | 2014-09-17 12:26:49 +0530 | [diff] [blame] | 416 | target_force_cont_splash_disable(false); |
Aravind Venkateswaran | 148e0df | 2014-03-28 16:26:05 -0700 | [diff] [blame] | 417 | ret = gcdb_display_init(panel_name, MDP_REV_50, fb_addr); |
Pradeep Jilagam | feb1598 | 2013-10-29 13:08:51 +0530 | [diff] [blame] | 418 | if (!ret || ret == ERR_NOT_SUPPORTED) { |
| 419 | break; |
| 420 | } else { |
| 421 | target_force_cont_splash_disable(true); |
| 422 | msm_display_off(); |
Pradeep Jilagam | feb1598 | 2013-10-29 13:08:51 +0530 | [diff] [blame] | 423 | } |
| 424 | } while (++panel_loop <= oem_panel_max_auto_detect_panels()); |
| 425 | |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame^] | 426 | if (cont_splash == '0') { |
| 427 | dprintf(INFO, "Forcing continuous splash disable\n"); |
| 428 | target_force_cont_splash_disable(true); |
| 429 | } |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 430 | } |
| 431 | |
Aravind Venkateswaran | dd50c1a | 2014-02-25 14:42:43 -0800 | [diff] [blame] | 432 | void target_display_shutdown(void) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 433 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 434 | gcdb_display_shutdown(); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 435 | } |