Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
| 11 | * * Neither the name of Code Aurora nor |
| 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <platform/iomap.h> |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 32 | #include <platform/clock.h> |
| 33 | #include <uart_dm.h> |
| 34 | #include <gsbi.h> |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame^] | 35 | #include <mmc.h> |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 36 | |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 37 | /* Set rate and enable the clock */ |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 38 | void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr) |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 39 | { |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 40 | unsigned int val = 0; |
| 41 | |
| 42 | /* Activate the reset for the M/N Counter */ |
| 43 | val = 1 << 7; |
| 44 | writel(val, ns_addr); |
| 45 | |
| 46 | /* Write the MD value into the MD register */ |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 47 | if (md_addr != 0x0) |
| 48 | writel(md, md_addr); |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 49 | |
| 50 | /* Write the ns value, and active reset for M/N Counter, again */ |
| 51 | val = 1 << 7; |
| 52 | val |= ns; |
| 53 | writel(val, ns_addr); |
| 54 | |
| 55 | /* De-activate the reset for M/N Counter */ |
| 56 | val = 1 << 7; |
| 57 | val = ~val; |
| 58 | val = val & readl(ns_addr); |
| 59 | writel(val, ns_addr); |
| 60 | |
| 61 | /* Enable the Clock Root */ |
| 62 | val = 1 << 11; |
| 63 | val = val | readl(ns_addr); |
| 64 | writel(val, ns_addr); |
| 65 | |
| 66 | /* Enable the Clock Branch */ |
| 67 | val = 1 << 9; |
| 68 | val = val | readl(ns_addr); |
| 69 | writel(val, ns_addr); |
| 70 | |
| 71 | /* Enable the M/N Counter */ |
| 72 | val = 1 << 8; |
| 73 | val = val | readl(ns_addr); |
| 74 | writel(val, ns_addr); |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 75 | } |
| 76 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 77 | /* Write the M,N,D values and enable the MMSS Clocks */ |
| 78 | void config_mmss_clk( uint32_t ns, |
| 79 | uint32_t md, |
| 80 | uint32_t cc, |
| 81 | uint32_t ns_addr, |
| 82 | uint32_t md_addr, |
| 83 | uint32_t cc_addr){ |
| 84 | unsigned int val = 0; |
| 85 | |
| 86 | clock_config(ns, md, ns_addr, md_addr); |
| 87 | |
| 88 | /* Enable MND counter */ |
| 89 | val = cc | (1 << 5); |
| 90 | val = val | readl(cc_addr); |
| 91 | writel(val, cc_addr); |
| 92 | |
| 93 | /* Enable the root of the clock tree */ |
| 94 | val = 1 << 2; |
| 95 | val = val | readl(cc_addr); |
| 96 | writel(val, cc_addr); |
| 97 | |
| 98 | /* Enable the Pixel Clock */ |
| 99 | val = 1 << 0; |
| 100 | val = val | readl(cc_addr); |
| 101 | writel(val, cc_addr); |
| 102 | |
| 103 | /* Force On */ |
| 104 | val = 1 << 31; |
| 105 | val = val | readl(cc_addr); |
| 106 | writel(val, cc_addr); |
| 107 | } |
| 108 | |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 109 | void pll8_enable(void) |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 110 | { |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 111 | unsigned int curr_value = 0; |
| 112 | |
| 113 | /* Vote for PLL8 to be enabled */ |
| 114 | curr_value = readl(MSM_BOOT_PLL_ENABLE_SC0); |
| 115 | curr_value |= (1 << 8); |
| 116 | writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0); |
| 117 | |
| 118 | /* Proceed only after PLL is enabled */ |
| 119 | while (!(readl(MSM_BOOT_PLL8_STATUS) & (1<<16))); |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | void hsusb_clock_init(void) |
| 123 | { |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 124 | /* TODO: Enable pll8 here */ |
| 125 | /* Setup USB AHB clock */ |
| 126 | |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 127 | /* Setup XCVR clock */ |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 128 | clock_config(USB_XCVR_CLK_NS, |
| 129 | USB_XCVR_CLK_MD, |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 130 | USB_HS1_XCVR_FS_CLK_NS, |
| 131 | USB_HS1_XCVR_FS_CLK_MD); |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 132 | } |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 133 | |
| 134 | /* Configure UART clock - based on the gsbi id */ |
| 135 | void clock_config_uart_dm(uint8_t id) |
| 136 | { |
| 137 | /* Enable gsbi_uart_clk */ |
| 138 | clock_config(UART_DM_CLK_NS_115200, |
| 139 | UART_DM_CLK_MD_115200, |
| 140 | GSBIn_UART_APPS_NS(id), |
| 141 | GSBIn_UART_APPS_MD(id)); |
| 142 | |
| 143 | |
| 144 | /* Enable gsbi_pclk */ |
| 145 | writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id)); |
| 146 | } |
| 147 | |
| 148 | /* Configure i2c clock */ |
| 149 | void clock_config_i2c(uint8_t id, uint32_t freq) |
| 150 | { |
| 151 | uint32_t ns; |
| 152 | uint32_t md; |
| 153 | |
| 154 | switch (freq) |
| 155 | { |
| 156 | case 24000000: |
| 157 | ns = I2C_CLK_NS_24MHz; |
| 158 | md = I2C_CLK_MD_24MHz; |
| 159 | break; |
| 160 | default: |
| 161 | ASSERT(0); |
| 162 | } |
| 163 | |
| 164 | clock_config(ns, md, GSBIn_QUP_APPS_NS(id), GSBIn_QUP_APPS_MD(id)); |
| 165 | |
| 166 | /* Enable the GSBI HCLK */ |
| 167 | writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id)); |
| 168 | } |
| 169 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 170 | void pll1_enable(void){ |
| 171 | uint32_t val = 0; |
| 172 | |
| 173 | /* Reset MND divider */ |
| 174 | val |= (1<<2); |
| 175 | writel(val, MM_PLL1_MODE_REG); |
| 176 | |
| 177 | /* Use PLL -- Disable Bypass */ |
| 178 | val |= (1<<1); |
| 179 | writel(val, MM_PLL1_MODE_REG); |
| 180 | |
| 181 | /* Activate PLL out control */ |
| 182 | val |= 1; |
| 183 | writel(val, MM_PLL1_MODE_REG); |
| 184 | |
| 185 | while (!readl(MM_PLL1_STATUS_REG)); |
| 186 | } |
| 187 | |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame^] | 188 | void config_mdp_lut_clk(void) |
| 189 | { |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 190 | /* Force on*/ |
| 191 | writel(MDP_LUT_VAL, MDP_LUT_CC_REG); |
| 192 | } |
| 193 | |
| 194 | /* Turn on MDP related clocks and pll's for MDP */ |
| 195 | void mdp_clock_init(void) |
| 196 | { |
| 197 | /* Turn on the PLL1, as source for MDP clock */ |
| 198 | pll1_enable(); |
| 199 | |
| 200 | /* Turn on MDP clk */ |
| 201 | config_mmss_clk(MDP_NS_VAL, MDP_MD_VAL, |
| 202 | MDP_CC_VAL, MDP_NS_REG, MDP_MD_REG, MDP_CC_REG); |
| 203 | |
| 204 | /* Seems to lose pixels without this from status 0x051E0048 */ |
| 205 | config_mdp_lut_clk(); |
| 206 | } |
| 207 | |
| 208 | /* Initialize all clocks needed by Display */ |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame^] | 209 | void mmss_clock_init(void) |
| 210 | { |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 211 | /* Configure Pixel clock */ |
| 212 | config_mmss_clk(PIXEL_NS_VAL, PIXEL_MD_VAL, PIXEL_CC_VAL, PIXEL_NS_REG, PIXEL_MD_REG, PIXEL_CC_REG); |
| 213 | |
| 214 | /* Configure DSI clock */ |
| 215 | config_mmss_clk(DSI_NS_VAL, DSI_MD_VAL, DSI_CC_VAL, DSI_NS_REG, DSI_MD_REG, DSI_CC_REG); |
| 216 | |
| 217 | /* Configure Byte clock */ |
| 218 | config_mmss_clk(BYTE_NS_VAL, 0x0, BYTE_CC_VAL, BYTE_NS_REG, 0x0, BYTE_CC_REG); |
| 219 | |
| 220 | /* Configure ESC clock */ |
| 221 | config_mmss_clk(ESC_NS_VAL, 0x0, ESC_CC_VAL, ESC_NS_REG, 0x0, ESC_CC_REG); |
| 222 | } |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame^] | 223 | |
| 224 | /* Intialize MMC clock */ |
| 225 | void clock_init_mmc(uint32_t interface) |
| 226 | { |
| 227 | /* Nothing to be done. */ |
| 228 | } |
| 229 | |
| 230 | /* Configure MMC clock */ |
| 231 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 232 | { |
| 233 | uint32_t reg = 0; |
| 234 | |
| 235 | switch(freq) |
| 236 | { |
| 237 | case MMC_CLK_400KHZ: |
| 238 | clock_config(SDC_CLK_NS_400KHZ, |
| 239 | SDC_CLK_MD_400KHZ, |
| 240 | SDC_NS(interface), |
| 241 | SDC_MD(interface)); |
| 242 | break; |
| 243 | case MMC_CLK_48MHZ: |
| 244 | case MMC_CLK_50MHZ: /* Max supported is 48MHZ */ |
| 245 | clock_config(SDC_CLK_NS_48MHZ, |
| 246 | SDC_CLK_MD_48MHZ, |
| 247 | SDC_NS(interface), |
| 248 | SDC_MD(interface)); |
| 249 | break; |
| 250 | default: |
| 251 | ASSERT(0); |
| 252 | |
| 253 | } |
| 254 | |
| 255 | reg |= MMC_BOOT_MCI_CLK_ENABLE; |
| 256 | reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 257 | reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; |
| 258 | writel( reg, MMC_BOOT_MCI_CLK ); |
| 259 | } |