Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008, Google Inc. |
| 3 | * All rights reserved. |
Tanya Brokhman | 646eedb | 2015-01-06 23:09:54 +0200 | [diff] [blame] | 4 | * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved. |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * * Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * * Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in |
| 12 | * the documentation and/or other materials provided with the |
| 13 | * distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 16 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 17 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 18 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 19 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 21 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 22 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 23 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 24 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 25 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 26 | * SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <qpic_nand.h> |
| 30 | #include <bam.h> |
| 31 | #include <dev/flash.h> |
| 32 | #include <lib/ptable.h> |
| 33 | #include <debug.h> |
| 34 | #include <string.h> |
| 35 | #include <malloc.h> |
Sridhar Parasuram | fb0d9c8 | 2015-02-02 15:23:13 -0800 | [diff] [blame] | 36 | #include <bits.h> |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 37 | #include <sys/types.h> |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 38 | #include <platform.h> |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 39 | #include <platform/clock.h> |
Smita Ghosh | f5431c6 | 2014-09-18 14:11:14 -0700 | [diff] [blame] | 40 | #include <platform/iomap.h> |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 41 | |
| 42 | static uint32_t nand_base; |
| 43 | static struct ptable *flash_ptable; |
| 44 | static struct flash_info flash; |
| 45 | static unsigned char *flash_spare_bytes; |
| 46 | static uint32_t cfg0; |
| 47 | static uint32_t cfg1; |
| 48 | static uint32_t cfg0_raw; |
| 49 | static uint32_t cfg1_raw; |
| 50 | static uint32_t ecc_bch_cfg; |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 51 | static uint32_t ecc_cfg_raw; |
| 52 | static uint32_t ecc_parity_bytes; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 53 | |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 54 | struct cmd_element ce_array[100] __attribute__ ((aligned(16))); |
| 55 | struct cmd_element ce_read_array[20] __attribute__ ((aligned(16))); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 56 | |
| 57 | #define QPIC_BAM_DATA_FIFO_SIZE 64 |
| 58 | #define QPIC_BAM_CMD_FIFO_SIZE 64 |
| 59 | |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 60 | #define THRESHOLD_BIT_FLIPS 4 |
| 61 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 62 | static struct bam_desc cmd_desc_fifo[QPIC_BAM_CMD_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE))); |
| 63 | static struct bam_desc data_desc_fifo[QPIC_BAM_DATA_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE))); |
| 64 | |
| 65 | static struct bam_instance bam; |
| 66 | static uint8_t *bbtbl; |
| 67 | |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 68 | static uint8_t* rdwr_buf; |
| 69 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 70 | static struct flash_id supported_flash[] = { |
Sridhar Parasuram | fb0d9c8 | 2015-02-02 15:23:13 -0800 | [diff] [blame] | 71 | /* Flash ID Flash ID2 ID Mask ID Mask2 Density(MB) Wid Pgsz Blksz oobsz 8-bit ECCf */ |
| 72 | {0x1590AC2C, 0x56, 0xFFFFFFFF, 0xFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 0}, |
| 73 | {0x1590AC2C, 0x57, 0xFFFFFFFF, 0xFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 1}, |
| 74 | {0x1590AA2C, 0x06, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0xE0, 1}, |
| 75 | {0x2690AC2C, 0x54, 0xFFFFFFFF, 0x0, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1}, |
| 76 | {0x1590ACAD, 0, 0xFFFFFFFF, 0x0, 0x20000000, 0, 2048, 0x00020000, 0x80, 0}, |
| 77 | {0x9590DC2C, 0x56, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0x40, 0}, |
| 78 | {0x1590aa98, 0x76, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0x80, 1}, |
vijay kumar | 94451f8 | 2015-07-23 12:41:24 +0530 | [diff] [blame^] | 79 | {0x2690A32C, 0x64, 0xFFFFFFFF, 0x0, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1}, |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 80 | /* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 81 | }; |
| 82 | |
Tanya Brokhman | 72b44dc | 2015-01-07 10:20:05 +0200 | [diff] [blame] | 83 | static int qpic_nand_mark_badblock(uint32_t page); |
| 84 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 85 | static void |
| 86 | qpic_nand_wait_for_cmd_exec(uint32_t num_desc) |
| 87 | { |
| 88 | /* Create a read/write event to notify the periperal of the added desc. */ |
| 89 | bam_sys_gen_event(&bam, CMD_PIPE_INDEX, num_desc); |
| 90 | |
| 91 | /* Wait for the descriptors to be processed */ |
| 92 | bam_wait_for_interrupt(&bam, CMD_PIPE_INDEX, P_PRCSD_DESC_EN_MASK); |
| 93 | |
| 94 | /* Read offset update for the circular FIFO */ |
| 95 | bam_read_offset_update(&bam, CMD_PIPE_INDEX); |
| 96 | } |
| 97 | |
| 98 | static void |
| 99 | qpic_nand_wait_for_data(uint32_t pipe_num) |
| 100 | { |
| 101 | /* Wait for the descriptors to be processed */ |
| 102 | bam_wait_for_interrupt(&bam, pipe_num, P_PRCSD_DESC_EN_MASK); |
| 103 | |
| 104 | /* Read offset update for the circular FIFO */ |
| 105 | bam_read_offset_update(&bam, pipe_num); |
| 106 | } |
| 107 | |
| 108 | static uint32_t |
| 109 | qpic_nand_read_reg(uint32_t reg_addr, |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 110 | uint8_t flags) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 111 | { |
| 112 | uint32_t val; |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 113 | struct cmd_element *cmd_list_read_ptr = ce_read_array; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 114 | |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 115 | bam_add_cmd_element(cmd_list_read_ptr, reg_addr, (uint32_t)PA((addr_t)&val), CE_READ_TYPE); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 116 | |
| 117 | /* Enqueue the desc for the above command */ |
| 118 | bam_add_one_desc(&bam, |
| 119 | CMD_PIPE_INDEX, |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 120 | (unsigned char*)PA((addr_t)cmd_list_read_ptr), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 121 | BAM_CE_SIZE, |
| 122 | BAM_DESC_CMD_FLAG| BAM_DESC_INT_FLAG | flags); |
| 123 | |
| 124 | qpic_nand_wait_for_cmd_exec(1); |
| 125 | |
| 126 | return val; |
| 127 | } |
| 128 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 129 | /* Assume the BAM is in a locked state. */ |
| 130 | void |
sundarajan srinivasan | 7ced648 | 2013-03-21 16:01:18 -0700 | [diff] [blame] | 131 | qpic_nand_erased_status_reset(struct cmd_element *cmd_list_ptr, uint8_t flags) |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 132 | { |
| 133 | uint32_t val = 0; |
| 134 | |
| 135 | /* Reset the Erased Codeword/Page detection controller. */ |
| 136 | val = NAND_ERASED_CW_DETECT_CFG_RESET_CTRL; |
| 137 | |
| 138 | bam_add_cmd_element(cmd_list_ptr, NAND_ERASED_CW_DETECT_CFG, val, CE_WRITE_TYPE); |
| 139 | |
| 140 | /* Enqueue the desc for the above command */ |
| 141 | bam_add_one_desc(&bam, |
| 142 | CMD_PIPE_INDEX, |
| 143 | (unsigned char*)cmd_list_ptr, |
| 144 | BAM_CE_SIZE, |
sundarajan srinivasan | 7ced648 | 2013-03-21 16:01:18 -0700 | [diff] [blame] | 145 | BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG | flags); |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 146 | |
| 147 | qpic_nand_wait_for_cmd_exec(1); |
| 148 | |
| 149 | /* Enable the Erased Codeword/Page detection |
| 150 | * controller to check the data as it arrives. |
| 151 | * Also disable ECC reporting for an erased CW. |
| 152 | */ |
| 153 | val = NAND_ERASED_CW_DETECT_CFG_ACTIVATE_CTRL | NAND_ERASED_CW_DETECT_ERASED_CW_ECC_MASK; |
| 154 | |
| 155 | bam_add_cmd_element(cmd_list_ptr, NAND_ERASED_CW_DETECT_CFG, val, CE_WRITE_TYPE); |
| 156 | |
| 157 | /* Enqueue the desc for the above command */ |
| 158 | bam_add_one_desc(&bam, |
| 159 | CMD_PIPE_INDEX, |
| 160 | (unsigned char*)cmd_list_ptr, |
| 161 | BAM_CE_SIZE, |
| 162 | BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG); |
| 163 | |
| 164 | qpic_nand_wait_for_cmd_exec(1); |
| 165 | } |
| 166 | |
| 167 | static nand_result_t |
| 168 | qpic_nand_check_status(uint32_t status) |
| 169 | { |
| 170 | uint32_t erase_sts; |
| 171 | |
| 172 | /* Check for errors */ |
| 173 | if (status & NAND_FLASH_ERR) |
| 174 | { |
| 175 | /* Check if this is an ECC error on an erased page. */ |
| 176 | if (status & NAND_FLASH_OP_ERR) |
| 177 | { |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 178 | erase_sts = qpic_nand_read_reg(NAND_ERASED_CW_DETECT_STATUS, 0); |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 179 | if ((erase_sts & (1 << NAND_ERASED_CW_DETECT_STATUS_PAGE_ALL_ERASED))) |
| 180 | { |
| 181 | /* Mask the OP ERROR. */ |
| 182 | status &= ~NAND_FLASH_OP_ERR; |
sundarajan srinivasan | 7ced648 | 2013-03-21 16:01:18 -0700 | [diff] [blame] | 183 | qpic_nand_erased_status_reset(ce_array, 0); |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 184 | } |
| 185 | } |
| 186 | |
| 187 | /* ECC error flagged on an erased page read. |
| 188 | * Ignore and return success. |
| 189 | */ |
| 190 | if (!(status & NAND_FLASH_ERR)) |
| 191 | return NANDC_RESULT_SUCCESS; |
| 192 | |
| 193 | dprintf(CRITICAL, "Nand Flash error. Status = %d\n", status); |
| 194 | |
| 195 | if (status & NAND_FLASH_TIMEOUT_ERR) |
| 196 | return NANDC_RESULT_TIMEOUT; |
| 197 | else |
| 198 | return NANDC_RESULT_FAILURE; |
| 199 | } |
| 200 | |
| 201 | return NANDC_RESULT_SUCCESS; |
| 202 | } |
| 203 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 204 | static uint32_t |
| 205 | qpic_nand_fetch_id(struct flash_info *flash) |
| 206 | { |
| 207 | struct cmd_element *cmd_list_ptr = ce_array; |
| 208 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 209 | int num_desc = 0; |
| 210 | uint32_t status; |
Sridhar Parasuram | fb0d9c8 | 2015-02-02 15:23:13 -0800 | [diff] [blame] | 211 | uint32_t id, id2; |
| 212 | uint32_t flash_cmd = NAND_CMD_FETCH_ID | BIT(19); //bit 19 needs to be set to get extended NAND ID |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 213 | uint32_t exec_cmd = 1; |
| 214 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 215 | |
| 216 | /* Issue the Fetch id command to the NANDc */ |
| 217 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)flash_cmd, CE_WRITE_TYPE); |
| 218 | cmd_list_ptr++; |
| 219 | |
| 220 | /* Execute the cmd */ |
| 221 | bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)exec_cmd, CE_WRITE_TYPE); |
| 222 | cmd_list_ptr++; |
| 223 | |
| 224 | /* Prepare the cmd desc for the above commands */ |
| 225 | bam_add_one_desc(&bam, |
| 226 | CMD_PIPE_INDEX, |
| 227 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 228 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 229 | BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG | |
| 230 | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG); |
| 231 | |
| 232 | /* Keep track of the number of desc added. */ |
| 233 | num_desc++; |
| 234 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 235 | |
| 236 | cmd_list_ptr_start = ce_array; |
| 237 | cmd_list_ptr = ce_array; |
| 238 | |
| 239 | /* Read the status register */ |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 240 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 241 | |
| 242 | /* Check for errors */ |
| 243 | nand_ret = qpic_nand_check_status(status); |
| 244 | if (nand_ret) |
| 245 | { |
| 246 | dprintf( CRITICAL, "Read ID cmd status failed\n"); |
| 247 | goto qpic_nand_fetch_id_err; |
| 248 | } |
| 249 | |
| 250 | /* Read the id */ |
Sridhar Parasuram | fb0d9c8 | 2015-02-02 15:23:13 -0800 | [diff] [blame] | 251 | id = qpic_nand_read_reg(NAND_READ_ID, 0); |
| 252 | id2 = qpic_nand_read_reg(NAND_READ_ID2, BAM_DESC_UNLOCK_FLAG); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 253 | |
| 254 | flash->id = id; |
Sridhar Parasuram | fb0d9c8 | 2015-02-02 15:23:13 -0800 | [diff] [blame] | 255 | flash->id2 = id2; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 256 | flash->vendor = id & 0xff; |
| 257 | flash->device = (id >> 8) & 0xff; |
| 258 | flash->dev_cfg = (id >> 24) & 0xFF; |
| 259 | flash->widebus = 0; |
| 260 | flash->widebus &= (id >> 24) & 0xFF; |
| 261 | flash->widebus = flash->widebus? 1: 0; |
| 262 | |
| 263 | qpic_nand_fetch_id_err: |
| 264 | return nand_ret; |
| 265 | } |
| 266 | |
| 267 | static int |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 268 | qpic_bam_init(struct qpic_nand_init_config *config) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 269 | { |
| 270 | uint32_t bam_ret = NANDC_RESULT_SUCCESS; |
| 271 | |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 272 | bam.base = config->bam_base; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 273 | /* Set Read pipe params. */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 274 | bam.pipe[DATA_PRODUCER_PIPE_INDEX].pipe_num = config->pipes.read_pipe; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 275 | /* System consumer */ |
| 276 | bam.pipe[DATA_PRODUCER_PIPE_INDEX].trans_type = BAM2SYS; |
| 277 | bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.size = QPIC_BAM_DATA_FIFO_SIZE; |
| 278 | bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.head = data_desc_fifo; |
Deepa Dinamani | 536d3f8 | 2013-07-09 13:05:56 -0700 | [diff] [blame] | 279 | bam.pipe[DATA_PRODUCER_PIPE_INDEX].lock_grp = config->pipes.read_pipe_grp; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 280 | |
| 281 | /* Set Write pipe params. */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 282 | bam.pipe[DATA_CONSUMER_PIPE_INDEX].pipe_num = config->pipes.write_pipe; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 283 | /* System producer */ |
| 284 | bam.pipe[DATA_CONSUMER_PIPE_INDEX].trans_type = SYS2BAM; |
| 285 | bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.size = QPIC_BAM_DATA_FIFO_SIZE; |
| 286 | bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.head = data_desc_fifo; |
Deepa Dinamani | 536d3f8 | 2013-07-09 13:05:56 -0700 | [diff] [blame] | 287 | bam.pipe[DATA_CONSUMER_PIPE_INDEX].lock_grp = config->pipes.write_pipe_grp; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 288 | |
| 289 | /* Set Cmd pipe params. */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 290 | bam.pipe[CMD_PIPE_INDEX].pipe_num = config->pipes.cmd_pipe; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 291 | /* System consumer */ |
Sundarajan Srinivasan | 357c35a | 2013-07-23 17:00:54 -0700 | [diff] [blame] | 292 | bam.pipe[CMD_PIPE_INDEX].trans_type = SYS2BAM; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 293 | bam.pipe[CMD_PIPE_INDEX].fifo.size = QPIC_BAM_CMD_FIFO_SIZE; |
| 294 | bam.pipe[CMD_PIPE_INDEX].fifo.head = cmd_desc_fifo; |
Deepa Dinamani | 536d3f8 | 2013-07-09 13:05:56 -0700 | [diff] [blame] | 295 | bam.pipe[CMD_PIPE_INDEX].lock_grp = config->pipes.cmd_pipe_grp; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 296 | |
| 297 | /* Programs the threshold for BAM transfer |
| 298 | * When this threshold is reached, BAM signals the peripheral via the pipe_bytes_available |
| 299 | * interface. |
| 300 | * The peripheral is signalled with this notification in the following cases: |
| 301 | * a. It has accumulated all the descriptors. |
| 302 | * b. It has accumulated more than threshold bytes. |
| 303 | * c. It has reached EOT (End Of Transfer). |
| 304 | * Note: this value needs to be set by the h/w folks and is specific for each peripheral. |
| 305 | */ |
| 306 | bam.threshold = 32; |
| 307 | |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 308 | /* Set the EE. */ |
| 309 | bam.ee = config->ee; |
| 310 | |
| 311 | /* Set the max desc length for this BAM. */ |
| 312 | bam.max_desc_len = config->max_desc_len; |
| 313 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 314 | /* BAM Init. */ |
| 315 | bam_init(&bam); |
| 316 | |
| 317 | /* Initialize BAM QPIC read pipe */ |
| 318 | bam_sys_pipe_init(&bam, DATA_PRODUCER_PIPE_INDEX); |
| 319 | |
| 320 | /* Init read fifo */ |
| 321 | bam_ret = bam_pipe_fifo_init(&bam, bam.pipe[DATA_PRODUCER_PIPE_INDEX].pipe_num); |
| 322 | |
| 323 | if (bam_ret) |
| 324 | { |
| 325 | dprintf(CRITICAL, "QPIC:NANDc BAM Read FIFO init error\n"); |
| 326 | bam_ret = NANDC_RESULT_FAILURE; |
| 327 | goto qpic_nand_bam_init_error; |
| 328 | } |
| 329 | |
| 330 | /* Initialize BAM QPIC write pipe */ |
| 331 | bam_sys_pipe_init(&bam, DATA_CONSUMER_PIPE_INDEX); |
| 332 | |
| 333 | /* Init write fifo. Use the same fifo as read fifo. */ |
| 334 | bam_ret = bam_pipe_fifo_init(&bam, bam.pipe[DATA_CONSUMER_PIPE_INDEX].pipe_num); |
| 335 | |
| 336 | if (bam_ret) |
| 337 | { |
| 338 | dprintf(CRITICAL, "QPIC: NANDc: BAM Write FIFO init error\n"); |
| 339 | bam_ret = NANDC_RESULT_FAILURE; |
| 340 | goto qpic_nand_bam_init_error; |
| 341 | } |
| 342 | |
| 343 | /* Initialize BAM QPIC cmd pipe */ |
| 344 | bam_sys_pipe_init(&bam, CMD_PIPE_INDEX); |
| 345 | |
| 346 | /* Init cmd fifo */ |
| 347 | bam_ret = bam_pipe_fifo_init(&bam, bam.pipe[CMD_PIPE_INDEX].pipe_num); |
| 348 | |
| 349 | if (bam_ret) |
| 350 | { |
| 351 | dprintf(CRITICAL, "QPIC:NANDc BAM CMD FIFO init error\n"); |
| 352 | bam_ret = NANDC_RESULT_FAILURE; |
| 353 | goto qpic_nand_bam_init_error; |
| 354 | } |
| 355 | |
| 356 | qpic_nand_bam_init_error: |
| 357 | return bam_ret; |
| 358 | } |
| 359 | |
| 360 | /* Adds command elements for addr and cfg register writes. |
| 361 | * cfg: Defines the configuration for the flash cmd. |
| 362 | * start: Address where the command elements are added. |
| 363 | * |
| 364 | * Returns the address where the next cmd element can be added. |
| 365 | */ |
| 366 | static struct cmd_element* |
| 367 | qpic_nand_add_addr_n_cfg_ce(struct cfg_params *cfg, |
| 368 | struct cmd_element *start) |
| 369 | { |
| 370 | struct cmd_element *cmd_list_ptr = start; |
| 371 | |
| 372 | bam_add_cmd_element(cmd_list_ptr, NAND_ADDR0, (uint32_t)cfg->addr0, CE_WRITE_TYPE); |
| 373 | cmd_list_ptr++; |
| 374 | bam_add_cmd_element(cmd_list_ptr, NAND_ADDR1, (uint32_t)cfg->addr1, CE_WRITE_TYPE); |
| 375 | cmd_list_ptr++; |
| 376 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_CFG0, (uint32_t)cfg->cfg0, CE_WRITE_TYPE); |
| 377 | cmd_list_ptr++; |
| 378 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_CFG1, (uint32_t)cfg->cfg1, CE_WRITE_TYPE); |
| 379 | cmd_list_ptr++; |
| 380 | |
| 381 | return cmd_list_ptr; |
| 382 | } |
| 383 | |
| 384 | |
| 385 | static struct cmd_element* |
| 386 | qpic_nand_add_onfi_probe_ce(struct onfi_probe_params *params, |
| 387 | struct cmd_element *start) |
| 388 | { |
| 389 | struct cmd_element *cmd_list_ptr = start; |
| 390 | |
| 391 | cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(¶ms->cfg, cmd_list_ptr); |
| 392 | |
| 393 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD1, (uint32_t)params->dev_cmd1, CE_WRITE_TYPE); |
| 394 | cmd_list_ptr++; |
| 395 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD_VLD, (uint32_t)params->vld, CE_WRITE_TYPE); |
| 396 | cmd_list_ptr++; |
| 397 | bam_add_cmd_element(cmd_list_ptr, NAND_READ_LOCATION_n(0), (uint32_t)params->cfg.addr_loc_0, CE_WRITE_TYPE); |
| 398 | cmd_list_ptr++; |
| 399 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)params->cfg.cmd, CE_WRITE_TYPE); |
| 400 | cmd_list_ptr++; |
| 401 | bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)params->cfg.exec, CE_WRITE_TYPE); |
| 402 | cmd_list_ptr++; |
| 403 | |
| 404 | return cmd_list_ptr; |
| 405 | } |
| 406 | |
| 407 | static int |
| 408 | onfi_probe_cmd_exec(struct onfi_probe_params *params, |
| 409 | unsigned char* data_ptr, |
| 410 | int data_len) |
| 411 | { |
| 412 | struct cmd_element *cmd_list_ptr = ce_array; |
| 413 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 414 | int num_desc = 0; |
| 415 | uint32_t status = 0; |
| 416 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 417 | uint8_t desc_flags = BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG |
| 418 | | BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG; |
| 419 | |
| 420 | params->cfg.addr_loc_0 = 0; |
| 421 | params->cfg.addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1); |
| 422 | params->cfg.addr_loc_0 |= NAND_RD_LOC_OFFSET(0); |
| 423 | params->cfg.addr_loc_0 |= NAND_RD_LOC_SIZE(data_len); |
| 424 | |
| 425 | cmd_list_ptr = qpic_nand_add_onfi_probe_ce(params, cmd_list_ptr); |
| 426 | |
| 427 | /* Enqueue the desc for the above commands */ |
| 428 | bam_add_one_desc(&bam, |
| 429 | CMD_PIPE_INDEX, |
| 430 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 431 | PA((addr_t)(uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 432 | desc_flags); |
| 433 | |
| 434 | cmd_list_ptr_start = cmd_list_ptr; |
| 435 | num_desc++; |
| 436 | |
| 437 | /* Add Data desc */ |
| 438 | bam_add_desc(&bam, |
| 439 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 440 | (unsigned char *)PA((addr_t)data_ptr), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 441 | data_len, |
| 442 | BAM_DESC_INT_FLAG); |
| 443 | |
| 444 | /* Wait for the commands to be executed */ |
| 445 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 446 | |
| 447 | /* Read buffer status and check for errors. */ |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 448 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 449 | |
| 450 | if (qpic_nand_check_status(status)) |
| 451 | { |
| 452 | nand_ret = NANDC_RESULT_FAILURE; |
| 453 | goto onfi_probe_exec_err; |
| 454 | } |
| 455 | |
| 456 | /* Wait for data to be available */ |
| 457 | qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); |
| 458 | |
| 459 | /* Check for errors */ |
| 460 | nand_ret = qpic_nand_check_status(status); |
| 461 | |
| 462 | onfi_probe_exec_err: |
| 463 | return nand_ret; |
| 464 | } |
| 465 | |
| 466 | /* TODO: check why both vld and cmd need to be written. */ |
| 467 | void |
| 468 | qpic_nand_onfi_probe_cleanup(uint32_t vld, uint32_t dev_cmd1) |
| 469 | { |
| 470 | struct cmd_element *cmd_list_ptr = ce_array; |
| 471 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 472 | |
| 473 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD1, dev_cmd1, CE_WRITE_TYPE); |
| 474 | cmd_list_ptr++; |
| 475 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD_VLD, vld, CE_WRITE_TYPE); |
| 476 | cmd_list_ptr++; |
| 477 | |
| 478 | /* Enqueue the desc for the above commands */ |
| 479 | bam_add_one_desc(&bam, |
| 480 | CMD_PIPE_INDEX, |
| 481 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 482 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 483 | BAM_DESC_UNLOCK_FLAG | BAM_DESC_CMD_FLAG| BAM_DESC_INT_FLAG); |
| 484 | |
| 485 | qpic_nand_wait_for_cmd_exec(1); |
| 486 | } |
| 487 | |
| 488 | static int |
| 489 | qpic_nand_onfi_save_params(struct onfi_param_page *param_page, struct flash_info *flash) |
| 490 | { |
| 491 | int onfi_ret = NANDC_RESULT_SUCCESS; |
| 492 | uint32_t ecc_bits; |
| 493 | |
| 494 | onfi_ret = qpic_nand_fetch_id(flash); |
| 495 | |
| 496 | if (onfi_ret) |
| 497 | { |
| 498 | dprintf(CRITICAL, "Fetch ID cmd failed\n"); |
| 499 | goto onfi_save_params_err; |
| 500 | } |
| 501 | |
| 502 | flash->page_size = param_page->data_per_pg; |
| 503 | flash->block_size = param_page->pgs_per_blk * flash->page_size; |
| 504 | flash->num_blocks = param_page->blks_per_LUN; |
| 505 | flash->widebus = param_page->feature_supported & 0x1; |
| 506 | flash->density = param_page->blks_per_LUN * flash->blksize; |
| 507 | flash->spare_size = param_page->spare_per_pg; |
| 508 | ecc_bits = param_page->num_bits_ecc_correctability; |
| 509 | flash->num_pages_per_blk = param_page->pgs_per_blk; |
| 510 | flash->num_pages_per_blk_mask = param_page->pgs_per_blk - 1; |
| 511 | |
| 512 | if (ecc_bits >= 8) |
| 513 | flash->ecc_width = NAND_WITH_8_BIT_ECC; |
| 514 | else |
| 515 | flash->ecc_width = NAND_WITH_4_BIT_ECC; |
| 516 | |
| 517 | onfi_save_params_err: |
| 518 | return onfi_ret; |
| 519 | } |
| 520 | |
| 521 | static void |
| 522 | qpic_nand_save_config(struct flash_info *flash) |
| 523 | { |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 524 | uint32_t spare_bytes = 0; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 525 | |
| 526 | /* Save Configurations */ |
| 527 | flash->cws_per_page = flash->page_size >> NAND_CW_DIV_RIGHT_SHIFT; |
| 528 | |
Deepa Dinamani | 16663a6 | 2013-02-07 16:25:59 -0800 | [diff] [blame] | 529 | /* Verify that we have enough buffer to handle all the cws in a page. */ |
| 530 | ASSERT(flash->cws_per_page <= QPIC_NAND_MAX_CWS_IN_PAGE); |
| 531 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 532 | /* Codeword Size = UD_SIZE_BYTES + ECC_PARITY_SIZE_BYTES |
| 533 | * + SPARE_SIZE_BYTES + Bad Block size |
| 534 | */ |
| 535 | if (flash->ecc_width & NAND_WITH_8_BIT_ECC) |
| 536 | { |
| 537 | flash->cw_size = NAND_CW_SIZE_8_BIT_ECC; |
| 538 | ecc_bch_cfg |= (1 << NAND_DEV0_ECC_MODE_SHIFT); /* Use 8-bit ecc */ |
| 539 | |
| 540 | if (flash->widebus) |
| 541 | { |
| 542 | cfg0 |= (0 << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); /* spare size bytes in each CW */ |
| 543 | ecc_bch_cfg |= (14 << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT); /* parity bytes in each CW */ |
| 544 | } |
| 545 | else |
| 546 | { |
| 547 | cfg0 |= (2 << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); /* spare size bytes in each CW */ |
| 548 | ecc_bch_cfg |= (13 << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT); /* parity bytes in each CW */ |
| 549 | } |
| 550 | } |
| 551 | else |
| 552 | { |
| 553 | flash->cw_size = NAND_CW_SIZE_4_BIT_ECC; |
| 554 | |
| 555 | if (flash->widebus) |
| 556 | { |
| 557 | cfg0 |= (2 << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); /* spare size bytes in each CW */ |
| 558 | ecc_bch_cfg |= (8 << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT); /* parity bytes in each CW */ |
| 559 | } |
| 560 | else |
| 561 | { |
| 562 | cfg0 |= (4 << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); /* spare size bytes in each CW */ |
| 563 | ecc_bch_cfg |= (7 << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT); /* parity bytes in each CW */ |
| 564 | } |
| 565 | } |
| 566 | |
| 567 | /* BAD_BLOCK_BYTE_NUM = Page Size - |
| 568 | * (CW_PER_PAGE * Codeword Size) + 1 |
| 569 | * Note: Set CW_PER_PAGE to 1 less than the actual number. |
| 570 | */ |
| 571 | flash->bad_blk_loc = flash->page_size - flash->cw_size * (flash->cws_per_page - 1) + 1; |
| 572 | |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 573 | /* Calculate the parity and spare bytes */ |
| 574 | ecc_parity_bytes = (flash->ecc_width & NAND_WITH_8_BIT_ECC) ? (flash->widebus ? 14 : 13) : (flash->widebus ? 8 : 7) ; |
| 575 | spare_bytes = flash->cw_size - (USER_DATA_BYTES_PER_CW + ecc_parity_bytes); |
| 576 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 577 | cfg0 |= ((flash->cws_per_page - 1) << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT) /* 4/8 cw/pg for 2/4k */ |
| 578 | |(DATA_BYTES_IN_IMG_PER_CW << NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT) /* 516 user data bytes */ |
| 579 | |(5 << NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT) /* 5 address cycles */ |
| 580 | |(0 << NAND_DEV0_CFG0_DIS_STS_AFTER_WR_SHIFT);/* Send read status cmd after each write. */ |
| 581 | |
| 582 | cfg1 |= (7 << NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT) /* 8 recovery cycles */ |
| 583 | |(0 << NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT) /* Allow CS deassertion */ |
| 584 | |(flash->bad_blk_loc << NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT)/* Bad block marker location */ |
| 585 | |(0 << NAND_DEV0_CFG1_BAD_BLK_IN_SPARE_SHIFT) /* Bad block in user data area */ |
| 586 | |(2 << NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT) /* 8 cycle tWB/tRB */ |
| 587 | |(flash->widebus << NAND_DEV0_CFG1_WIDE_BUS_SHIFT); /* preserve wide flash flag */ |
| 588 | |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 589 | cfg0_raw = ((flash->cws_per_page - 1) << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 590 | |(5 << NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT) |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 591 | |(512 << NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT) |
| 592 | | (spare_bytes << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 593 | |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 594 | cfg1_raw = (2 << NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 595 | | (1 << NAND_DEV0_CFG1_BAD_BLK_IN_SPARE_SHIFT) |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 596 | | (21 << NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT) |
| 597 | | (0 << NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT) |
| 598 | | (7 << NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 599 | | (flash->widebus << NAND_DEV0_CFG1_WIDE_BUS_SHIFT) |
| 600 | |1 ; /* to disable reed solomon ecc..this feild is now read only. */ |
| 601 | |
| 602 | ecc_bch_cfg |= (0 << NAND_DEV0_ECC_DISABLE_SHIFT) /* Enable ECC */ |
| 603 | | (0 << NAND_DEV0_ECC_SW_RESET_SHIFT) /* Put ECC core in op mode */ |
| 604 | | (DATA_BYTES_IN_IMG_PER_CW << NAND_DEV0_ECC_NUM_DATA_BYTES) |
| 605 | | (1 << NAND_DEV0_ECC_FORCE_CLK_OPEN_SHIFT); /* Enable all clocks */ |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 606 | |
| 607 | ecc_cfg_raw = (1 << NAND_DEV0_ECC_FORCE_CLK_OPEN_SHIFT) |
| 608 | | (DATA_BYTES_IN_IMG_PER_CW << NAND_DEV0_ECC_NUM_DATA_BYTES) |
| 609 | | (ecc_parity_bytes << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT) |
| 610 | | (0 << NAND_DEV0_ECC_SW_RESET_SHIFT) |
| 611 | | (1 << NAND_DEV0_ECC_DISABLE_SHIFT); |
| 612 | |
| 613 | #if DEBUG_QPIC_NAND |
| 614 | dprintf(INFO, "CFG0: 0x%08x CFG1: 0x%08x\n", cfg0, cfg1); |
| 615 | dprintf(INFO, "CFG0_RAW: 0x%08x CFG1_RAW: 0x%08x\n", cfg0_raw, cfg1_raw); |
| 616 | dprintf(INFO, "ECC_BCH_CFG: 0x%08x ECC_CFG_RAW: 0x%08x\n", ecc_bch_cfg, ecc_cfg_raw); |
| 617 | #endif |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | /* Onfi probe should issue the following commands to the flash device: |
| 621 | * 1. Read ID - with addr ONFI_READ_ID_ADDR. |
| 622 | * This returns the ONFI ASCII string indicating support for ONFI. |
| 623 | * 2. Read Prameter Page - with addr ONFI_READ_PARAM_PAGE_ADDR. |
| 624 | * This returns the params for the device. |
| 625 | * Each command inturn issues commands- ADDR0, ADDR1, chip_select, |
| 626 | * cfg0, cfg1, cmd_vld, dev_cmd1, read_loc0, flash, exec. |
| 627 | */ |
| 628 | static int |
| 629 | qpic_nand_onfi_probe(struct flash_info *flash) |
| 630 | { |
| 631 | struct onfi_probe_params params; |
| 632 | uint32_t vld; |
| 633 | uint32_t dev_cmd1; |
| 634 | unsigned char *buffer; |
| 635 | unsigned char onfi_str[4]; |
| 636 | uint32_t *id; |
| 637 | struct onfi_param_page *param_page; |
| 638 | int onfi_ret = NANDC_RESULT_SUCCESS; |
| 639 | |
| 640 | /* Allocate memory required to read the onfi param page */ |
| 641 | buffer = (unsigned char*) malloc(ONFI_READ_PARAM_PAGE_BUFFER_SIZE); |
Maria Yu | 7190974 | 2014-07-04 17:30:00 +0800 | [diff] [blame] | 642 | ASSERT(buffer != NULL); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 643 | |
| 644 | /* Read the vld and dev_cmd1 registers before modifying */ |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 645 | vld = qpic_nand_read_reg(NAND_DEV_CMD_VLD, 0); |
| 646 | dev_cmd1 = qpic_nand_read_reg(NAND_DEV_CMD1, 0); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 647 | |
| 648 | /* Initialize flash cmd */ |
| 649 | params.cfg.cmd = NAND_CMD_PAGE_READ; |
| 650 | params.cfg.exec = 1; |
| 651 | |
| 652 | /* Execute Read ID cmd */ |
| 653 | |
| 654 | /* Initialize the config */ |
| 655 | params.cfg.cfg0 = NAND_CFG0_RAW_ONFI_ID; |
| 656 | params.cfg.cfg1 = NAND_CFG1_RAW_ONFI_ID; |
| 657 | |
| 658 | /* Initialize the cmd and vld */ |
| 659 | params.dev_cmd1 = (dev_cmd1 & 0xFFFFFF00) | ONFI_READ_ID_CMD; |
| 660 | params.vld = vld & 0xFFFFFFFE; |
| 661 | |
| 662 | /* Initialize the address |
| 663 | * addr1 is not used bcos of the cfg. |
| 664 | */ |
| 665 | params.cfg.addr0 = ONFI_READ_ID_ADDR; |
| 666 | params.cfg.addr1 = 0; |
| 667 | |
| 668 | /* Lock the pipe and execute the cmd. */ |
| 669 | onfi_ret = onfi_probe_cmd_exec(¶ms, onfi_str, ONFI_READ_ID_BUFFER_SIZE); |
| 670 | if (onfi_ret) |
| 671 | { |
| 672 | dprintf(CRITICAL, "ONFI Read id cmd failed\n"); |
| 673 | goto qpic_nand_onfi_probe_err; |
| 674 | } |
| 675 | |
| 676 | /* Write back vld and cmd and unlock the pipe. */ |
| 677 | qpic_nand_onfi_probe_cleanup(vld, dev_cmd1); |
| 678 | |
| 679 | /* Check for onfi string */ |
| 680 | id = (uint32_t*)onfi_str; |
| 681 | if (*id != ONFI_SIGNATURE) |
| 682 | { |
| 683 | dprintf(CRITICAL, "Not an ONFI device\n"); |
| 684 | /* Not an onfi device. Return error. */ |
| 685 | onfi_ret = NANDC_RESULT_DEV_NOT_SUPPORTED; |
| 686 | goto qpic_nand_onfi_probe_err; |
| 687 | } |
| 688 | |
| 689 | dprintf(INFO, "ONFI device found\n"); |
| 690 | /* Now read the param page */ |
| 691 | /* Initialize the config */ |
| 692 | params.cfg.cfg0 = NAND_CFG0_RAW_ONFI_PARAM_PAGE; |
| 693 | params.cfg.cfg1 = NAND_CFG1_RAW_ONFI_PARAM_PAGE; |
| 694 | |
| 695 | /* Initialize the cmd and vld */ |
| 696 | params.dev_cmd1 = (dev_cmd1 & 0xFFFFFF00) | ONFI_READ_PARAM_PAGE_CMD; |
| 697 | params.vld = vld & 0xFFFFFFFE; |
| 698 | |
| 699 | /* Initialize the address |
| 700 | * addr1 is not used bcos of the cfg. |
| 701 | */ |
| 702 | params.cfg.addr0 = ONFI_READ_PARAM_PAGE_ADDR; |
| 703 | params.cfg.addr1 = 0; |
| 704 | |
| 705 | /* Lock the pipe and execute the cmd. */ |
| 706 | onfi_ret = onfi_probe_cmd_exec(¶ms, buffer, ONFI_READ_PARAM_PAGE_BUFFER_SIZE); |
| 707 | if (onfi_ret) |
| 708 | { |
| 709 | dprintf(CRITICAL, "ONFI Read param page failed\n"); |
| 710 | goto qpic_nand_onfi_probe_err; |
| 711 | } |
| 712 | |
| 713 | /* Write back vld and cmd and unlock the pipe. */ |
| 714 | qpic_nand_onfi_probe_cleanup(vld, dev_cmd1); |
| 715 | |
| 716 | /* Verify the integrity of the returned page */ |
| 717 | param_page = (struct onfi_param_page*)buffer; |
| 718 | |
| 719 | /* TODO: Add CRC check to validate the param page. */ |
| 720 | |
| 721 | /* Save the parameter values */ |
| 722 | onfi_ret = qpic_nand_onfi_save_params(param_page, flash); |
| 723 | |
| 724 | qpic_nand_onfi_probe_err: |
| 725 | if (onfi_ret) |
| 726 | dprintf(CRITICAL, "ONFI probe failed\n"); |
| 727 | |
| 728 | free(buffer); |
| 729 | |
| 730 | return onfi_ret; |
| 731 | } |
| 732 | |
| 733 | /* Enquues a desc for a flash cmd with NWD flag set: |
| 734 | * cfg: Defines the configuration for the flash cmd. |
| 735 | * start: Address where the command elements are added. |
| 736 | * |
| 737 | * Returns the address where the next cmd element can be added. |
| 738 | */ |
| 739 | struct cmd_element* |
| 740 | qpic_nand_add_cmd_ce(struct cfg_params *cfg, |
| 741 | struct cmd_element *start) |
| 742 | { |
| 743 | struct cmd_element *cmd_list_ptr; |
| 744 | |
| 745 | cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(cfg, start); |
| 746 | |
| 747 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)cfg->cmd, CE_WRITE_TYPE); |
| 748 | cmd_list_ptr++; |
| 749 | |
| 750 | bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)cfg->exec, CE_WRITE_TYPE); |
| 751 | cmd_list_ptr++; |
| 752 | |
| 753 | return cmd_list_ptr; |
| 754 | } |
| 755 | |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 756 | /* Reads nand_flash_status */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 757 | struct cmd_element* |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 758 | qpic_nand_add_read_ce(struct cmd_element *start, uint32_t *flash_status_read) |
| 759 | { |
| 760 | struct cmd_element *cmd_list_ptr = start; |
| 761 | |
| 762 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)flash_status_read), CE_READ_TYPE); |
| 763 | cmd_list_ptr++; |
| 764 | |
| 765 | return cmd_list_ptr; |
| 766 | } |
| 767 | |
| 768 | /* Resets nand_flash_status and nand_read_status */ |
| 769 | struct cmd_element* |
| 770 | qpic_nand_reset_status_ce(struct cmd_element *start, uint32_t read_status) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 771 | { |
| 772 | struct cmd_element *cmd_list_ptr = start; |
| 773 | uint32_t flash_status_reset; |
| 774 | uint32_t read_status_reset; |
| 775 | |
| 776 | /* Read and reset the status registers. */ |
| 777 | flash_status_reset = NAND_FLASH_STATUS_RESET; |
| 778 | read_status_reset = NAND_READ_STATUS_RESET; |
| 779 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 780 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)flash_status_reset, CE_WRITE_TYPE); |
| 781 | cmd_list_ptr++; |
| 782 | |
| 783 | if (read_status) |
| 784 | { |
| 785 | bam_add_cmd_element(cmd_list_ptr, NAND_READ_STATUS, (uint32_t)read_status_reset, CE_WRITE_TYPE); |
| 786 | cmd_list_ptr++; |
| 787 | } |
| 788 | |
| 789 | return cmd_list_ptr; |
| 790 | } |
| 791 | |
| 792 | struct cmd_element* |
| 793 | qpic_nand_add_isbad_cmd_ce(struct cfg_params *cfg, |
| 794 | struct cmd_element *start) |
| 795 | { |
| 796 | struct cmd_element *cmd_list_ptr = start; |
| 797 | |
| 798 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_ECC_CFG, (uint32_t)cfg->ecc_cfg, CE_WRITE_TYPE); |
| 799 | cmd_list_ptr++; |
| 800 | |
| 801 | bam_add_cmd_element(cmd_list_ptr, NAND_READ_LOCATION_n(0), (uint32_t)cfg->addr_loc_0, CE_WRITE_TYPE); |
| 802 | cmd_list_ptr++; |
| 803 | |
| 804 | cmd_list_ptr = qpic_nand_add_cmd_ce(cfg, cmd_list_ptr); |
| 805 | |
| 806 | return cmd_list_ptr; |
| 807 | } |
| 808 | |
| 809 | static int |
| 810 | qpic_nand_block_isbad_exec(struct cfg_params *params, |
| 811 | uint8_t *bad_block) |
| 812 | { |
| 813 | |
| 814 | struct cmd_element *cmd_list_ptr = ce_array; |
| 815 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 816 | uint8_t desc_flags = BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG |
| 817 | | BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG; |
| 818 | int num_desc = 0; |
| 819 | uint32_t status = 0; |
| 820 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 821 | |
| 822 | cmd_list_ptr = qpic_nand_add_isbad_cmd_ce(params, cmd_list_ptr); |
| 823 | |
| 824 | /* Enqueue the desc for the above commands */ |
| 825 | bam_add_one_desc(&bam, |
| 826 | CMD_PIPE_INDEX, |
| 827 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 828 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 829 | desc_flags); |
| 830 | |
| 831 | num_desc++; |
| 832 | |
| 833 | /* Add Data desc */ |
| 834 | bam_add_desc(&bam, |
| 835 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 836 | (unsigned char *)PA((addr_t)bad_block), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 837 | 4, |
| 838 | BAM_DESC_INT_FLAG); |
| 839 | |
| 840 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 841 | |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 842 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0); |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 843 | |
| 844 | nand_ret = qpic_nand_check_status(status); |
| 845 | |
| 846 | /* Dummy read to unlock pipe. */ |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 847 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 848 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 849 | if (nand_ret) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 850 | return NANDC_RESULT_FAILURE; |
| 851 | |
| 852 | qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); |
| 853 | |
| 854 | return nand_ret; |
| 855 | } |
| 856 | |
Tanya Brokhman | 72b44dc | 2015-01-07 10:20:05 +0200 | [diff] [blame] | 857 | /** |
| 858 | * qpic_nand_block_isbad() - Checks is given block is bad |
| 859 | * @page - number of page the block starts at |
| 860 | * |
| 861 | * Returns nand_result_t |
| 862 | */ |
| 863 | nand_result_t qpic_nand_block_isbad(unsigned page) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 864 | { |
| 865 | unsigned cwperpage; |
| 866 | struct cfg_params params; |
| 867 | uint8_t bad_block[4]; |
| 868 | unsigned nand_ret = NANDC_RESULT_SUCCESS; |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 869 | uint32_t blk = page / flash.num_pages_per_blk; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 870 | |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 871 | if (bbtbl[blk] == NAND_BAD_BLK_VALUE_IS_GOOD) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 872 | return NANDC_RESULT_SUCCESS; |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 873 | else if (bbtbl[blk] == NAND_BAD_BLK_VALUE_IS_BAD) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 874 | return NANDC_RESULT_BAD_BLOCK; |
| 875 | else |
| 876 | { |
| 877 | /* Read the bad block value from the flash. |
| 878 | * Bad block value is stored in the first page of the block. |
| 879 | */ |
| 880 | /* Read the first page in the block. */ |
| 881 | cwperpage = flash.cws_per_page; |
| 882 | |
| 883 | /* Read page cmd */ |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 884 | params.cmd = NAND_CMD_PAGE_READ_ECC; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 885 | /* Clear the CW per page bits */ |
| 886 | params.cfg0 = cfg0_raw & ~(7U << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT); |
| 887 | params.cfg1 = cfg1_raw; |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 888 | /* addr0 - Write column addr + few bits in row addr upto 32 bits. */ |
| 889 | params.addr0 = (page << 16) | (USER_DATA_BYTES_PER_CW * cwperpage); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 890 | |
| 891 | /* addr1 - Write rest of row addr. |
| 892 | * This will be all 0s. |
| 893 | */ |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 894 | params.addr1 = (page >> 16) & 0xff; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 895 | params.addr_loc_0 = NAND_RD_LOC_OFFSET(0); |
| 896 | params.addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1); |
| 897 | params.addr_loc_0 |= NAND_RD_LOC_SIZE(4); /* Read 4 bytes */ |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 898 | params.ecc_cfg = ecc_bch_cfg | 0x1; /* Disable ECC */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 899 | params.exec = 1; |
| 900 | |
| 901 | if (qpic_nand_block_isbad_exec(¶ms, bad_block)) |
| 902 | { |
| 903 | dprintf(CRITICAL, |
| 904 | "Could not read bad block value\n"); |
| 905 | return NANDC_RESULT_FAILURE; |
| 906 | } |
| 907 | |
| 908 | if (flash.widebus) |
| 909 | { |
| 910 | if (bad_block[0] != 0xFF && bad_block[1] != 0xFF) |
| 911 | { |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 912 | bbtbl[blk] = NAND_BAD_BLK_VALUE_IS_BAD; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 913 | nand_ret = NANDC_RESULT_BAD_BLOCK; |
| 914 | } |
| 915 | } |
| 916 | else if (bad_block[0] != 0xFF) |
| 917 | { |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 918 | bbtbl[blk] = NAND_BAD_BLK_VALUE_IS_BAD; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 919 | nand_ret = NANDC_RESULT_BAD_BLOCK; |
| 920 | } |
| 921 | else |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 922 | bbtbl[blk] = NAND_BAD_BLK_VALUE_IS_GOOD; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 923 | |
| 924 | return nand_ret; |
| 925 | } |
| 926 | } |
| 927 | |
| 928 | /* Function to erase a block on the nand. |
| 929 | * page: Starting page address for the block. |
| 930 | */ |
Tanya Brokhman | 72b44dc | 2015-01-07 10:20:05 +0200 | [diff] [blame] | 931 | nand_result_t qpic_nand_blk_erase(uint32_t page) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 932 | { |
| 933 | struct cfg_params cfg; |
| 934 | struct cmd_element *cmd_list_ptr = ce_array; |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 935 | struct cmd_element *cmd_list_read_ptr = ce_read_array; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 936 | struct cmd_element *cmd_list_ptr_start = ce_array; |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 937 | struct cmd_element *cmd_list_read_ptr_start = ce_read_array; |
Veera Sundaram Sankaran | 0018151 | 2014-12-09 11:23:39 -0800 | [diff] [blame] | 938 | uint32_t status; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 939 | int num_desc = 0; |
| 940 | uint32_t blk_addr = page / flash.num_pages_per_blk; |
| 941 | |
| 942 | /* Erase only if the block is not bad */ |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 943 | if (qpic_nand_block_isbad(page)) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 944 | { |
| 945 | dprintf(CRITICAL, |
| 946 | "NAND Erase error: Block address belongs to bad block: %d\n", |
| 947 | blk_addr); |
| 948 | return NANDC_RESULT_FAILURE; |
| 949 | } |
| 950 | |
| 951 | /* Fill in params for the erase flash cmd */ |
| 952 | cfg.addr0 = page; |
| 953 | cfg.addr1 = 0; |
| 954 | /* Clear CW_PER_PAGE in cfg0 */ |
| 955 | cfg.cfg0 = cfg0 & ~(7U << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT); |
| 956 | cfg.cfg1 = cfg1; |
| 957 | cfg.cmd = NAND_CMD_BLOCK_ERASE; |
| 958 | cfg.exec = 1; |
| 959 | |
| 960 | cmd_list_ptr = qpic_nand_add_cmd_ce(&cfg, cmd_list_ptr); |
| 961 | |
| 962 | /* Enqueue the desc for the above commands */ |
| 963 | bam_add_one_desc(&bam, |
| 964 | CMD_PIPE_INDEX, |
| 965 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 966 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 967 | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG | BAM_DESC_LOCK_FLAG); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 968 | |
| 969 | cmd_list_ptr_start = cmd_list_ptr; |
| 970 | num_desc++; |
| 971 | |
| 972 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 973 | |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 974 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 975 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 976 | cmd_list_ptr_start = cmd_list_ptr; |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 977 | cmd_list_read_ptr_start = cmd_list_read_ptr; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 978 | |
| 979 | /* QPIC controller automatically sends |
| 980 | * GET_STATUS cmd to the nand card because |
| 981 | * of the configuration programmed. |
| 982 | * Read the result of GET_STATUS cmd. |
| 983 | */ |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 984 | cmd_list_read_ptr = qpic_nand_add_read_ce(cmd_list_read_ptr, &status); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 985 | |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 986 | /* Enqueue the desc for the NAND_FLASH_STATUS read command */ |
| 987 | bam_add_one_desc(&bam, |
| 988 | CMD_PIPE_INDEX, |
| 989 | (unsigned char*)cmd_list_read_ptr_start, |
| 990 | PA((uint32_t)cmd_list_read_ptr - (uint32_t)cmd_list_read_ptr_start), |
| 991 | BAM_DESC_CMD_FLAG) ; |
| 992 | |
| 993 | cmd_list_ptr = qpic_nand_reset_status_ce(cmd_list_ptr, 1); |
| 994 | |
| 995 | /* Enqueue the desc for NAND_FLASH_STATUS and NAND_READ_STATUS write commands */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 996 | bam_add_one_desc(&bam, |
| 997 | CMD_PIPE_INDEX, |
| 998 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 999 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1000 | BAM_DESC_INT_FLAG | BAM_DESC_CMD_FLAG) ; |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 1001 | num_desc = 2; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1002 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 1003 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1004 | status = qpic_nand_check_status(status); |
| 1005 | |
| 1006 | /* Dummy read to unlock pipe. */ |
Veera Sundaram Sankaran | 0018151 | 2014-12-09 11:23:39 -0800 | [diff] [blame] | 1007 | qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG); |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1008 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1009 | /* Check for status errors*/ |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1010 | if (status) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1011 | { |
| 1012 | dprintf(CRITICAL, |
| 1013 | "NAND Erase error: Block address belongs to bad block: %d\n", |
| 1014 | blk_addr); |
Tanya Brokhman | 72b44dc | 2015-01-07 10:20:05 +0200 | [diff] [blame] | 1015 | qpic_nand_mark_badblock(page); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1016 | return NANDC_RESULT_FAILURE; |
| 1017 | } |
| 1018 | |
| 1019 | /* Check for PROG_ERASE_OP_RESULT bit for the result of erase operation. */ |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 1020 | if (!(status & PROG_ERASE_OP_RESULT)) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1021 | return NANDC_RESULT_SUCCESS; |
| 1022 | |
Tanya Brokhman | 72b44dc | 2015-01-07 10:20:05 +0200 | [diff] [blame] | 1023 | qpic_nand_mark_badblock(page); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1024 | return NANDC_RESULT_FAILURE; |
| 1025 | } |
| 1026 | |
| 1027 | /* Return num of desc added. */ |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1028 | static void |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1029 | qpic_nand_add_wr_page_cws_cmd_desc(struct cfg_params *cfg, |
| 1030 | uint32_t status[], |
| 1031 | enum nand_cfg_value cfg_mode) |
| 1032 | { |
| 1033 | struct cmd_element *cmd_list_ptr = ce_array; |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 1034 | struct cmd_element *cmd_list_read_ptr = ce_read_array; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1035 | struct cmd_element *cmd_list_ptr_start = ce_array; |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 1036 | struct cmd_element *cmd_list_read_ptr_start = ce_read_array; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1037 | uint32_t ecc; |
| 1038 | int num_desc = 0; |
| 1039 | int int_flag = 0; |
| 1040 | |
| 1041 | if (cfg_mode == NAND_CFG) |
| 1042 | ecc = ecc_bch_cfg; |
| 1043 | else |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 1044 | ecc = ecc_bch_cfg | 0x1; /* Disable ECC */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1045 | |
| 1046 | /* Add ECC configuration */ |
| 1047 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_ECC_CFG, |
| 1048 | (uint32_t)ecc, CE_WRITE_TYPE); |
| 1049 | cmd_list_ptr++; |
| 1050 | cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(cfg, cmd_list_ptr); |
| 1051 | |
| 1052 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, |
| 1053 | (uint32_t)cfg->cmd, CE_WRITE_TYPE); |
| 1054 | cmd_list_ptr++; |
| 1055 | |
| 1056 | /* Enqueue the desc for the above commands */ |
| 1057 | bam_add_one_desc(&bam, |
| 1058 | CMD_PIPE_INDEX, |
| 1059 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1060 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1061 | BAM_DESC_CMD_FLAG | BAM_DESC_LOCK_FLAG); |
| 1062 | |
| 1063 | num_desc++; |
| 1064 | |
| 1065 | /* Add CE for all the CWs */ |
| 1066 | for (unsigned i = 0; i < flash.cws_per_page; i++) |
| 1067 | { |
| 1068 | cmd_list_ptr_start = cmd_list_ptr; |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1069 | int_flag = BAM_DESC_INT_FLAG; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1070 | |
| 1071 | bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)cfg->exec, CE_WRITE_TYPE); |
| 1072 | cmd_list_ptr++; |
| 1073 | |
| 1074 | /* Enqueue the desc for the above commands */ |
| 1075 | bam_add_one_desc(&bam, |
| 1076 | CMD_PIPE_INDEX, |
| 1077 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1078 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1079 | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG); |
| 1080 | |
| 1081 | num_desc++; |
| 1082 | cmd_list_ptr_start = cmd_list_ptr; |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 1083 | cmd_list_read_ptr_start = cmd_list_read_ptr; |
| 1084 | |
| 1085 | cmd_list_read_ptr = qpic_nand_add_read_ce(cmd_list_read_ptr_start, &status[i]); |
| 1086 | /* Enqueue the desc for the NAND_FLASH_STATUS read command */ |
| 1087 | bam_add_one_desc(&bam, |
| 1088 | CMD_PIPE_INDEX, |
| 1089 | (unsigned char*)cmd_list_read_ptr_start, |
| 1090 | PA((uint32_t)cmd_list_read_ptr - (uint32_t)cmd_list_read_ptr_start), |
| 1091 | BAM_DESC_CMD_FLAG); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1092 | |
| 1093 | /* Set interrupt bit only for the last CW */ |
| 1094 | if (i == flash.cws_per_page - 1) |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 1095 | cmd_list_ptr = qpic_nand_reset_status_ce(cmd_list_ptr, 1); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1096 | else |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 1097 | cmd_list_ptr = qpic_nand_reset_status_ce(cmd_list_ptr, 0); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1098 | |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 1099 | /* Enqueue the desc for NAND_FLASH_STATUS and NAND_READ_STATUS write commands */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1100 | bam_add_one_desc(&bam, |
| 1101 | CMD_PIPE_INDEX, |
| 1102 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1103 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1104 | int_flag | BAM_DESC_CMD_FLAG); |
Sridhar Parasuram | f5188d8 | 2014-11-17 15:39:55 -0800 | [diff] [blame] | 1105 | num_desc += 2; |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1106 | |
| 1107 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 1108 | |
| 1109 | status[i] = qpic_nand_check_status(status[i]); |
| 1110 | |
| 1111 | num_desc = 0; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1112 | } |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1113 | return; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1114 | } |
| 1115 | |
| 1116 | void |
| 1117 | qpic_add_wr_page_cws_data_desc(const void *buffer, |
| 1118 | enum nand_cfg_value cfg_mode, |
| 1119 | const void *spareaddr) |
| 1120 | { |
| 1121 | int len; |
| 1122 | int flags; |
| 1123 | uint32_t start; |
| 1124 | unsigned num_desc = 0; |
| 1125 | |
| 1126 | for( unsigned i = 0; i < flash.cws_per_page; i++) |
| 1127 | { |
| 1128 | flags = 0; |
| 1129 | |
| 1130 | /* Set the interrupt flag on the last CW write for the page. */ |
| 1131 | if( i == flash.cws_per_page - 1) |
| 1132 | flags |= BAM_DESC_INT_FLAG; |
| 1133 | |
| 1134 | if (cfg_mode != NAND_CFG_RAW) |
| 1135 | { |
| 1136 | start = (uint32_t)buffer + i * DATA_BYTES_IN_IMG_PER_CW; |
| 1137 | |
| 1138 | if (i < (flash.cws_per_page - 1)) |
| 1139 | { |
| 1140 | len = DATA_BYTES_IN_IMG_PER_CW; |
| 1141 | flags |= BAM_DESC_EOT_FLAG; |
| 1142 | } |
| 1143 | else |
| 1144 | { |
| 1145 | /* Allow space for spare bytes in the last page */ |
| 1146 | len = USER_DATA_BYTES_PER_CW - ((flash.cws_per_page - 1) << 2); |
| 1147 | flags = 0; |
| 1148 | } |
| 1149 | } |
| 1150 | else |
| 1151 | { |
| 1152 | start = (uint32_t)buffer; |
| 1153 | len = flash.cw_size; |
| 1154 | flags |= BAM_DESC_EOT_FLAG; |
| 1155 | } |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1156 | bam_add_one_desc(&bam, DATA_CONSUMER_PIPE_INDEX, (unsigned char*)PA(start), len, flags); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1157 | num_desc++; |
| 1158 | |
| 1159 | if ((i == (flash.cws_per_page - 1)) && (cfg_mode == NAND_CFG)) |
| 1160 | { |
| 1161 | /* write extra data */ |
| 1162 | start = (uint32_t)spareaddr; |
| 1163 | len = (flash.cws_per_page << 2); |
| 1164 | flags = BAM_DESC_EOT_FLAG | BAM_DESC_INT_FLAG; |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1165 | bam_add_one_desc(&bam, DATA_CONSUMER_PIPE_INDEX, (unsigned char*)PA(start), len, flags); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1166 | num_desc++; |
| 1167 | } |
| 1168 | } |
| 1169 | |
| 1170 | bam_sys_gen_event(&bam, DATA_CONSUMER_PIPE_INDEX, num_desc); |
| 1171 | } |
| 1172 | |
| 1173 | static nand_result_t |
| 1174 | qpic_nand_write_page(uint32_t pg_addr, |
| 1175 | enum nand_cfg_value cfg_mode, |
| 1176 | const void* buffer, |
| 1177 | const void* spareaddr) |
| 1178 | { |
| 1179 | struct cfg_params cfg; |
Deepa Dinamani | 16663a6 | 2013-02-07 16:25:59 -0800 | [diff] [blame] | 1180 | uint32_t status[QPIC_NAND_MAX_CWS_IN_PAGE]; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1181 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 1182 | |
| 1183 | if (cfg_mode == NAND_CFG_RAW) |
| 1184 | { |
| 1185 | cfg.cfg0 = cfg0_raw; |
| 1186 | cfg.cfg1 = cfg1_raw; |
| 1187 | } |
| 1188 | else |
| 1189 | { |
| 1190 | cfg.cfg0 = cfg0; |
| 1191 | cfg.cfg1 = cfg1; |
| 1192 | } |
| 1193 | |
| 1194 | cfg.cmd = NAND_CMD_PRG_PAGE; |
| 1195 | cfg.exec = 1; |
| 1196 | |
| 1197 | cfg.addr0 = pg_addr << 16; |
| 1198 | cfg.addr1 = (pg_addr >> 16) & 0xff; |
| 1199 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1200 | qpic_add_wr_page_cws_data_desc(buffer, cfg_mode, spareaddr); |
| 1201 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1202 | qpic_nand_add_wr_page_cws_cmd_desc(&cfg, status, cfg_mode); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1203 | |
| 1204 | /* Check for errors */ |
| 1205 | for(unsigned i = 0; i < flash.cws_per_page; i++) |
| 1206 | { |
| 1207 | nand_ret = qpic_nand_check_status(status[i]); |
| 1208 | if (nand_ret) |
| 1209 | { |
| 1210 | dprintf(CRITICAL, |
| 1211 | "Failed to write CW %d for page: %d\n", |
| 1212 | i, pg_addr); |
| 1213 | break; |
| 1214 | } |
| 1215 | } |
| 1216 | |
| 1217 | /* Wait for data to be available */ |
| 1218 | qpic_nand_wait_for_data(DATA_CONSUMER_PIPE_INDEX); |
| 1219 | |
| 1220 | return nand_ret; |
| 1221 | } |
| 1222 | |
| 1223 | static int |
| 1224 | qpic_nand_mark_badblock(uint32_t page) |
| 1225 | { |
| 1226 | char empty_buf[NAND_CW_SIZE_8_BIT_ECC]; |
| 1227 | |
| 1228 | memset(empty_buf, 0, NAND_CW_SIZE_8_BIT_ECC); |
| 1229 | |
| 1230 | /* Going to first page of the block */ |
| 1231 | if (page & flash.num_pages_per_blk_mask) |
| 1232 | page = page - (page & flash.num_pages_per_blk_mask); |
| 1233 | |
| 1234 | return qpic_nand_write_page(page, NAND_CFG_RAW, empty_buf, 0); |
| 1235 | } |
| 1236 | |
| 1237 | static void |
| 1238 | qpic_nand_non_onfi_probe(struct flash_info *flash) |
| 1239 | { |
| 1240 | int dev_found = 0; |
| 1241 | unsigned index; |
| 1242 | uint32_t ecc_bits; |
| 1243 | |
| 1244 | /* Read the nand id. */ |
| 1245 | qpic_nand_fetch_id(flash); |
| 1246 | |
| 1247 | /* Check if we support the device */ |
Deepa Dinamani | 649a94a | 2013-03-07 14:37:31 -0800 | [diff] [blame] | 1248 | for (index = 0; index < (ARRAY_SIZE(supported_flash)); index++) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1249 | { |
Sridhar Parasuram | fb0d9c8 | 2015-02-02 15:23:13 -0800 | [diff] [blame] | 1250 | if (((flash->id & supported_flash[index].mask) == |
| 1251 | (supported_flash[index].flash_id & (supported_flash[index].mask))) && |
| 1252 | ((flash->id2 & supported_flash[index].mask2) == |
| 1253 | (supported_flash[index].flash_id2 & (supported_flash[index].mask2)))) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1254 | { |
| 1255 | dev_found = 1; |
| 1256 | break; |
| 1257 | } |
| 1258 | } |
| 1259 | |
| 1260 | if (dev_found) |
| 1261 | { |
| 1262 | flash->page_size = supported_flash[index].pagesize; |
| 1263 | flash->block_size = supported_flash[index].blksize; |
| 1264 | flash->spare_size = supported_flash[index].oobsize; |
| 1265 | ecc_bits = supported_flash[index].ecc_8_bits; |
| 1266 | |
| 1267 | /* Make sure that the block size and page size are defined. */ |
| 1268 | ASSERT(flash->block_size); |
| 1269 | ASSERT(flash->page_size); |
| 1270 | |
| 1271 | flash->num_blocks = supported_flash[index].density; |
| 1272 | flash->num_blocks /= (flash->block_size); |
| 1273 | flash->num_pages_per_blk = flash->block_size / flash->page_size; |
| 1274 | flash->num_pages_per_blk_mask = flash->num_pages_per_blk - 1; |
| 1275 | |
| 1276 | /* Look for 8bit BCH ECC Nand, TODO: ECC Correctability >= 8 */ |
| 1277 | if (ecc_bits) |
| 1278 | flash->ecc_width = NAND_WITH_8_BIT_ECC; |
| 1279 | else |
| 1280 | flash->ecc_width = NAND_WITH_4_BIT_ECC; |
| 1281 | |
| 1282 | flash->density = supported_flash[index].density; |
| 1283 | flash->widebus = supported_flash[index].widebus; |
| 1284 | |
| 1285 | return; |
| 1286 | } |
| 1287 | |
| 1288 | /* Flash device is not supported, print flash device info and halt */ |
| 1289 | if (dev_found == 0) |
| 1290 | { |
| 1291 | dprintf(CRITICAL, "NAND device is not supported: nandid: 0x%x" |
| 1292 | "maker=0x%02x device=0x%02x\n", |
| 1293 | flash->id, |
| 1294 | flash->vendor, |
| 1295 | flash->device); |
| 1296 | ASSERT(0); |
| 1297 | } |
| 1298 | |
| 1299 | dprintf(INFO, "nandid: 0x%x maker=0x%02x device=0x%02x page_size=%d\n", |
| 1300 | flash->id, |
| 1301 | flash->vendor, |
| 1302 | flash->device, |
| 1303 | flash->page_size); |
| 1304 | |
| 1305 | dprintf(INFO, "spare_size=%d block_size=%d num_blocks=%d\n", |
| 1306 | flash->spare_size, |
| 1307 | flash->block_size, |
| 1308 | flash->num_blocks); |
| 1309 | } |
| 1310 | |
| 1311 | void |
| 1312 | qpic_nand_init(struct qpic_nand_init_config *config) |
| 1313 | { |
| 1314 | uint32_t i; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1315 | |
| 1316 | nand_base = config->nand_base; |
| 1317 | |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 1318 | qpic_bam_init(config); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1319 | |
Deepa Dinamani | 649a94a | 2013-03-07 14:37:31 -0800 | [diff] [blame] | 1320 | qpic_nand_non_onfi_probe(&flash); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1321 | |
| 1322 | /* Save the RAW and read/write configs */ |
| 1323 | qpic_nand_save_config(&flash); |
| 1324 | |
| 1325 | flash_spare_bytes = (unsigned char *)malloc(flash.spare_size); |
| 1326 | |
| 1327 | if (flash_spare_bytes == NULL) |
| 1328 | { |
| 1329 | dprintf(CRITICAL, "Failed to allocate memory for spare bytes\n"); |
| 1330 | return; |
| 1331 | } |
| 1332 | |
| 1333 | /* Create a bad block table */ |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1334 | bbtbl = (uint8_t *) malloc(sizeof(uint8_t) * flash.num_blocks); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1335 | |
| 1336 | if (bbtbl == NULL) |
| 1337 | { |
| 1338 | dprintf(CRITICAL, "Failed to allocate memory for bad block table\n"); |
| 1339 | return; |
| 1340 | } |
| 1341 | |
| 1342 | for (i = 0; i < flash.num_blocks; i++) |
| 1343 | bbtbl[i] = NAND_BAD_BLK_VALUE_NOT_READ; |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1344 | |
| 1345 | /* Set aside contiguous memory for reads/writes. |
| 1346 | * This is needed as the BAM transfers only work with |
| 1347 | * physically contiguous buffers. |
| 1348 | * We will copy any data to be written/ to be read from |
| 1349 | * nand to this buffer and this buffer will be submitted to BAM. |
| 1350 | */ |
| 1351 | rdwr_buf = (uint8_t*) malloc(flash.page_size + flash.spare_size); |
| 1352 | |
| 1353 | if (rdwr_buf == NULL) |
| 1354 | { |
| 1355 | dprintf(CRITICAL, "Failed to allocate memory for page reads or writes\n"); |
| 1356 | return; |
| 1357 | } |
| 1358 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1359 | } |
| 1360 | |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1361 | unsigned |
| 1362 | flash_page_size(void) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1363 | { |
| 1364 | return flash.page_size; |
| 1365 | } |
| 1366 | |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1367 | unsigned |
| 1368 | flash_block_size(void) |
| 1369 | { |
| 1370 | return flash.block_size; |
| 1371 | } |
| 1372 | |
Deepa Dinamani | 8e6b243 | 2012-10-17 17:12:44 -0700 | [diff] [blame] | 1373 | unsigned |
| 1374 | flash_num_blocks(void) |
| 1375 | { |
| 1376 | return flash.num_blocks; |
| 1377 | } |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1378 | |
Tanya Brokhman | 72b44dc | 2015-01-07 10:20:05 +0200 | [diff] [blame] | 1379 | unsigned |
| 1380 | flash_spare_size(void) |
| 1381 | { |
| 1382 | return flash.spare_size; |
| 1383 | } |
| 1384 | |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1385 | struct ptable * |
| 1386 | flash_get_ptable(void) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1387 | { |
| 1388 | return flash_ptable; |
| 1389 | } |
| 1390 | |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1391 | void |
Deepa Dinamani | 87feab8 | 2012-10-04 14:28:05 -0700 | [diff] [blame] | 1392 | qpic_nand_uninit() |
| 1393 | { |
| 1394 | bam_pipe_reset(&bam, DATA_PRODUCER_PIPE_INDEX); |
| 1395 | bam_pipe_reset(&bam, DATA_CONSUMER_PIPE_INDEX); |
| 1396 | bam_pipe_reset(&bam, CMD_PIPE_INDEX); |
| 1397 | |
| 1398 | } |
| 1399 | void |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1400 | flash_set_ptable(struct ptable *new_ptable) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1401 | { |
| 1402 | ASSERT(flash_ptable == NULL && new_ptable != NULL); |
| 1403 | flash_ptable = new_ptable; |
| 1404 | } |
| 1405 | |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1406 | static int find_num_zeros_per_cw(uint8_t *ecc_buf, uint32_t ecc_bytes) |
| 1407 | { |
| 1408 | uint8_t val; |
| 1409 | uint32_t i; |
| 1410 | int num_zeros = 0; |
| 1411 | |
| 1412 | for (i = 0; i < ecc_bytes; i++) |
| 1413 | { |
| 1414 | val = ecc_buf[i]; |
| 1415 | while (val) |
| 1416 | { |
| 1417 | if ((val & 1) == 0) |
| 1418 | num_zeros++; |
| 1419 | if (num_zeros > THRESHOLD_BIT_FLIPS) |
| 1420 | goto out; |
| 1421 | val >>= 1; |
| 1422 | } |
| 1423 | } |
| 1424 | |
| 1425 | out: |
| 1426 | return num_zeros; |
| 1427 | } |
| 1428 | |
| 1429 | static int qpic_nand_read_erased_page(uint32_t page) |
| 1430 | { |
| 1431 | struct cfg_params params; |
| 1432 | uint32_t ecc; |
| 1433 | uint32_t flash_sts[QPIC_NAND_MAX_CWS_IN_PAGE]; |
| 1434 | uint32_t buffer_sts[QPIC_NAND_MAX_CWS_IN_PAGE]; |
| 1435 | uint32_t addr_loc_0; |
| 1436 | uint32_t total_ecc_bytes = 0; |
| 1437 | struct cmd_element *cmd_list_ptr = ce_array; |
| 1438 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 1439 | uint32_t num_cmd_desc = 0; |
| 1440 | uint32_t num_data_desc = 0; |
| 1441 | uint32_t i; |
| 1442 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 1443 | uint8_t flags = 0; |
| 1444 | uint32_t *cmd_list_temp = NULL; |
| 1445 | uint8_t *ecc_buf = NULL; |
| 1446 | uint8_t *ecc_temp = NULL; |
| 1447 | int num_zeros = 0; |
| 1448 | #if DEBUG_QPIC_NAND |
| 1449 | uint32_t *buffer_temp = NULL; |
| 1450 | #endif |
| 1451 | |
| 1452 | total_ecc_bytes = (ecc_parity_bytes * flash.cws_per_page); |
| 1453 | ecc_buf = memalign(16, total_ecc_bytes); |
| 1454 | ASSERT(ecc_buf); |
| 1455 | |
| 1456 | memset(ecc_buf, 0, total_ecc_bytes); |
| 1457 | |
| 1458 | ecc_temp = ecc_buf; |
| 1459 | #if DEBUG_QPIC_NAND |
| 1460 | buffer_temp = (uint32_t*)ecc_buf; |
| 1461 | #endif |
| 1462 | params.addr0 = page << 16; |
| 1463 | params.addr1 = (page >> 16) & 0xff; |
| 1464 | params.cfg0 = cfg0_raw; |
| 1465 | params.cfg1 = cfg1_raw; |
| 1466 | params.cmd = NAND_CMD_PAGE_READ; |
| 1467 | params.exec = 1; |
| 1468 | ecc = ecc_cfg_raw; |
| 1469 | |
| 1470 | /* Read all the Data bytes in the first 3 CWs. */ |
| 1471 | addr_loc_0 = NAND_RD_LOC_OFFSET(517); |
| 1472 | addr_loc_0 |= NAND_RD_LOC_SIZE(ecc_parity_bytes); |
| 1473 | addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1); |
| 1474 | |
| 1475 | /* Queue up the command and data descriptors for all the codewords in a page |
| 1476 | * and do a single bam transfer at the end.*/ |
| 1477 | for (i = 0; i < flash.cws_per_page; i++) |
| 1478 | { |
| 1479 | num_cmd_desc = 0; |
| 1480 | num_data_desc = 0; |
| 1481 | flags = 0; |
| 1482 | |
| 1483 | if (i == 0) |
| 1484 | { |
| 1485 | /* Set the lock flag for the first CW */ |
| 1486 | flags = BAM_DESC_LOCK_FLAG; |
| 1487 | |
| 1488 | cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(¶ms, cmd_list_ptr); |
| 1489 | |
| 1490 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_ECC_CFG,(uint32_t)ecc, CE_WRITE_TYPE); |
| 1491 | cmd_list_ptr++; |
| 1492 | |
| 1493 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)params.cmd, CE_WRITE_TYPE); |
| 1494 | cmd_list_ptr++; |
| 1495 | |
| 1496 | /* Write addr loc 0. */ |
| 1497 | bam_add_cmd_element(cmd_list_ptr, |
| 1498 | NAND_READ_LOCATION_n(0), |
| 1499 | (uint32_t)addr_loc_0, |
| 1500 | CE_WRITE_TYPE); |
| 1501 | |
| 1502 | cmd_list_ptr++; |
| 1503 | } |
| 1504 | else |
| 1505 | cmd_list_ptr_start = cmd_list_ptr; |
| 1506 | |
| 1507 | if (i == flash.cws_per_page - 1) |
| 1508 | flags = BAM_DESC_INT_FLAG; |
| 1509 | |
| 1510 | /* Add Data desc */ |
| 1511 | bam_add_one_desc(&bam, |
| 1512 | DATA_PRODUCER_PIPE_INDEX, |
| 1513 | (unsigned char *)PA((addr_t)ecc_temp), |
| 1514 | ecc_parity_bytes, |
| 1515 | flags); |
| 1516 | num_data_desc++; |
| 1517 | bam_sys_gen_event(&bam, DATA_PRODUCER_PIPE_INDEX, num_data_desc); |
| 1518 | |
| 1519 | bam_add_cmd_element(cmd_list_ptr, |
| 1520 | NAND_EXEC_CMD, |
| 1521 | (uint32_t)params.exec, |
| 1522 | CE_WRITE_TYPE); |
| 1523 | cmd_list_ptr++; |
| 1524 | |
| 1525 | /* Enqueue the desc for the above commands */ |
| 1526 | bam_add_one_desc(&bam, |
| 1527 | CMD_PIPE_INDEX, |
| 1528 | (unsigned char*)cmd_list_ptr_start, |
| 1529 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
| 1530 | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG | flags); |
| 1531 | num_cmd_desc++; |
| 1532 | |
| 1533 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)&(flash_sts[i])), CE_READ_TYPE); |
| 1534 | |
| 1535 | cmd_list_temp = (uint32_t *)cmd_list_ptr; |
| 1536 | |
| 1537 | cmd_list_ptr++; |
| 1538 | |
| 1539 | bam_add_cmd_element(cmd_list_ptr, NAND_BUFFER_STATUS, (uint32_t)PA((addr_t)&(buffer_sts[i])), CE_READ_TYPE); |
| 1540 | cmd_list_ptr++; |
| 1541 | |
| 1542 | if (i == flash.cws_per_page - 1) |
| 1543 | { |
| 1544 | /* Unlock flag for the last CW */ |
| 1545 | flags = BAM_DESC_CMD_FLAG | BAM_DESC_UNLOCK_FLAG; |
| 1546 | } |
| 1547 | else |
| 1548 | flags = BAM_DESC_CMD_FLAG; |
| 1549 | |
| 1550 | /* Enqueue the desc for the above command */ |
| 1551 | bam_add_one_desc(&bam, |
| 1552 | CMD_PIPE_INDEX, |
| 1553 | (unsigned char*)PA((addr_t)cmd_list_temp), |
| 1554 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_temp), |
| 1555 | flags); |
| 1556 | num_cmd_desc++; |
| 1557 | |
| 1558 | ecc_temp += ecc_parity_bytes; |
| 1559 | |
| 1560 | /* Notify BAM HW about the newly added descriptors */ |
| 1561 | bam_sys_gen_event(&bam, CMD_PIPE_INDEX, num_cmd_desc); |
| 1562 | } |
| 1563 | |
| 1564 | qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); |
| 1565 | |
| 1566 | /* Find number of bit flips in the ecc & if there are more than "threshold" bit flips then |
| 1567 | * the page is bad otherwise the page is erased page |
| 1568 | */ |
| 1569 | ecc_temp = ecc_buf; |
| 1570 | |
| 1571 | for (i = 0; i < flash.cws_per_page; i++) |
| 1572 | { |
| 1573 | num_zeros = find_num_zeros_per_cw(ecc_temp, ecc_parity_bytes); |
| 1574 | |
| 1575 | if (num_zeros > THRESHOLD_BIT_FLIPS) |
| 1576 | { |
| 1577 | nand_ret = NANDC_RESULT_BAD_PAGE; |
| 1578 | goto qpic_nand_read_page_error; |
| 1579 | } |
| 1580 | |
| 1581 | ecc_temp += ecc_parity_bytes; |
| 1582 | } |
| 1583 | |
| 1584 | qpic_nand_read_page_error: |
| 1585 | |
| 1586 | #if DEBUG_QPIC_NAND |
| 1587 | for(i = 0; i < 24; i += 8) |
| 1588 | { |
| 1589 | printf("ECC: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
| 1590 | buffer_temp[i], buffer_temp[i+1], buffer_temp[i+2], buffer_temp[i+3], |
| 1591 | buffer_temp[i+4], buffer_temp[i+5], buffer_temp[i+6], buffer_temp[i+7]); |
| 1592 | } |
| 1593 | printf("ECC: %08x %08x\n", buffer_temp[24], buffer_temp[25]); |
| 1594 | #endif |
| 1595 | |
| 1596 | free(ecc_buf); |
| 1597 | return nand_ret; |
| 1598 | } |
| 1599 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1600 | /* Note: No support for raw reads. */ |
| 1601 | static int |
| 1602 | qpic_nand_read_page(uint32_t page, unsigned char* buffer, unsigned char* spareaddr) |
| 1603 | { |
| 1604 | struct cfg_params params; |
| 1605 | uint32_t ecc; |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1606 | uint32_t flash_sts[QPIC_NAND_MAX_CWS_IN_PAGE] = {0}; |
| 1607 | uint32_t buffer_sts[QPIC_NAND_MAX_CWS_IN_PAGE] = {0}; |
| 1608 | uint32_t erased_cw_sts[QPIC_NAND_MAX_CWS_IN_PAGE] = {0}; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1609 | uint32_t addr_loc_0; |
| 1610 | uint32_t addr_loc_1; |
| 1611 | struct cmd_element *cmd_list_ptr = ce_array; |
| 1612 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 1613 | uint32_t num_cmd_desc = 0; |
| 1614 | uint32_t num_data_desc = 0; |
| 1615 | uint32_t status; |
| 1616 | uint32_t i; |
| 1617 | int nand_ret = NANDC_RESULT_SUCCESS; |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1618 | uint8_t flags = 0; |
| 1619 | uint32_t *cmd_list_temp = NULL; |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1620 | #if DEBUG_QPIC_NAND |
| 1621 | uint8_t *buffer_temp = buffer; |
| 1622 | #endif |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1623 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1624 | /* UD bytes in last CW is 512 - cws_per_page *4. |
| 1625 | * Since each of the CW read earlier reads 4 spare bytes. |
| 1626 | */ |
| 1627 | uint16_t ud_bytes_in_last_cw = USER_DATA_BYTES_PER_CW - ((flash.cws_per_page - 1) << 2); |
| 1628 | uint16_t oob_bytes = DATA_BYTES_IN_IMG_PER_CW - ud_bytes_in_last_cw; |
| 1629 | |
| 1630 | params.addr0 = page << 16; |
| 1631 | params.addr1 = (page >> 16) & 0xff; |
| 1632 | params.cfg0 = cfg0; |
| 1633 | params.cfg1 = cfg1; |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1634 | params.cmd = NAND_CMD_PAGE_READ_ECC; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1635 | params.exec = 1; |
| 1636 | ecc = ecc_bch_cfg; |
| 1637 | |
| 1638 | /* Read all the Data bytes in the first 3 CWs. */ |
| 1639 | addr_loc_0 = NAND_RD_LOC_OFFSET(0); |
| 1640 | addr_loc_0 |= NAND_RD_LOC_SIZE(DATA_BYTES_IN_IMG_PER_CW); |
| 1641 | addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1); |
| 1642 | |
| 1643 | |
| 1644 | addr_loc_1 = NAND_RD_LOC_OFFSET(ud_bytes_in_last_cw); |
| 1645 | addr_loc_1 |= NAND_RD_LOC_SIZE(oob_bytes); |
| 1646 | addr_loc_1 |= NAND_RD_LOC_LAST_BIT(1); |
| 1647 | |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 1648 | status = qpic_nand_block_isbad(page); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1649 | |
| 1650 | if (status) |
| 1651 | return status; |
| 1652 | |
sundarajan srinivasan | 7ced648 | 2013-03-21 16:01:18 -0700 | [diff] [blame] | 1653 | /* Reset and Configure erased CW/page detection controller */ |
| 1654 | qpic_nand_erased_status_reset(ce_array, BAM_DESC_LOCK_FLAG); |
| 1655 | |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1656 | /* Queue up the command and data descriptors for all the codewords in a page |
| 1657 | * and do a single bam transfer at the end.*/ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1658 | for (i = 0; i < flash.cws_per_page; i++) |
| 1659 | { |
| 1660 | num_cmd_desc = 0; |
| 1661 | num_data_desc = 0; |
| 1662 | |
| 1663 | if (i == 0) |
| 1664 | { |
| 1665 | cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(¶ms, cmd_list_ptr); |
| 1666 | |
| 1667 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_ECC_CFG,(uint32_t)ecc, CE_WRITE_TYPE); |
| 1668 | cmd_list_ptr++; |
| 1669 | } |
| 1670 | else |
| 1671 | cmd_list_ptr_start = cmd_list_ptr; |
| 1672 | |
| 1673 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)params.cmd, CE_WRITE_TYPE); |
| 1674 | cmd_list_ptr++; |
| 1675 | |
| 1676 | if (i == flash.cws_per_page - 1) |
| 1677 | { |
| 1678 | addr_loc_0 = NAND_RD_LOC_OFFSET(0); |
| 1679 | addr_loc_0 |= NAND_RD_LOC_SIZE(ud_bytes_in_last_cw); |
| 1680 | addr_loc_0 |= NAND_RD_LOC_LAST_BIT(0); |
| 1681 | |
| 1682 | /* Write addr loc 1 only for the last CW. */ |
| 1683 | bam_add_cmd_element(cmd_list_ptr, NAND_READ_LOCATION_n(1), (uint32_t)addr_loc_1, CE_WRITE_TYPE); |
| 1684 | cmd_list_ptr++; |
| 1685 | |
| 1686 | /* Add Data desc */ |
| 1687 | bam_add_one_desc(&bam, |
| 1688 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1689 | (unsigned char *)PA((addr_t)buffer), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1690 | ud_bytes_in_last_cw, |
| 1691 | 0); |
| 1692 | num_data_desc++; |
| 1693 | |
| 1694 | bam_add_one_desc(&bam, |
| 1695 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1696 | (unsigned char *)PA((addr_t)spareaddr), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1697 | oob_bytes, |
| 1698 | BAM_DESC_INT_FLAG); |
| 1699 | num_data_desc++; |
| 1700 | |
| 1701 | bam_sys_gen_event(&bam, DATA_PRODUCER_PIPE_INDEX, num_data_desc); |
| 1702 | } |
| 1703 | else |
| 1704 | { |
| 1705 | /* Add Data desc */ |
| 1706 | bam_add_one_desc(&bam, |
| 1707 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1708 | (unsigned char *)PA((addr_t)buffer), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1709 | DATA_BYTES_IN_IMG_PER_CW, |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1710 | 0); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1711 | num_data_desc++; |
| 1712 | bam_sys_gen_event(&bam, DATA_PRODUCER_PIPE_INDEX, num_data_desc); |
| 1713 | } |
| 1714 | |
| 1715 | /* Write addr loc 0. */ |
| 1716 | bam_add_cmd_element(cmd_list_ptr, |
| 1717 | NAND_READ_LOCATION_n(0), |
| 1718 | (uint32_t)addr_loc_0, |
| 1719 | CE_WRITE_TYPE); |
| 1720 | |
| 1721 | cmd_list_ptr++; |
| 1722 | bam_add_cmd_element(cmd_list_ptr, |
| 1723 | NAND_EXEC_CMD, |
| 1724 | (uint32_t)params.exec, |
| 1725 | CE_WRITE_TYPE); |
| 1726 | cmd_list_ptr++; |
| 1727 | |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1728 | /* Enqueue the desc for the above commands */ |
| 1729 | bam_add_one_desc(&bam, |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1730 | CMD_PIPE_INDEX, |
| 1731 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1732 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1733 | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG); |
| 1734 | num_cmd_desc++; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1735 | |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1736 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)&(flash_sts[i])), CE_READ_TYPE); |
| 1737 | |
vijay kumar | 4f4405f | 2014-08-08 11:49:53 +0530 | [diff] [blame] | 1738 | cmd_list_temp = (uint32_t *)cmd_list_ptr; |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1739 | |
| 1740 | cmd_list_ptr++; |
| 1741 | |
| 1742 | bam_add_cmd_element(cmd_list_ptr, NAND_BUFFER_STATUS, (uint32_t)PA((addr_t)&(buffer_sts[i])), CE_READ_TYPE); |
| 1743 | cmd_list_ptr++; |
| 1744 | |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1745 | /* Read erased CW status */ |
| 1746 | bam_add_cmd_element(cmd_list_ptr, NAND_ERASED_CW_DETECT_STATUS, (uint32_t)PA((addr_t)&erased_cw_sts[i]), CE_READ_TYPE); |
| 1747 | cmd_list_ptr++; |
| 1748 | |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1749 | if (i == flash.cws_per_page - 1) |
| 1750 | { |
| 1751 | flags = BAM_DESC_CMD_FLAG | BAM_DESC_UNLOCK_FLAG; |
| 1752 | } |
| 1753 | else |
| 1754 | flags = BAM_DESC_CMD_FLAG; |
| 1755 | |
| 1756 | /* Enqueue the desc for the above command */ |
| 1757 | bam_add_one_desc(&bam, |
| 1758 | CMD_PIPE_INDEX, |
| 1759 | (unsigned char*)PA((addr_t)cmd_list_temp), |
| 1760 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_temp), |
| 1761 | flags); |
| 1762 | num_cmd_desc++; |
| 1763 | |
| 1764 | buffer += DATA_BYTES_IN_IMG_PER_CW; |
| 1765 | |
| 1766 | /* Notify BAM HW about the newly added descriptors */ |
| 1767 | bam_sys_gen_event(&bam, CMD_PIPE_INDEX, num_cmd_desc); |
| 1768 | } |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1769 | |
| 1770 | qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); |
| 1771 | |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1772 | /* Check flash read status & errors */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1773 | for (i = 0; i < flash.cws_per_page ; i ++) |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1774 | { |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1775 | #if DEBUG_QPIC_NAND |
| 1776 | dprintf(INFO, "FLASH STATUS: 0x%08x, BUFFER STATUS: 0x%08x, ERASED CW STATUS: 0x%08x\n", |
| 1777 | flash_sts[i], buffer_sts[i], erased_cw_sts[i]); |
| 1778 | #endif |
| 1779 | |
| 1780 | /* If MPU or flash op erros are set, look for erased cw status. |
| 1781 | * If erased CW status is not set then look for bit flips to confirm |
| 1782 | * if the page is and erased page or a bad page |
| 1783 | */ |
| 1784 | if (flash_sts[i] & (NAND_FLASH_OP_ERR | NAND_FLASH_MPU_ERR)) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1785 | { |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1786 | if ((erased_cw_sts[i] & NAND_ERASED_CW) != NAND_ERASED_CW) |
| 1787 | { |
| 1788 | #if DEBUG_QPIC_NAND |
| 1789 | dprintf(CRITICAL, "Page: 0x%08x, addr0: 0x%08x, addr1: 0x%08x\n", page, params.addr0, params.addr1); |
| 1790 | #endif |
| 1791 | /* |
| 1792 | * Depending on the process technology used there could be bit flips on |
| 1793 | * pages on the NAND card |
| 1794 | * When any page is erased the controller fills the page with all 1's. |
| 1795 | * When we try to read from an erased page and there are bit flips the |
| 1796 | * controller would not detect the page as erased page instead throws |
| 1797 | * an uncorrectable ecc error. |
| 1798 | * The NAND data sheet for that card would specify the number of bit flips |
| 1799 | * expected per code word. If the number of bit flips is less than expected |
| 1800 | * bit flips then we should ignore the uncorrectable ECC error and consider |
| 1801 | * the page as an erased page. |
| 1802 | */ |
| 1803 | #if DEBUG_QPIC_NAND |
| 1804 | for(i = 0; i < 4096; i += 8) |
| 1805 | { |
| 1806 | printf("DATA: %x %x %x %x %x %x %x %x", |
| 1807 | buffer_temp[i], buffer_temp[i+1], buffer_temp[i+2], buffer_temp[i+3], |
| 1808 | buffer_temp[i+4], buffer_temp[i+5], buffer_temp[i+6], buffer_temp[i+7]); |
| 1809 | i += 8; |
| 1810 | printf("DATA: %x %x %x %x %x %x %x %x\n", |
| 1811 | buffer_temp[i], buffer_temp[i+1], buffer_temp[i+2], buffer_temp[i+3], |
| 1812 | buffer_temp[i+4], buffer_temp[i+5], buffer_temp[i+6], buffer_temp[i+7]); |
| 1813 | } |
| 1814 | #endif |
| 1815 | nand_ret = qpic_nand_read_erased_page(page); |
| 1816 | goto qpic_nand_read_page_error; |
| 1817 | } |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1818 | } |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 1819 | } |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1820 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1821 | qpic_nand_read_page_error: |
Channagoud Kadabi | b1dc47c | 2015-05-21 17:02:44 -0700 | [diff] [blame] | 1822 | return nand_ret; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1823 | } |
| 1824 | |
Tanya Brokhman | 72b44dc | 2015-01-07 10:20:05 +0200 | [diff] [blame] | 1825 | /** |
| 1826 | * qpic_nand_read() - read data |
| 1827 | * @start_page: number of page to begin reading from |
| 1828 | * @num_pages: number of pages to read |
| 1829 | * @buffer: buffer where to store the read data |
| 1830 | * @spareaddr: buffer where to store spare data. |
| 1831 | * If null, spare data wont be read |
| 1832 | * |
| 1833 | * This function reads @num_pages starting from @start_page and stores the |
| 1834 | * read data in buffer. Note that it's in the caller responsibility to make |
| 1835 | * sure the read pages are all from same partition. |
| 1836 | * |
| 1837 | * Returns nand_result_t |
| 1838 | */ |
| 1839 | nand_result_t qpic_nand_read(uint32_t start_page, uint32_t num_pages, |
| 1840 | unsigned char* buffer, unsigned char* spareaddr) |
| 1841 | { |
| 1842 | unsigned i = 0, ret = 0; |
| 1843 | |
| 1844 | if (!buffer) { |
| 1845 | dprintf(CRITICAL, "qpic_nand_read: buffer = null\n"); |
| 1846 | return NANDC_RESULT_PARAM_INVALID; |
| 1847 | } |
| 1848 | while (i < num_pages) { |
| 1849 | ret = qpic_nand_read_page(start_page + i, buffer + flash.page_size * i, |
| 1850 | spareaddr); |
| 1851 | i++; |
| 1852 | if (ret == NANDC_RESULT_BAD_PAGE) |
| 1853 | qpic_nand_mark_badblock(start_page + i); |
| 1854 | if (ret) { |
| 1855 | dprintf(CRITICAL, |
| 1856 | "qpic_nand_read: reading page %d failed with %d err\n", |
| 1857 | start_page + i, ret); |
| 1858 | return ret; |
| 1859 | } |
| 1860 | } |
| 1861 | return NANDC_RESULT_SUCCESS; |
| 1862 | } |
| 1863 | |
| 1864 | /** |
| 1865 | * qpic_nand_write() - read data |
| 1866 | * @start_page: number of page to begin writing to |
| 1867 | * @num_pages: number of pages to write |
| 1868 | * @buffer: buffer to be written |
| 1869 | * @write_extra_bytes: true if spare data (ox 0xff) to be written |
| 1870 | * |
| 1871 | * This function writes @num_pages starting from @start_page. Note that it's |
| 1872 | * in the caller responsibility to make sure the written pages are all from |
| 1873 | * same partition. |
| 1874 | * |
| 1875 | * Returns nand_result_t |
| 1876 | */ |
| 1877 | nand_result_t qpic_nand_write(uint32_t start_page, uint32_t num_pages, |
| 1878 | unsigned char* buffer, unsigned write_extra_bytes) |
| 1879 | { |
| 1880 | int i = 0, ret = NANDC_RESULT_SUCCESS; |
| 1881 | uint32_t *spare = (unsigned *)flash_spare_bytes; |
| 1882 | uint32_t wsize; |
| 1883 | uint32_t spare_byte_count = 0; |
| 1884 | |
| 1885 | if (!buffer) { |
| 1886 | dprintf(CRITICAL, "qpic_nand_write: buffer = null\n"); |
| 1887 | return NANDC_RESULT_PARAM_INVALID; |
| 1888 | } |
| 1889 | spare_byte_count = ((flash.cw_size * flash.cws_per_page)- flash.page_size); |
| 1890 | |
| 1891 | if (write_extra_bytes) |
| 1892 | wsize = flash.page_size + spare_byte_count; |
| 1893 | else |
| 1894 | wsize = flash.page_size; |
| 1895 | |
| 1896 | memset(spare, 0xff, (spare_byte_count / flash.cws_per_page)); |
| 1897 | |
| 1898 | for (i = 0; i < (int)num_pages; i++) { |
| 1899 | memcpy(rdwr_buf, buffer, flash.page_size); |
| 1900 | if (write_extra_bytes) { |
| 1901 | memcpy(rdwr_buf + flash.page_size, |
| 1902 | buffer + flash.page_size, spare_byte_count); |
| 1903 | ret = qpic_nand_write_page(start_page + i, |
| 1904 | NAND_CFG, rdwr_buf, rdwr_buf + flash.page_size); |
| 1905 | } else { |
| 1906 | ret = qpic_nand_write_page(start_page + i, |
| 1907 | NAND_CFG, rdwr_buf, spare); |
| 1908 | } |
| 1909 | if (ret) { |
| 1910 | dprintf(CRITICAL, |
| 1911 | "flash_write: write failure @ page %d, block %d\n", |
| 1912 | start_page + i, |
| 1913 | (start_page + i) / flash.num_pages_per_blk); |
| 1914 | if (ret == NANDC_RESULT_BAD_PAGE) |
| 1915 | qpic_nand_mark_badblock(start_page + i); |
| 1916 | goto out; |
| 1917 | } |
| 1918 | buffer += wsize; |
| 1919 | } |
| 1920 | out: |
| 1921 | return ret; |
| 1922 | } |
| 1923 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1924 | /* Function to read a flash partition. |
| 1925 | * ptn : Partition to read. |
| 1926 | * extra_per_page : Spare data to be read. |
| 1927 | * offset : Num of bytes offset into the partition. |
| 1928 | * data : Buffer to read the data into. |
| 1929 | * bytes : Num of bytes to be read. |
| 1930 | */ |
| 1931 | /* TODO: call this func read_partition. */ |
| 1932 | int |
| 1933 | flash_read_ext(struct ptentry *ptn, |
| 1934 | unsigned extra_per_page, |
| 1935 | unsigned offset, |
| 1936 | void *data, |
| 1937 | unsigned bytes) |
| 1938 | { |
| 1939 | uint32_t page = |
| 1940 | (ptn->start * flash.num_pages_per_blk) + (offset / flash.page_size); |
| 1941 | uint32_t lastpage = (ptn->start + ptn->length) * flash.num_pages_per_blk; |
| 1942 | uint32_t count = |
| 1943 | (bytes + flash.page_size - 1 + extra_per_page) / (flash.page_size + |
| 1944 | extra_per_page); |
| 1945 | uint32_t *spare = (unsigned *)flash_spare_bytes; |
| 1946 | uint32_t errors = 0; |
| 1947 | unsigned char *image = data; |
| 1948 | int result = 0; |
| 1949 | uint32_t current_block = |
| 1950 | (page - (page & flash.num_pages_per_blk_mask)) / flash.num_pages_per_blk; |
| 1951 | uint32_t start_block = ptn->start; |
| 1952 | uint32_t start_block_count = 0; |
| 1953 | uint32_t isbad = 0; |
Deepa Dinamani | 2f7006c | 2013-08-19 11:59:38 -0700 | [diff] [blame] | 1954 | uint32_t current_page; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1955 | |
| 1956 | /* Verify first byte is at page boundary. */ |
| 1957 | if (offset & (flash.page_size - 1)) |
| 1958 | { |
| 1959 | dprintf(CRITICAL, "Read request start not at page boundary: %d\n", |
| 1960 | offset); |
| 1961 | return NANDC_RESULT_PARAM_INVALID; |
| 1962 | } |
| 1963 | |
Deepa Dinamani | 2f7006c | 2013-08-19 11:59:38 -0700 | [diff] [blame] | 1964 | current_page = start_block * flash.num_pages_per_blk; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1965 | /* Adjust page offset based on number of bad blocks from start to current page */ |
| 1966 | if (start_block < current_block) |
| 1967 | { |
| 1968 | start_block_count = (current_block - start_block); |
| 1969 | while (start_block_count |
| 1970 | && (start_block < (ptn->start + ptn->length))) |
| 1971 | { |
Deepa Dinamani | 2f7006c | 2013-08-19 11:59:38 -0700 | [diff] [blame] | 1972 | isbad = qpic_nand_block_isbad(current_page); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1973 | if (isbad) |
| 1974 | page += flash.num_pages_per_blk; |
| 1975 | else |
| 1976 | start_block_count--; |
| 1977 | start_block++; |
Deepa Dinamani | 2f7006c | 2013-08-19 11:59:38 -0700 | [diff] [blame] | 1978 | current_page += flash.num_pages_per_blk; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1979 | } |
| 1980 | } |
| 1981 | |
| 1982 | while ((page < lastpage) && !start_block_count) |
| 1983 | { |
| 1984 | if (count == 0) |
| 1985 | { |
Deepa Dinamani | 52aca8d | 2013-02-05 11:41:41 -0800 | [diff] [blame] | 1986 | dprintf(SPEW, "flash_read_image: success (%d errors)\n", |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1987 | errors); |
| 1988 | return NANDC_RESULT_SUCCESS; |
| 1989 | } |
| 1990 | |
Sundarajan Srinivasan | 29d927c | 2014-02-10 14:11:24 -0800 | [diff] [blame] | 1991 | #if CONTIGUOUS_MEMORY |
| 1992 | result = qpic_nand_read_page(page, image, (unsigned char *) spare); |
| 1993 | #else |
| 1994 | result = qpic_nand_read_page(page, rdwr_buf, (unsigned char *) spare); |
| 1995 | #endif |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1996 | if (result == NANDC_RESULT_BAD_PAGE) |
| 1997 | { |
| 1998 | /* bad page, go to next page. */ |
| 1999 | page++; |
| 2000 | errors++; |
| 2001 | continue; |
| 2002 | } |
| 2003 | else if (result == NANDC_RESULT_BAD_BLOCK) |
| 2004 | { |
| 2005 | /* bad block, go to next block same offset. */ |
| 2006 | page += flash.num_pages_per_blk; |
| 2007 | errors++; |
| 2008 | continue; |
| 2009 | } |
| 2010 | |
Sundarajan Srinivasan | 29d927c | 2014-02-10 14:11:24 -0800 | [diff] [blame] | 2011 | #ifndef CONTIGUOUS_MEMORY |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 2012 | /* Copy the read page into correct location. */ |
| 2013 | memcpy(image, rdwr_buf, flash.page_size); |
Sundarajan Srinivasan | 29d927c | 2014-02-10 14:11:24 -0800 | [diff] [blame] | 2014 | #endif |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2015 | page++; |
| 2016 | image += flash.page_size; |
| 2017 | /* Copy spare bytes to image */ |
Sundarajan Srinivasan | 29d927c | 2014-02-10 14:11:24 -0800 | [diff] [blame] | 2018 | if(extra_per_page) |
| 2019 | { |
| 2020 | memcpy(image, spare, extra_per_page); |
| 2021 | image += extra_per_page; |
| 2022 | } |
| 2023 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2024 | count -= 1; |
| 2025 | } |
| 2026 | |
| 2027 | /* could not find enough valid pages before we hit the end */ |
| 2028 | dprintf(CRITICAL, "flash_read_image: failed (%d errors)\n", errors); |
| 2029 | return NANDC_RESULT_FAILURE; |
| 2030 | } |
| 2031 | |
| 2032 | int |
| 2033 | flash_erase(struct ptentry *ptn) |
| 2034 | { |
Tanya Brokhman | 646eedb | 2015-01-06 23:09:54 +0200 | [diff] [blame] | 2035 | int ret = 0, i; |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 2036 | |
Tanya Brokhman | 646eedb | 2015-01-06 23:09:54 +0200 | [diff] [blame] | 2037 | for (i = 0; i < (int)ptn->length; i++) { |
| 2038 | ret = qpic_nand_blk_erase((ptn->start + i) * flash.num_pages_per_blk); |
| 2039 | if (ret) |
| 2040 | dprintf(CRITICAL, "Erase operation failed @ page #%d\n", |
| 2041 | ptn->start + i); |
| 2042 | } |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 2043 | return ret; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2044 | } |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 2045 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2046 | int |
| 2047 | flash_ecc_bch_enabled() |
| 2048 | { |
| 2049 | return (flash.ecc_width == NAND_WITH_4_BIT_ECC)? 0 : 1; |
| 2050 | } |
| 2051 | |
| 2052 | int |
| 2053 | flash_write(struct ptentry *ptn, |
Deepa Dinamani | c13d594 | 2013-04-30 15:48:53 -0700 | [diff] [blame] | 2054 | unsigned write_extra_bytes, |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2055 | const void *data, |
| 2056 | unsigned bytes) |
| 2057 | { |
| 2058 | uint32_t page = ptn->start * flash.num_pages_per_blk; |
| 2059 | uint32_t lastpage = (ptn->start + ptn->length) * flash.num_pages_per_blk; |
| 2060 | uint32_t *spare = (unsigned *)flash_spare_bytes; |
| 2061 | const unsigned char *image = data; |
Deepa Dinamani | c13d594 | 2013-04-30 15:48:53 -0700 | [diff] [blame] | 2062 | uint32_t wsize; |
Sundarajan Srinivasan | 223d700 | 2014-02-11 19:48:11 -0800 | [diff] [blame] | 2063 | uint32_t spare_byte_count = 0; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2064 | int r; |
| 2065 | |
Sundarajan Srinivasan | 223d700 | 2014-02-11 19:48:11 -0800 | [diff] [blame] | 2066 | spare_byte_count = ((flash.cw_size * flash.cws_per_page)- flash.page_size); |
| 2067 | |
Deepa Dinamani | c13d594 | 2013-04-30 15:48:53 -0700 | [diff] [blame] | 2068 | if(write_extra_bytes) |
Sundarajan Srinivasan | 223d700 | 2014-02-11 19:48:11 -0800 | [diff] [blame] | 2069 | wsize = flash.page_size + spare_byte_count; |
Deepa Dinamani | c13d594 | 2013-04-30 15:48:53 -0700 | [diff] [blame] | 2070 | else |
| 2071 | wsize = flash.page_size; |
| 2072 | |
Sundarajan Srinivasan | 223d700 | 2014-02-11 19:48:11 -0800 | [diff] [blame] | 2073 | memset(spare, 0xff, (spare_byte_count / flash.cws_per_page)); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2074 | |
| 2075 | while (bytes > 0) |
| 2076 | { |
| 2077 | if (bytes < wsize) |
| 2078 | { |
| 2079 | dprintf(CRITICAL, |
| 2080 | "flash_write_image: image undersized (%d < %d)\n", |
| 2081 | bytes, |
| 2082 | wsize); |
| 2083 | return -1; |
| 2084 | } |
| 2085 | |
| 2086 | if (page >= lastpage) |
| 2087 | { |
| 2088 | dprintf(CRITICAL, "flash_write_image: out of space\n"); |
| 2089 | return -1; |
| 2090 | } |
| 2091 | |
| 2092 | if ((page & flash.num_pages_per_blk_mask) == 0) |
| 2093 | { |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 2094 | if (qpic_nand_blk_erase(page)) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2095 | { |
| 2096 | dprintf(INFO, |
| 2097 | "flash_write_image: bad block @ %d\n", |
| 2098 | page / flash.num_pages_per_blk); |
| 2099 | |
| 2100 | page += flash.num_pages_per_blk; |
| 2101 | continue; |
| 2102 | } |
| 2103 | } |
| 2104 | |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 2105 | memcpy(rdwr_buf, image, flash.page_size); |
| 2106 | |
Deepa Dinamani | c13d594 | 2013-04-30 15:48:53 -0700 | [diff] [blame] | 2107 | if (write_extra_bytes) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2108 | { |
Sundarajan Srinivasan | 223d700 | 2014-02-11 19:48:11 -0800 | [diff] [blame] | 2109 | memcpy(rdwr_buf + flash.page_size, image + flash.page_size, spare_byte_count); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2110 | r = qpic_nand_write_page(page, |
| 2111 | NAND_CFG, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 2112 | rdwr_buf, |
| 2113 | rdwr_buf + flash.page_size); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2114 | } |
| 2115 | else |
| 2116 | { |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 2117 | r = qpic_nand_write_page(page, NAND_CFG, rdwr_buf, spare); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 2118 | } |
| 2119 | |
| 2120 | if (r) |
| 2121 | { |
| 2122 | dprintf(INFO, |
| 2123 | "flash_write_image: write failure @ page %d (src %d)\n", |
| 2124 | page, |
| 2125 | image - (const unsigned char *)data); |
| 2126 | |
| 2127 | image -= (page & flash.num_pages_per_blk_mask) * wsize; |
| 2128 | bytes += (page & flash.num_pages_per_blk_mask) * wsize; |
| 2129 | page &= ~flash.num_pages_per_blk_mask; |
| 2130 | if (qpic_nand_blk_erase(page)) |
| 2131 | { |
| 2132 | dprintf(INFO, |
| 2133 | "flash_write_image: erase failure @ page %d\n", |
| 2134 | page); |
| 2135 | } |
| 2136 | |
| 2137 | qpic_nand_mark_badblock(page); |
| 2138 | |
| 2139 | dprintf(INFO, |
| 2140 | "flash_write_image: restart write @ page %d (src %d)\n", |
| 2141 | page, image - (const unsigned char *)data); |
| 2142 | |
| 2143 | page += flash.num_pages_per_blk; |
| 2144 | continue; |
| 2145 | } |
| 2146 | page++; |
| 2147 | image += wsize; |
| 2148 | bytes -= wsize; |
| 2149 | } |
| 2150 | |
| 2151 | /* erase any remaining pages in the partition */ |
| 2152 | page = (page + flash.num_pages_per_blk_mask) & (~flash.num_pages_per_blk_mask); |
| 2153 | |
| 2154 | while (page < lastpage) |
| 2155 | { |
| 2156 | if (qpic_nand_blk_erase(page)) |
| 2157 | { |
| 2158 | dprintf(INFO, "flash_write_image: bad block @ %d\n", |
| 2159 | page / flash.num_pages_per_blk); |
| 2160 | } |
| 2161 | page += flash.num_pages_per_blk; |
| 2162 | } |
| 2163 | |
| 2164 | dprintf(INFO, "flash_write_image: success\n"); |
| 2165 | return 0; |
| 2166 | } |
Smita Ghosh | f5431c6 | 2014-09-18 14:11:14 -0700 | [diff] [blame] | 2167 | |
| 2168 | uint32_t nand_device_base() |
| 2169 | { |
| 2170 | return nand_base; |
| 2171 | } |