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gerrit-public.fairphone.software / kernel / lk / a6cedd20ff10d4bab0269a241621933a9b047084 / . / platform / msm8996 / include / platform / iomap.h
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Tatenda Chipeperekwab785c042015-11-02 11:56:51 -0800[diff] [blame]1/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_THULIUM_IOMAP_H_
30#define _PLATFORM_THULIUM_IOMAP_H_
31
32#define MSM_SHARED_BASE 0x86000000
33
34#define MSM_IOMAP_HMSS_START 0x09800000
35
36#define MSM_IOMAP_BASE 0x00000000
37#define MSM_IOMAP_END 0x10000000
38
39#define MSM_SHARED_IMEM_BASE 0x066BF000
40#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]41#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + 0x6B0)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]42
43#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
44#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
45
46#define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000)
47#define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE
48
Sridhar Parasurambe12c3d2015-01-16 13:42:26 -0800[diff] [blame]49#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS 0x00068000
50#define RPM_SS_MSG_RAM_START_ADDRESS_BASE RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS
51#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE 0x00006000
52
Sridhar Parasuram103702f2015-01-26 18:07:55 -0800[diff] [blame]53#define APCS_HLOS_IPC_INTERRUPT_0 0x9820010
54
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]55#define PERIPH_SS_BASE 0x07400000
56
57#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000)
58#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
59#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
60#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
61
62#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0016F000)
63#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x00170000)
64#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x00171000)
65#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00172000)
66#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00173000)
67#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00174000)
68
69#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x001B0000)
70
Siddharth Zaveri1cf08b92015-12-02 17:09:14 -0500[diff] [blame]71/* I2C */
72#define BLSP_QUP_BASE(blsp_id, qup_id) (PERIPH_SS_BASE + ((blsp_id) - 1) * 0x100000 \
73 + 0xB5000 + 0x1000 * (qup_id))
74#define GCC_BLSP2_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x28008)
75#define GCC_BLSP2_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x28010)
76#define GCC_BLSP2_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x2800C)
77
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]78/* USB3.0 */
79#define MSM_USB30_BASE 0x6A00000
80#define MSM_USB30_QSCRATCH_BASE 0x6AF8800
81/* SS QMP (Qulacomm Multi Protocol) */
82#define QMP_PHY_BASE 0x7410000
83
84/* QUSB2 PHY */
85#define QUSB2_PHY_BASE 0x7411000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]86#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00012038)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]87
Channagoud Kadabi4517eb12015-09-02 18:43:13 -0700[diff] [blame]88#define AHB2_PHY_BASE 0x7416000
89#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
Channagoud Kadabidf6d7ad2015-09-24 15:17:03 -0700[diff] [blame]90#define GCC_RX2_USB2_CLKREF_EN 0x00388014
Channagoud Kadabi4517eb12015-09-02 18:43:13 -0700[diff] [blame]91
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]92/* Clocks */
93#define CLK_CTL_BASE 0x300000
94
c_wufeng78f7a5f2015-09-21 13:02:06 +0800[diff] [blame]95#define PMI_SLAVE_BASE 2
96#define PMI_FIRST_SLAVE_OFFSET 0
97#define PMI_SECOND_SLAVE_OFFSET 1
98
99#define PMI_FIRST_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_FIRST_SLAVE_OFFSET ) << 16)
100#define PMI_SECOND_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_SECOND_SLAVE_OFFSET) << 16)
101
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]102/* GPLL */
103#define GPLL0_MODE (CLK_CTL_BASE + 0x0000)
104#define GPLL4_MODE (CLK_CTL_BASE + 0x77000)
105#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x52000)
106#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
107
108/* UART Clocks */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]109#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x25004)
110#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29004)
Channagoud Kadabi35503c42014-11-14 16:22:43 -0800[diff] [blame]111#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C)
112#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010)
113#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014)
114#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0x29018)
115#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0x2901C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]116
117/* USB3 clocks */
118#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]119#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]120#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]121#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
122#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]123#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014)
124#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018)
125#define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C)
126#define USB30_MASTER_N (CLK_CTL_BASE + 0xF020)
127#define USB30_MASTER_D (CLK_CTL_BASE + 0xF024)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]128#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF028)
129#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF02C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]130#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C)
131
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]132#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C)
133#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010)
134#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000)
135#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004)
136#define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020)
137#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]138#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]139#define GCC_AGGRE2_USB3_AXI_CBCR (CLK_CTL_BASE + 0x83018)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]140
141/* SDCC */
142#define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */
143#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x13004) /* branch control */
144#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x13008)
145#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x13010) /* cmd */
146#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x13014) /* cfg */
147#define SDCC1_M (CLK_CTL_BASE + 0x13018) /* m */
148#define SDCC1_N (CLK_CTL_BASE + 0x1301C) /* n */
149#define SDCC1_D (CLK_CTL_BASE + 0x13020) /* d */
150
151/* SDCC2 */
152#define SDCC2_BCR (CLK_CTL_BASE + 0x14000) /* block reset */
153#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x14004) /* branch control */
154#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x14008)
155#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x14010) /* cmd */
156#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x14014) /* cfg */
157#define SDCC2_M (CLK_CTL_BASE + 0x14018) /* m */
158#define SDCC2_N (CLK_CTL_BASE + 0x1401C) /* n */
159#define SDCC2_D (CLK_CTL_BASE + 0x14020) /* d */
160
161#define UFS_BASE 0x624000
162
163#define SPMI_BASE 0x4000000
164#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
165#define SPMI_PIC_BASE (SPMI_BASE + 0x1800000)
Channagoud Kadabi7b20dea2014-11-11 13:27:33 -0800[diff] [blame]166#define PMIC_ARB_CORE 0x400F000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]167
Channagoud Kadabi037c8b82015-02-05 12:09:32 -0800[diff] [blame]168#define MSM_CE_BAM_BASE 0x644000
169#define MSM_CE_BASE 0x67A000
170#define GCC_CE1_BCR (CLK_CTL_BASE + 0x00041000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]171
172#define TLMM_BASE_ADDR 0x1010000
173#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
174#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x4 + (x)*0x1000)
175
176#define MPM2_MPM_CTRL_BASE 0x4A1000
177#define MPM2_MPM_PS_HOLD 0x4AB000
178#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
179
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]180/* QSEECOM: Secure app region notification */
181#define APP_REGION_ADDR 0x86600000
Zhen Kong327fac52015-06-12 17:04:24 -0700[diff] [blame]182#define APP_REGION_SIZE 0x2200000
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]183
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]184/* DRV strength for sdcc */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]185#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0012C000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]186
187/* SDHCI - power control registers */
188#define SDCC_MCI_HC_MODE (0x00000078)
189#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
190#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
191#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
192#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
193
194/* Boot config */
195#define SEC_CTRL_CORE_BASE 0x70000
196#define BOOT_CONFIG_OFFSET 0x00006044
197#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
198
Channagoud Kadabi652a6f62014-11-17 17:23:23 -0800[diff] [blame]199/* QMP rev registers */
200#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x788)
201#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x78C)
202#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x790)
203#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x794)
204
205/* Dummy macro needed for compilation only */
206#define PLATFORM_QMP_OFFSET 0x0
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]207
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]208/* RPMB send receive buffer needs to be mapped
209 * as device memory, define the start address
210 * and size in MB
211 */
Channagoud Kadabi40039922015-09-29 15:23:03 -0700[diff] [blame]212#define RPMB_SND_RCV_BUF 0x91A00000
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700[diff] [blame]213#define RPMB_SND_RCV_BUF_SZ 0x2
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]214
Channagoud Kadabi23edc0c2015-03-27 18:31:32 -0700[diff] [blame]215#define TCSR_BOOT_MISC_DETECT 0x007B3000
Dhaval Patel0f3cbeb2015-03-17 11:52:12 -0700[diff] [blame]216
217#define MSM_MMSS_CLK_CTL_BASE 0x8C0000
218#define MMSS_MISC_AHB_CBCR (MSM_MMSS_CLK_CTL_BASE + 0x5018)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]219
220#define MIPI_DSI_BASE (0x994000)
221#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
222#define MIPI_DSI1_BASE (0x996000)
223#define DSI0_PHY_BASE (0x994400)
224#define DSI1_PHY_BASE (0x996400)
225#define DSI0_PLL_BASE (0x994800)
226#define DSI1_PLL_BASE (0x996800)
227#define DSI0_REGULATOR_BASE (0x994000)
228#define DSI1_REGULATOR_BASE (0x996000)
229
Jeevan Shriram3c20e632015-08-03 15:21:04 -0700[diff] [blame]230#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0D0
231#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0D4
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]232
233#define MDP_BASE (0x900000)
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]234#define REG_MDP(off) (MDP_BASE + (off))
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]235
236#ifdef MDP_PP_0_BASE
237#undef MDP_PP_0_BASE
238#endif
239#define MDP_PP_0_BASE REG_MDP(0x71000)
240
241#ifdef MDP_PP_1_BASE
242#undef MDP_PP_1_BASE
243#endif
244#define MDP_PP_1_BASE REG_MDP(0x71800)
245
Ujwal Patel41a665a2015-07-17 13:51:30 -0700[diff] [blame]246#ifdef MDP_DSC_0_BASE
247#undef MDP_DSC_0_BASE
248#endif
249#define MDP_DSC_0_BASE REG_MDP(0x81000)
250
251#ifdef MDP_DSC_1_BASE
252#undef MDP_DSC_1_BASE
253#endif
254#define MDP_DSC_1_BASE REG_MDP(0x81400)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]255
256#ifdef MDP_HW_REV
257#undef MDP_HW_REV
258#endif
259#define MDP_HW_REV REG_MDP(0x1000)
260
261#ifdef MDP_INTR_EN
262#undef MDP_INTR_EN
263#endif
264#define MDP_INTR_EN REG_MDP(0x1010)
265
266#ifdef MDP_INTR_CLEAR
267#undef MDP_INTR_CLEAR
268#endif
269#define MDP_INTR_CLEAR REG_MDP(0x1018)
270
271#ifdef MDP_HIST_INTR_EN
272#undef MDP_HIST_INTR_EN
273#endif
274#define MDP_HIST_INTR_EN REG_MDP(0x101C)
275
276#ifdef MDP_DISP_INTF_SEL
277#undef MDP_DISP_INTF_SEL
278#endif
279#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
280
281#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
282#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
283#endif
284#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
285
286#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
287#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
288#endif
289#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
290
291#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
292#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
293#endif
294#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
295
296#ifdef MDP_INTF_0_TIMING_ENGINE_EN
297#undef MDP_INTF_0_TIMING_ENGINE_EN
298#endif
299#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
300
301#ifdef MDP_INTF_1_TIMING_ENGINE_EN
302#undef MDP_INTF_1_TIMING_ENGINE_EN
303#endif
304#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
305
306#ifdef MDP_INTF_2_TIMING_ENGINE_EN
307#undef MDP_INTF_2_TIMING_ENGINE_EN
308#endif
309#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x6C000)
310
Tatenda Chipeperekwab785c042015-11-02 11:56:51 -0800[diff] [blame]311#ifdef MDP_INTF_3_TIMING_ENGINE_EN
312#undef MDP_INTF_3_TIMING_ENGINE_EN
313#endif
314#define MDP_INTF_3_TIMING_ENGINE_EN REG_MDP(0x6C800)
315
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]316#ifdef MDP_CTL_0_BASE
317#undef MDP_CTL_0_BASE
318#endif
319#define MDP_CTL_0_BASE REG_MDP(0x2000)
320
321#ifdef MDP_CTL_1_BASE
322#undef MDP_CTL_1_BASE
323#endif
324#define MDP_CTL_1_BASE REG_MDP(0x2200)
325
326#ifdef MDP_REG_SPLIT_DISPLAY_EN
327#undef MDP_REG_SPLIT_DISPLAY_EN
328#endif
329#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
330
331#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
332#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
333#endif
334#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
335
336#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
337#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
338#endif
339#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
340
341#ifdef MDP_INTF_0_BASE
342#undef MDP_INTF_0_BASE
343#endif
344#define MDP_INTF_0_BASE REG_MDP(0x6b000)
345
346#ifdef MDP_INTF_1_BASE
347#undef MDP_INTF_1_BASE
348#endif
349#define MDP_INTF_1_BASE REG_MDP(0x6b800)
350
351#ifdef MDP_INTF_2_BASE
352#undef MDP_INTF_2_BASE
353#endif
354#define MDP_INTF_2_BASE REG_MDP(0x6c000)
355
Tatenda Chipeperekwab785c042015-11-02 11:56:51 -0800[diff] [blame]356#ifdef MDP_INTF_3_BASE
357#undef MDP_INTF_3_BASE
358#endif
359#define MDP_INTF_3_BASE REG_MDP(0x6c800)
360
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]361#ifdef MDP_CLK_CTRL0
362#undef MDP_CLK_CTRL0
363#endif
364#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
365
366#ifdef MDP_CLK_CTRL1
367#undef MDP_CLK_CTRL1
368#endif
369#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
370
371#ifdef MDP_CLK_CTRL2
372#undef MDP_CLK_CTRL2
373#endif
374#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
375
376#ifdef MDP_CLK_CTRL3
377#undef MDP_CLK_CTRL3
378#endif
379#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
380
381#ifdef MDP_CLK_CTRL4
382#undef MDP_CLK_CTRL4
383#endif
384#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
385
386#ifdef MDP_CLK_CTRL5
387#undef MDP_CLK_CTRL5
388#endif
389#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
390
391#ifdef MDP_CLK_CTRL6
392#undef MDP_CLK_CTRL6
393#endif
394#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
395
396#ifdef MDP_CLK_CTRL7
397#undef MDP_CLK_CTRL7
398#endif
399#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
400
401#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
402#undef MMSS_MDP_SMP_ALLOC_W_BASE
403#endif
404#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
405
406#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
407#undef MMSS_MDP_SMP_ALLOC_R_BASE
408#endif
409#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
410
411#ifdef MDP_QOS_REMAPPER_CLASS_0
412#undef MDP_QOS_REMAPPER_CLASS_0
413#endif
414#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
415
416#ifdef MDP_QOS_REMAPPER_CLASS_1
417#undef MDP_QOS_REMAPPER_CLASS_1
418#endif
419#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
420
421#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
422#undef VBIF_VBIF_DDR_FORCE_CLK_ON
423#endif
424#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xb0004)
425
426#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
427#undef VBIF_VBIF_DDR_OUT_MAX_BURST
428#endif
429#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xb00D8)
430
431#ifdef VBIF_VBIF_DDR_ARB_CTRL
432#undef VBIF_VBIF_DDR_ARB_CTRL
433#endif
434#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xb00F0)
435
436#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
437#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
438#endif
439#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xb0124)
440
441#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
442#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
443#endif
444#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xb0160)
445
446#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
447#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
448#endif
449#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xb0164)
450
451#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
452#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
453#endif
454#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xb0178)
455
456#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
457#undef VBIF_VBIF_DDR_OUT_AX_AOOO
458#endif
459#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xb017C)
460
461#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
462#undef VBIF_VBIF_IN_RD_LIM_CONF0
463#endif
464#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xb00B0)
465
466#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
467#undef VBIF_VBIF_IN_RD_LIM_CONF1
468#endif
469#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xb00B4)
470
471#ifdef VBIF_VBIF_IN_RD_LIM_CONF2
472#undef VBIF_VBIF_IN_RD_LIM_CONF2
473#endif
474#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xb00B8)
475
476#ifdef VBIF_VBIF_IN_RD_LIM_CONF3
477#undef VBIF_VBIF_IN_RD_LIM_CONF3
478#endif
479#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xb00BC)
480
481#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
482#undef VBIF_VBIF_IN_WR_LIM_CONF0
483#endif
484#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xb00C0)
485
486#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
487#undef VBIF_VBIF_IN_WR_LIM_CONF1
488#endif
489#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xb00C4)
490
491#ifdef VBIF_VBIF_IN_WR_LIM_CONF2
492#undef VBIF_VBIF_IN_WR_LIM_CONF2
493#endif
494#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xb00C8)
495
496#ifdef VBIF_VBIF_IN_WR_LIM_CONF3
497#undef VBIF_VBIF_IN_WR_LIM_CONF3
498#endif
499#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xb00CC)
500
501#ifdef VBIF_VBIF_ABIT_SHORT
502#undef VBIF_VBIF_ABIT_SHORT
503#endif
504#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xb0070)
505
506#ifdef VBIF_VBIF_ABIT_SHORT_CONF
507#undef VBIF_VBIF_ABIT_SHORT_CONF
508#endif
509#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xb0074)
510
511#ifdef VBIF_VBIF_GATE_OFF_WRREQ_EN
512#undef VBIF_VBIF_GATE_OFF_WRREQ_EN
513#endif
514#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xb00A8)
515
516#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
517#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
518#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
519#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
520#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
521#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
522#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
523#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
524
525#define DMA_CMD_OFFSET 0x048
526#define DMA_CMD_LENGTH 0x04C
527
528#define INT_CTRL 0x110
529#define CMD_MODE_DMA_SW_TRIGGER 0x090
530
531#define EOT_PACKET_CTRL 0x0CC
532#define MISR_CMD_CTRL 0x0A0
533#define MISR_VIDEO_CTRL 0x0A4
534#define VIDEO_MODE_CTRL 0x010
535#define HS_TIMER_CTRL 0x0BC
536
537#define SOFT_RESET 0x118
538#define CLK_CTRL 0x11C
539#define TRIG_CTRL 0x084
540#define CTRL 0x004
541#define COMMAND_MODE_DMA_CTRL 0x03C
542#define COMMAND_MODE_MDP_CTRL 0x040
543#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
544#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
545#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
546#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
547#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
548#define ERR_INT_MASK0 0x10C
549
550#define LANE_CTL 0x0AC
551#define LANE_SWAP_CTL 0x0B0
552#define TIMING_CTL 0x0C4
553
554#define VIDEO_MODE_ACTIVE_H 0x024
555#define VIDEO_MODE_ACTIVE_V 0x028
556#define VIDEO_MODE_TOTAL 0x02C
557#define VIDEO_MODE_HSYNC 0x030
558#define VIDEO_MODE_VSYNC 0x034
559#define VIDEO_MODE_VSYNC_VPOS 0x038
560
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]561#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
562#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
563#define CMD_COMPRESSION_MODE_CTRL 0x2A8
564#define CMD_COMPRESSION_MODE_CTRL_2 0x2Ac
565#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
566
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]567#define QPNP_LED_CTRL_BASE 0xD000
568#define QPNP_BLUE_LPG_CTRL_BASE 0xB100
569#define QPNP_GREEN_LPG_CTRL_BASE 0xB200
570#define QPNP_RED_LPG_CTRL_BASE 0xB300
571
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700[diff] [blame]572#define APSS_WDOG_BASE 0x9830000
573#define APPS_WDOG_BARK_VAL_REG (APSS_WDOG_BASE + 0x10)
574#define APPS_WDOG_BITE_VAL_REG (APSS_WDOG_BASE + 0x14)
575#define APPS_WDOG_RESET_REG (APSS_WDOG_BASE + 0x04)
576#define APPS_WDOG_CTL_REG (APSS_WDOG_BASE + 0x08)
577
Tatenda Chipeperekwab785c042015-11-02 11:56:51 -0800[diff] [blame]578/* HDMI reg addresses */
579#define HDMI_BASE 0x9A0000
580#define REG_HDMI(off) (HDMI_BASE + (off))
581
582#define HDMI_ACR_32_0 REG_HDMI(0xC4)
583#define HDMI_ACR_32_1 REG_HDMI(0xC8)
584#define HDMI_ACR_44_0 REG_HDMI(0xCC)
585#define HDMI_ACR_44_1 REG_HDMI(0xD0)
586#define HDMI_ACR_48_0 REG_HDMI(0xD4)
587#define HDMI_ACR_48_1 REG_HDMI(0xD8)
588#define HDMI_AUDIO_PKT_CTRL2 REG_HDMI(0x44)
589#define HDMI_ACR_PKT_CTRL REG_HDMI(0x24)
590#define HDMI_INFOFRAME_CTRL0 REG_HDMI(0x2C)
Tatenda Chipeperekwa40196782016-02-23 16:29:30 -0800[diff] [blame]591#define HDMI_INFOFRAME_CTRL1 REG_HDMI(0x30)
Tatenda Chipeperekwab785c042015-11-02 11:56:51 -0800[diff] [blame]592#define HDMI_AUDIO_INFO0 REG_HDMI(0xE4)
593#define HDMI_AUDIO_INFO1 REG_HDMI(0xE8)
594#define HDMI_AUDIO_PKT_CTRL REG_HDMI(0x20)
595#define HDMI_VBI_PKT_CTRL REG_HDMI(0x28)
596#define HDMI_GEN_PKT_CTRL REG_HDMI(0x34)
597#define HDMI_GC REG_HDMI(0x40)
598#define HDMI_AUDIO_CFG REG_HDMI(0x1D0)
599
600#define HDMI_DDC_SPEED REG_HDMI(0x220)
601#define HDMI_DDC_SETUP REG_HDMI(0x224)
602#define HDMI_DDC_REF REG_HDMI(0x27C)
603#define HDMI_DDC_DATA REG_HDMI(0x238)
604#define HDMI_DDC_TRANS0 REG_HDMI(0x228)
605#define HDMI_DDC_TRANS1 REG_HDMI(0x22C)
Tatenda Chipeperekwaa6cedd22016-03-28 11:44:30 -0700[diff] [blame^]606#define HDMI_DDC_TRANS2 REG_HDMI(0x230)
607#define HDMI_DDC_TRANS3 REG_HDMI(0x234)
Tatenda Chipeperekwab785c042015-11-02 11:56:51 -0800[diff] [blame]608#define HDMI_DDC_CTRL REG_HDMI(0x20C)
609#define HDMI_DDC_INT_CTRL REG_HDMI(0x214)
610#define HDMI_DDC_SW_STATUS REG_HDMI(0x218)
611#define HDMI_DDC_ARBITRATION REG_HDMI(0x210)
Tatenda Chipeperekwaa6cedd22016-03-28 11:44:30 -0700[diff] [blame^]612#define HDMI_HW_DDC_CTRL REG_HDMI(0x4CC)
613#define HDMI_DDC_INT_CTRL0 REG_HDMI(0x430)
614#define HDMI_DDC_INT_CTRL1 REG_HDMI(0x434)
615#define HDMI_DDC_INT_CTRL2 REG_HDMI(0x438)
616#define HDMI_DDC_INT_CTRL3 REG_HDMI(0x43C)
617#define HDMI_DDC_INT_CTRL4 REG_HDMI(0x440)
618#define HDMI_DDC_INT_CTRL5 REG_HDMI(0x444)
619#define HDMI_DDC_HW_STATUS REG_HDMI(0x21C)
620#define HDMI_SCRAMBLER_STATUS_DDC_CTRL REG_HDMI(0x464)
621#define HDMI_SCRAMBLER_STATUS_DDC_TIMER_CTRL REG_HDMI(0x468)
622#define HDMI_SCRAMBLER_STATUS_DDC_TIMER_CTRL2 REG_HDMI(0x46C)
623#define HDMI_SCRAMBLER_STATUS_DDC_STATUS REG_HDMI(0x470)
624#define HDMI_SCRAMBLER_STATUS_DDC_TIMER_STATUS REG_HDMI(0x474)
625#define HDMI_SCRAMBLER_STATUS_DDC_TIMER_STATUS2 REG_HDMI(0x478)
Tatenda Chipeperekwab785c042015-11-02 11:56:51 -0800[diff] [blame]626
627#define HDMI_USEC_REFTIMER REG_HDMI(0x208)
628#define HDMI_CTRL REG_HDMI(0x000)
629#define HDMI_HPD_INT_STATUS REG_HDMI(0x250)
630#define HDMI_HPD_INT_CTRL REG_HDMI(0x254)
631#define HDMI_HPD_CTRL REG_HDMI(0x258)
632#define HDMI_PHY_CTRL REG_HDMI(0x2D4)
633#define HDMI_TOTAL REG_HDMI(0x2C0)
634#define HDMI_ACTIVE_H REG_HDMI(0x2B4)
635#define HDMI_ACTIVE_V REG_HDMI(0x2B8)
636#define HDMI_V_TOTAL_F2 REG_HDMI(0x2C4)
637#define HDMI_ACTIVE_V_F2 REG_HDMI(0x2BC)
638#define HDMI_FRAME_CTRL REG_HDMI(0x2C8)
639
640#define HDMI_AVI_INFO0 REG_HDMI(0x06C)
641#define HDMI_AVI_INFO1 REG_HDMI(0x070)
642#define HDMI_AVI_INFO2 REG_HDMI(0x074)
643#define HDMI_AVI_INFO3 REG_HDMI(0x078)
644
645#define LPASS_LPAIF_RDDMA_CTL0 0x0910D000
646#define LPASS_LPAIF_RDDMA_BASE0 0x0910D004
647#define LPASS_LPAIF_RDDMA_BUFF_LEN0 0x0910D008
648#define LPASS_LPAIF_RDDMA_PER_LEN0 0x0910D010
649#define LPASS_LPAIF_DEBUG_CTL 0x0910000C
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]650#endif