Sachin Bhayare | 5e5f32a | 2015-10-07 11:47:19 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved. |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
Unnati Gandhi | 89d71a1 | 2014-09-18 12:01:08 +0530 | [diff] [blame] | 29 | #ifndef _PLATFORM_MSM8909_IOMAP_H_ |
| 30 | #define _PLATFORM_MSM8909_IOMAP_H_ |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 31 | |
| 32 | #define MSM_IOMAP_BASE 0x00000000 |
| 33 | #define MSM_IOMAP_END 0x08000000 |
| 34 | |
Unnati Gandhi | f4cb662 | 2014-08-28 13:54:56 +0530 | [diff] [blame] | 35 | #define A7_SS_BASE 0x0B000000 |
| 36 | #define A7_SS_END 0x0B200000 |
| 37 | |
| 38 | #define SYSTEM_IMEM_BASE 0x08600000 |
| 39 | #define MSM_SHARED_IMEM_BASE 0x08600000 |
| 40 | |
| 41 | #define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C) |
| 42 | #define BS_INFO_OFFSET (0x6B0) |
| 43 | #define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET) |
| 44 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 45 | #define SDRAM_START_ADDR 0x80000000 |
| 46 | |
Unnati Gandhi | 0a9a9d1 | 2014-09-23 19:18:11 +0530 | [diff] [blame] | 47 | #define MSM_SHARED_BASE 0x87D00000 |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 48 | |
Unnati Gandhi | c43a280 | 2014-09-19 17:27:25 +0530 | [diff] [blame] | 49 | #define MSM_NAND_BASE 0x79B0000 |
| 50 | /* NAND BAM */ |
| 51 | #define MSM_NAND_BAM_BASE 0x7984000 |
| 52 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 53 | #define APPS_SS_BASE 0x0B000000 |
| 54 | |
| 55 | #define MSM_GIC_DIST_BASE APPS_SS_BASE |
| 56 | #define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000) |
| 57 | #define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000) |
| 58 | #define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000) |
Unnati Gandhi | c24a86f | 2014-09-19 16:07:16 +0530 | [diff] [blame] | 59 | #define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00011008) |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 60 | #define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE |
| 61 | |
| 62 | #define PERIPH_SS_BASE 0x07800000 |
| 63 | |
| 64 | #define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000) |
Unnati Gandhi | 4d637e4 | 2014-07-11 14:47:25 +0530 | [diff] [blame] | 65 | #define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900) |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 66 | #define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000) |
Unnati Gandhi | 4d637e4 | 2014-07-11 14:47:25 +0530 | [diff] [blame] | 67 | #define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900) |
| 68 | |
| 69 | /* SDHCI */ |
| 70 | #define SDCC_MCI_HC_MODE (0x00000078) |
| 71 | #define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC) |
| 72 | #define SDCC_HC_PWRCTL_MASK_REG (0x000000E0) |
| 73 | #define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4) |
| 74 | #define SDCC_HC_PWRCTL_CTL_REG (0x000000E8) |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 75 | |
| 76 | #define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000) |
| 77 | #define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000) |
| 78 | #define MSM_USB_BASE (PERIPH_SS_BASE + 0x000D9000) |
| 79 | |
| 80 | #define CLK_CTL_BASE 0x1800000 |
| 81 | |
Mayank Grover | ad30916 | 2017-06-30 16:27:47 +0530 | [diff] [blame^] | 82 | #define PMI_SECOND_SLAVE_OFFSET 0x1 |
| 83 | #define PMI_SECOND_SLAVE_ADDR_BASE (PMI_SECOND_SLAVE_OFFSET << 16) |
| 84 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 85 | #define SPMI_BASE 0x02000000 |
| 86 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
| 87 | #define SPMI_PIC_BASE (SPMI_BASE + 0x01800000) |
Unnati Gandhi | 8e4711b | 2014-10-13 05:03:00 +0530 | [diff] [blame] | 88 | #define PMIC_ARB_CORE 0x200F000 |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 89 | |
| 90 | #define TLMM_BASE_ADDR 0x1000000 |
| 91 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000) |
| 92 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000) |
| 93 | |
| 94 | #define MPM2_MPM_CTRL_BASE 0x004A0000 |
| 95 | #define MPM2_MPM_PS_HOLD 0x004AB000 |
Unnati Gandhi | f4cb662 | 2014-08-28 13:54:56 +0530 | [diff] [blame] | 96 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000 |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 97 | |
| 98 | /* CRYPTO ENGINE */ |
| 99 | #define MSM_CE1_BASE 0x073A000 |
| 100 | #define MSM_CE1_BAM_BASE 0x0704000 |
Unnati Gandhi | f4cb662 | 2014-08-28 13:54:56 +0530 | [diff] [blame] | 101 | #define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000) |
| 102 | #define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004) |
| 103 | #define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008) |
| 104 | #define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C) |
| 105 | #define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020) |
| 106 | #define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024) |
| 107 | |
| 108 | /* I2C */ |
Unnati Gandhi | 88cf23b | 2014-12-10 15:39:12 +0530 | [diff] [blame] | 109 | #define BLSP_QUP_BASE(blsp_id, qup_id) (PERIPH_SS_BASE + 0xB5000 + 0x1000 * qup_id) |
| 110 | #define GCC_BLSP1_QUP1_APPS_CBCR (CLK_CTL_BASE + 0x2008) |
| 111 | #define GCC_BLSP1_QUP1_CFG_RCGR (CLK_CTL_BASE + 0x2010) |
| 112 | #define GCC_BLSP1_QUP1_CMD_RCGR (CLK_CTL_BASE + 0x200C) |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 113 | |
Unnati Gandhi | 88cf23b | 2014-12-10 15:39:12 +0530 | [diff] [blame] | 114 | #define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010) |
| 115 | #define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3004) |
| 116 | #define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3000) |
| 117 | |
| 118 | #define GCC_BLSP1_QUP3_APPS_CBCR (CLK_CTL_BASE + 0x4020) |
| 119 | #define GCC_BLSP1_QUP3_CFG_RCGR (CLK_CTL_BASE + 0x4004) |
| 120 | #define GCC_BLSP1_QUP3_CMD_RCGR (CLK_CTL_BASE + 0x4000) |
| 121 | |
| 122 | #define GCC_BLSP1_QUP4_APPS_CBCR (CLK_CTL_BASE + 0x5020) |
| 123 | #define GCC_BLSP1_QUP4_CFG_RCGR (CLK_CTL_BASE + 0x5004) |
| 124 | #define GCC_BLSP1_QUP4_CMD_RCGR (CLK_CTL_BASE + 0x5000) |
| 125 | |
| 126 | #define GCC_BLSP1_QUP5_APPS_CBCR (CLK_CTL_BASE + 0x6020) |
| 127 | #define GCC_BLSP1_QUP5_CFG_RCGR (CLK_CTL_BASE + 0x6004) |
| 128 | #define GCC_BLSP1_QUP5_CMD_RCGR (CLK_CTL_BASE + 0x6000) |
| 129 | |
| 130 | #define GCC_BLSP1_QUP6_APPS_CBCR (CLK_CTL_BASE + 0x7020) |
| 131 | #define GCC_BLSP1_QUP6_CFG_RCGR (CLK_CTL_BASE + 0x7004) |
| 132 | #define GCC_BLSP1_QUP6_CMD_RCGR (CLK_CTL_BASE + 0x7000) |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 133 | |
| 134 | /* GPLL */ |
| 135 | #define GPLL0_STATUS (CLK_CTL_BASE + 0x21024) |
Aparna Mallavarapu | babab6d | 2014-10-16 14:32:40 -0700 | [diff] [blame] | 136 | #define GPLL0_MODE (CLK_CTL_BASE + 0x21000) |
Unnati Gandhi | f4cb662 | 2014-08-28 13:54:56 +0530 | [diff] [blame] | 137 | #define GPLL1_STATUS (CLK_CTL_BASE + 0x2001C) |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 138 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000) |
| 139 | #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004) |
| 140 | |
| 141 | /* SDCC */ |
| 142 | #define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000) |
| 143 | #define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/ |
| 144 | #define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */ |
| 145 | #define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C) |
| 146 | #define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */ |
| 147 | #define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */ |
| 148 | #define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */ |
| 149 | #define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */ |
| 150 | #define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */ |
| 151 | |
Unnati Gandhi | f4cb662 | 2014-08-28 13:54:56 +0530 | [diff] [blame] | 152 | #define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */ |
| 153 | #define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */ |
| 154 | #define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C) |
| 155 | #define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */ |
| 156 | #define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */ |
| 157 | #define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */ |
| 158 | #define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */ |
| 159 | #define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */ |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 160 | |
| 161 | /* UART */ |
| 162 | #define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008) |
| 163 | #define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C) |
| 164 | #define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034) |
| 165 | #define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038) |
| 166 | #define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C) |
| 167 | #define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040) |
| 168 | #define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044) |
| 169 | |
Unnati Gandhi | d119ebc | 2014-10-14 03:41:46 -0700 | [diff] [blame] | 170 | #define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x203C) |
| 171 | #define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2044) |
| 172 | #define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x2048) |
| 173 | #define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x204C) |
| 174 | #define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x2050) |
| 175 | #define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x2054) |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 176 | |
| 177 | /* USB */ |
| 178 | #define USB_HS_BCR (CLK_CTL_BASE + 0x41000) |
| 179 | #define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004) |
| 180 | #define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008) |
| 181 | #define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010) |
| 182 | #define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014) |
| 183 | |
Shivaraj Shetty | 83479fc | 2014-09-17 03:35:19 +0530 | [diff] [blame] | 184 | |
Mayank Grover | 7e35183 | 2017-04-21 15:03:58 +0530 | [diff] [blame] | 185 | /* RPMB send receive buffer needs to be mapped |
| 186 | * as device memory, define the start address |
| 187 | * and size in MB |
| 188 | */ |
| 189 | #define RPMB_SND_RCV_BUF 0x90000000 |
| 190 | #define RPMB_SND_RCV_BUF_SZ 0x1 |
| 191 | |
| 192 | /* QSEECOM: Secure app region notification */ |
| 193 | #define APP_REGION_ADDR 0x87b00000 |
| 194 | #define APP_REGION_SIZE 0x100000 |
| 195 | |
| 196 | |
Shivaraj Shetty | 83479fc | 2014-09-17 03:35:19 +0530 | [diff] [blame] | 197 | /* MDSS */ |
| 198 | #define MIPI_DSI_BASE (0x1AC8000) |
| 199 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 200 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 201 | #define DSI0_PHY_BASE (0x1AC8500) |
| 202 | #define DSI1_PHY_BASE DSI0_PHY_BASE |
| 203 | #define DSI0_PLL_BASE (0x1AC8300) |
| 204 | #define DSI1_PLL_BASE DSI0_PLL_BASE |
Jeevan Shriram | 89b72f4 | 2015-01-07 16:33:25 -0800 | [diff] [blame] | 205 | #define DSI0_REGULATOR_BASE (0x1AC8780) |
| 206 | #define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE |
Shivaraj Shetty | 83479fc | 2014-09-17 03:35:19 +0530 | [diff] [blame] | 207 | |
| 208 | /* MDP */ |
| 209 | #define MDP_BASE 0x1A00000 |
| 210 | #define REG_MDP(off) (MDP_BASE + (off)) |
| 211 | |
| 212 | #define MDP_DMA_P_CONFIG REG_MDP(0x90000) |
| 213 | #define MDP_DMA_P_OUT_XY REG_MDP(0x90010) |
| 214 | #define MDP_DMA_P_SIZE REG_MDP(0x90004) |
| 215 | #define MDP_DMA_P_BUF_ADDR REG_MDP(0x90008) |
| 216 | #define MDP_DMA_P_BUF_Y_STRIDE REG_MDP(0x9000C) |
| 217 | |
Sandeep Panda | c5aa91d | 2014-12-17 18:37:24 +0530 | [diff] [blame] | 218 | #define MDP_DMA_P_QOS_REMAPPER REG_MDP(0x90090) |
| 219 | #define MDP_DMA_P_WATERMARK_0 REG_MDP(0x90094) |
| 220 | #define MDP_DMA_P_WATERMARK_1 REG_MDP(0x90098) |
| 221 | #define MDP_DMA_P_WATERMARK_2 REG_MDP(0x9009C) |
| 222 | #define MDP_PANIC_ROBUST_CTRL REG_MDP(0x900A0) |
| 223 | #define MDP_PANIC_LUT0 REG_MDP(0x900A4) |
Sachin Bhayare | 5e5f32a | 2015-10-07 11:47:19 +0530 | [diff] [blame] | 224 | #define MDP_PANIC_LUT1 REG_MDP(0x900A8) |
Sandeep Panda | c5aa91d | 2014-12-17 18:37:24 +0530 | [diff] [blame] | 225 | #define MDP_ROBUST_LUT REG_MDP(0x900AC) |
| 226 | |
Shivaraj Shetty | 83479fc | 2014-09-17 03:35:19 +0530 | [diff] [blame] | 227 | #define MDP_DSI_VIDEO_EN REG_MDP(0xF0000) |
| 228 | #define MDP_DSI_VIDEO_HSYNC_CTL REG_MDP(0xF0004) |
| 229 | #define MDP_DSI_VIDEO_VSYNC_PERIOD REG_MDP(0xF0008) |
| 230 | #define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH REG_MDP(0xF000C) |
| 231 | #define MDP_DSI_VIDEO_DISPLAY_HCTL REG_MDP(0xF0010) |
| 232 | #define MDP_DSI_VIDEO_DISPLAY_V_START REG_MDP(0xF0014) |
| 233 | #define MDP_DSI_VIDEO_DISPLAY_V_END REG_MDP(0xF0018) |
| 234 | #define MDP_DSI_VIDEO_BORDER_CLR REG_MDP(0xF0028) |
| 235 | #define MDP_DSI_VIDEO_HSYNC_SKEW REG_MDP(0xF0030) |
| 236 | #define MDP_DSI_VIDEO_CTL_POLARITY REG_MDP(0xF0038) |
| 237 | #define MDP_DSI_VIDEO_TEST_CTL REG_MDP(0xF0034) |
| 238 | |
| 239 | #define MDP_DMA_P_START REG_MDP(0x00044) |
| 240 | #define MDP_DMA_S_START REG_MDP(0x00048) |
| 241 | #define MDP_DISP_INTF_SEL REG_MDP(0x00038) |
| 242 | #define MDP_MAX_RD_PENDING_CMD_CONFIG REG_MDP(0x0004C) |
| 243 | #define MDP_INTR_ENABLE REG_MDP(0x00020) |
| 244 | #define MDP_INTR_CLEAR REG_MDP(0x00028) |
| 245 | #define MDP_DSI_CMD_MODE_ID_MAP REG_MDP(0xF1000) |
| 246 | #define MDP_DSI_CMD_MODE_TRIGGER_EN REG_MDP(0XF1004) |
| 247 | |
| 248 | #define MDP_TEST_MODE_CLK REG_MDP(0xF0000) |
| 249 | #define MDP_INTR_STATUS REG_MDP(0x00054) |
| 250 | |
Shivaraj Shetty | 41d2d48 | 2014-11-04 16:07:32 +0530 | [diff] [blame] | 251 | #define MDP_CGC_EN REG_MDP(0x100) |
| 252 | |
Shivaraj Shetty | 83479fc | 2014-09-17 03:35:19 +0530 | [diff] [blame] | 253 | #define SOFT_RESET 0x118 |
| 254 | #define CLK_CTRL 0x11C |
| 255 | #define TRIG_CTRL 0x084 |
| 256 | #define CTRL 0x004 |
| 257 | #define COMMAND_MODE_DMA_CTRL 0x03C |
| 258 | #define COMMAND_MODE_MDP_CTRL 0x040 |
| 259 | #define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044 |
| 260 | #define COMMAND_MODE_MDP_STREAM0_CTRL 0x058 |
| 261 | #define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C |
| 262 | #define COMMAND_MODE_MDP_STREAM1_CTRL 0x060 |
| 263 | #define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064 |
| 264 | #define ERR_INT_MASK0 0x10C |
| 265 | |
Ray Zhang | d1cd085 | 2015-01-20 15:31:33 +0800 | [diff] [blame] | 266 | #define LANE_CTL 0x0AC |
Shivaraj Shetty | 83479fc | 2014-09-17 03:35:19 +0530 | [diff] [blame] | 267 | #define LANE_SWAP_CTL 0x0B0 |
| 268 | #define TIMING_CTL 0x0C4 |
| 269 | |
| 270 | #define VIDEO_MODE_ACTIVE_H 0x024 |
| 271 | #define VIDEO_MODE_ACTIVE_V 0x028 |
| 272 | #define VIDEO_MODE_TOTAL 0x02C |
| 273 | #define VIDEO_MODE_HSYNC 0x030 |
| 274 | #define VIDEO_MODE_VSYNC 0x034 |
| 275 | #define VIDEO_MODE_VSYNC_VPOS 0x038 |
| 276 | |
| 277 | #define DMA_CMD_OFFSET 0x048 |
| 278 | #define DMA_CMD_LENGTH 0x04C |
| 279 | |
| 280 | #define INT_CTRL 0x110 |
| 281 | #define CMD_MODE_DMA_SW_TRIGGER 0x090 |
| 282 | |
| 283 | #define EOT_PACKET_CTRL 0x0CC |
| 284 | #define MISR_CMD_CTRL 0x0A0 |
| 285 | #define MISR_VIDEO_CTRL 0x0A4 |
| 286 | #define VIDEO_MODE_CTRL 0x010 |
| 287 | #define HS_TIMER_CTRL 0x0BC |
| 288 | |
Unnati Gandhi | f4cb662 | 2014-08-28 13:54:56 +0530 | [diff] [blame] | 289 | #define TCSR_TZ_WONCE 0x193D000 |
Unnati Gandhi | c43a280 | 2014-09-19 17:27:25 +0530 | [diff] [blame] | 290 | |
| 291 | /* Boot config */ |
| 292 | #define SEC_CTRL_CORE_BASE 0x00058000 |
| 293 | #define BOOT_CONFIG_OFFSET 0x0000602C |
| 294 | #define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET) |
| 295 | |
Unnati Gandhi | 2488505 | 2014-11-27 16:57:49 +0530 | [diff] [blame] | 296 | #define SECURITY_CONTROL_CORE_FEATURE_CONFIG0 0x0005E004 |
Aparna Mallavarapu | 5f80cbf | 2014-10-13 11:10:22 -0700 | [diff] [blame] | 297 | /* EBI2 */ |
| 298 | #define TLMM_EBI2_EMMC_GPIO_CFG (TLMM_BASE_ADDR + 0x00111000) |
Aparna Mallavarapu | ec8b7cf | 2014-12-11 12:14:54 +0530 | [diff] [blame] | 299 | #define TCSR_BOOT_MISC_DETECT 0x193D100 |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 300 | #endif |