Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
| 11 | * * Neither the name of Code Aurora nor |
| 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <debug.h> |
| 31 | #include <kernel/thread.h> |
| 32 | #include <platform/iomap.h> |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 33 | #include <platform/clock.h> |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 34 | #include <reg.h> |
| 35 | |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 36 | /* Read, modify, then write-back a register. */ |
| 37 | static void rmwreg(uint32_t val, uint32_t reg, uint32_t mask) |
| 38 | { |
| 39 | uint32_t regval = readl(reg); |
| 40 | regval &= ~mask; |
| 41 | regval |= val; |
| 42 | writel(regval, reg); |
| 43 | } |
| 44 | |
| 45 | |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 46 | /* Enable/disable for non-shared NT PLLs. */ |
| 47 | int nt_pll_enable(uint8_t src, uint8_t enable) |
| 48 | { |
| 49 | static const struct { |
| 50 | uint32_t const mode_reg; |
| 51 | uint32_t const status_reg; |
| 52 | } pll_reg[] = { |
| 53 | [PLL_1] = { MM_PLL0_MODE_REG, MM_PLL0_STATUS_REG }, |
| 54 | [PLL_2] = { MM_PLL1_MODE_REG, MM_PLL1_STATUS_REG }, |
| 55 | [PLL_3] = { MM_PLL2_MODE_REG, MM_PLL2_STATUS_REG }, |
| 56 | }; |
| 57 | uint32_t pll_mode; |
| 58 | |
| 59 | pll_mode = readl(pll_reg[src].mode_reg); |
| 60 | if (enable) { |
| 61 | /* Disable PLL bypass mode. */ |
| 62 | pll_mode |= (1<<1); |
| 63 | writel( pll_mode, pll_reg[src].mode_reg); |
| 64 | |
| 65 | /* H/W requires a 5us delay between disabling the bypass and |
| 66 | * de-asserting the reset. Delay 10us just to be safe. */ |
| 67 | udelay(10); |
| 68 | |
| 69 | /* De-assert active-low PLL reset. */ |
| 70 | pll_mode |= (1<<2); |
| 71 | writel( pll_mode, pll_reg[src].mode_reg); |
| 72 | |
| 73 | /* Enable PLL output. */ |
| 74 | pll_mode |= (1<<0); |
| 75 | writel( pll_mode, pll_reg[src].mode_reg); |
| 76 | |
| 77 | /* Wait until PLL is enabled. */ |
| 78 | while (!readl(pll_reg[src].status_reg)); |
| 79 | } else { |
| 80 | /* Disable the PLL output, disable test mode, enable |
| 81 | * the bypass mode, and assert the reset. */ |
| 82 | pll_mode &= 0xFFFFFFF0; |
| 83 | writel( pll_mode, pll_reg[src].mode_reg); |
| 84 | } |
| 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | |
| 90 | /* Write the M,N,D values and enable the MDP Core Clock */ |
| 91 | void config_mdp_clk( uint32_t ns, |
| 92 | uint32_t md, |
| 93 | uint32_t cc, |
| 94 | uint32_t ns_addr, |
| 95 | uint32_t md_addr, |
| 96 | uint32_t cc_addr) |
| 97 | { |
| 98 | int val = 0; |
| 99 | |
| 100 | /* MN counter reset */ |
| 101 | val = 1 << 31; |
| 102 | writel(val, ns_addr); |
| 103 | |
| 104 | /* Write the MD and CC register values */ |
| 105 | writel(md, md_addr); |
| 106 | writel(cc, cc_addr); |
| 107 | |
| 108 | /* Reset the clk control, and Write ns val */ |
| 109 | val = 1 << 31; |
| 110 | val |= ns; |
| 111 | writel(val, ns_addr); |
| 112 | |
| 113 | /* Clear MN counter reset */ |
| 114 | val = 1 << 31; |
| 115 | val = ~val; |
| 116 | val = val & readl(ns_addr); |
| 117 | writel(val, ns_addr); |
| 118 | |
| 119 | /* Enable MND counter */ |
| 120 | val = 1 << 8; |
| 121 | val = val | readl(cc_addr); |
| 122 | writel(val, cc_addr); |
| 123 | |
| 124 | /* Enable the root of the clock tree */ |
| 125 | val = 1 << 2; |
| 126 | val = val | readl(cc_addr); |
| 127 | writel(val, cc_addr); |
| 128 | |
| 129 | /* Enable the MDP Clock */ |
| 130 | val = 1 << 0; |
| 131 | val = val | readl(cc_addr); |
| 132 | writel(val, cc_addr); |
| 133 | } |
| 134 | |
| 135 | /* Write the M,N,D values and enable the Pixel Core Clock */ |
| 136 | void config_pixel_clk( uint32_t ns, |
| 137 | uint32_t md, |
| 138 | uint32_t cc, |
| 139 | uint32_t ns_addr, |
| 140 | uint32_t md_addr, |
| 141 | uint32_t cc_addr){ |
| 142 | unsigned int val = 0; |
| 143 | |
| 144 | /* Activate the reset for the M/N Counter */ |
| 145 | val = 1 << 7; |
| 146 | writel(val, ns_addr); |
| 147 | |
| 148 | /* Write the MD and CC register values */ |
| 149 | writel(md, md_addr); |
| 150 | writel(cc, cc_addr); |
| 151 | |
| 152 | /* Write the ns value, and active reset for M/N Counter, again */ |
| 153 | val = 1 << 7; |
| 154 | val |= ns; |
| 155 | writel(val, ns_addr); |
| 156 | |
| 157 | /* De-activate the reset for M/N Counter */ |
| 158 | val = 1 << 7; |
| 159 | val = ~val; |
| 160 | val = val & readl(ns_addr); |
| 161 | writel(val, ns_addr); |
| 162 | |
| 163 | /* Enable MND counter */ |
| 164 | val = 1 << 5; |
| 165 | val = val | readl(cc_addr); |
| 166 | writel(val, cc_addr); |
| 167 | |
| 168 | /* Enable the root of the clock tree */ |
| 169 | val = 1 << 2; |
| 170 | val = val | readl(cc_addr); |
| 171 | writel(val, cc_addr); |
| 172 | |
| 173 | /* Enable the MDP Clock */ |
| 174 | val = 1 << 0; |
| 175 | val = val | readl(cc_addr); |
| 176 | writel(val, cc_addr); |
| 177 | |
| 178 | /* Enable the LCDC Clock */ |
| 179 | val = 1 << 8; |
| 180 | val = val | readl(cc_addr); |
| 181 | writel(val, cc_addr); |
| 182 | } |
| 183 | |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 184 | /* Set rate and enable the clock */ |
| 185 | void clock_config(uint32_t ns, |
| 186 | uint32_t md, |
| 187 | uint32_t ns_addr, |
| 188 | uint32_t md_addr) |
| 189 | { |
| 190 | unsigned int val = 0; |
| 191 | |
| 192 | /* Activate the reset for the M/N Counter */ |
| 193 | val = 1 << 7; |
| 194 | writel(val, ns_addr); |
| 195 | |
| 196 | /* Write the MD value into the MD register */ |
| 197 | writel(md, md_addr); |
| 198 | |
| 199 | /* Write the ns value, and active reset for M/N Counter, again */ |
| 200 | val = 1 << 7; |
| 201 | val |= ns; |
| 202 | writel(val, ns_addr); |
| 203 | |
| 204 | /* De-activate the reset for M/N Counter */ |
| 205 | val = 1 << 7; |
| 206 | val = ~val; |
| 207 | val = val & readl(ns_addr); |
| 208 | writel(val, ns_addr); |
| 209 | |
| 210 | /* Enable the M/N Counter */ |
| 211 | val = 1 << 8; |
| 212 | val = val | readl(ns_addr); |
| 213 | writel(val, ns_addr); |
| 214 | |
| 215 | /* Enable the Clock Root */ |
| 216 | val = 1 << 11; |
| 217 | val = val | readl(ns_addr); |
| 218 | writel(val, ns_addr); |
| 219 | |
| 220 | /* Enable the Clock Branch */ |
| 221 | val = 1 << 9; |
| 222 | val = val | readl(ns_addr); |
| 223 | writel(val, ns_addr); |
| 224 | } |
| 225 | |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 226 | void acpu_clock_init (void) |
| 227 | { |
| 228 | } |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 229 | |
| 230 | void hsusb_clock_init(void) |
| 231 | { |
| 232 | int val; |
| 233 | /* Vote for PLL8 */ |
| 234 | val = readl(0x009034C0); |
| 235 | val |= (1<<8); |
| 236 | writel(val, 0x009034C0); |
| 237 | /* Wait until PLL is enabled. */ |
| 238 | while (!(readl(0x00903158) & (1<<16))); |
| 239 | |
| 240 | //Set 7th bit in NS Register |
| 241 | val = 1 << 7; |
| 242 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 243 | |
| 244 | //Set rate specific value in MD |
| 245 | writel(0x000500DF, USB_HS1_XVCR_FS_CLK_MD); |
| 246 | |
| 247 | //Set value in NS register |
| 248 | val = 1 << 7; |
| 249 | val |= 0x00E400C3; |
| 250 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 251 | |
| 252 | // Clear 7th bit |
| 253 | val = 1 << 7; |
| 254 | val = ~val; |
| 255 | val = val & readl(USB_HS1_XVCR_FS_CLK_NS); |
| 256 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 257 | |
| 258 | //set 11th bit |
| 259 | val = 1 << 11; |
| 260 | val |= readl(USB_HS1_XVCR_FS_CLK_NS); |
| 261 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 262 | |
| 263 | //set 9th bit |
| 264 | val = 1 << 9; |
| 265 | val |= readl(USB_HS1_XVCR_FS_CLK_NS); |
| 266 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 267 | |
| 268 | //set 8th bit |
| 269 | val = 1 << 8; |
| 270 | val |= readl(USB_HS1_XVCR_FS_CLK_NS); |
| 271 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 272 | } |
| 273 | |