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Channagoud Kadabif8ad8e72015-01-06 15:10:13 -08001/* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <debug.h>
30#include <platform/iomap.h>
31#include <platform/irqs.h>
32#include <platform/gpio.h>
33#include <reg.h>
34#include <target.h>
35#include <platform.h>
36#include <dload_util.h>
37#include <uart_dm.h>
38#include <mmc.h>
39#include <spmi.h>
40#include <board.h>
41#include <smem.h>
42#include <baseband.h>
Sridhar Parasuramd75ade52015-03-09 15:45:16 -070043#include <regulator.h>
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070044#include <dev/keys.h>
45#include <pm8x41.h>
46#include <crypto5_wrapper.h>
47#include <clock.h>
48#include <partition_parser.h>
49#include <scm.h>
50#include <platform/clock.h>
51#include <platform/gpio.h>
52#include <platform/timer.h>
53#include <stdlib.h>
54#include <ufs.h>
55#include <boot_device.h>
56#include <qmp_phy.h>
Channagoud Kadabi7d308202014-12-22 12:07:04 -080057#include <sdhci_msm.h>
58#include <qusb2_phy.h>
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -080059#include <rpmb.h>
Sridhar Parasuram9f28f672015-03-17 15:40:47 -070060#include <rpm-glink.h>
Channagoud Kadabibb8f1f92015-04-27 11:14:45 -070061#if ENABLE_WBC
62#include <pm_app_smbchg.h>
63#endif
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070064
Channagoud Kadabi4a870cf2015-01-21 10:39:01 -080065#define CE_INSTANCE 1
66#define CE_EE 1
67#define CE_FIFO_SIZE 64
68#define CE_READ_PIPE 3
69#define CE_WRITE_PIPE 2
70#define CE_READ_PIPE_LOCK_GRP 0
71#define CE_WRITE_PIPE_LOCK_GRP 0
72#define CE_ARRAY_SIZE 20
73
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070074#define PMIC_ARB_CHANNEL_NUM 0
75#define PMIC_ARB_OWNER_ID 0
76
77static void set_sdc_power_ctrl(void);
78static uint32_t mmc_pwrctl_base[] =
79 { MSM_SDC1_BASE, MSM_SDC2_BASE };
80
81static uint32_t mmc_sdhci_base[] =
82 { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
83
84static uint32_t mmc_sdc_pwrctl_irq[] =
85 { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
86
87struct mmc_device *dev;
88struct ufs_dev ufs_device;
89
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070090void target_early_init(void)
91{
92#if WITH_DEBUG_UART
Channagoud Kadabi35503c42014-11-14 16:22:43 -080093 uart_dm_init(8, 0, BLSP2_UART1_BASE);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070094#endif
95}
96
97/* Return 1 if vol_up pressed */
Amit Blay6a3e88b2015-06-23 22:25:06 +030098int target_volume_up()
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070099{
100 uint8_t status = 0;
101 struct pm8x41_gpio gpio;
102
103 /* Configure the GPIO */
104 gpio.direction = PM_GPIO_DIR_IN;
105 gpio.function = 0;
106 gpio.pull = PM_GPIO_PULL_UP_30;
107 gpio.vin_sel = 2;
108
109 pm8x41_gpio_config(2, &gpio);
110
111 /* Wait for the pmic gpio config to take effect */
112 thread_sleep(1);
113
114 /* Get status of P_GPIO_5 */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800115 pm8x41_gpio_get(2, &status);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700116
117 return !status; /* active low */
118}
119
120/* Return 1 if vol_down pressed */
121uint32_t target_volume_down()
122{
123 return pm8x41_resin_status();
124}
125
126static void target_keystatus()
127{
128 keys_init();
129
130 if(target_volume_down())
131 keys_post_event(KEY_VOLUMEDOWN, 1);
132
133 if(target_volume_up())
134 keys_post_event(KEY_VOLUMEUP, 1);
135}
136
137void target_uninit(void)
138{
139 if (platform_boot_dev_isemmc())
140 {
141 mmc_put_card_to_sleep(dev);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700142 }
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800143
144 if (is_sec_app_loaded())
145 {
146 if (unload_sec_app() < 0)
147 {
148 dprintf(CRITICAL, "Failed to unload App for rpmb\n");
149 ASSERT(0);
150 }
151 }
152
Channagoud Kadabibb8f1f92015-04-27 11:14:45 -0700153#if ENABLE_WBC
154 pm_appsbl_set_dcin_suspend(1);
155#endif
156
Sridhar Parasuram9f28f672015-03-17 15:40:47 -0700157 /* Tear down glink channels */
158 rpm_glink_uninit();
159
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800160 if (rpmb_uninit() < 0)
161 {
162 dprintf(CRITICAL, "RPMB uninit failed\n");
163 ASSERT(0);
164 }
165
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700166}
167
168static void set_sdc_power_ctrl()
169{
170 /* Drive strength configs for sdc pins */
171 struct tlmm_cfgs sdc1_hdrv_cfg[] =
172 {
173 { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
174 { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
175 { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
176 };
177
178 /* Pull configs for sdc pins */
179 struct tlmm_cfgs sdc1_pull_cfg[] =
180 {
181 { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
182 { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
183 { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
184 };
185
186 struct tlmm_cfgs sdc1_rclk_cfg[] =
187 {
188 { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
189 };
190
191 /* Set the drive strength & pull control values */
192 tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
193 tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
194 tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
195}
196
197void target_sdc_init()
198{
199 struct mmc_config_data config = {0};
200
201 /* Set drive strength & pull ctrl values */
202 set_sdc_power_ctrl();
203
204 config.bus_width = DATA_BUS_WIDTH_8BIT;
205 config.max_clk_rate = MMC_CLK_192MHZ;
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800206 config.hs400_support = 1;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700207
208 /* Try slot 1*/
209 config.slot = 1;
210 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
211 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
212 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
213
214 if (!(dev = mmc_init(&config)))
215 {
216 /* Try slot 2 */
217 config.slot = 2;
218 config.max_clk_rate = MMC_CLK_200MHZ;
219 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
220 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
221 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
222
223 if (!(dev = mmc_init(&config)))
224 {
225 dprintf(CRITICAL, "mmc init failed!");
226 ASSERT(0);
227 }
228 }
229}
230
231void *target_mmc_device()
232{
233 if (platform_boot_dev_isemmc())
234 return (void *) dev;
235 else
236 return (void *) &ufs_device;
237}
238
239void target_init(void)
240{
241 dprintf(INFO, "target_init()\n");
242
Sridhar Parasuram1d224322015-06-15 11:03:40 -0700243 pmic_info_populate();
244
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700245 spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
246
Channagoud Kadabibb8f1f92015-04-27 11:14:45 -0700247 /* Initialize Glink */
248 rpm_glink_init();
249
250#if ENABLE_WBC
251 /* Look for battery voltage and make sure we have enough to bootup
252 * Otherwise initiate battery charging
253 * Charging should happen as early as possible, any other driver
254 * initialization before this should consider the power impact
255 */
256 pm_appsbl_chg_check_weak_battery_status(1);
257#endif
258
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700259 target_keystatus();
260
261 if (target_use_signed_kernel())
262 target_crypto_init_params();
263
264 platform_read_boot_config();
265
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800266#ifdef MMC_SDHCI_SUPPORT
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700267 if (platform_boot_dev_isemmc())
268 {
269 target_sdc_init();
270 }
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800271#endif
272#ifdef UFS_SUPPORT
273 if (!platform_boot_dev_isemmc())
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700274 {
275 ufs_device.base = UFS_BASE;
276 ufs_init(&ufs_device);
277 }
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800278#endif
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700279
280 /* Storage initialization is complete, read the partition table info */
Channagoud Kadabi58a273b2015-02-10 12:56:22 -0800281 mmc_read_partition_table(0);
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800282
283 if (rpmb_init() < 0)
284 {
285 dprintf(CRITICAL, "RPMB init failed\n");
286 ASSERT(0);
287 }
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700288}
289
290unsigned board_machtype(void)
291{
292 return LINUX_MACHTYPE_UNKNOWN;
293}
294
295/* Detect the target type */
296void target_detect(struct board_data *board)
297{
298 /* This is filled from board.c */
299}
300
Dhaval Patelb95039c2015-03-16 11:14:06 -0700301static uint8_t splash_override;
302/* Returns 1 if target supports continuous splash screen. */
303int target_cont_splash_screen()
304{
305 uint8_t splash_screen = 0;
306 if(!splash_override) {
307 switch(board_hardware_id())
308 {
309 case HW_PLATFORM_SURF:
310 case HW_PLATFORM_MTP:
311 case HW_PLATFORM_FLUID:
312 dprintf(SPEW, "Target_cont_splash=1\n");
313 splash_screen = 1;
314 break;
315 default:
316 dprintf(SPEW, "Target_cont_splash=0\n");
317 splash_screen = 0;
318 }
319 }
320 return splash_screen;
321}
322
323void target_force_cont_splash_disable(uint8_t override)
324{
325 splash_override = override;
326}
327
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700328/* Detect the modem type */
329void target_baseband_detect(struct board_data *board)
330{
331 uint32_t platform;
332
333 platform = board->platform;
334
335 switch(platform) {
Channagoud Kadabi439df822015-05-26 11:14:16 -0700336 case APQ8096:
337 board->baseband = BASEBAND_APQ;
338 break;
Channagoud Kadabi4a4c05e2015-03-30 15:18:58 -0700339 case MSM8996:
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800340 if (board->platform_version == 0x10000)
341 board->baseband = BASEBAND_APQ;
342 else
343 board->baseband = BASEBAND_MSM;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700344 break;
345 default:
346 dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
347 ASSERT(0);
348 };
349}
350unsigned target_baseband()
351{
352 return board_baseband();
353}
354
355void target_serialno(unsigned char *buf)
356{
357 unsigned int serialno;
358 if (target_is_emmc_boot()) {
359 serialno = mmc_get_psn();
360 snprintf((char *)buf, 13, "%x", serialno);
361 }
362}
363
364unsigned check_reboot_mode(void)
365{
366 uint32_t restart_reason = 0;
367 uint32_t restart_reason_addr;
368
369 restart_reason_addr = RESTART_REASON_ADDR;
370
371 /* Read reboot reason and scrub it */
372 restart_reason = readl(restart_reason_addr);
373 writel(0x00, restart_reason_addr);
374
375 return restart_reason;
376}
377
378void reboot_device(unsigned reboot_reason)
379{
380 uint8_t reset_type = 0;
381
382 /* Write the reboot reason */
383 writel(reboot_reason, RESTART_REASON_ADDR);
384
385 if(reboot_reason)
386 reset_type = PON_PSHOLD_WARM_RESET;
387 else
388 reset_type = PON_PSHOLD_HARD_RESET;
389
Channagoud Kadabiffc4b902015-06-25 23:14:27 -0700390 pm8994_reset_configure(reset_type);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700391
392 /* Drop PS_HOLD for MSM */
393 writel(0x00, MPM2_MPM_PS_HOLD);
394
395 mdelay(5000);
396
397 dprintf(CRITICAL, "Rebooting failed\n");
398}
399
400int emmc_recovery_init(void)
401{
402 return _emmc_recovery_init();
403}
404
405void target_usb_phy_reset()
406{
407 usb30_qmp_phy_reset();
408 qusb2_phy_reset();
409}
410
411target_usb_iface_t* target_usb30_init()
412{
413 target_usb_iface_t *t_usb_iface;
414
415 t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
416 ASSERT(t_usb_iface);
417
418 t_usb_iface->phy_init = usb30_qmp_phy_init;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700419 t_usb_iface->phy_reset = target_usb_phy_reset;
420 t_usb_iface->clock_init = clock_usb30_init;
421 t_usb_iface->vbus_override = 1;
422
423 return t_usb_iface;
424}
425
426/* identify the usb controller to be used for the target */
427const char * target_usb_controller()
428{
429 return "dwc";
430}
431
432uint32_t target_override_pll()
433{
Channagoud Kadabi1e5144b2015-04-28 17:15:05 -0700434 if (board_soc_version() >= 0x20000)
435 return 0;
436 else
437 return 1;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700438}
439
Channagoud Kadabi4a870cf2015-01-21 10:39:01 -0800440crypto_engine_type board_ce_type(void)
441{
442 return CRYPTO_ENGINE_TYPE_SW;
443}
444
445/* Set up params for h/w CE. */
446void target_crypto_init_params()
447{
448 struct crypto_init_params ce_params;
449
450 /* Set up base addresses and instance. */
451 ce_params.crypto_instance = CE_INSTANCE;
452 ce_params.crypto_base = MSM_CE_BASE;
453 ce_params.bam_base = MSM_CE_BAM_BASE;
454
455 /* Set up BAM config. */
456 ce_params.bam_ee = CE_EE;
457 ce_params.pipes.read_pipe = CE_READ_PIPE;
458 ce_params.pipes.write_pipe = CE_WRITE_PIPE;
459 ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
460 ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
461
462 /* Assign buffer sizes. */
463 ce_params.num_ce = CE_ARRAY_SIZE;
464 ce_params.read_fifo_size = CE_FIFO_SIZE;
465 ce_params.write_fifo_size = CE_FIFO_SIZE;
466
467 /* BAM is initialized by TZ for this platform.
468 * Do not do it again as the initialization address space
469 * is locked.
470 */
471 ce_params.do_bam_init = 0;
472
473 crypto_init_params(&ce_params);
474}
Channagoud Kadabi083290f2015-03-13 14:18:38 -0700475
476unsigned target_pause_for_battery_charge(void)
477{
478 uint8_t pon_reason = pm8x41_get_pon_reason();
479 uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
480 dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
481 pon_reason, is_cold_boot);
482 /* In case of fastboot reboot,adb reboot or if we see the power key
483 * pressed we do not want go into charger mode.
484 * fastboot reboot is warm boot with PON hard reset bit not set
485 * adb reboot is a cold boot with PON hard reset bit set
486 */
487 if (is_cold_boot &&
488 (!(pon_reason & HARD_RST)) &&
489 (!(pon_reason & KPDPWR_N)) &&
490 ((pon_reason & PON1)))
491 return 1;
492 else
493 return 0;
494}
Channagoud Kadabi23edc0c2015-03-27 18:31:32 -0700495
496int set_download_mode(enum dload_mode mode)
497{
498 int ret = 0;
499 ret = scm_dload_mode(mode);
500
501 return ret;
502}
Channagoud Kadabiffc4b902015-06-25 23:14:27 -0700503
504void shutdown_device()
505{
506 dprintf(CRITICAL, "Going down for shutdown.\n");
507
508 /* Configure PMIC for shutdown. */
509 pm8994_reset_configure(PON_PSHOLD_SHUTDOWN);
510
511 /* Drop PS_HOLD for MSM */
512 writel(0x00, MPM2_MPM_PS_HOLD);
513
514 mdelay(5000);
515
516 dprintf(CRITICAL, "Shutdown failed\n");
517
518 ASSERT(0);
519}