blob: 2b33fd172c39927475f017cb33d55c5075828ee2 [file] [log] [blame]
Jeevan Shriram2d3500b2014-12-29 16:25:06 -08001/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
Dhaval Patel019057a2014-08-12 13:52:25 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions
5 * are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in
10 * the documentation and/or other materials provided with the
11 * distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
19 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
20 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <debug.h>
Veera Sundaram Sankaran089f70d2014-12-09 14:17:05 -080031#include <string.h>
Dhaval Patel019057a2014-08-12 13:52:25 -070032#include <smem.h>
33#include <err.h>
34#include <msm_panel.h>
35#include <mipi_dsi.h>
36#include <pm8x41.h>
37#include <pm8x41_wled.h>
38#include <qpnp_wled.h>
39#include <board.h>
40#include <mdp5.h>
41#include <scm.h>
42#include <endian.h>
Veera Sundaram Sankaran089f70d2014-12-09 14:17:05 -080043#include <regulator.h>
44#include <qtimer.h>
45#include <arch/defines.h>
Dhaval Patel019057a2014-08-12 13:52:25 -070046#include <platform/gpio.h>
47#include <platform/clock.h>
48#include <platform/iomap.h>
49#include <target/display.h>
50#include "include/panel.h"
51#include "include/display_resource.h"
Veera Sundaram Sankaran089f70d2014-12-09 14:17:05 -080052#include "gcdb_display.h"
Dhaval Patel019057a2014-08-12 13:52:25 -070053
54#define HFPLL_LDO_ID 12
55
56#define GPIO_STATE_LOW 0
57#define GPIO_STATE_HIGH 2
58#define RESET_GPIO_SEQ_LEN 3
59
60#define PWM_DUTY_US 13
61#define PWM_PERIOD_US 27
62#define PMIC_WLED_SLAVE_ID 3
63#define PMIC_MPP_SLAVE_ID 2
64
Jeevan Shriram7aacc322014-12-29 16:02:25 -080065#define DSI0_BASE_ADJUST -0x4000
66#define DSI1_BASE_ADJUST -0xA000
67
Veera Sundaram Sankaran089f70d2014-12-09 14:17:05 -080068/*---------------------------------------------------------------------------*/
69/* GPIO configuration */
70/*---------------------------------------------------------------------------*/
71static struct gpio_pin reset_gpio = {
72 "msmgpio", 78, 3, 1, 0, 1
73};
74
75static struct gpio_pin lcd_reg_en = { /* boost regulator */
76 "pm8994_gpios", 14, 3, 1, 0, 1
77};
78
79static struct gpio_pin bklt_gpio = { /* lcd_bklt_reg_en */
80 "pmi8994_gpios", 2, 3, 1, 0, 1
81};
82
Dhaval Patel019057a2014-08-12 13:52:25 -070083static uint32_t dsi_pll_20nm_enable_seq(uint32_t pll_base)
84{
85 uint32_t pll_locked;
Jeevan Shriram5a9f8f42014-12-14 14:56:14 -080086 /* MDSS_DSI_0_PHY_DSIPHY_CTRL_1 */
87 writel(0x00, pll_base + 0x374);
Dhaval Patel019057a2014-08-12 13:52:25 -070088 dmb();
Jeevan Shriram5a9f8f42014-12-14 14:56:14 -080089 /* MDSS_DSI_0_PHY_DSIPHY_CTRL_0 */
90 writel(0x7f, pll_base + 0x370);
91 dmb();
92 pll_locked = mdss_dsi_pll_20nm_lock_status(pll_base);
93 if (!pll_locked)
94 dprintf(INFO, "%s: DSI PLL lock failed\n", __func__);
95 else
96 dprintf(INFO, "%s: DSI PLL lock Success\n", __func__);
Dhaval Patel019057a2014-08-12 13:52:25 -070097
98 return pll_locked;
99}
100
101static int msm8994_wled_backlight_ctrl(uint8_t enable)
102{
Kuogee Hsieh911866e2014-09-02 16:41:18 -0700103 uint8_t slave_id = 3; /* pmi */
Dhaval Patel019057a2014-08-12 13:52:25 -0700104
Veera Sundaram Sankaranf9ddd6c2014-12-02 11:04:52 -0800105 pm8x41_wled_config_slave_id(slave_id);
106 qpnp_wled_enable_backlight(enable);
Dhaval Patel019057a2014-08-12 13:52:25 -0700107 qpnp_ibb_enable(enable);
108 return NO_ERROR;
109}
110
111static int msm8994_pwm_backlight_ctrl(uint8_t enable)
112{
Kuogee Hsieh911866e2014-09-02 16:41:18 -0700113 uint8_t slave_id = 3; /* lpg at pmi */
114
115 if (enable) {
116 /* mpp-1 had been configured already */
117 /* lpg channel 4 */
118
119 /* LPG_ENABLE_CONTROL */
120 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0x0);
121 mdelay(100);
122
123 /* LPG_VALUE_LSB, duty cycle = 0x80/0x200 = 1/4 */
124 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x44, 0x80);
125 /* LPG_VALUE_MSB */
126 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x45, 0x00);
127 /* LPG_PWM_SYNC */
128 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x47, 0x01);
129
130 /* LPG_PWM_SIZE_CLK, */
131 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x41, 0x13);
132 /* LPG_PWM_FREQ_PREDIV */
133 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x42, 0x02);
134 /* LPG_PWM_TYPE_CONFIG */
135 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x43, 0x20);
136 /* LPG_ENABLE_CONTROL */
137 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0x04);
138
139 /* SEC_ACCESS */
140 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0xD0, 0xA5);
141 /* DTEST4, OUT_HI */
142 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0xE5, 0x01);
143 /* LPG_ENABLE_CONTROL */
144 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0xA4);
145 } else {
146 /* LPG_ENABLE_CONTROL */
147 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0x0);
148 }
149
150 return NO_ERROR;
151}
152
153void lcd_bklt_reg_enable(void)
154{
155 uint8_t slave_id = 2; /* gpio at pmi */
156
157 struct pm8x41_gpio gpio = {
158 .direction = PM_GPIO_DIR_OUT,
159 .function = PM_GPIO_FUNC_HIGH,
160 .vin_sel = 2, /* VIN_2 */
161 .output_buffer = PM_GPIO_OUT_CMOS,
162 .out_strength = PM_GPIO_OUT_DRIVE_LOW,
163 };
164
165 pm8x41_gpio_config_sid(slave_id, bklt_gpio.pin_id, &gpio);
166 pm8x41_gpio_set_sid(slave_id, bklt_gpio.pin_id, 1);
167}
168
169void lcd_bklt_reg_disable(void)
170{
171 uint8_t slave_id = 2; /* gpio at pmi */
172
173 pm8x41_gpio_set_sid(slave_id, bklt_gpio.pin_id, 0);
Dhaval Patel019057a2014-08-12 13:52:25 -0700174}
175
Kuogee Hsieh208736d2014-08-22 14:16:55 -0700176void lcd_reg_enable(void)
Dhaval Patel019057a2014-08-12 13:52:25 -0700177{
178 struct pm8x41_gpio gpio = {
179 .direction = PM_GPIO_DIR_OUT,
180 .function = PM_GPIO_FUNC_HIGH,
181 .vin_sel = 2, /* VIN_2 */
182 .output_buffer = PM_GPIO_OUT_CMOS,
183 .out_strength = PM_GPIO_OUT_DRIVE_MED,
184 };
185
Kuogee Hsieh208736d2014-08-22 14:16:55 -0700186 pm8x41_gpio_config(lcd_reg_en.pin_id, &gpio);
187 pm8x41_gpio_set(lcd_reg_en.pin_id, 1);
188}
189
190void lcd_reg_disable(void)
191{
192 pm8x41_gpio_set(lcd_reg_en.pin_id, 0);
Dhaval Patel019057a2014-08-12 13:52:25 -0700193}
194
195int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
196{
197 uint32_t ret = NO_ERROR;
198 struct pm8x41_mpp mpp;
199 int rc;
200
201 if (!bl) {
202 dprintf(CRITICAL, "backlight structure is not available\n");
203 return ERR_INVALID_ARGS;
204 }
205
206 switch (bl->bl_interface_type) {
207 case BL_WLED:
208 /* Enable MPP4 */
209 pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID);
210 mpp.base = PM8x41_MMP4_BASE;
211 mpp.vin = MPP_VIN2;
212 if (enable) {
213 pm_pwm_enable(false);
214 rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
215 if (rc < 0) {
216 mpp.mode = MPP_HIGH;
217 } else {
218 mpp.mode = MPP_DTEST1;
219 pm_pwm_enable(true);
220 }
221 pm8x41_config_output_mpp(&mpp);
222 pm8x41_enable_mpp(&mpp, MPP_ENABLE);
223 } else {
224 pm_pwm_enable(false);
225 pm8x41_enable_mpp(&mpp, MPP_DISABLE);
226 }
227 /* Need delay before power on regulators */
228 mdelay(20);
229 /* Enable WLED backlight control */
230 ret = msm8994_wled_backlight_ctrl(enable);
231 break;
232 case BL_PWM:
Kuogee Hsieh911866e2014-09-02 16:41:18 -0700233 /* Enable MPP1 */
234 pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID);
235 mpp.base = PM8x41_MMP1_BASE;
236 mpp.vin = MPP_VIN2;
237 mpp.mode = MPP_DTEST4;
238 if (enable) {
239 pm8x41_config_output_mpp(&mpp);
240 pm8x41_enable_mpp(&mpp, MPP_ENABLE);
241 } else {
242 pm8x41_enable_mpp(&mpp, MPP_DISABLE);
243 }
244 /* Need delay before power on regulators */
245 mdelay(20);
Dhaval Patel019057a2014-08-12 13:52:25 -0700246 ret = msm8994_pwm_backlight_ctrl(enable);
247 break;
248 default:
249 dprintf(CRITICAL, "backlight type:%d not supported\n",
250 bl->bl_interface_type);
251 return ERR_NOT_SUPPORTED;
252 }
253
254 return ret;
255}
256
257int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
258{
259 uint32_t ret;
260 struct mdss_dsi_pll_config *pll_data;
Aravind Venkateswaranf3554322014-12-08 12:03:48 -0800261 uint32_t flags;
262
263 if (pinfo->dest == DISPLAY_2) {
264 flags = MMSS_DSI_CLKS_FLAG_DSI1;
265 if (pinfo->mipi.dual_dsi)
266 flags |= MMSS_DSI_CLKS_FLAG_DSI0;
267 } else {
268 flags = MMSS_DSI_CLKS_FLAG_DSI0;
269 if (pinfo->mipi.dual_dsi)
270 flags |= MMSS_DSI_CLKS_FLAG_DSI1;
271 }
Dhaval Patel019057a2014-08-12 13:52:25 -0700272
273 pll_data = pinfo->mipi.dsi_pll_config;
274 if (enable) {
275 mdp_gdsc_ctrl(enable);
276 mmss_bus_clock_enable();
277 mdp_clock_enable();
278 ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
279 if (ret) {
280 dprintf(CRITICAL,
281 "%s: Failed to restore MDP security configs",
282 __func__);
283 mdp_clock_disable();
284 mmss_bus_clock_disable();
285 mdp_gdsc_ctrl(0);
286 return ret;
287 }
Jeevan Shriram2d3500b2014-12-29 16:25:06 -0800288 mdss_dsi_auto_pll_20nm_config(pinfo->mipi.pll_0_base,
Huaibin Yang90991f12014-12-29 13:24:43 -0800289 pinfo->mipi.pll_1_base, pll_data);
Jeevan Shriram2d3500b2014-12-29 16:25:06 -0800290 dsi_pll_20nm_enable_seq(pinfo->mipi.pll_0_base);
Aravind Venkateswaranf3554322014-12-08 12:03:48 -0800291 mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, flags,
Dhaval Patel019057a2014-08-12 13:52:25 -0700292 pll_data->pclk_m,
293 pll_data->pclk_n,
294 pll_data->pclk_d);
295 } else if(!target_cont_splash_screen()) {
296 /* Disable clocks if continuous splash off */
Aravind Venkateswaranf3554322014-12-08 12:03:48 -0800297 mmss_dsi_clock_disable(flags);
Dhaval Patel019057a2014-08-12 13:52:25 -0700298 mdp_clock_disable();
299 mmss_bus_clock_disable();
300 mdp_gdsc_ctrl(enable);
301 }
302
303 return NO_ERROR;
304}
305
306int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
307 struct msm_panel_info *pinfo)
308{
309 uint32_t i = 0;
310
311 if (enable) {
312 gpio_tlmm_config(reset_gpio.pin_id, 0,
313 reset_gpio.pin_direction, reset_gpio.pin_pull,
314 reset_gpio.pin_strength, reset_gpio.pin_state);
315 /* reset */
316 for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
317 if (resetseq->pin_state[i] == GPIO_STATE_LOW)
318 gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
319 else
320 gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
321 mdelay(resetseq->sleep[i]);
322 }
Kuogee Hsieh911866e2014-09-02 16:41:18 -0700323 lcd_bklt_reg_enable();
Dhaval Patel019057a2014-08-12 13:52:25 -0700324 } else {
Kuogee Hsieh911866e2014-09-02 16:41:18 -0700325 lcd_bklt_reg_disable();
Dhaval Patel019057a2014-08-12 13:52:25 -0700326 gpio_set(reset_gpio.pin_id, 0);
327 }
328
329 return NO_ERROR;
330}
331
Kuogee Hsieh099022f2014-12-05 15:43:40 -0800332static void wled_init(struct msm_panel_info *pinfo)
333{
334 struct qpnp_wled_config_data config = {0};
335 struct labibb_desc *labibb;
336 int display_type = 0;
337
338 labibb = pinfo->labibb;
339
340 if (labibb)
341 display_type = labibb->amoled_panel;
342
343 config.display_type = display_type;
344 config.lab_init_volt = 4600000; /* fixed, see pmi register */
345 config.ibb_init_volt = 1400000; /* fixed, see pmi register */
346
347 if (labibb && labibb->force_config) {
348 config.lab_min_volt = labibb->lab_min_volt;
349 config.lab_max_volt = labibb->lab_max_volt;
350 config.ibb_min_volt = labibb->ibb_min_volt;
351 config.ibb_max_volt = labibb->ibb_max_volt;
352 config.pwr_up_delay = labibb->pwr_up_delay;
353 config.pwr_down_delay = labibb->pwr_down_delay;
354 config.ibb_discharge_en = labibb->ibb_discharge_en;
355 } else {
356 /* default */
357 config.pwr_up_delay = 3;
358 config.pwr_down_delay = 3;
359 config.ibb_discharge_en = 1;
360 if (display_type) { /* amoled */
361 config.lab_min_volt = 4600000;
362 config.lab_max_volt = 4600000;
363 config.ibb_min_volt = 4000000;
364 config.ibb_max_volt = 4000000;
365 } else { /* lcd */
366 config.lab_min_volt = 5500000;
367 config.lab_max_volt = 5500000;
368 config.ibb_min_volt = 5500000;
369 config.ibb_max_volt = 5500000;
370 }
371 }
372
373 dprintf(SPEW, "%s: %d %d %d %d %d %d %d %d %d %d\n", __func__,
374 config.display_type,
375 config.lab_min_volt, config.lab_max_volt,
376 config.ibb_min_volt, config.ibb_max_volt,
377 config.lab_init_volt, config.ibb_init_volt,
378 config.pwr_up_delay, config.pwr_down_delay,
379 config.ibb_discharge_en);
380
381
382 /* QPNP WLED init for display backlight */
383 pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID);
384
385 qpnp_wled_init(&config);
386}
387
Kuogee Hsieh93bcff62014-08-22 14:02:08 -0700388int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
Dhaval Patel019057a2014-08-12 13:52:25 -0700389{
390 if (enable) {
391 regulator_enable(); /* L2, L12, L14, and L28 */
392 mdelay(10);
Kuogee Hsieh099022f2014-12-05 15:43:40 -0800393 wled_init(pinfo);
Dhaval Patel019057a2014-08-12 13:52:25 -0700394 qpnp_ibb_enable(true); /* +5V and -5V */
395 mdelay(50);
Kuogee Hsieh208736d2014-08-22 14:16:55 -0700396
397 if (pinfo->lcd_reg_en)
398 lcd_reg_enable();
Dhaval Patel019057a2014-08-12 13:52:25 -0700399 } else {
Kuogee Hsieh208736d2014-08-22 14:16:55 -0700400 if (pinfo->lcd_reg_en)
401 lcd_reg_disable();
402
Dhaval Patel019057a2014-08-12 13:52:25 -0700403 regulator_disable();
404 }
405
406 return NO_ERROR;
407}
408
409int target_display_pre_on()
410{
Ingrid Gallardoc9776bd2014-09-04 14:13:28 -0700411 writel(0xC0000CCC, MDP_CLK_CTRL0);
412 writel(0xC0000CCC, MDP_CLK_CTRL1);
Dhaval Patel019057a2014-08-12 13:52:25 -0700413 writel(0x00CCCCCC, MDP_CLK_CTRL2);
414 writel(0x000000CC, MDP_CLK_CTRL6);
415 writel(0x0CCCC0C0, MDP_CLK_CTRL3);
416 writel(0xCCCCC0C0, MDP_CLK_CTRL4);
417 writel(0xCCCCC0C0, MDP_CLK_CTRL5);
418 writel(0x00CCC000, MDP_CLK_CTRL7);
419
Dhaval Patel019057a2014-08-12 13:52:25 -0700420 return NO_ERROR;
421}
422
Jeevan Shriram7aacc322014-12-29 16:02:25 -0800423int target_display_get_base_offset(uint32_t base)
424{
425 if(platform_is_msm8992()) {
426 if (base == MIPI_DSI0_BASE)
427 return DSI0_BASE_ADJUST;
428 else if (base == MIPI_DSI1_BASE)
429 return DSI1_BASE_ADJUST;
430 }
431
432 return 0;
433}
434
Dhaval Patel019057a2014-08-12 13:52:25 -0700435bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
436{
Ajay Singh Parmarcc6477b2014-11-14 16:59:44 -0800437 int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
438 bool ret = true;
Dhaval Patel019057a2014-08-12 13:52:25 -0700439
Ajay Singh Parmarcc6477b2014-11-14 16:59:44 -0800440 panel_name += strspn(panel_name, " ");
441
442 if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
443 if (buf_size < (prefix_string_len + LK_OVERRIDE_PANEL_LEN +
444 strlen(HDMI_CONTROLLER_STRING))) {
445 dprintf(CRITICAL, "command line argument is greater than buffer size\n");
446 return false;
447 }
448
449 strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
450 buf_size -= prefix_string_len;
451 strlcat(pbuf, LK_OVERRIDE_PANEL, buf_size);
452 buf_size -= LK_OVERRIDE_PANEL_LEN;
453 strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
454 } else {
455 ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
456 }
457
458 return ret;
Dhaval Patel019057a2014-08-12 13:52:25 -0700459}
460
461void target_display_init(const char *panel_name)
462{
Veera Sundaram Sankaran7868d542015-01-02 14:48:47 -0800463 char cont_splash = '\0';
Veera Sundaram Sankaran3b758822014-10-17 12:15:39 -0700464
Veera Sundaram Sankaran7868d542015-01-02 14:48:47 -0800465 set_panel_cmd_string(panel_name, &cont_splash);
466 panel_name += strspn(panel_name, " ");
Veera Sundaram Sankaran3b758822014-10-17 12:15:39 -0700467 if (!strcmp(panel_name, NO_PANEL_CONFIG)
468 || !strcmp(panel_name, SIM_VIDEO_PANEL)
469 || !strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL)
470 || !strcmp(panel_name, SIM_CMD_PANEL)
471 || !strcmp(panel_name, SIM_DUALDSI_CMD_PANEL)) {
Veera Sundaram Sankaranb620f232014-09-03 22:43:53 -0700472 dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
Veera Sundaram Sankaran3b758822014-10-17 12:15:39 -0700473 panel_name);
Veera Sundaram Sankaranb620f232014-09-03 22:43:53 -0700474 return;
Ajay Singh Parmarcc6477b2014-11-14 16:59:44 -0800475 } else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
476 return;
Veera Sundaram Sankaranb620f232014-09-03 22:43:53 -0700477 }
Veera Sundaram Sankaran7868d542015-01-02 14:48:47 -0800478
Veera Sundaram Sankaran089f70d2014-12-09 14:17:05 -0800479 if (gcdb_display_init(panel_name, MDP_REV_50, (void *)MIPI_FB_ADDR)) {
Justin Philipbe9de5c2014-09-17 12:26:49 +0530480 target_force_cont_splash_disable(true);
Dhaval Patel019057a2014-08-12 13:52:25 -0700481 msm_display_off();
Justin Philipbe9de5c2014-09-17 12:26:49 +0530482 }
Veera Sundaram Sankaran7868d542015-01-02 14:48:47 -0800483
484 if (cont_splash == '0') {
485 dprintf(INFO, "Forcing continuous splash disable\n");
486 target_force_cont_splash_disable(true);
487 }
Dhaval Patel019057a2014-08-12 13:52:25 -0700488}
489
490void target_display_shutdown(void)
491{
492 gcdb_display_shutdown();
493}