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gerrit-public.fairphone.software / kernel / lk / e22e6a7129e810a9d5cf22fab99062e8b313cea7 / . / platform / msm8996 / include / platform / iomap.h
blob: 657ea505ca143b01f7917602599e2139894d9aeb [file] [log] [blame]
Sridhar Parasurambe12c3d2015-01-16 13:42:26 -0800[diff] [blame]1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_THULIUM_IOMAP_H_
30#define _PLATFORM_THULIUM_IOMAP_H_
31
32#define MSM_SHARED_BASE 0x86000000
33
34#define MSM_IOMAP_HMSS_START 0x09800000
35
36#define MSM_IOMAP_BASE 0x00000000
37#define MSM_IOMAP_END 0x10000000
38
39#define MSM_SHARED_IMEM_BASE 0x066BF000
40#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]41#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + 0x6B0)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]42
43#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
44#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
45
46#define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000)
47#define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE
48
Sridhar Parasurambe12c3d2015-01-16 13:42:26 -0800[diff] [blame]49#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS 0x00068000
50#define RPM_SS_MSG_RAM_START_ADDRESS_BASE RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS
51#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE 0x00006000
52
Sridhar Parasuram103702f2015-01-26 18:07:55 -0800[diff] [blame]53#define APCS_HLOS_IPC_INTERRUPT_0 0x9820010
54
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]55#define PERIPH_SS_BASE 0x07400000
56
57#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000)
58#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
59#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
60#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
61
62#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0016F000)
63#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x00170000)
64#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x00171000)
65#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00172000)
66#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00173000)
67#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00174000)
68
69#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x001B0000)
70
71/* USB3.0 */
72#define MSM_USB30_BASE 0x6A00000
73#define MSM_USB30_QSCRATCH_BASE 0x6AF8800
74/* SS QMP (Qulacomm Multi Protocol) */
75#define QMP_PHY_BASE 0x7410000
76
77/* QUSB2 PHY */
78#define QUSB2_PHY_BASE 0x7411000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]79#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00012038)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]80
Channagoud Kadabi4517eb12015-09-02 18:43:13 -0700[diff] [blame]81#define AHB2_PHY_BASE 0x7416000
82#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
Channagoud Kadabidf6d7ad2015-09-24 15:17:03 -0700[diff] [blame]83#define GCC_RX2_USB2_CLKREF_EN 0x00388014
Channagoud Kadabi4517eb12015-09-02 18:43:13 -0700[diff] [blame]84
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]85/* Clocks */
86#define CLK_CTL_BASE 0x300000
87
88/* GPLL */
89#define GPLL0_MODE (CLK_CTL_BASE + 0x0000)
90#define GPLL4_MODE (CLK_CTL_BASE + 0x77000)
91#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x52000)
92#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
93
94/* UART Clocks */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]95#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x25004)
96#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29004)
Channagoud Kadabi35503c42014-11-14 16:22:43 -0800[diff] [blame]97#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C)
98#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010)
99#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014)
100#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0x29018)
101#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0x2901C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]102
103/* USB3 clocks */
104#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]105#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]106#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]107#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
108#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]109#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014)
110#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018)
111#define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C)
112#define USB30_MASTER_N (CLK_CTL_BASE + 0xF020)
113#define USB30_MASTER_D (CLK_CTL_BASE + 0xF024)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]114#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF028)
115#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF02C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]116#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C)
117
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]118#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C)
119#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010)
120#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000)
121#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004)
122#define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020)
123#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]124#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]125#define GCC_AGGRE2_USB3_AXI_CBCR (CLK_CTL_BASE + 0x83018)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]126
127/* SDCC */
128#define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */
129#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x13004) /* branch control */
130#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x13008)
131#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x13010) /* cmd */
132#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x13014) /* cfg */
133#define SDCC1_M (CLK_CTL_BASE + 0x13018) /* m */
134#define SDCC1_N (CLK_CTL_BASE + 0x1301C) /* n */
135#define SDCC1_D (CLK_CTL_BASE + 0x13020) /* d */
136
137/* SDCC2 */
138#define SDCC2_BCR (CLK_CTL_BASE + 0x14000) /* block reset */
139#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x14004) /* branch control */
140#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x14008)
141#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x14010) /* cmd */
142#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x14014) /* cfg */
143#define SDCC2_M (CLK_CTL_BASE + 0x14018) /* m */
144#define SDCC2_N (CLK_CTL_BASE + 0x1401C) /* n */
145#define SDCC2_D (CLK_CTL_BASE + 0x14020) /* d */
146
147#define UFS_BASE 0x624000
148
149#define SPMI_BASE 0x4000000
150#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
151#define SPMI_PIC_BASE (SPMI_BASE + 0x1800000)
Channagoud Kadabi7b20dea2014-11-11 13:27:33 -0800[diff] [blame]152#define PMIC_ARB_CORE 0x400F000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]153
Channagoud Kadabi037c8b82015-02-05 12:09:32 -0800[diff] [blame]154#define MSM_CE_BAM_BASE 0x644000
155#define MSM_CE_BASE 0x67A000
156#define GCC_CE1_BCR (CLK_CTL_BASE + 0x00041000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]157
158#define TLMM_BASE_ADDR 0x1010000
159#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
160#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x4 + (x)*0x1000)
161
162#define MPM2_MPM_CTRL_BASE 0x4A1000
163#define MPM2_MPM_PS_HOLD 0x4AB000
164#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
165
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]166/* QSEECOM: Secure app region notification */
167#define APP_REGION_ADDR 0x86600000
Zhen Kong327fac52015-06-12 17:04:24 -0700[diff] [blame]168#define APP_REGION_SIZE 0x2200000
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]169
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]170/* DRV strength for sdcc */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]171#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0012C000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]172
173/* SDHCI - power control registers */
174#define SDCC_MCI_HC_MODE (0x00000078)
175#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
176#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
177#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
178#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
179
180/* Boot config */
181#define SEC_CTRL_CORE_BASE 0x70000
182#define BOOT_CONFIG_OFFSET 0x00006044
183#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
184
Channagoud Kadabi652a6f62014-11-17 17:23:23 -0800[diff] [blame]185/* QMP rev registers */
186#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x788)
187#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x78C)
188#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x790)
189#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x794)
190
191/* Dummy macro needed for compilation only */
192#define PLATFORM_QMP_OFFSET 0x0
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]193
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]194/* RPMB send receive buffer needs to be mapped
195 * as device memory, define the start address
196 * and size in MB
197 */
Channagoud Kadabi40039922015-09-29 15:23:03 -0700[diff] [blame]198#define RPMB_SND_RCV_BUF 0x91A00000
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700[diff] [blame]199#define RPMB_SND_RCV_BUF_SZ 0x2
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]200
Channagoud Kadabi23edc0c2015-03-27 18:31:32 -0700[diff] [blame]201#define TCSR_BOOT_MISC_DETECT 0x007B3000
Dhaval Patel0f3cbeb2015-03-17 11:52:12 -0700[diff] [blame]202
203#define MSM_MMSS_CLK_CTL_BASE 0x8C0000
204#define MMSS_MISC_AHB_CBCR (MSM_MMSS_CLK_CTL_BASE + 0x5018)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]205
206#define MIPI_DSI_BASE (0x994000)
207#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
208#define MIPI_DSI1_BASE (0x996000)
209#define DSI0_PHY_BASE (0x994400)
210#define DSI1_PHY_BASE (0x996400)
211#define DSI0_PLL_BASE (0x994800)
212#define DSI1_PLL_BASE (0x996800)
213#define DSI0_REGULATOR_BASE (0x994000)
214#define DSI1_REGULATOR_BASE (0x996000)
215
Jeevan Shriram3c20e632015-08-03 15:21:04 -0700[diff] [blame]216#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0D0
217#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0D4
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]218
219#define MDP_BASE (0x900000)
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]220#define REG_MDP(off) (MDP_BASE + (off))
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]221
222#ifdef MDP_PP_0_BASE
223#undef MDP_PP_0_BASE
224#endif
225#define MDP_PP_0_BASE REG_MDP(0x71000)
226
227#ifdef MDP_PP_1_BASE
228#undef MDP_PP_1_BASE
229#endif
230#define MDP_PP_1_BASE REG_MDP(0x71800)
231
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]232#define MDP_DSC_0_BASE REG_MDP(0x81000)
233#define MDP_DSC_1_BASE REG_MDP(0x81400)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]234
235#ifdef MDP_HW_REV
236#undef MDP_HW_REV
237#endif
238#define MDP_HW_REV REG_MDP(0x1000)
239
240#ifdef MDP_INTR_EN
241#undef MDP_INTR_EN
242#endif
243#define MDP_INTR_EN REG_MDP(0x1010)
244
245#ifdef MDP_INTR_CLEAR
246#undef MDP_INTR_CLEAR
247#endif
248#define MDP_INTR_CLEAR REG_MDP(0x1018)
249
250#ifdef MDP_HIST_INTR_EN
251#undef MDP_HIST_INTR_EN
252#endif
253#define MDP_HIST_INTR_EN REG_MDP(0x101C)
254
255#ifdef MDP_DISP_INTF_SEL
256#undef MDP_DISP_INTF_SEL
257#endif
258#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
259
260#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
261#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
262#endif
263#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
264
265#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
266#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
267#endif
268#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
269
270#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
271#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
272#endif
273#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
274
275#ifdef MDP_INTF_0_TIMING_ENGINE_EN
276#undef MDP_INTF_0_TIMING_ENGINE_EN
277#endif
278#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
279
280#ifdef MDP_INTF_1_TIMING_ENGINE_EN
281#undef MDP_INTF_1_TIMING_ENGINE_EN
282#endif
283#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
284
285#ifdef MDP_INTF_2_TIMING_ENGINE_EN
286#undef MDP_INTF_2_TIMING_ENGINE_EN
287#endif
288#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x6C000)
289
290#ifdef MDP_CTL_0_BASE
291#undef MDP_CTL_0_BASE
292#endif
293#define MDP_CTL_0_BASE REG_MDP(0x2000)
294
295#ifdef MDP_CTL_1_BASE
296#undef MDP_CTL_1_BASE
297#endif
298#define MDP_CTL_1_BASE REG_MDP(0x2200)
299
300#ifdef MDP_REG_SPLIT_DISPLAY_EN
301#undef MDP_REG_SPLIT_DISPLAY_EN
302#endif
303#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
304
305#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
306#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
307#endif
308#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
309
310#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
311#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
312#endif
313#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
314
315#ifdef MDP_INTF_0_BASE
316#undef MDP_INTF_0_BASE
317#endif
318#define MDP_INTF_0_BASE REG_MDP(0x6b000)
319
320#ifdef MDP_INTF_1_BASE
321#undef MDP_INTF_1_BASE
322#endif
323#define MDP_INTF_1_BASE REG_MDP(0x6b800)
324
325#ifdef MDP_INTF_2_BASE
326#undef MDP_INTF_2_BASE
327#endif
328#define MDP_INTF_2_BASE REG_MDP(0x6c000)
329
330#ifdef MDP_CLK_CTRL0
331#undef MDP_CLK_CTRL0
332#endif
333#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
334
335#ifdef MDP_CLK_CTRL1
336#undef MDP_CLK_CTRL1
337#endif
338#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
339
340#ifdef MDP_CLK_CTRL2
341#undef MDP_CLK_CTRL2
342#endif
343#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
344
345#ifdef MDP_CLK_CTRL3
346#undef MDP_CLK_CTRL3
347#endif
348#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
349
350#ifdef MDP_CLK_CTRL4
351#undef MDP_CLK_CTRL4
352#endif
353#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
354
355#ifdef MDP_CLK_CTRL5
356#undef MDP_CLK_CTRL5
357#endif
358#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
359
360#ifdef MDP_CLK_CTRL6
361#undef MDP_CLK_CTRL6
362#endif
363#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
364
365#ifdef MDP_CLK_CTRL7
366#undef MDP_CLK_CTRL7
367#endif
368#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
369
370#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
371#undef MMSS_MDP_SMP_ALLOC_W_BASE
372#endif
373#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
374
375#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
376#undef MMSS_MDP_SMP_ALLOC_R_BASE
377#endif
378#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
379
380#ifdef MDP_QOS_REMAPPER_CLASS_0
381#undef MDP_QOS_REMAPPER_CLASS_0
382#endif
383#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
384
385#ifdef MDP_QOS_REMAPPER_CLASS_1
386#undef MDP_QOS_REMAPPER_CLASS_1
387#endif
388#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
389
390#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
391#undef VBIF_VBIF_DDR_FORCE_CLK_ON
392#endif
393#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xb0004)
394
395#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
396#undef VBIF_VBIF_DDR_OUT_MAX_BURST
397#endif
398#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xb00D8)
399
400#ifdef VBIF_VBIF_DDR_ARB_CTRL
401#undef VBIF_VBIF_DDR_ARB_CTRL
402#endif
403#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xb00F0)
404
405#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
406#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
407#endif
408#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xb0124)
409
410#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
411#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
412#endif
413#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xb0160)
414
415#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
416#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
417#endif
418#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xb0164)
419
420#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
421#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
422#endif
423#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xb0178)
424
425#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
426#undef VBIF_VBIF_DDR_OUT_AX_AOOO
427#endif
428#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xb017C)
429
430#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
431#undef VBIF_VBIF_IN_RD_LIM_CONF0
432#endif
433#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xb00B0)
434
435#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
436#undef VBIF_VBIF_IN_RD_LIM_CONF1
437#endif
438#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xb00B4)
439
440#ifdef VBIF_VBIF_IN_RD_LIM_CONF2
441#undef VBIF_VBIF_IN_RD_LIM_CONF2
442#endif
443#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xb00B8)
444
445#ifdef VBIF_VBIF_IN_RD_LIM_CONF3
446#undef VBIF_VBIF_IN_RD_LIM_CONF3
447#endif
448#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xb00BC)
449
450#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
451#undef VBIF_VBIF_IN_WR_LIM_CONF0
452#endif
453#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xb00C0)
454
455#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
456#undef VBIF_VBIF_IN_WR_LIM_CONF1
457#endif
458#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xb00C4)
459
460#ifdef VBIF_VBIF_IN_WR_LIM_CONF2
461#undef VBIF_VBIF_IN_WR_LIM_CONF2
462#endif
463#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xb00C8)
464
465#ifdef VBIF_VBIF_IN_WR_LIM_CONF3
466#undef VBIF_VBIF_IN_WR_LIM_CONF3
467#endif
468#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xb00CC)
469
470#ifdef VBIF_VBIF_ABIT_SHORT
471#undef VBIF_VBIF_ABIT_SHORT
472#endif
473#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xb0070)
474
475#ifdef VBIF_VBIF_ABIT_SHORT_CONF
476#undef VBIF_VBIF_ABIT_SHORT_CONF
477#endif
478#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xb0074)
479
480#ifdef VBIF_VBIF_GATE_OFF_WRREQ_EN
481#undef VBIF_VBIF_GATE_OFF_WRREQ_EN
482#endif
483#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xb00A8)
484
485#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
486#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
487#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
488#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
489#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
490#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
491#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
492#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
493
494#define DMA_CMD_OFFSET 0x048
495#define DMA_CMD_LENGTH 0x04C
496
497#define INT_CTRL 0x110
498#define CMD_MODE_DMA_SW_TRIGGER 0x090
499
500#define EOT_PACKET_CTRL 0x0CC
501#define MISR_CMD_CTRL 0x0A0
502#define MISR_VIDEO_CTRL 0x0A4
503#define VIDEO_MODE_CTRL 0x010
504#define HS_TIMER_CTRL 0x0BC
505
506#define SOFT_RESET 0x118
507#define CLK_CTRL 0x11C
508#define TRIG_CTRL 0x084
509#define CTRL 0x004
510#define COMMAND_MODE_DMA_CTRL 0x03C
511#define COMMAND_MODE_MDP_CTRL 0x040
512#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
513#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
514#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
515#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
516#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
517#define ERR_INT_MASK0 0x10C
518
519#define LANE_CTL 0x0AC
520#define LANE_SWAP_CTL 0x0B0
521#define TIMING_CTL 0x0C4
522
523#define VIDEO_MODE_ACTIVE_H 0x024
524#define VIDEO_MODE_ACTIVE_V 0x028
525#define VIDEO_MODE_TOTAL 0x02C
526#define VIDEO_MODE_HSYNC 0x030
527#define VIDEO_MODE_VSYNC 0x034
528#define VIDEO_MODE_VSYNC_VPOS 0x038
529
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]530#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
531#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
532#define CMD_COMPRESSION_MODE_CTRL 0x2A8
533#define CMD_COMPRESSION_MODE_CTRL_2 0x2Ac
534#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
535
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]536#define QPNP_LED_CTRL_BASE 0xD000
537#define QPNP_BLUE_LPG_CTRL_BASE 0xB100
538#define QPNP_GREEN_LPG_CTRL_BASE 0xB200
539#define QPNP_RED_LPG_CTRL_BASE 0xB300
540
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700[diff] [blame]541#define APSS_WDOG_BASE 0x9830000
542#define APPS_WDOG_BARK_VAL_REG (APSS_WDOG_BASE + 0x10)
543#define APPS_WDOG_BITE_VAL_REG (APSS_WDOG_BASE + 0x14)
544#define APPS_WDOG_RESET_REG (APSS_WDOG_BASE + 0x04)
545#define APPS_WDOG_CTL_REG (APSS_WDOG_BASE + 0x08)
546
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]547#endif