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Channagoud Kadabie86a40b2014-03-12 17:48:51 -07001/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MMC_SDHCI_H__
30#define __MMC_SDHCI_H__
31
32#include <sdhci.h>
33
34/* Emmc Card bus commands */
35#define CMD0_GO_IDLE_STATE 0
36#define CMD1_SEND_OP_COND 1
37#define CMD2_ALL_SEND_CID 2
38#define CMD3_SEND_RELATIVE_ADDR 3
39#define CMD4_SET_DSR 4
Channagoud Kadabi9e3c3b92013-06-18 18:32:32 -070040#define CMD5_SLEEP_AWAKE 5
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -070041#define CMD6_SWITCH_FUNC 6
42#define CMD7_SELECT_DESELECT_CARD 7
43#define CMD8_SEND_EXT_CSD 8
44#define CMD9_SEND_CSD 9
45#define CMD10_SEND_CID 10
46#define CMD12_STOP_TRANSMISSION 12
47#define CMD13_SEND_STATUS 13
48#define CMD15_GO_INACTIVE_STATUS 15
49#define CMD16_SET_BLOCKLEN 16
50#define CMD17_READ_SINGLE_BLOCK 17
51#define CMD18_READ_MULTIPLE_BLOCK 18
Channagoud Kadabi9b8f8fc2013-07-26 12:02:49 -070052#define CMD21_SEND_TUNING_BLOCK 21
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -070053#define CMD23_SET_BLOCK_COUNT 23
54#define CMD24_WRITE_SINGLE_BLOCK 24
55#define CMD25_WRITE_MULTIPLE_BLOCK 25
56#define CMD28_SET_WRITE_PROTECT 28
57#define CMD29_CLEAR_WRITE_PROTECT 29
58#define CMD31_SEND_WRITE_PROT_TYPE 31
59#define CMD32_ERASE_WR_BLK_START 32
60#define CMD33_ERASE_WR_BLK_END 33
61#define CMD35_ERASE_GROUP_START 35
62#define CMD36_ERASE_GROUP_END 36
63#define CMD38_ERASE 38
64
65/* Card type */
66#define MMC_TYPE_STD_SD 0
67#define MMC_TYPE_SDHC 1
68#define MMC_TYPE_SDIO 2
69#define MMC_TYPE_MMCHC 3
70#define MMC_TYPE_STD_MMC 4
71
72/* OCR Register */
73#define MMC_OCR_17_19 (1 << 7)
74#define MMC_OCR_27_36 (0x1FF << 15)
75#define MMC_OCR_SEC_MODE (2 << 29)
76#define MMC_OCR_BUSY (1 << 31)
77
78/* Card status */
79#define MMC_CARD_STATUS(x) ((x >> 9) & 0x0F)
80#define MMC_TRAN_STATE 4
81#define MMC_PROG_STATE 7
82#define MMC_SWITCH_FUNC_ERR_FLAG (1 << 7)
83#define MMC_STATUS_INACTIVE 0
84#define MMC_STATUS_ACTIVE 1
Channagoud Kadabi003171e2013-05-29 15:21:12 -070085#define MMC_READY_FOR_DATA (1 << 8)
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -070086
87/* EXT_CSD */
88/* Offsets in the ext csd */
Channagoud Kadabifaf20f62014-10-21 22:22:37 -070089#define MMC_EXT_CSD_RST_N_FUNC 162
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -070090#define MMC_EXT_MMC_BUS_WIDTH 183
91#define MMC_EXT_MMC_HS_TIMING 185
92#define MMC_DEVICE_TYPE 196
Channagoud Kadabie106d1f2014-04-25 18:26:26 -070093#define MMC_EXT_MMC_DRV_STRENGTH 197
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -070094#define MMC_EXT_HC_WP_GRP_SIZE 221
95#define MMC_SEC_COUNT4 215
96#define MMC_SEC_COUNT3 214
97#define MMC_SEC_COUNT2 213
98#define MMC_SEC_COUNT1 212
99#define MMC_PART_CONFIG 179
100#define MMC_ERASE_GRP_DEF 175
101#define MMC_USR_WP 171
Channagoud Kadabie86a40b2014-03-12 17:48:51 -0700102#define MMC_ERASE_TIMEOUT_MULT 223
Channagoud Kadabi003171e2013-05-29 15:21:12 -0700103#define MMC_HC_ERASE_GRP_SIZE 224
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700104
105/* Values for ext csd fields */
106#define MMC_HS_TIMING 0x1
107#define MMC_HS200_TIMING 0x2
Channagoud Kadabi9b8f8fc2013-07-26 12:02:49 -0700108#define MMC_HS400_TIMING 0x3
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700109#define MMC_ACCESS_WRITE 0x3
Channagoud Kadabi003171e2013-05-29 15:21:12 -0700110#define MMC_SET_BIT 0x1
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700111#define MMC_HS_DDR_MODE (BIT(2) | BIT(3))
112#define MMC_HS_HS200_MODE (BIT(4) | BIT(5))
Channagoud Kadabi9b8f8fc2013-07-26 12:02:49 -0700113#define MMC_HS_HS400_MODE (BIT(6) | BIT(7))
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700114#define MMC_SEC_COUNT4_SHIFT 24
115#define MMC_SEC_COUNT3_SHIFT 16
116#define MMC_SEC_COUNT2_SHIFT 8
Channagoud Kadabi003171e2013-05-29 15:21:12 -0700117#define MMC_HC_ERASE_MULT (512 * 1024)
Channagoud Kadabifaf20f62014-10-21 22:22:37 -0700118#define RST_N_FUNC_ENABLE BIT(0)
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700119
120/* Command related */
121#define MMC_MAX_COMMAND_RETRY 1000
Channagoud Kadabi003171e2013-05-29 15:21:12 -0700122#define MMC_MAX_CARD_STAT_RETRY 10000
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700123#define MMC_RD_BLOCK_LEN 512
124#define MMC_WR_BLOCK_LEN 512
Channagoud Kadabi003171e2013-05-29 15:21:12 -0700125#define MMC_R1_WP_ERASE_SKIP BIT(15)
126#define MMC_US_PERM_WP_DIS BIT(4)
127#define MMC_US_PWR_WP_DIS BIT(3)
128#define MMC_US_PERM_WP_EN BIT(2)
129#define MMC_US_PWR_WP_EN BIT(0)
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700130
Channagoud Kadabi14fd2052013-10-17 18:00:50 -0700131/* MMC errors */
132#define MMC_R1_BLOCK_LEN_ERR (1 << 29)
133#define MMC_R1_ADDR_ERR (1 << 30)
134#define MMC_R1_GENERIC_ERR (1 << 19)
135#define MMC_R1_CC_ERROR (1 << 20)
136#define MMC_R1_WP_VIOLATION (1 << 26)
137#define MMC_R1_ADDR_OUT_OF_RANGE (1 << 31)
138
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700139/* RCA of the card */
140#define MMC_RCA 2
Channagoud Kadabi9e3c3b92013-06-18 18:32:32 -0700141#define MMC_CARD_RCA_BIT 16
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700142
143/* Misc card macros */
144#define MMC_BLK_SZ 512
Channagoud Kadabi9e3c3b92013-06-18 18:32:32 -0700145#define MMC_CARD_SLEEP (1 << 15)
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700146
147/* Clock rates */
148#define MMC_CLK_400KHZ 400000
149#define MMC_CLK_144KHZ 144000
150#define MMC_CLK_20MHZ 20000000
151#define MMC_CLK_25MHZ 25000000
152#define MMC_CLK_48MHZ 48000000
153#define MMC_CLK_50MHZ 49152000
154#define MMC_CLK_96MHZ 96000000
Aparna Mallavarapu20282d12014-02-27 21:48:27 -0800155#define MMC_CLK_177MHZ 177770000
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700156#define MMC_CLK_200MHZ 200000000
Channagoud Kadabi9b8f8fc2013-07-26 12:02:49 -0700157#define MMC_CLK_192MHZ 192000000
158#define MMC_CLK_400MHZ 400000000
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700159
Channagoud Kadabi003171e2013-05-29 15:21:12 -0700160#define MMC_ADDR_OUT_OF_RANGE(resp) ((resp >> 31) & 0x01)
161
Channagoud Kadabi4d13b2c2013-06-18 12:43:29 -0700162/* SD card related Macros */
163/* Arguments for commands */
164#define MMC_SD_HC_VOLT_SUPPLIED 0x000001AA
165#define MMC_SD_OCR 0x00FF8000
166#define MMC_SD_HC_HCS 0x40000000
167#define MMC_SD_DEV_READY 0x80000000
168#define MMC_CARD_TYPE_SDHC 0x1
169#define MMC_CARD_TYPE_STD_SD 0x0
170#define SD_CARD_RCA 0x0
171#define MMC_SD_SWITCH_HS 0x80FFFFF1
172
173#define SD_CMD8_MAX_RETRY 0x3
174#define SD_ACMD41_MAX_RETRY 0x14
175
176/* SCR(SD Card Register) related */
177#define SD_SCR_BUS_WIDTH 16
178#define SD_SCR_SD_SPEC 24
179#define SD_SCR_SD_SPEC3 15
180#define SD_SCR_BUS_WIDTH_MASK 0xf0000
181#define SD_SCR_SD_SPEC_MASK 0x0f000000
182#define SD_SCR_SD_SPEC3_MASK 0x8000
183#define SD_SCR_CMD23_SUPPORT BIT(1)
184#define SD_SCR_WIDTH_4BIT BIT(2)
185
186/* SSR related macros */
187#define MMC_SD_AU_SIZE_BIT 428
188#define MMC_SD_AU_SIZE_LEN 4
189#define MMC_SD_ERASE_SIZE_BIT 408
190#define MMC_SD_ERASE_SIZE_LEN 16
191
192/* Commands for SD card */
193#define CMD8_SEND_IF_COND 8
194#define ACMD6_SET_BUS_WIDTH 6
195#define ACMD13_SEND_SD_STATUS 13
196#define ACMD41_SEND_OP_COND 41
197#define ACMD51_READ_CARD_SCR 51
198#define CMD55_APP_CMD 55
199
Channagoud Kadabi9b8f8fc2013-07-26 12:02:49 -0700200#define MMC_SAVE_TIMING(host, TIMING) host->timing = TIMING
201
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700202/* Can be used to unpack array of upto 32 bits data */
203#define UNPACK_BITS(array, start, len, size_of) \
204 ({ \
205 uint32_t indx = (start) / (size_of); \
206 uint32_t offset = (start) % (size_of); \
207 uint32_t mask = (((len)<(size_of))? 1<<(len):0) - 1; \
208 uint32_t unpck = array[indx] >> offset; \
209 uint32_t indx2 = ((start) + (len) - 1) / (size_of); \
210 if(indx2 > indx) \
211 unpck |= array[indx2] << ((size_of) - offset); \
212 unpck & mask; \
213 })
214
Channagoud Kadabi4d13b2c2013-06-18 12:43:29 -0700215#define swap_endian32(x) \
216 ((uint32_t)( \
217 (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
218 (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \
219 (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \
220 (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24) ))
221
222
223#define MMC_CARD_SD(card) ((card->type == MMC_CARD_TYPE_SDHC) || \
224 (card->type == MMC_CARD_TYPE_STD_SD))
225
226#define MMC_CARD_MMC(card) ((card->type == MMC_TYPE_STD_MMC) || \
227 (card->type == MMC_TYPE_MMCHC))
228
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700229/* CSD Register.
230 * Note: not all the fields have been defined here
231 */
232struct mmc_csd {
233 uint32_t cmmc_structure;
234 uint32_t spec_vers;
235 uint32_t card_cmd_class;
236 uint32_t write_blk_len;
237 uint32_t read_blk_len;
238 uint32_t r2w_factor;
239 uint32_t sector_size;
240 uint32_t c_size_mult;
241 uint32_t c_size;
242 uint32_t nsac_clk_cycle;
243 uint32_t taac_ns;
244 uint32_t tran_speed;
245 uint32_t erase_grp_size;
246 uint32_t erase_grp_mult;
247 uint32_t wp_grp_size;
248 uint32_t wp_grp_enable:1;
249 uint32_t perm_wp:1;
250 uint32_t temp_wp:1;
251 uint32_t erase_blk_len:1;
252 uint32_t read_blk_misalign:1;
253 uint32_t write_blk_misalign:1;
254 uint32_t read_blk_partial:1;
255 uint32_t write_blk_partial:1;
256};
257
258/* CID Register */
259struct mmc_cid {
260 uint32_t mid; /* 8 bit manufacturer id */
261 uint32_t oid; /* 16 bits 2 character ASCII - OEM ID */
262 uint8_t pnm[7]; /* 6 character ASCII - product name */
263 uint32_t prv; /* 8 bits - product revision */
264 uint32_t psn; /* 32 bits - product serial number */
265 uint32_t month; /* 4 bits manufacturing month */
266 uint32_t year; /* 4 bits manufacturing year */
267};
268
Channagoud Kadabi4d13b2c2013-06-18 12:43:29 -0700269/* SCR register for SD card */
270struct mmc_sd_scr {
271 uint32_t bus_widths; /* Bus width support, 8 or 1 bit */
272 uint32_t sd_spec; /* sd spec version */
273 uint32_t sd3_spec; /* sd spec 3 version */
274 uint32_t cmd23_support; /* cmd23 supported or not */
275};
276
277/* SD Status Register */
278struct mmc_sd_ssr {
279 uint32_t au_size; /* Allocation unit (AU) size */
280 uint32_t num_aus; /* Number of AUs */
281};
282
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700283/* mmc card register */
284struct mmc_card {
285 uint32_t rca; /* Relative addres of the card*/
286 uint32_t ocr; /* Operating range of the card*/
Channagoud Kadabi96c629e2013-09-10 14:21:30 -0700287 uint32_t block_size; /* Block size for the card */
vijay kumar697dbfd2014-04-24 17:12:49 +0530288 uint32_t wp_grp_size; /* WP group size for the card */
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700289 uint64_t capacity; /* card capacity */
290 uint32_t type; /* Type of the card */
291 uint32_t status; /* Card status */
292 uint8_t *ext_csd; /* Ext CSD for the card info */
293 uint32_t raw_csd[4]; /* Raw CSD for the card */
Channagoud Kadabi4d13b2c2013-06-18 12:43:29 -0700294 uint32_t raw_scr[2]; /* SCR for SD card */
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700295 struct mmc_cid cid; /* CID structure */
296 struct mmc_csd csd; /* CSD structure */
Channagoud Kadabi4d13b2c2013-06-18 12:43:29 -0700297 struct mmc_sd_scr scr; /* SCR structure */
298 struct mmc_sd_ssr ssr; /* SSR Register */
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700299};
300
301/* mmc device config data */
302struct mmc_config_data {
303 uint8_t slot; /* Sdcc slot used */
Channagoud Kadabi4b2f9672013-08-08 17:44:03 -0700304 uint32_t pwr_irq; /* Power Irq from card to host */
Channagoud Kadabi4d13b2c2013-06-18 12:43:29 -0700305 uint32_t sdhc_base; /* Base address for the sdhc */
306 uint32_t pwrctl_base; /* Base address for power control registers */
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700307 uint16_t bus_width; /* Bus width used */
308 uint32_t max_clk_rate; /* Max clock rate supported */
Aparna Mallavarapue1cdd302014-03-07 07:12:44 +0530309 uint8_t hs400_support; /* SDHC HS400 mode supported or not */
Channagoud Kadabi17e69972014-10-13 11:42:24 -0700310 uint8_t use_io_switch; /* IO pad switch flag for shared sdc controller */
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700311};
312
313/* mmc device structure */
314struct mmc_device {
315 struct sdhci_host host; /* Handle to host controller */
316 struct mmc_card card; /* Handle to mmc card */
317 struct mmc_config_data config; /* Handle for the mmc config data */
318};
319
320/*
321 * APIS exposed to block level driver
322 */
323/* API: Initialize the mmc card */
324struct mmc_device *mmc_init(struct mmc_config_data *);
325/* API: Read required number of blocks from card into destination */
326uint32_t mmc_sdhci_read(struct mmc_device *dev, void *dest, uint64_t blk_addr, uint32_t num_blocks);
327/* API: Write requried number of blocks from source to card */
328uint32_t mmc_sdhci_write(struct mmc_device *dev, void *src, uint64_t blk_addr, uint32_t num_blocks);
Channagoud Kadabi003171e2013-05-29 15:21:12 -0700329/* API: Erase len bytes (after converting to number of erase groups), from specified address */
330uint32_t mmc_sdhci_erase(struct mmc_device *dev, uint32_t blk_addr, uint64_t len);
331/* API: Write protect or release len bytes (after converting to number of write protect groups) from specified start address*/
332uint32_t mmc_set_clr_power_on_wp_user(struct mmc_device *dev, uint32_t addr, uint64_t len, uint8_t set_clr);
333/* API: Get the WP status of write protect groups starting at addr */
334uint32_t mmc_get_wp_status(struct mmc_device *dev, uint32_t addr, uint8_t *wp_status);
Channagoud Kadabi9e3c3b92013-06-18 18:32:32 -0700335/* API: Put the mmc card in sleep mode */
336void mmc_put_card_to_sleep(struct mmc_device *dev);
Channagoud Kadabie106d1f2014-04-25 18:26:26 -0700337/* API: Change the driver type of the card */
338bool mmc_set_drv_type(struct sdhci_host *host, struct mmc_card *card, uint8_t drv_type);
Channagoud Kadabiec0f7f72013-03-11 15:21:36 -0700339#endif