Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | #include <platform.h> |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define gpll4_source_val 2 |
| 43 | #define cxo_mm_source_val 0 |
Padmanabhan Komanduru | 2655ea6 | 2015-06-08 12:23:32 +0530 | [diff] [blame] | 44 | #define gpll0_mm_source_val 6 |
| 45 | #define gpll6_mm_source_val 3 |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 46 | |
| 47 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 48 | |
| 49 | |
| 50 | /* Clock Operations */ |
| 51 | static struct clk_ops clk_ops_branch = |
| 52 | { |
| 53 | .enable = clock_lib2_branch_clk_enable, |
| 54 | .disable = clock_lib2_branch_clk_disable, |
| 55 | .set_rate = clock_lib2_branch_set_rate, |
| 56 | }; |
| 57 | |
| 58 | static struct clk_ops clk_ops_rcg_mnd = |
| 59 | { |
| 60 | .enable = clock_lib2_rcg_enable, |
| 61 | .set_rate = clock_lib2_rcg_set_rate, |
| 62 | }; |
| 63 | |
| 64 | static struct clk_ops clk_ops_rcg = |
| 65 | { |
| 66 | .enable = clock_lib2_rcg_enable, |
| 67 | .set_rate = clock_lib2_rcg_set_rate, |
| 68 | }; |
| 69 | |
| 70 | static struct clk_ops clk_ops_cxo = |
| 71 | { |
| 72 | .enable = cxo_clk_enable, |
| 73 | .disable = cxo_clk_disable, |
| 74 | }; |
| 75 | |
| 76 | static struct clk_ops clk_ops_pll_vote = |
| 77 | { |
| 78 | .enable = pll_vote_clk_enable, |
| 79 | .disable = pll_vote_clk_disable, |
| 80 | .auto_off = pll_vote_clk_disable, |
| 81 | .is_enabled = pll_vote_clk_is_enabled, |
| 82 | }; |
| 83 | |
| 84 | static struct clk_ops clk_ops_vote = |
| 85 | { |
| 86 | .enable = clock_lib2_vote_clk_enable, |
| 87 | .disable = clock_lib2_vote_clk_disable, |
| 88 | }; |
| 89 | |
| 90 | /* Clock Sources */ |
| 91 | static struct fixed_clk cxo_clk_src = |
| 92 | { |
| 93 | .c = { |
| 94 | .rate = 19200000, |
| 95 | .dbg_name = "cxo_clk_src", |
| 96 | .ops = &clk_ops_cxo, |
| 97 | }, |
| 98 | }; |
| 99 | |
| 100 | static struct pll_vote_clk gpll0_clk_src = |
| 101 | { |
| 102 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 103 | .en_mask = BIT(0), |
| 104 | .status_reg = (void *) GPLL0_STATUS, |
| 105 | .status_mask = BIT(17), |
| 106 | .parent = &cxo_clk_src.c, |
| 107 | |
| 108 | .c = { |
| 109 | .rate = 800000000, |
| 110 | .dbg_name = "gpll0_clk_src", |
| 111 | .ops = &clk_ops_pll_vote, |
| 112 | }, |
| 113 | }; |
| 114 | |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 115 | static struct pll_vote_clk gpll4_clk_src = |
| 116 | { |
| 117 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 118 | .en_mask = BIT(5), |
| 119 | .status_reg = (void *) GPLL4_MODE, |
| 120 | .status_mask = BIT(30), |
| 121 | .parent = &cxo_clk_src.c, |
| 122 | |
| 123 | .c = { |
| 124 | .rate = 1152000000, |
| 125 | .dbg_name = "gpll4_clk_src", |
| 126 | .ops = &clk_ops_pll_vote, |
| 127 | }, |
| 128 | }; |
| 129 | |
Padmanabhan Komanduru | 2655ea6 | 2015-06-08 12:23:32 +0530 | [diff] [blame] | 130 | static struct pll_vote_clk gpll6_clk_src = |
| 131 | { |
| 132 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 133 | .en_mask = BIT(7), |
| 134 | .status_reg = (void *) GPLL6_STATUS, |
| 135 | .status_mask = BIT(17), |
| 136 | .parent = &cxo_clk_src.c, |
| 137 | |
| 138 | .c = { |
| 139 | .rate = 1080000000, |
| 140 | .dbg_name = "gpll6_clk_src", |
| 141 | .ops = &clk_ops_pll_vote, |
| 142 | }, |
| 143 | }; |
| 144 | |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 145 | /* SDCC Clocks */ |
| 146 | static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = |
| 147 | { |
| 148 | F( 144000, cxo, 16, 3, 25), |
| 149 | F( 400000, cxo, 12, 1, 4), |
| 150 | F( 20000000, gpll0, 10, 1, 4), |
| 151 | F( 25000000, gpll0, 16, 1, 2), |
| 152 | F( 50000000, gpll0, 16, 0, 0), |
| 153 | F(100000000, gpll0, 8, 0, 0), |
| 154 | F(177770000, gpll0, 4.5, 0, 0), |
Aparna Mallavarapu | f47a868 | 2015-04-20 13:22:08 +0530 | [diff] [blame] | 155 | F(192000000, gpll4, 6, 0, 0), |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 156 | F(384000000, gpll4, 3, 0, 0), |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 157 | F_END |
| 158 | }; |
| 159 | |
| 160 | static struct rcg_clk sdcc1_apps_clk_src = |
| 161 | { |
| 162 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 163 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 164 | .m_reg = (uint32_t *) SDCC1_M, |
| 165 | .n_reg = (uint32_t *) SDCC1_N, |
| 166 | .d_reg = (uint32_t *) SDCC1_D, |
| 167 | |
| 168 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 169 | .freq_tbl = ftbl_gcc_sdcc1_apps_clk, |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 170 | .current_freq = &rcg_dummy_freq, |
| 171 | |
| 172 | .c = { |
| 173 | .dbg_name = "sdc1_clk", |
| 174 | .ops = &clk_ops_rcg_mnd, |
| 175 | }, |
| 176 | }; |
| 177 | |
| 178 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 179 | { |
| 180 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 181 | .parent = &sdcc1_apps_clk_src.c, |
| 182 | |
| 183 | .c = { |
| 184 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 185 | .ops = &clk_ops_branch, |
| 186 | }, |
| 187 | }; |
| 188 | |
| 189 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 190 | { |
| 191 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 192 | .has_sibling = 1, |
| 193 | |
| 194 | .c = { |
| 195 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 196 | .ops = &clk_ops_branch, |
| 197 | }, |
| 198 | }; |
| 199 | |
| 200 | static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = |
| 201 | { |
| 202 | F( 144000, cxo, 16, 3, 25), |
| 203 | F( 400000, cxo, 12, 1, 4), |
| 204 | F( 20000000, gpll0, 10, 1, 4), |
| 205 | F( 25000000, gpll0, 16, 1, 2), |
| 206 | F( 50000000, gpll0, 16, 0, 0), |
| 207 | F(100000000, gpll0, 8, 0, 0), |
| 208 | F(177770000, gpll0, 4.5, 0, 0), |
| 209 | F(200000000, gpll0, 4, 0, 0), |
| 210 | F_END |
| 211 | }; |
| 212 | |
| 213 | static struct rcg_clk sdcc2_apps_clk_src = |
| 214 | { |
| 215 | .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR, |
| 216 | .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR, |
| 217 | .m_reg = (uint32_t *) SDCC2_M, |
| 218 | .n_reg = (uint32_t *) SDCC2_N, |
| 219 | .d_reg = (uint32_t *) SDCC2_D, |
| 220 | |
| 221 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 222 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk, |
| 223 | .current_freq = &rcg_dummy_freq, |
| 224 | |
| 225 | .c = { |
| 226 | .dbg_name = "sdc2_clk", |
| 227 | .ops = &clk_ops_rcg_mnd, |
| 228 | }, |
| 229 | }; |
| 230 | |
| 231 | static struct branch_clk gcc_sdcc2_apps_clk = |
| 232 | { |
| 233 | .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR, |
| 234 | .parent = &sdcc2_apps_clk_src.c, |
| 235 | |
| 236 | .c = { |
| 237 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 238 | .ops = &clk_ops_branch, |
| 239 | }, |
| 240 | }; |
| 241 | |
| 242 | static struct branch_clk gcc_sdcc2_ahb_clk = |
| 243 | { |
| 244 | .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR, |
| 245 | .has_sibling = 1, |
| 246 | |
| 247 | .c = { |
| 248 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 249 | .ops = &clk_ops_branch, |
| 250 | }, |
| 251 | }; |
| 252 | |
| 253 | /* UART Clocks */ |
| 254 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = |
| 255 | { |
| 256 | F( 3686400, gpll0, 1, 72, 15625), |
| 257 | F( 7372800, gpll0, 1, 144, 15625), |
| 258 | F(14745600, gpll0, 1, 288, 15625), |
| 259 | F(16000000, gpll0, 10, 1, 5), |
| 260 | F(19200000, cxo, 1, 0, 0), |
| 261 | F(24000000, gpll0, 1, 3, 100), |
| 262 | F(25000000, gpll0, 16, 1, 2), |
| 263 | F(32000000, gpll0, 1, 1, 25), |
| 264 | F(40000000, gpll0, 1, 1, 20), |
| 265 | F(46400000, gpll0, 1, 29, 500), |
| 266 | F(48000000, gpll0, 1, 3, 50), |
| 267 | F(51200000, gpll0, 1, 8, 125), |
| 268 | F(56000000, gpll0, 1, 7, 100), |
| 269 | F(58982400, gpll0, 1,1152, 15625), |
| 270 | F(60000000, gpll0, 1, 3, 40), |
| 271 | F_END |
| 272 | }; |
| 273 | |
| 274 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 275 | { |
| 276 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 277 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 278 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 279 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 280 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 281 | |
| 282 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 283 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk, |
| 284 | .current_freq = &rcg_dummy_freq, |
| 285 | |
| 286 | .c = { |
| 287 | .dbg_name = "blsp1_uart2_apps_clk", |
| 288 | .ops = &clk_ops_rcg_mnd, |
| 289 | }, |
| 290 | }; |
| 291 | |
| 292 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 293 | { |
| 294 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 295 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 296 | |
| 297 | .c = { |
| 298 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 299 | .ops = &clk_ops_branch, |
| 300 | }, |
| 301 | }; |
| 302 | |
| 303 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 304 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 305 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 306 | .en_mask = BIT(10), |
| 307 | |
| 308 | .c = { |
| 309 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 310 | .ops = &clk_ops_vote, |
| 311 | }, |
| 312 | }; |
| 313 | |
| 314 | /* USB Clocks */ |
| 315 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 316 | { |
Aparna Mallavarapu | bbec463 | 2015-05-27 17:48:01 +0530 | [diff] [blame] | 317 | F(100000000, gpll0, 10, 0, 0), |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 318 | F(133330000, gpll0, 6, 0, 0), |
| 319 | F_END |
| 320 | }; |
| 321 | |
| 322 | static struct rcg_clk usb_hs_system_clk_src = |
| 323 | { |
| 324 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 325 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 326 | |
| 327 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 328 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 329 | .current_freq = &rcg_dummy_freq, |
| 330 | |
| 331 | .c = { |
| 332 | .dbg_name = "usb_hs_system_clk", |
| 333 | .ops = &clk_ops_rcg, |
| 334 | }, |
| 335 | }; |
| 336 | |
| 337 | static struct branch_clk gcc_usb_hs_system_clk = |
| 338 | { |
| 339 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 340 | .parent = &usb_hs_system_clk_src.c, |
| 341 | |
| 342 | .c = { |
| 343 | .dbg_name = "gcc_usb_hs_system_clk", |
| 344 | .ops = &clk_ops_branch, |
| 345 | }, |
| 346 | }; |
| 347 | |
| 348 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 349 | { |
| 350 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 351 | .has_sibling = 1, |
| 352 | |
| 353 | .c = { |
| 354 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 355 | .ops = &clk_ops_branch, |
| 356 | }, |
| 357 | }; |
| 358 | |
Padmanabhan Komanduru | fba6632 | 2015-04-13 12:47:31 -0700 | [diff] [blame] | 359 | /* Display clocks */ |
| 360 | static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = { |
| 361 | F_MM(19200000, cxo, 1, 0, 0), |
| 362 | F_END |
| 363 | }; |
| 364 | |
Padmanabhan Komanduru | 2655ea6 | 2015-06-08 12:23:32 +0530 | [diff] [blame] | 365 | static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = { |
| 366 | F_MM(19200000, cxo, 1, 0, 0), |
| 367 | F_END |
| 368 | }; |
| 369 | |
Padmanabhan Komanduru | fba6632 | 2015-04-13 12:47:31 -0700 | [diff] [blame] | 370 | static struct clk_freq_tbl ftbl_mdp_clk[] = { |
Padmanabhan Komanduru | 2655ea6 | 2015-06-08 12:23:32 +0530 | [diff] [blame] | 371 | F( 80000000, gpll0, 10, 0, 0), |
| 372 | F( 100000000, gpll0, 8, 0, 0), |
| 373 | F( 200000000, gpll0, 4, 0, 0), |
| 374 | F( 320000000, gpll0, 2.5, 0, 0), |
| 375 | F_END |
| 376 | }; |
| 377 | |
| 378 | static struct clk_freq_tbl ftbl_mdp_clk_8956[] = { |
| 379 | F_MM( 50000000, gpll0, 16, 0, 0), |
| 380 | F_MM( 80000000, gpll0, 10, 0, 0), |
| 381 | F_MM( 100000000, gpll0, 8, 0, 0), |
| 382 | F_MM( 145454545, gpll0, 5.5, 0, 0), |
| 383 | F_MM( 160000000, gpll0, 5, 0, 0), |
| 384 | F_MM( 177777778, gpll0, 4.5, 0, 0), |
| 385 | F_MM( 200000000, gpll0, 4, 0, 0), |
| 386 | F_MM( 270000000, gpll6, 4, 0, 0), |
| 387 | F_MM( 320000000, gpll0, 2.5, 0, 0), |
| 388 | F_MM( 360000000, gpll6, 3, 0, 0), |
Padmanabhan Komanduru | fba6632 | 2015-04-13 12:47:31 -0700 | [diff] [blame] | 389 | F_END |
| 390 | }; |
| 391 | |
| 392 | static struct rcg_clk dsi_esc0_clk_src = { |
| 393 | .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR, |
| 394 | .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR, |
| 395 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 396 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
| 397 | |
| 398 | .c = { |
| 399 | .dbg_name = "dsi_esc0_clk_src", |
| 400 | .ops = &clk_ops_rcg, |
| 401 | }, |
| 402 | }; |
| 403 | |
Padmanabhan Komanduru | 2655ea6 | 2015-06-08 12:23:32 +0530 | [diff] [blame] | 404 | static struct rcg_clk dsi_esc1_clk_src = { |
| 405 | .cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR, |
| 406 | .cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR, |
| 407 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 408 | .freq_tbl = ftbl_mdss_esc1_1_clk, |
| 409 | |
| 410 | .c = { |
| 411 | .dbg_name = "dsi_esc1_clk_src", |
| 412 | .ops = &clk_ops_rcg, |
| 413 | }, |
| 414 | }; |
| 415 | |
Padmanabhan Komanduru | fba6632 | 2015-04-13 12:47:31 -0700 | [diff] [blame] | 416 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 417 | F_MM(19200000, cxo, 1, 0, 0), |
| 418 | F_END |
| 419 | }; |
| 420 | |
| 421 | static struct rcg_clk vsync_clk_src = { |
| 422 | .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR, |
| 423 | .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR, |
| 424 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 425 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 426 | |
| 427 | .c = { |
| 428 | .dbg_name = "vsync_clk_src", |
| 429 | .ops = &clk_ops_rcg, |
| 430 | }, |
| 431 | }; |
| 432 | |
| 433 | static struct branch_clk mdss_esc0_clk = { |
| 434 | .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR, |
| 435 | .parent = &dsi_esc0_clk_src.c, |
| 436 | .has_sibling = 0, |
| 437 | |
| 438 | .c = { |
| 439 | .dbg_name = "mdss_esc0_clk", |
| 440 | .ops = &clk_ops_branch, |
| 441 | }, |
| 442 | }; |
| 443 | |
Padmanabhan Komanduru | 2655ea6 | 2015-06-08 12:23:32 +0530 | [diff] [blame] | 444 | static struct branch_clk mdss_esc1_clk = { |
| 445 | .cbcr_reg = (uint32_t *) DSI_ESC1_CBCR, |
| 446 | .parent = &dsi_esc1_clk_src.c, |
| 447 | .has_sibling = 0, |
| 448 | |
| 449 | .c = { |
| 450 | .dbg_name = "mdss_esc1_clk", |
| 451 | .ops = &clk_ops_branch, |
| 452 | }, |
| 453 | }; |
| 454 | |
Padmanabhan Komanduru | fba6632 | 2015-04-13 12:47:31 -0700 | [diff] [blame] | 455 | static struct branch_clk mdss_axi_clk = { |
| 456 | .cbcr_reg = (uint32_t *) MDP_AXI_CBCR, |
| 457 | .has_sibling = 1, |
| 458 | |
| 459 | .c = { |
| 460 | .dbg_name = "mdss_axi_clk", |
| 461 | .ops = &clk_ops_branch, |
| 462 | }, |
| 463 | }; |
| 464 | |
| 465 | static struct branch_clk mdp_ahb_clk = { |
| 466 | .cbcr_reg = (uint32_t *) MDP_AHB_CBCR, |
| 467 | .has_sibling = 1, |
| 468 | |
| 469 | .c = { |
| 470 | .dbg_name = "mdp_ahb_clk", |
| 471 | .ops = &clk_ops_branch, |
| 472 | }, |
| 473 | }; |
| 474 | |
| 475 | static struct rcg_clk mdss_mdp_clk_src = { |
| 476 | .cmd_reg = (uint32_t *) MDP_CMD_RCGR, |
| 477 | .cfg_reg = (uint32_t *) MDP_CFG_RCGR, |
| 478 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 479 | .freq_tbl = ftbl_mdp_clk, |
| 480 | .current_freq = &rcg_dummy_freq, |
| 481 | |
| 482 | .c = { |
| 483 | .dbg_name = "mdss_mdp_clk_src", |
| 484 | .ops = &clk_ops_rcg, |
| 485 | }, |
| 486 | }; |
| 487 | |
| 488 | static struct branch_clk mdss_mdp_clk = { |
| 489 | .cbcr_reg = (uint32_t *) MDP_CBCR, |
| 490 | .parent = &mdss_mdp_clk_src.c, |
| 491 | .has_sibling = 0, |
| 492 | |
| 493 | .c = { |
| 494 | .dbg_name = "mdss_mdp_clk", |
| 495 | .ops = &clk_ops_branch, |
| 496 | }, |
| 497 | }; |
| 498 | |
| 499 | static struct branch_clk mdss_vsync_clk = { |
| 500 | .cbcr_reg = (uint32_t *) MDSS_VSYNC_CBCR, |
| 501 | .parent = &vsync_clk_src.c, |
| 502 | .has_sibling = 0, |
| 503 | |
| 504 | .c = { |
| 505 | .dbg_name = "mdss_vsync_clk", |
| 506 | .ops = &clk_ops_branch, |
| 507 | }, |
| 508 | }; |
| 509 | |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 510 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 511 | F(160000000, gpll0, 5, 0, 0), |
| 512 | F_END |
| 513 | }; |
| 514 | |
| 515 | static struct rcg_clk ce1_clk_src = { |
| 516 | .cmd_reg = (uint32_t *) GCC_CRYPTO_CMD_RCGR, |
| 517 | .cfg_reg = (uint32_t *) GCC_CRYPTO_CFG_RCGR, |
| 518 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 519 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 520 | .current_freq = &rcg_dummy_freq, |
| 521 | |
| 522 | .c = { |
| 523 | .dbg_name = "ce1_clk_src", |
| 524 | .ops = &clk_ops_rcg, |
| 525 | }, |
| 526 | }; |
| 527 | |
| 528 | static struct vote_clk gcc_ce1_clk = { |
| 529 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_CBCR, |
| 530 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 531 | .en_mask = BIT(2), |
| 532 | |
| 533 | .c = { |
| 534 | .dbg_name = "gcc_ce1_clk", |
| 535 | .ops = &clk_ops_vote, |
| 536 | }, |
| 537 | }; |
| 538 | |
| 539 | static struct vote_clk gcc_ce1_ahb_clk = { |
| 540 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR, |
| 541 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 542 | .en_mask = BIT(0), |
| 543 | |
| 544 | .c = { |
| 545 | .dbg_name = "gcc_ce1_ahb_clk", |
| 546 | .ops = &clk_ops_vote, |
| 547 | }, |
| 548 | }; |
| 549 | |
| 550 | static struct vote_clk gcc_ce1_axi_clk = { |
| 551 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AXI_CBCR, |
| 552 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 553 | .en_mask = BIT(1), |
| 554 | |
| 555 | .c = { |
| 556 | .dbg_name = "gcc_ce1_axi_clk", |
| 557 | .ops = &clk_ops_vote, |
| 558 | }, |
| 559 | }; |
| 560 | |
| 561 | /* Clock lookup table */ |
| 562 | static struct clk_lookup msm_clocks_8952[] = |
| 563 | { |
| 564 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 565 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 566 | |
| 567 | CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c), |
| 568 | CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c), |
| 569 | |
| 570 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 571 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 572 | |
| 573 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 574 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
| 575 | |
Padmanabhan Komanduru | fba6632 | 2015-04-13 12:47:31 -0700 | [diff] [blame] | 576 | CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c), |
| 577 | CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c), |
Padmanabhan Komanduru | 2655ea6 | 2015-06-08 12:23:32 +0530 | [diff] [blame] | 578 | CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c), |
Padmanabhan Komanduru | fba6632 | 2015-04-13 12:47:31 -0700 | [diff] [blame] | 579 | CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c), |
| 580 | CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c), |
| 581 | CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c), |
| 582 | CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c), |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 583 | |
| 584 | CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c), |
| 585 | CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c), |
| 586 | CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c), |
| 587 | CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), |
| 588 | }; |
| 589 | |
Unnati Gandhi | 81b7706 | 2015-05-28 14:23:39 +0530 | [diff] [blame] | 590 | void msm8956_clock_override() |
| 591 | { |
| 592 | gpll4_clk_src.status_reg = (void *)GPLL4_STATUS; |
| 593 | gpll4_clk_src.status_mask = BIT(17); |
Padmanabhan Komanduru | 2655ea6 | 2015-06-08 12:23:32 +0530 | [diff] [blame] | 594 | mdss_mdp_clk_src.freq_tbl = ftbl_mdp_clk_8956; |
Unnati Gandhi | 81b7706 | 2015-05-28 14:23:39 +0530 | [diff] [blame] | 595 | } |
| 596 | |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 597 | void platform_clock_init(void) |
| 598 | { |
Unnati Gandhi | 81b7706 | 2015-05-28 14:23:39 +0530 | [diff] [blame] | 599 | if (platform_is_msm8956()) |
| 600 | msm8956_clock_override(); |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 601 | clk_init(msm_clocks_8952, ARRAY_SIZE(msm_clocks_8952)); |
| 602 | } |