blob: 2cde8ea62443729d6eafecd5094ab10b04f0cd65 [file] [log] [blame]
Jayant Shekhar3ecc0f82014-03-27 13:30:41 +05301/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +05302 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
Padmanabhan Komandurufa4be752012-10-08 16:51:56 +053012 * * Neither the name of The Linux Foundation, Inc. nor the names of its
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053013 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29#include <mdp3.h>
30#include <debug.h>
31#include <reg.h>
Channagoud Kadabi539ef722012-03-29 16:02:50 +053032#include <msm_panel.h>
33#include <err.h>
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053034#include <target/display.h>
35#include <platform/timer.h>
36#include <platform/iomap.h>
37
Shashank Mittal4bfb2e32012-04-16 10:56:27 -070038static int mdp_rev;
39
Channagoud Kadabi539ef722012-03-29 16:02:50 +053040int mdp_dsi_video_config(struct msm_panel_info *pinfo,
41 struct fbcon_config *fb)
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053042{
Ajay Dudanib01e5062011-12-03 23:23:42 -080043 unsigned long hsync_period;
44 unsigned long vsync_period;
45 unsigned long vsync_period_intmd;
Channagoud Kadabi539ef722012-03-29 16:02:50 +053046 struct lcdc_panel_info *lcdc = NULL;
47 int ystride = 3;
Terence Hampson7385f6a2013-08-16 15:31:25 -040048 int mdp_rev = mdp_get_revision();
Channagoud Kadabi539ef722012-03-29 16:02:50 +053049
50 if (pinfo == NULL)
51 return ERR_INVALID_ARGS;
52
53 lcdc = &(pinfo->lcdc);
54 if (lcdc == NULL)
55 return ERR_INVALID_ARGS;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053056
Ajay Dudanib01e5062011-12-03 23:23:42 -080057 dprintf(SPEW, "MDP3.0.3 for DSI Video Mode\n");
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053058
Channagoud Kadabi539ef722012-03-29 16:02:50 +053059 hsync_period = pinfo->xres + lcdc->h_front_porch + \
60 lcdc->h_back_porch + 1;
61 vsync_period_intmd = pinfo->yres + lcdc->v_front_porch + \
62 lcdc->v_back_porch + 1;
Terence Hampson7385f6a2013-08-16 15:31:25 -040063 if (mdp_rev == MDP_REV_304) {
64 hsync_period += lcdc->h_pulse_width - 1;
65 vsync_period_intmd += lcdc->v_pulse_width - 1;
66 }
Ajay Dudanib01e5062011-12-03 23:23:42 -080067 vsync_period = vsync_period_intmd * hsync_period;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053068
Ajay Dudanib01e5062011-12-03 23:23:42 -080069 // ------------- programming MDP_DMA_P_CONFIG ---------------------
70 writel(0x1800bf, MDP_DMA_P_CONFIG); // rgb888
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053071
Ajay Dudanib01e5062011-12-03 23:23:42 -080072 writel(0x00000000, MDP_DMA_P_OUT_XY);
Channagoud Kadabi539ef722012-03-29 16:02:50 +053073 writel(pinfo->yres << 16 | pinfo->xres, MDP_DMA_P_SIZE);
74 writel(MIPI_FB_ADDR, MDP_DMA_P_BUF_ADDR);
75 writel(pinfo->xres * ystride, MDP_DMA_P_BUF_Y_STRIDE);
76 writel(hsync_period << 16 | lcdc->h_pulse_width, \
77 MDP_DSI_VIDEO_HSYNC_CTL);
Ajay Dudanib01e5062011-12-03 23:23:42 -080078 writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
Channagoud Kadabi539ef722012-03-29 16:02:50 +053079 writel(lcdc->v_pulse_width * hsync_period, \
80 MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
Terence Hampson7385f6a2013-08-16 15:31:25 -040081 if (mdp_rev == MDP_REV_304) {
82 writel((pinfo->xres + lcdc->h_back_porch + \
83 lcdc->h_pulse_width - 1) << 16 | \
84 lcdc->h_back_porch + lcdc->h_pulse_width, \
85 MDP_DSI_VIDEO_DISPLAY_HCTL);
86 writel((lcdc->v_back_porch + lcdc->v_pulse_width) \
87 * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
88 writel(vsync_period - lcdc->v_front_porch * hsync_period - 1,
Ajay Dudanib01e5062011-12-03 23:23:42 -080089 MDP_DSI_VIDEO_DISPLAY_V_END);
Terence Hampson7385f6a2013-08-16 15:31:25 -040090 } else {
91 writel((pinfo->xres + lcdc->h_back_porch - 1) << 16 | \
92 lcdc->h_back_porch, MDP_DSI_VIDEO_DISPLAY_HCTL);
93 writel(lcdc->v_back_porch * hsync_period, \
94 MDP_DSI_VIDEO_DISPLAY_V_START);
95 writel((pinfo->yres + lcdc->v_back_porch) * hsync_period,
96 MDP_DSI_VIDEO_DISPLAY_V_END);
97 }
Ajay Dudanib01e5062011-12-03 23:23:42 -080098 writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
99 writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
100 writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
101 // end of cmd mdp
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530102
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530103 return 0;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530104}
Ajay Dudanib01e5062011-12-03 23:23:42 -0800105
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530106int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
107 struct fbcon_config *fb)
108{
109 int ret = 0;
110 unsigned short pack_pattern = 0x21;
111 unsigned char ystride = 3;
112
113 writel(0x03ffffff, MDP_INTR_ENABLE);
114
115 // ------------- programming MDP_DMA_P_CONFIG ---------------------
116 writel(pack_pattern << 8 | 0x3f | (0 << 25)| (1 << 19) | (1 << 7) , MDP_DMA_P_CONFIG); // rgb888
117 writel(0x00000000, MDP_DMA_P_OUT_XY);
118 writel(pinfo->yres << 16 | pinfo->xres, MDP_DMA_P_SIZE);
119 writel(MIPI_FB_ADDR, MDP_DMA_P_BUF_ADDR);
120
121 writel(pinfo->xres * ystride, MDP_DMA_P_BUF_Y_STRIDE);
122
123 writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
124 writel(0x11, MDP_DSI_CMD_MODE_TRIGGER_EN);
125 mdelay(10);
126
127 return ret;
128}
129
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530130void mdp_disable(void)
131{
Channagoud Kadabif2488462012-06-12 15:22:48 +0530132 if (!target_cont_splash_screen())
133 writel(0x00000000, MDP_DSI_VIDEO_EN);
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530134}
135
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530136int mdp_dsi_video_off(void)
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530137{
Channagoud Kadabif2488462012-06-12 15:22:48 +0530138 if (!target_cont_splash_screen()) {
139 mdp_disable();
140 mdelay(60);
Channagoud Kadabif2488462012-06-12 15:22:48 +0530141 }
Padmanabhan Komandurufa4be752012-10-08 16:51:56 +0530142 writel(0x00000000, MDP_INTR_ENABLE);
143 writel(0x01ffffff, MDP_INTR_CLEAR);
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530144 return NO_ERROR;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530145}
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700146
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530147int mdp_dsi_cmd_off(void)
148{
Channagoud Kadabif2488462012-06-12 15:22:48 +0530149 if (!target_cont_splash_screen()) {
150 mdp_dma_off();
151 /*
152 * Allow sometime for the DMA channel to
153 * stop the data transfer
154 */
155 mdelay(10);
Channagoud Kadabif2488462012-06-12 15:22:48 +0530156 }
Padmanabhan Komandurufa4be752012-10-08 16:51:56 +0530157 writel(0x00000000, MDP_INTR_ENABLE);
158 writel(0x01ffffff, MDP_INTR_CLEAR);
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530159 return NO_ERROR;
160}
161
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700162void mdp_set_revision(int rev)
163{
164 mdp_rev = rev;
165}
166
167int mdp_get_revision(void)
168{
169 return mdp_rev;
170}
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530171
Jayant Shekhar3ecc0f82014-03-27 13:30:41 +0530172int mdp_dsi_video_on(struct msm_panel_info *pinfo)
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530173{
174 int ret = 0;
175
176 writel(0x00000001, MDP_DSI_VIDEO_EN);
177
178 return ret;
179}
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530180
Jayant Shekhar3ecc0f82014-03-27 13:30:41 +0530181int mdp_dma_on(struct msm_panel_info *pinfo)
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530182{
183 int ret = 0;
Xiaoming Zhou8d534dd2013-07-29 15:49:19 -0400184 mdelay(100);
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530185 writel(0x00000001, MDP_DMA_P_START);
186
187 return ret;
188}
189
190int mdp_dma_off()
191{
192 int ret = 0;
193
Channagoud Kadabif2488462012-06-12 15:22:48 +0530194 if (!target_cont_splash_screen())
195 writel(0x00000000, MDP_DMA_P_START);
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530196
197 return ret;
198}
Asaf Penso6c58a6b2013-07-14 19:57:29 +0300199
200int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
201{
202 return NO_ERROR;
203}
204
Jayant Shekhar3ecc0f82014-03-27 13:30:41 +0530205int mdp_edp_on(struct msm_panel_info *pinfo)
Asaf Penso6c58a6b2013-07-14 19:57:29 +0300206{
207 return NO_ERROR;
208}
209
210int mdp_edp_off(void)
211{
212 return NO_ERROR;
213}