Baochu Xu | 6788fad | 2017-12-05 18:45:28 +0800 | [diff] [blame] | 1 | /* Copyright (c) 2014,2018, The Linux Foundation. All rights reserved. |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define cxo_mm_source_val 0 |
| 43 | #define gpll0_mm_source_val 1 |
Unnati Gandhi | f4cb662 | 2014-08-28 13:54:56 +0530 | [diff] [blame] | 44 | #define gpll1_mm_source_val 3 |
| 45 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 46 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 47 | |
| 48 | |
| 49 | /* Clock Operations */ |
| 50 | static struct clk_ops clk_ops_branch = |
| 51 | { |
| 52 | .enable = clock_lib2_branch_clk_enable, |
| 53 | .disable = clock_lib2_branch_clk_disable, |
| 54 | .set_rate = clock_lib2_branch_set_rate, |
| 55 | }; |
| 56 | |
| 57 | static struct clk_ops clk_ops_rcg_mnd = |
| 58 | { |
| 59 | .enable = clock_lib2_rcg_enable, |
| 60 | .set_rate = clock_lib2_rcg_set_rate, |
| 61 | }; |
| 62 | |
| 63 | static struct clk_ops clk_ops_rcg = |
| 64 | { |
| 65 | .enable = clock_lib2_rcg_enable, |
| 66 | .set_rate = clock_lib2_rcg_set_rate, |
| 67 | }; |
| 68 | |
| 69 | static struct clk_ops clk_ops_cxo = |
| 70 | { |
| 71 | .enable = cxo_clk_enable, |
| 72 | .disable = cxo_clk_disable, |
| 73 | }; |
| 74 | |
| 75 | static struct clk_ops clk_ops_pll_vote = |
| 76 | { |
| 77 | .enable = pll_vote_clk_enable, |
| 78 | .disable = pll_vote_clk_disable, |
| 79 | .auto_off = pll_vote_clk_disable, |
| 80 | .is_enabled = pll_vote_clk_is_enabled, |
| 81 | }; |
| 82 | |
| 83 | static struct clk_ops clk_ops_vote = |
| 84 | { |
| 85 | .enable = clock_lib2_vote_clk_enable, |
| 86 | .disable = clock_lib2_vote_clk_disable, |
| 87 | }; |
| 88 | |
| 89 | /* Clock Sources */ |
| 90 | static struct fixed_clk cxo_clk_src = |
| 91 | { |
| 92 | .c = { |
| 93 | .rate = 19200000, |
| 94 | .dbg_name = "cxo_clk_src", |
| 95 | .ops = &clk_ops_cxo, |
| 96 | }, |
| 97 | }; |
| 98 | |
| 99 | static struct pll_vote_clk gpll0_clk_src = |
| 100 | { |
| 101 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 102 | .en_mask = BIT(0), |
Aparna Mallavarapu | babab6d | 2014-10-16 14:32:40 -0700 | [diff] [blame] | 103 | .status_reg = (void *) GPLL0_MODE, |
| 104 | .status_mask = BIT(30), |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 105 | .parent = &cxo_clk_src.c, |
| 106 | |
| 107 | .c = { |
| 108 | .rate = 800000000, |
| 109 | .dbg_name = "gpll0_clk_src", |
| 110 | .ops = &clk_ops_pll_vote, |
| 111 | }, |
| 112 | }; |
| 113 | |
Unnati Gandhi | f4cb662 | 2014-08-28 13:54:56 +0530 | [diff] [blame] | 114 | static struct pll_vote_clk gpll1_clk_src = |
| 115 | { |
| 116 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 117 | .en_mask = BIT(1), |
| 118 | .status_reg = (void *) GPLL1_STATUS, |
| 119 | .status_mask = BIT(17), |
| 120 | .parent = &cxo_clk_src.c, |
| 121 | |
| 122 | .c = { |
| 123 | .rate = 614400000, |
| 124 | .dbg_name = "gpll1_clk_src", |
| 125 | .ops = &clk_ops_pll_vote, |
| 126 | }, |
| 127 | }; |
| 128 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 129 | /* SDCC Clocks */ |
| 130 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = |
| 131 | { |
| 132 | F( 144000, cxo, 16, 3, 25), |
| 133 | F( 400000, cxo, 12, 1, 4), |
| 134 | F( 20000000, gpll0, 10, 1, 4), |
| 135 | F( 25000000, gpll0, 16, 1, 2), |
| 136 | F( 50000000, gpll0, 16, 0, 0), |
| 137 | F(100000000, gpll0, 8, 0, 0), |
| 138 | F(177770000, gpll0, 4.5, 0, 0), |
| 139 | F(200000000, gpll0, 4, 0, 0), |
| 140 | F_END |
| 141 | }; |
| 142 | |
| 143 | static struct rcg_clk sdcc1_apps_clk_src = |
| 144 | { |
| 145 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 146 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 147 | .m_reg = (uint32_t *) SDCC1_M, |
| 148 | .n_reg = (uint32_t *) SDCC1_N, |
| 149 | .d_reg = (uint32_t *) SDCC1_D, |
| 150 | |
| 151 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 152 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 153 | .current_freq = &rcg_dummy_freq, |
| 154 | |
| 155 | .c = { |
| 156 | .dbg_name = "sdc1_clk", |
| 157 | .ops = &clk_ops_rcg_mnd, |
| 158 | }, |
| 159 | }; |
| 160 | |
| 161 | /* BLSP1_QUP2 Clocks */ |
| 162 | static struct clk_freq_tbl ftbl_gcc_blsp1_qup2_i2c_apps_clk_src[] = |
| 163 | { |
| 164 | F( 96000, cxo, 10, 1, 2), |
| 165 | F( 4800000, cxo, 4, 0, 0), |
| 166 | F( 9600000, cxo, 2, 0, 0), |
| 167 | F( 16000000, gpll0, 10, 1, 5), |
| 168 | F( 19200000, gpll0, 1, 0, 0), |
| 169 | F( 25000000, gpll0, 16, 1, 2), |
| 170 | F( 50000000, gpll0, 16, 0, 0), |
| 171 | F_END |
| 172 | }; |
| 173 | |
| 174 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 175 | { |
| 176 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 177 | .parent = &sdcc1_apps_clk_src.c, |
| 178 | |
| 179 | .c = { |
| 180 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 181 | .ops = &clk_ops_branch, |
| 182 | }, |
| 183 | }; |
| 184 | |
| 185 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 186 | { |
| 187 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 188 | .has_sibling = 1, |
| 189 | |
| 190 | .c = { |
| 191 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 192 | .ops = &clk_ops_branch, |
| 193 | }, |
| 194 | }; |
| 195 | |
| 196 | static struct rcg_clk sdcc2_apps_clk_src = |
| 197 | { |
| 198 | .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR, |
| 199 | .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR, |
| 200 | .m_reg = (uint32_t *) SDCC2_M, |
| 201 | .n_reg = (uint32_t *) SDCC2_N, |
| 202 | .d_reg = (uint32_t *) SDCC2_D, |
| 203 | |
| 204 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 205 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 206 | .current_freq = &rcg_dummy_freq, |
| 207 | |
| 208 | .c = { |
| 209 | .dbg_name = "sdc2_clk", |
| 210 | .ops = &clk_ops_rcg_mnd, |
| 211 | }, |
| 212 | }; |
| 213 | |
| 214 | static struct branch_clk gcc_sdcc2_apps_clk = |
| 215 | { |
| 216 | .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR, |
| 217 | .parent = &sdcc2_apps_clk_src.c, |
| 218 | |
| 219 | .c = { |
| 220 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 221 | .ops = &clk_ops_branch, |
| 222 | }, |
| 223 | }; |
| 224 | |
| 225 | static struct branch_clk gcc_sdcc2_ahb_clk = |
| 226 | { |
| 227 | .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR, |
| 228 | .has_sibling = 1, |
| 229 | |
| 230 | .c = { |
| 231 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 232 | .ops = &clk_ops_branch, |
| 233 | }, |
| 234 | }; |
| 235 | |
| 236 | /* UART Clocks */ |
| 237 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 238 | { |
| 239 | F( 3686400, gpll0, 1, 72, 15625), |
| 240 | F( 7372800, gpll0, 1, 144, 15625), |
| 241 | F(14745600, gpll0, 1, 288, 15625), |
| 242 | F(16000000, gpll0, 10, 1, 5), |
| 243 | F(19200000, cxo, 1, 0, 0), |
| 244 | F(24000000, gpll0, 1, 3, 100), |
| 245 | F(25000000, gpll0, 16, 1, 2), |
| 246 | F(32000000, gpll0, 1, 1, 25), |
| 247 | F(40000000, gpll0, 1, 1, 20), |
| 248 | F(46400000, gpll0, 1, 29, 500), |
| 249 | F(48000000, gpll0, 1, 3, 50), |
| 250 | F(51200000, gpll0, 1, 8, 125), |
| 251 | F(56000000, gpll0, 1, 7, 100), |
| 252 | F(58982400, gpll0, 1,1152, 15625), |
| 253 | F(60000000, gpll0, 1, 3, 40), |
| 254 | F_END |
| 255 | }; |
| 256 | |
Unnati Gandhi | d119ebc | 2014-10-14 03:41:46 -0700 | [diff] [blame] | 257 | static struct rcg_clk blsp1_uart1_apps_clk_src = |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 258 | { |
Unnati Gandhi | d119ebc | 2014-10-14 03:41:46 -0700 | [diff] [blame] | 259 | .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR, |
| 260 | .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR, |
| 261 | .m_reg = (uint32_t *) BLSP1_UART1_APPS_M, |
| 262 | .n_reg = (uint32_t *) BLSP1_UART1_APPS_N, |
| 263 | .d_reg = (uint32_t *) BLSP1_UART1_APPS_D, |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 264 | |
| 265 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 266 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 267 | .current_freq = &rcg_dummy_freq, |
| 268 | |
| 269 | .c = { |
Unnati Gandhi | d119ebc | 2014-10-14 03:41:46 -0700 | [diff] [blame] | 270 | .dbg_name = "blsp1_uart1_apps_clk", |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 271 | .ops = &clk_ops_rcg_mnd, |
| 272 | }, |
| 273 | }; |
| 274 | |
Unnati Gandhi | d119ebc | 2014-10-14 03:41:46 -0700 | [diff] [blame] | 275 | static struct branch_clk gcc_blsp1_uart1_apps_clk = |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 276 | { |
Unnati Gandhi | d119ebc | 2014-10-14 03:41:46 -0700 | [diff] [blame] | 277 | .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR, |
| 278 | .parent = &blsp1_uart1_apps_clk_src.c, |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 279 | |
| 280 | .c = { |
Unnati Gandhi | d119ebc | 2014-10-14 03:41:46 -0700 | [diff] [blame] | 281 | .dbg_name = "gcc_blsp1_uart1_apps_clk", |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 282 | .ops = &clk_ops_branch, |
| 283 | }, |
| 284 | }; |
| 285 | |
Baochu Xu | 71110b9 | 2017-12-04 19:13:46 +0800 | [diff] [blame] | 286 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 287 | { |
| 288 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 289 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 290 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 291 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 292 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 293 | |
| 294 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 295 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 296 | .current_freq = &rcg_dummy_freq, |
| 297 | |
| 298 | .c = { |
| 299 | .dbg_name = "blsp1_uart2_apps_clk", |
| 300 | .ops = &clk_ops_rcg_mnd, |
| 301 | }, |
| 302 | }; |
| 303 | |
| 304 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 305 | { |
| 306 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 307 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 308 | |
| 309 | .c = { |
| 310 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 311 | .ops = &clk_ops_branch, |
| 312 | }, |
| 313 | }; |
| 314 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 315 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 316 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 317 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 318 | .en_mask = BIT(10), |
| 319 | |
| 320 | .c = { |
| 321 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 322 | .ops = &clk_ops_vote, |
| 323 | }, |
| 324 | }; |
| 325 | |
Baochu Xu | 71110b9 | 2017-12-04 19:13:46 +0800 | [diff] [blame] | 326 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 327 | /* USB Clocks */ |
| 328 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 329 | { |
| 330 | F(80000000, gpll0, 10, 0, 0), |
| 331 | F_END |
| 332 | }; |
| 333 | |
| 334 | static struct rcg_clk usb_hs_system_clk_src = |
| 335 | { |
| 336 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 337 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 338 | |
| 339 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 340 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 341 | .current_freq = &rcg_dummy_freq, |
| 342 | |
| 343 | .c = { |
| 344 | .dbg_name = "usb_hs_system_clk", |
| 345 | .ops = &clk_ops_rcg, |
| 346 | }, |
| 347 | }; |
| 348 | |
| 349 | static struct branch_clk gcc_usb_hs_system_clk = |
| 350 | { |
| 351 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 352 | .parent = &usb_hs_system_clk_src.c, |
| 353 | |
| 354 | .c = { |
| 355 | .dbg_name = "gcc_usb_hs_system_clk", |
| 356 | .ops = &clk_ops_branch, |
| 357 | }, |
| 358 | }; |
| 359 | |
| 360 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 361 | { |
| 362 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 363 | .has_sibling = 1, |
| 364 | |
| 365 | .c = { |
| 366 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 367 | .ops = &clk_ops_branch, |
| 368 | }, |
| 369 | }; |
| 370 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 371 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 372 | F(160000000, gpll0, 5, 0, 0), |
| 373 | F_END |
| 374 | }; |
| 375 | |
| 376 | static struct rcg_clk ce1_clk_src = { |
| 377 | .cmd_reg = (uint32_t *) GCC_CRYPTO_CMD_RCGR, |
| 378 | .cfg_reg = (uint32_t *) GCC_CRYPTO_CFG_RCGR, |
| 379 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 380 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 381 | .current_freq = &rcg_dummy_freq, |
| 382 | |
| 383 | .c = { |
| 384 | .dbg_name = "ce1_clk_src", |
| 385 | .ops = &clk_ops_rcg, |
| 386 | }, |
| 387 | }; |
| 388 | |
| 389 | static struct vote_clk gcc_ce1_clk = { |
| 390 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_CBCR, |
| 391 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 392 | .en_mask = BIT(2), |
| 393 | |
| 394 | .c = { |
| 395 | .dbg_name = "gcc_ce1_clk", |
| 396 | .ops = &clk_ops_vote, |
| 397 | }, |
| 398 | }; |
| 399 | |
| 400 | static struct vote_clk gcc_ce1_ahb_clk = { |
| 401 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR, |
| 402 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 403 | .en_mask = BIT(0), |
| 404 | |
| 405 | .c = { |
| 406 | .dbg_name = "gcc_ce1_ahb_clk", |
| 407 | .ops = &clk_ops_vote, |
| 408 | }, |
| 409 | }; |
| 410 | |
| 411 | static struct vote_clk gcc_ce1_axi_clk = { |
| 412 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AXI_CBCR, |
| 413 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 414 | .en_mask = BIT(1), |
| 415 | |
| 416 | .c = { |
| 417 | .dbg_name = "gcc_ce1_axi_clk", |
| 418 | .ops = &clk_ops_vote, |
| 419 | }, |
| 420 | }; |
| 421 | |
Unnati Gandhi | 88cf23b | 2014-12-10 15:39:12 +0530 | [diff] [blame] | 422 | static struct rcg_clk gcc_blsp1_qup1_i2c_apps_clk_src = |
| 423 | { |
| 424 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP1_CMD_RCGR, |
| 425 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP1_CFG_RCGR, |
| 426 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 427 | .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src, |
| 428 | .current_freq = &rcg_dummy_freq, |
| 429 | |
| 430 | .c = { |
| 431 | .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk_src", |
| 432 | .ops = &clk_ops_rcg, |
| 433 | }, |
| 434 | }; |
| 435 | |
| 436 | static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = { |
| 437 | .cbcr_reg = GCC_BLSP1_QUP1_APPS_CBCR, |
| 438 | .parent = &gcc_blsp1_qup1_i2c_apps_clk_src.c, |
| 439 | |
| 440 | .c = { |
| 441 | .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk", |
| 442 | .ops = &clk_ops_branch, |
| 443 | }, |
| 444 | }; |
| 445 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 446 | |
| 447 | static struct rcg_clk gcc_blsp1_qup2_i2c_apps_clk_src = |
| 448 | { |
| 449 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP2_CMD_RCGR, |
| 450 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP2_CFG_RCGR, |
| 451 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 452 | .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src, |
| 453 | .current_freq = &rcg_dummy_freq, |
| 454 | |
| 455 | .c = { |
| 456 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk_src", |
| 457 | .ops = &clk_ops_rcg, |
| 458 | }, |
| 459 | }; |
| 460 | |
| 461 | static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = { |
| 462 | .cbcr_reg = GCC_BLSP1_QUP2_APPS_CBCR, |
| 463 | .parent = &gcc_blsp1_qup2_i2c_apps_clk_src.c, |
| 464 | |
| 465 | .c = { |
| 466 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk", |
| 467 | .ops = &clk_ops_branch, |
| 468 | }, |
| 469 | }; |
Shivaraj Shetty | 720fd6b | 2014-10-30 19:15:26 +0530 | [diff] [blame] | 470 | |
Unnati Gandhi | 88cf23b | 2014-12-10 15:39:12 +0530 | [diff] [blame] | 471 | static struct rcg_clk gcc_blsp1_qup3_i2c_apps_clk_src = |
| 472 | { |
| 473 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP3_CMD_RCGR, |
| 474 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP3_CFG_RCGR, |
| 475 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 476 | .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src, |
| 477 | .current_freq = &rcg_dummy_freq, |
| 478 | |
| 479 | .c = { |
| 480 | .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk_src", |
| 481 | .ops = &clk_ops_rcg, |
| 482 | }, |
| 483 | }; |
| 484 | |
| 485 | static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = { |
| 486 | .cbcr_reg = GCC_BLSP1_QUP3_APPS_CBCR, |
| 487 | .parent = &gcc_blsp1_qup3_i2c_apps_clk_src.c, |
| 488 | |
| 489 | .c = { |
| 490 | .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk", |
| 491 | .ops = &clk_ops_branch, |
| 492 | }, |
| 493 | }; |
| 494 | |
| 495 | static struct rcg_clk gcc_blsp1_qup4_i2c_apps_clk_src = |
| 496 | { |
| 497 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP4_CMD_RCGR, |
| 498 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP4_CFG_RCGR, |
| 499 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 500 | .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src, |
| 501 | .current_freq = &rcg_dummy_freq, |
| 502 | |
| 503 | .c = { |
| 504 | .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk_src", |
| 505 | .ops = &clk_ops_rcg, |
| 506 | }, |
| 507 | }; |
| 508 | |
| 509 | static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = { |
| 510 | .cbcr_reg = GCC_BLSP1_QUP4_APPS_CBCR, |
| 511 | .parent = &gcc_blsp1_qup4_i2c_apps_clk_src.c, |
| 512 | |
| 513 | .c = { |
| 514 | .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk", |
| 515 | .ops = &clk_ops_branch, |
| 516 | }, |
| 517 | }; |
| 518 | |
| 519 | static struct rcg_clk gcc_blsp1_qup5_i2c_apps_clk_src = |
| 520 | { |
| 521 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP5_CMD_RCGR, |
| 522 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP5_CFG_RCGR, |
| 523 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 524 | .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src, |
| 525 | .current_freq = &rcg_dummy_freq, |
| 526 | |
| 527 | .c = { |
| 528 | .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk_src", |
| 529 | .ops = &clk_ops_rcg, |
| 530 | }, |
| 531 | }; |
| 532 | |
| 533 | static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = { |
| 534 | .cbcr_reg = GCC_BLSP1_QUP5_APPS_CBCR, |
| 535 | .parent = &gcc_blsp1_qup5_i2c_apps_clk_src.c, |
| 536 | |
| 537 | .c = { |
| 538 | .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk", |
| 539 | .ops = &clk_ops_branch, |
| 540 | }, |
| 541 | }; |
| 542 | |
| 543 | static struct rcg_clk gcc_blsp1_qup6_i2c_apps_clk_src = |
| 544 | { |
| 545 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP6_CMD_RCGR, |
| 546 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP6_CFG_RCGR, |
| 547 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 548 | .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src, |
| 549 | .current_freq = &rcg_dummy_freq, |
| 550 | |
| 551 | .c = { |
| 552 | .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk_src", |
| 553 | .ops = &clk_ops_rcg, |
| 554 | }, |
| 555 | }; |
| 556 | |
| 557 | static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = { |
| 558 | .cbcr_reg = GCC_BLSP1_QUP6_APPS_CBCR, |
| 559 | .parent = &gcc_blsp1_qup6_i2c_apps_clk_src.c, |
| 560 | |
| 561 | .c = { |
| 562 | .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk", |
| 563 | .ops = &clk_ops_branch, |
| 564 | }, |
| 565 | }; |
| 566 | |
Baochu Xu | 6788fad | 2017-12-05 18:45:28 +0800 | [diff] [blame] | 567 | |
| 568 | static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk[] = { |
| 569 | F( 960000, cxo, 10, 1, 2), |
| 570 | F( 4800000, cxo, 4, 0, 0), |
| 571 | F( 9600000, cxo, 2, 0, 0), |
| 572 | F( 16000000, gpll0, 10, 1, 5), |
| 573 | F( 19200000, cxo, 1, 0, 0), |
| 574 | F( 25000000, gpll0, 16, 1, 2), |
| 575 | F( 50000000, gpll0, 16, 0, 0), |
| 576 | F_END |
| 577 | }; |
| 578 | |
| 579 | static struct rcg_clk gcc_blsp1_qup3_spi_apps_clk_src = |
| 580 | { |
| 581 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR, |
| 582 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP3_SPI_CFG_RCGR, |
| 583 | .m_reg = (uint32_t *) GCC_BLSP1_QUP3_SPI_APPS_M, |
| 584 | .n_reg = (uint32_t *) GCC_BLSP1_QUP3_SPI_APPS_N, |
| 585 | .d_reg = (uint32_t *) GCC_BLSP1_QUP3_SPI_APPS_D, |
| 586 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 587 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk, |
| 588 | .current_freq = &rcg_dummy_freq, |
| 589 | |
| 590 | .c = { |
| 591 | .dbg_name = "gcc_blsp1_qup3_spi_apps_clk_src", |
| 592 | .ops = &clk_ops_rcg, |
| 593 | }, |
| 594 | }; |
| 595 | |
| 596 | static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = { |
| 597 | .cbcr_reg = GCC_BLSP1_QUP3_SPI_APPS_CBCR, |
| 598 | .parent = &gcc_blsp1_qup3_spi_apps_clk_src.c, |
| 599 | |
| 600 | .c = { |
| 601 | .dbg_name = "gcc_blsp1_qup3_spi_apps_clk", |
| 602 | .ops = &clk_ops_branch, |
| 603 | }, |
| 604 | }; |
| 605 | |
| 606 | static struct rcg_clk gcc_blsp1_qup4_spi_apps_clk_src = |
| 607 | { |
| 608 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR, |
| 609 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP4_SPI_CFG_RCGR, |
| 610 | .m_reg = (uint32_t *) GCC_BLSP1_QUP4_SPI_APPS_M, |
| 611 | .n_reg = (uint32_t *) GCC_BLSP1_QUP4_SPI_APPS_N, |
| 612 | .d_reg = (uint32_t *) GCC_BLSP1_QUP4_SPI_APPS_D, |
| 613 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 614 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk, |
| 615 | .current_freq = &rcg_dummy_freq, |
| 616 | |
| 617 | .c = { |
| 618 | .dbg_name = "gcc_blsp1_qup4_spi_apps_clk_src", |
| 619 | .ops = &clk_ops_rcg, |
| 620 | }, |
| 621 | }; |
| 622 | |
| 623 | static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = { |
| 624 | .cbcr_reg = GCC_BLSP1_QUP4_SPI_APPS_CBCR, |
| 625 | .parent = &gcc_blsp1_qup4_spi_apps_clk_src.c, |
| 626 | |
| 627 | .c = { |
| 628 | .dbg_name = "gcc_blsp1_qup4_spi_apps_clk", |
| 629 | .ops = &clk_ops_branch, |
| 630 | }, |
| 631 | }; |
| 632 | |
| 633 | static struct rcg_clk gcc_blsp1_qup5_spi_apps_clk_src = |
| 634 | { |
| 635 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR, |
| 636 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP5_SPI_CFG_RCGR, |
| 637 | .m_reg = (uint32_t *) GCC_BLSP1_QUP5_SPI_APPS_M, |
| 638 | .n_reg = (uint32_t *) GCC_BLSP1_QUP5_SPI_APPS_N, |
| 639 | .d_reg = (uint32_t *) GCC_BLSP1_QUP5_SPI_APPS_D, |
| 640 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 641 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk, |
| 642 | .current_freq = &rcg_dummy_freq, |
| 643 | |
| 644 | .c = { |
| 645 | .dbg_name = "gcc_blsp1_qup5_spi_apps_clk_src", |
| 646 | .ops = &clk_ops_rcg, |
| 647 | }, |
| 648 | }; |
| 649 | |
| 650 | static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = { |
| 651 | .cbcr_reg = GCC_BLSP1_QUP5_SPI_APPS_CBCR, |
| 652 | .parent = &gcc_blsp1_qup5_spi_apps_clk_src.c, |
| 653 | |
| 654 | .c = { |
| 655 | .dbg_name = "gcc_blsp1_qup5_spi_apps_clk", |
| 656 | .ops = &clk_ops_branch, |
| 657 | }, |
| 658 | }; |
| 659 | |
Shivaraj Shetty | 720fd6b | 2014-10-30 19:15:26 +0530 | [diff] [blame] | 660 | /* Display clocks */ |
| 661 | static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = { |
| 662 | F_MM(19200000, cxo, 1, 0, 0), |
| 663 | F_END |
| 664 | }; |
| 665 | |
| 666 | static struct clk_freq_tbl ftbl_mdp_clk[] = { |
| 667 | F_MM( 50000000, gpll0, 16, 0, 0), |
| 668 | F_MM( 80000000, gpll0, 10, 0, 0), |
| 669 | F_MM( 100000000, gpll0, 8, 0, 0), |
| 670 | F_MM( 160000000, gpll0, 5, 0, 0), |
| 671 | F_MM( 177780000, gpll0, 4.5, 0, 0), |
| 672 | F_MM( 200000000, gpll0, 4, 0, 0), |
| 673 | F_MM( 266670000, gpll0, 3, 0, 0), |
| 674 | F_MM( 307200000, gpll1, 4, 0, 0), |
| 675 | F_END |
| 676 | }; |
| 677 | |
| 678 | static struct rcg_clk dsi_esc0_clk_src = { |
| 679 | .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR, |
| 680 | .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR, |
| 681 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 682 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
| 683 | |
| 684 | .c = { |
| 685 | .dbg_name = "dsi_esc0_clk_src", |
| 686 | .ops = &clk_ops_rcg, |
| 687 | }, |
| 688 | }; |
| 689 | |
| 690 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 691 | F_MM(19200000, cxo, 1, 0, 0), |
| 692 | F_END |
| 693 | }; |
| 694 | |
| 695 | static struct rcg_clk vsync_clk_src = { |
| 696 | .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR, |
| 697 | .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR, |
| 698 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 699 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 700 | |
| 701 | .c = { |
| 702 | .dbg_name = "vsync_clk_src", |
| 703 | .ops = &clk_ops_rcg, |
| 704 | }, |
| 705 | }; |
| 706 | |
| 707 | static struct branch_clk mdss_esc0_clk = { |
| 708 | .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR, |
| 709 | .parent = &dsi_esc0_clk_src.c, |
| 710 | .has_sibling = 0, |
| 711 | |
| 712 | .c = { |
| 713 | .dbg_name = "mdss_esc0_clk", |
| 714 | .ops = &clk_ops_branch, |
| 715 | }, |
| 716 | }; |
| 717 | |
| 718 | static struct branch_clk mdss_axi_clk = { |
| 719 | .cbcr_reg = (uint32_t *) MDP_AXI_CBCR, |
| 720 | .has_sibling = 1, |
| 721 | |
| 722 | .c = { |
| 723 | .dbg_name = "mdss_axi_clk", |
| 724 | .ops = &clk_ops_branch, |
| 725 | }, |
| 726 | }; |
| 727 | |
| 728 | static struct branch_clk mdp_ahb_clk = { |
| 729 | .cbcr_reg = (uint32_t *) MDP_AHB_CBCR, |
| 730 | .has_sibling = 1, |
| 731 | |
| 732 | .c = { |
| 733 | .dbg_name = "mdp_ahb_clk", |
| 734 | .ops = &clk_ops_branch, |
| 735 | }, |
| 736 | }; |
| 737 | |
| 738 | static struct rcg_clk mdss_mdp_clk_src = { |
| 739 | .cmd_reg = (uint32_t *) MDP_CMD_RCGR, |
| 740 | .cfg_reg = (uint32_t *) MDP_CFG_RCGR, |
| 741 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 742 | .freq_tbl = ftbl_mdp_clk, |
| 743 | .current_freq = &rcg_dummy_freq, |
| 744 | |
| 745 | .c = { |
| 746 | .dbg_name = "mdss_mdp_clk_src", |
| 747 | .ops = &clk_ops_rcg, |
| 748 | }, |
| 749 | }; |
| 750 | |
| 751 | static struct branch_clk mdss_mdp_clk = { |
| 752 | .cbcr_reg = (uint32_t *) MDP_CBCR, |
| 753 | .parent = &mdss_mdp_clk_src.c, |
| 754 | .has_sibling = 0, |
| 755 | |
| 756 | .c = { |
| 757 | .dbg_name = "mdss_mdp_clk", |
| 758 | .ops = &clk_ops_branch, |
| 759 | }, |
| 760 | }; |
| 761 | |
| 762 | static struct branch_clk mdss_vsync_clk = { |
| 763 | .cbcr_reg = MDSS_VSYNC_CBCR, |
| 764 | .parent = &vsync_clk_src.c, |
| 765 | .has_sibling = 0, |
| 766 | |
| 767 | .c = { |
| 768 | .dbg_name = "mdss_vsync_clk", |
| 769 | .ops = &clk_ops_branch, |
| 770 | }, |
| 771 | }; |
| 772 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 773 | /* Clock lookup table */ |
Unnati Gandhi | 89d71a1 | 2014-09-18 12:01:08 +0530 | [diff] [blame] | 774 | static struct clk_lookup msm_clocks_msm8909[] = |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 775 | { |
| 776 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 777 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 778 | |
| 779 | CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c), |
| 780 | CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c), |
| 781 | |
Unnati Gandhi | d119ebc | 2014-10-14 03:41:46 -0700 | [diff] [blame] | 782 | CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c), |
| 783 | CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c), |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 784 | |
Baochu Xu | 71110b9 | 2017-12-04 19:13:46 +0800 | [diff] [blame] | 785 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 786 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 787 | |
| 788 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 789 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 790 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
| 791 | |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 792 | CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c), |
| 793 | CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c), |
| 794 | CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c), |
| 795 | CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), |
| 796 | |
| 797 | CLK_LOOKUP("blsp1_qup2_ahb_iface_clk", gcc_blsp1_ahb_clk.c), |
Unnati Gandhi | 88cf23b | 2014-12-10 15:39:12 +0530 | [diff] [blame] | 798 | CLK_LOOKUP("gcc_blsp1_qup1_i2c_apps_clk_src", gcc_blsp1_qup1_i2c_apps_clk_src.c), |
| 799 | CLK_LOOKUP("gcc_blsp1_qup1_i2c_apps_clk", gcc_blsp1_qup1_i2c_apps_clk.c), |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 800 | CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk_src", gcc_blsp1_qup2_i2c_apps_clk_src.c), |
| 801 | CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk", gcc_blsp1_qup2_i2c_apps_clk.c), |
Unnati Gandhi | 88cf23b | 2014-12-10 15:39:12 +0530 | [diff] [blame] | 802 | CLK_LOOKUP("gcc_blsp1_qup3_i2c_apps_clk_src", gcc_blsp1_qup3_i2c_apps_clk_src.c), |
| 803 | CLK_LOOKUP("gcc_blsp1_qup3_i2c_apps_clk", gcc_blsp1_qup3_i2c_apps_clk.c), |
| 804 | CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk_src", gcc_blsp1_qup4_i2c_apps_clk_src.c), |
| 805 | CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk", gcc_blsp1_qup4_i2c_apps_clk.c), |
| 806 | CLK_LOOKUP("gcc_blsp1_qup5_i2c_apps_clk_src", gcc_blsp1_qup5_i2c_apps_clk_src.c), |
| 807 | CLK_LOOKUP("gcc_blsp1_qup5_i2c_apps_clk", gcc_blsp1_qup5_i2c_apps_clk.c), |
| 808 | CLK_LOOKUP("gcc_blsp1_qup6_i2c_apps_clk_src", gcc_blsp1_qup5_i2c_apps_clk_src.c), |
| 809 | CLK_LOOKUP("gcc_blsp1_qup6_i2c_apps_clk", gcc_blsp1_qup5_i2c_apps_clk.c), |
Baochu Xu | 6788fad | 2017-12-05 18:45:28 +0800 | [diff] [blame] | 810 | CLK_LOOKUP("blsp1_ahb_iface_clk", gcc_blsp1_ahb_clk.c), |
| 811 | CLK_LOOKUP("gcc_blsp1_qup3_spi_apps_clk_src", gcc_blsp1_qup3_spi_apps_clk_src.c), |
| 812 | CLK_LOOKUP("gcc_blsp1_qup3_spi_apps_clk", gcc_blsp1_qup3_spi_apps_clk.c), |
| 813 | CLK_LOOKUP("gcc_blsp1_qup4_spi_apps_clk_src", gcc_blsp1_qup4_spi_apps_clk_src.c), |
| 814 | CLK_LOOKUP("gcc_blsp1_qup4_spi_apps_clk", gcc_blsp1_qup4_spi_apps_clk.c), |
| 815 | CLK_LOOKUP("gcc_blsp1_qup5_spi_apps_clk_src", gcc_blsp1_qup5_spi_apps_clk_src.c), |
| 816 | CLK_LOOKUP("gcc_blsp1_qup5_spi_apps_clk", gcc_blsp1_qup5_spi_apps_clk.c), |
Shivaraj Shetty | 720fd6b | 2014-10-30 19:15:26 +0530 | [diff] [blame] | 817 | |
| 818 | CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c), |
| 819 | CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c), |
| 820 | CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c), |
| 821 | CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c), |
| 822 | CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c), |
| 823 | CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c), |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 824 | }; |
| 825 | |
| 826 | void platform_clock_init(void) |
| 827 | { |
Unnati Gandhi | 89d71a1 | 2014-09-18 12:01:08 +0530 | [diff] [blame] | 828 | clk_init(msm_clocks_msm8909, ARRAY_SIZE(msm_clocks_msm8909)); |
Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame] | 829 | } |