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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnes5669fca2009-02-17 15:13:31 -080030#include <linux/device.h>
Jesse Barnese5747e32014-06-12 08:35:47 -070031#include <linux/acpi.h>
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
33#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030035#include "i915_trace.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070036#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040039#include <linux/module.h>
Imre Deakd6102972014-05-07 19:57:49 +030040#include <linux/pm_runtime.h>
David Howells760285e2012-10-02 18:01:07 +010041#include <drm/drm_crtc_helper.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080042
Kristian Høgsberg112b7152009-01-04 16:55:33 -050043static struct drm_driver driver;
44
Antti Koskipaaa57c7742014-02-04 14:22:24 +020045#define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
Antti Koskipaaa57c7742014-02-04 14:22:24 +020050 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030052#define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030057 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
Antti Koskipaaa57c7742014-02-04 14:22:24 +020059
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030060#define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
62
63#define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
65
Tobias Klauser9a7e8492010-05-20 10:33:46 +020066static const struct intel_device_info intel_i830_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070067 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +010068 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070069 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020070 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030071 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050072};
73
Tobias Klauser9a7e8492010-05-20 10:33:46 +020074static const struct intel_device_info intel_845g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070075 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010076 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070077 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020078 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030079 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050080};
81
Tobias Klauser9a7e8492010-05-20 10:33:46 +020082static const struct intel_device_info intel_i85x_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070083 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
Adam Jackson5ce8ba72010-04-15 14:03:30 -040084 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +010085 .has_overlay = 1, .overlay_needs_physical = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +020086 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070087 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020088 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030089 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050090};
91
Tobias Klauser9a7e8492010-05-20 10:33:46 +020092static const struct intel_device_info intel_i865g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070093 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010094 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070095 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020096 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030097 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050098};
99
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200100static const struct intel_device_info intel_i915g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700101 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100102 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700103 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200104 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300105 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500106};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200107static const struct intel_device_info intel_i915gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700108 .gen = 3, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500109 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100110 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100111 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200112 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700113 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200114 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300115 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500116};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200117static const struct intel_device_info intel_i945g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700118 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100119 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700120 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200121 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300122 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500123};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200124static const struct intel_device_info intel_i945gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700125 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500126 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100127 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100128 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200129 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700130 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200131 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300132 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500133};
134
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200135static const struct intel_device_info intel_i965g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700136 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100137 .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100138 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700139 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200140 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300141 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500142};
143
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200144static const struct intel_device_info intel_i965gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700145 .gen = 4, .is_crestline = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000146 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100147 .has_overlay = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100148 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700149 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200150 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300151 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500152};
153
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200154static const struct intel_device_info intel_g33_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700155 .gen = 3, .is_g33 = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100156 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100157 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700158 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200159 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300160 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500161};
162
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200163static const struct intel_device_info intel_g45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700164 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100165 .has_pipe_cxsr = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700166 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200167 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300168 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500169};
170
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200171static const struct intel_device_info intel_gm45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700172 .gen = 4, .is_g4x = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000173 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100174 .has_pipe_cxsr = 1, .has_hotplug = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100175 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700176 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200177 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300178 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500179};
180
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200181static const struct intel_device_info intel_pineview_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700182 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100183 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100184 .has_overlay = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200185 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300186 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500187};
188
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200189static const struct intel_device_info intel_ironlake_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700190 .gen = 5, .num_pipes = 2,
Eugeni Dodonov5a117db2012-01-05 09:34:29 -0200191 .need_gfx_hws = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700192 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200193 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300194 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500195};
196
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200197static const struct intel_device_info intel_ironlake_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700198 .gen = 5, .is_mobile = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000199 .need_gfx_hws = 1, .has_hotplug = 1,
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700200 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700201 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200202 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300203 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500204};
205
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200206static const struct intel_device_info intel_sandybridge_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700207 .gen = 6, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100208 .need_gfx_hws = 1, .has_hotplug = 1,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200209 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700210 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200211 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200212 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300213 CURSOR_OFFSETS,
Eric Anholtf6e450a2009-11-02 12:08:22 -0800214};
215
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200216static const struct intel_device_info intel_sandybridge_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700217 .gen = 6, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100218 .need_gfx_hws = 1, .has_hotplug = 1,
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800219 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700220 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200221 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200222 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300223 CURSOR_OFFSETS,
Eric Anholta13e4092010-01-07 15:08:18 -0800224};
225
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700226#define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200229 .has_fbc = 1, \
Ben Widawsky73ae4782013-10-15 10:02:57 -0700230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
Ben Widawskyab484f82013-10-05 17:57:11 -0700231 .has_llc = 1
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700232
Jesse Barnesc76b6152011-04-28 14:32:07 -0700233static const struct intel_device_info intel_ivybridge_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700234 GEN7_FEATURES,
235 .is_ivybridge = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200236 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300237 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700238};
239
240static const struct intel_device_info intel_ivybridge_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700241 GEN7_FEATURES,
242 .is_ivybridge = 1,
243 .is_mobile = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200244 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300245 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700246};
247
Ben Widawsky999bcde2013-04-05 13:12:45 -0700248static const struct intel_device_info intel_ivybridge_q_info = {
249 GEN7_FEATURES,
250 .is_ivybridge = 1,
251 .num_pipes = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200252 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300253 IVB_CURSOR_OFFSETS,
Ben Widawsky999bcde2013-04-05 13:12:45 -0700254};
255
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700256static const struct intel_device_info intel_valleyview_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700257 GEN7_FEATURES,
258 .is_mobile = 1,
259 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700260 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200261 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200262 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700263 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200264 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300265 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700266};
267
268static const struct intel_device_info intel_valleyview_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700269 GEN7_FEATURES,
270 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700271 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200272 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200273 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700274 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200275 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300276 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700277};
278
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300279static const struct intel_device_info intel_haswell_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700280 GEN7_FEATURES,
281 .is_haswell = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100282 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100283 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200285 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300286 IVB_CURSOR_OFFSETS,
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300287};
288
289static const struct intel_device_info intel_haswell_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700290 GEN7_FEATURES,
291 .is_haswell = 1,
292 .is_mobile = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100293 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100294 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200296 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300297 IVB_CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500298};
299
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800300static const struct intel_device_info intel_broadwell_d_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700301 .gen = 8, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800302 .need_gfx_hws = 1, .has_hotplug = 1,
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
304 .has_llc = 1,
305 .has_ddi = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800306 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200307 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300308 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800309};
310
311static const struct intel_device_info intel_broadwell_m_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700312 .gen = 8, .is_mobile = 1, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800313 .need_gfx_hws = 1, .has_hotplug = 1,
314 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
315 .has_llc = 1,
316 .has_ddi = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800317 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200318 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700319 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800320};
321
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800322static const struct intel_device_info intel_broadwell_gt3d_info = {
323 .gen = 8, .num_pipes = 3,
324 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800325 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800326 .has_llc = 1,
327 .has_ddi = 1,
328 .has_fbc = 1,
329 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700330 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800331};
332
333static const struct intel_device_info intel_broadwell_gt3m_info = {
334 .gen = 8, .is_mobile = 1, .num_pipes = 3,
335 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800336 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800337 .has_llc = 1,
338 .has_ddi = 1,
339 .has_fbc = 1,
340 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300341 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800342};
343
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300344static const struct intel_device_info intel_cherryview_info = {
345 .is_preliminary = 1,
Ville Syrjälä07fddb12014-04-09 13:28:54 +0300346 .gen = 8, .num_pipes = 3,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300347 .need_gfx_hws = 1, .has_hotplug = 1,
348 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
349 .is_valleyview = 1,
350 .display_mmio_offset = VLV_DISPLAY_BASE,
Rafael Barbalho84fd4f42014-04-28 14:00:42 +0300351 GEN_CHV_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300352 CURSOR_OFFSETS,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300353};
354
Jesse Barnesa0a18072013-07-26 13:32:51 -0700355/*
356 * Make sure any device matches here are from most specific to most
357 * general. For example, since the Quanta match is based on the subsystem
358 * and subvendor IDs, we need it to come before the more general IVB
359 * PCI ID matches, otherwise we'll use the wrong info struct above.
360 */
361#define INTEL_PCI_IDS \
362 INTEL_I830_IDS(&intel_i830_info), \
363 INTEL_I845G_IDS(&intel_845g_info), \
364 INTEL_I85X_IDS(&intel_i85x_info), \
365 INTEL_I865G_IDS(&intel_i865g_info), \
366 INTEL_I915G_IDS(&intel_i915g_info), \
367 INTEL_I915GM_IDS(&intel_i915gm_info), \
368 INTEL_I945G_IDS(&intel_i945g_info), \
369 INTEL_I945GM_IDS(&intel_i945gm_info), \
370 INTEL_I965G_IDS(&intel_i965g_info), \
371 INTEL_G33_IDS(&intel_g33_info), \
372 INTEL_I965GM_IDS(&intel_i965gm_info), \
373 INTEL_GM45_IDS(&intel_gm45_info), \
374 INTEL_G45_IDS(&intel_g45_info), \
375 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
376 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
377 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
378 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
379 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
380 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
381 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
382 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
383 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
384 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
385 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800386 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800387 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
388 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
389 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300390 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
391 INTEL_CHV_IDS(&intel_cherryview_info)
Jesse Barnesa0a18072013-07-26 13:32:51 -0700392
Chris Wilson6103da02010-07-05 18:01:47 +0100393static const struct pci_device_id pciidlist[] = { /* aka */
Jesse Barnesa0a18072013-07-26 13:32:51 -0700394 INTEL_PCI_IDS,
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500395 {0, 0, 0}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396};
397
Jesse Barnes79e53942008-11-07 14:24:08 -0800398#if defined(CONFIG_DRM_I915_KMS)
399MODULE_DEVICE_TABLE(pci, pciidlist);
400#endif
401
Akshay Joshi0206e352011-08-16 15:34:10 -0400402void intel_detect_pch(struct drm_device *dev)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800403{
404 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbcdb72a2014-02-14 20:23:54 +0200405 struct pci_dev *pch = NULL;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800406
Ben Widawskyce1bb322013-04-05 13:12:44 -0700407 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
408 * (which really amounts to a PCH but no South Display).
409 */
410 if (INTEL_INFO(dev)->num_pipes == 0) {
411 dev_priv->pch_type = PCH_NOP;
Ben Widawskyce1bb322013-04-05 13:12:44 -0700412 return;
413 }
414
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800415 /*
416 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
417 * make graphics device passthrough work easy for VMM, that only
418 * need to expose ISA bridge to let driver know the real hardware
419 * underneath. This is a requirement from virtualization team.
Rui Guo6a9c4b32013-06-19 21:10:23 +0800420 *
421 * In some virtualized environments (e.g. XEN), there is irrelevant
422 * ISA bridge in the system. To work reliably, we should scan trhough
423 * all the ISA bridge devices and check for the first match, instead
424 * of only checking the first one.
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800425 */
Imre Deakbcdb72a2014-02-14 20:23:54 +0200426 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800427 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Imre Deakbcdb72a2014-02-14 20:23:54 +0200428 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200429 dev_priv->pch_id = id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800430
Jesse Barnes90711d52011-04-28 14:48:02 -0700431 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
432 dev_priv->pch_type = PCH_IBX;
433 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100434 WARN_ON(!IS_GEN5(dev));
Jesse Barnes90711d52011-04-28 14:48:02 -0700435 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800436 dev_priv->pch_type = PCH_CPT;
437 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100438 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Jesse Barnesc7925132011-04-07 12:33:56 -0700439 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
440 /* PantherPoint is CPT compatible */
441 dev_priv->pch_type = PCH_CPT;
Jani Nikula492ab662013-10-01 12:12:33 +0300442 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100443 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300444 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
445 dev_priv->pch_type = PCH_LPT;
446 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100447 WARN_ON(!IS_HASWELL(dev));
Paulo Zanoni08e14132013-04-12 18:16:54 -0300448 WARN_ON(IS_ULT(dev));
Paulo Zanoni018f52c2013-11-02 21:07:35 -0700449 } else if (IS_BROADWELL(dev)) {
450 dev_priv->pch_type = PCH_LPT;
451 dev_priv->pch_id =
452 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
453 DRM_DEBUG_KMS("This is Broadwell, assuming "
454 "LynxPoint LP PCH\n");
Ben Widawskye76e0632013-11-07 21:40:41 -0800455 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
456 dev_priv->pch_type = PCH_LPT;
457 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
458 WARN_ON(!IS_HASWELL(dev));
459 WARN_ON(!IS_ULT(dev));
Imre Deakbcdb72a2014-02-14 20:23:54 +0200460 } else
461 continue;
462
Rui Guo6a9c4b32013-06-19 21:10:23 +0800463 break;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800464 }
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800465 }
Rui Guo6a9c4b32013-06-19 21:10:23 +0800466 if (!pch)
Imre Deakbcdb72a2014-02-14 20:23:54 +0200467 DRM_DEBUG_KMS("No PCH found.\n");
468
469 pci_dev_put(pch);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800470}
471
Ben Widawsky2911a352012-04-05 14:47:36 -0700472bool i915_semaphore_is_enabled(struct drm_device *dev)
473{
474 if (INTEL_INFO(dev)->gen < 6)
Daniel Vettera08acaf2013-12-17 09:56:53 +0100475 return false;
Ben Widawsky2911a352012-04-05 14:47:36 -0700476
Jani Nikulad330a952014-01-21 11:24:25 +0200477 if (i915.semaphores >= 0)
478 return i915.semaphores;
Ben Widawsky2911a352012-04-05 14:47:36 -0700479
Daniel Vetter59de3292012-04-02 20:48:43 +0200480#ifdef CONFIG_INTEL_IOMMU
Ben Widawsky2911a352012-04-05 14:47:36 -0700481 /* Enable semaphores on SNB when IO remapping is off */
Daniel Vetter59de3292012-04-02 20:48:43 +0200482 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
483 return false;
484#endif
Ben Widawsky2911a352012-04-05 14:47:36 -0700485
Daniel Vettera08acaf2013-12-17 09:56:53 +0100486 return true;
Ben Widawsky2911a352012-04-05 14:47:36 -0700487}
488
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100489static int i915_drm_freeze(struct drm_device *dev)
490{
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100491 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes24576d22013-03-26 09:25:45 -0700492 struct drm_crtc *crtc;
Jesse Barnese5747e32014-06-12 08:35:47 -0700493 pci_power_t opregion_target_state;
Paulo Zanoni8a187452013-12-06 20:32:13 -0200494
Zhang Ruib8efb172013-02-05 15:41:53 +0800495 /* ignore lid events during suspend */
496 mutex_lock(&dev_priv->modeset_restore_lock);
497 dev_priv->modeset_restore = MODESET_SUSPENDED;
498 mutex_unlock(&dev_priv->modeset_restore_lock);
499
Paulo Zanonic67a4702013-08-19 13:18:09 -0300500 /* We do a lot of poking in a lot of registers, make sure they work
501 * properly. */
Imre Deakda7e29b2014-02-18 00:02:02 +0200502 intel_display_set_init_power(dev_priv, true);
Paulo Zanonicb107992013-01-25 16:59:15 -0200503
Dave Airlie5bcf7192010-12-07 09:20:40 +1000504 drm_kms_helper_poll_disable(dev);
505
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100506 pci_save_state(dev->pdev);
507
508 /* If KMS is active, we do the leavevt stuff here */
509 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200510 int error;
511
Chris Wilson45c5f202013-10-16 11:50:01 +0100512 error = i915_gem_suspend(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100513 if (error) {
514 dev_err(&dev->pdev->dev,
515 "GEM idle failed, resume might fail\n");
516 return error;
517 }
Daniel Vettera261b242012-07-26 19:21:47 +0200518
Paulo Zanoni84a2ab82014-06-27 18:51:51 -0300519 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
520
Imre Deakfe5b1882014-05-12 18:35:05 +0300521
Jesse Barnes156c7ca2014-06-12 08:35:45 -0700522 intel_suspend_gt_powersave(dev);
Imre Deakfe5b1882014-05-12 18:35:05 +0300523
Jesse Barnes24576d22013-03-26 09:25:45 -0700524 /*
525 * Disable CRTCs directly since we want to preserve sw state
526 * for _thaw.
527 */
Daniel Vetter6e9f7982014-05-29 23:54:47 +0200528 drm_modeset_lock_all(dev);
Chris Wilsonf7ef3fa2014-05-22 09:44:40 +0100529 for_each_crtc(dev, crtc) {
Jesse Barnes24576d22013-03-26 09:25:45 -0700530 dev_priv->display.crtc_disable(crtc);
Chris Wilsonf7ef3fa2014-05-22 09:44:40 +0100531 }
Daniel Vetter6e9f7982014-05-29 23:54:47 +0200532 drm_modeset_unlock_all(dev);
Imre Deak7d708ee2013-04-17 14:04:50 +0300533
Dave Airlie0e32b392014-05-02 14:02:48 +1000534 intel_dp_mst_suspend(dev);
535 intel_runtime_pm_disable_interrupts(dev);
536
Imre Deak7d708ee2013-04-17 14:04:50 +0300537 intel_modeset_suspend_hw(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100538 }
539
Ben Widawsky828c7902013-10-16 09:21:30 -0700540 i915_gem_suspend_gtt_mappings(dev);
541
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100542 i915_save_state(dev);
543
Imre Deak95fa2ee2014-06-23 15:46:02 +0300544 opregion_target_state = PCI_D3cold;
545#if IS_ENABLED(CONFIG_ACPI_SLEEP)
546 if (acpi_target_system_state() < ACPI_STATE_S3)
Jesse Barnese5747e32014-06-12 08:35:47 -0700547 opregion_target_state = PCI_D1;
Imre Deak95fa2ee2014-06-23 15:46:02 +0300548#endif
Jesse Barnese5747e32014-06-12 08:35:47 -0700549 intel_opregion_notify_adapter(dev, opregion_target_state);
550
Jesse Barnes156c7ca2014-06-12 08:35:45 -0700551 intel_uncore_forcewake_reset(dev, false);
Chris Wilson44834a62010-08-19 16:09:23 +0100552 intel_opregion_fini(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100553
Dave Airlie3fa016a2012-03-28 10:48:49 +0100554 console_lock();
Damien Lespiaub6f3eff2013-06-10 15:48:09 +0100555 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
Dave Airlie3fa016a2012-03-28 10:48:49 +0100556 console_unlock();
557
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200558 dev_priv->suspend_count++;
559
Kristen Carlson Accardi85e90672014-06-12 08:35:44 -0700560 intel_display_set_init_power(dev_priv, false);
561
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100562 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100563}
564
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000565int i915_suspend(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100566{
567 int error;
568
569 if (!dev || !dev->dev_private) {
570 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700571 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000572 return -ENODEV;
573 }
574
Dave Airlieb932ccb2008-02-20 10:02:20 +1000575 if (state.event == PM_EVENT_PRETHAW)
576 return 0;
577
Dave Airlie5bcf7192010-12-07 09:20:40 +1000578
579 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
580 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +0100581
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100582 error = i915_drm_freeze(dev);
583 if (error)
584 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000585
Dave Airlieb932ccb2008-02-20 10:02:20 +1000586 if (state.event == PM_EVENT_SUSPEND) {
587 /* Shut down the device */
588 pci_disable_device(dev->pdev);
589 pci_set_power_state(dev->pdev, PCI_D3hot);
590 }
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000591
592 return 0;
593}
594
Jesse Barnes073f34d2012-11-02 11:13:59 -0700595void intel_console_resume(struct work_struct *work)
596{
597 struct drm_i915_private *dev_priv =
598 container_of(work, struct drm_i915_private,
599 console_resume_work);
600 struct drm_device *dev = dev_priv->dev;
601
602 console_lock();
Damien Lespiaub6f3eff2013-06-10 15:48:09 +0100603 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
Jesse Barnes073f34d2012-11-02 11:13:59 -0700604 console_unlock();
605}
606
Imre Deak76c4b252014-04-01 19:55:22 +0300607static int i915_drm_thaw_early(struct drm_device *dev)
608{
609 struct drm_i915_private *dev_priv = dev->dev_private;
610
Kristen Carlson Accardi8abdc172014-06-12 08:35:48 -0700611 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
612 hsw_disable_pc8(dev_priv);
613
Imre Deak10018602014-06-06 12:59:39 +0300614 intel_uncore_early_sanitize(dev, true);
Imre Deak76c4b252014-04-01 19:55:22 +0300615 intel_uncore_sanitize(dev);
616 intel_power_domains_init_hw(dev_priv);
617
618 return 0;
619}
620
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300621static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000622{
Jesse Barnes5669fca2009-02-17 15:13:31 -0800623 struct drm_i915_private *dev_priv = dev->dev_private;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100624
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300625 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
626 restore_gtt_mappings) {
627 mutex_lock(&dev->struct_mutex);
628 i915_gem_restore_gtt_mappings(dev);
629 mutex_unlock(&dev->struct_mutex);
630 }
631
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100632 i915_restore_state(dev);
Chris Wilson44834a62010-08-19 16:09:23 +0100633 intel_opregion_setup(dev);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100634
Jesse Barnes5669fca2009-02-17 15:13:31 -0800635 /* KMS EnterVT equivalent */
636 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Paulo Zanonidde86e22012-12-01 12:04:25 -0200637 intel_init_pch_refclk(dev);
Daniel Vetter754970e2014-01-16 22:28:44 +0100638 drm_mode_config_reset(dev);
Chris Wilson1833b132012-05-09 11:56:28 +0100639
Jesse Barnes5669fca2009-02-17 15:13:31 -0800640 mutex_lock(&dev->struct_mutex);
Chris Wilson074c6ad2014-04-09 09:19:43 +0100641 if (i915_gem_init_hw(dev)) {
642 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
643 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
644 }
Jesse Barnes5669fca2009-02-17 15:13:31 -0800645 mutex_unlock(&dev->struct_mutex);
Jesse Barnes226485e2009-02-23 15:41:09 -0800646
Jesse Barnese11aa362014-06-18 09:52:55 -0700647 intel_runtime_pm_restore_interrupts(dev);
Daniel Vetter15239092013-03-05 09:50:58 +0100648
Chris Wilson1833b132012-05-09 11:56:28 +0100649 intel_modeset_init_hw(dev);
Jesse Barnes24576d22013-03-26 09:25:45 -0700650
Dave Airlie0e32b392014-05-02 14:02:48 +1000651 {
652 unsigned long irqflags;
653 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
654 if (dev_priv->display.hpd_irq_setup)
655 dev_priv->display.hpd_irq_setup(dev);
656 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
657 }
658
659 intel_dp_mst_resume(dev);
Jesse Barnes24576d22013-03-26 09:25:45 -0700660 drm_modeset_lock_all(dev);
661 intel_modeset_setup_hw_state(dev, true);
662 drm_modeset_unlock_all(dev);
Daniel Vetter15239092013-03-05 09:50:58 +0100663
664 /*
665 * ... but also need to make sure that hotplug processing
666 * doesn't cause havoc. Like in the driver load code we don't
667 * bother with the tiny race here where we might loose hotplug
668 * notifications.
669 * */
Daniel Vetter20afbda2012-12-11 14:05:07 +0100670 intel_hpd_init(dev);
Jesse Barnesbb60b962013-03-26 09:25:46 -0700671 /* Config may have changed between suspend and resume */
Jesse Barnes1ff74cf2014-05-20 15:25:33 -0700672 drm_helper_hpd_irq_event(dev);
Jesse Barnesd5bb0812011-01-05 12:01:26 -0800673 }
Jesse Barnes1daed3f2011-01-05 12:01:25 -0800674
Chris Wilson44834a62010-08-19 16:09:23 +0100675 intel_opregion_init(dev);
676
Jesse Barnes073f34d2012-11-02 11:13:59 -0700677 /*
678 * The console lock can be pretty contented on resume due
679 * to all the printk activity. Try to keep it out of the hot
680 * path of resume if possible.
681 */
682 if (console_trylock()) {
Damien Lespiaub6f3eff2013-06-10 15:48:09 +0100683 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
Jesse Barnes073f34d2012-11-02 11:13:59 -0700684 console_unlock();
685 } else {
686 schedule_work(&dev_priv->console_resume_work);
687 }
688
Zhang Ruib8efb172013-02-05 15:41:53 +0800689 mutex_lock(&dev_priv->modeset_restore_lock);
690 dev_priv->modeset_restore = MODESET_DONE;
691 mutex_unlock(&dev_priv->modeset_restore_lock);
Paulo Zanoni8a187452013-12-06 20:32:13 -0200692
Jesse Barnese5747e32014-06-12 08:35:47 -0700693 intel_opregion_notify_adapter(dev, PCI_D0);
694
Chris Wilson074c6ad2014-04-09 09:19:43 +0100695 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100696}
697
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700698static int i915_drm_thaw(struct drm_device *dev)
699{
Daniel Vetter7f16e5c2013-11-04 16:28:47 +0100700 if (drm_core_check_feature(dev, DRIVER_MODESET))
Ben Widawsky828c7902013-10-16 09:21:30 -0700701 i915_check_and_clear_faults(dev);
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700702
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300703 return __i915_drm_thaw(dev, true);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100704}
705
Imre Deak76c4b252014-04-01 19:55:22 +0300706static int i915_resume_early(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100707{
Dave Airlie5bcf7192010-12-07 09:20:40 +1000708 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
709 return 0;
710
Imre Deak76c4b252014-04-01 19:55:22 +0300711 /*
712 * We have a resume ordering issue with the snd-hda driver also
713 * requiring our device to be power up. Due to the lack of a
714 * parent/child relationship we currently solve this with an early
715 * resume hook.
716 *
717 * FIXME: This should be solved with a special hdmi sink device or
718 * similar so that power domains can be employed.
719 */
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100720 if (pci_enable_device(dev->pdev))
721 return -EIO;
722
723 pci_set_master(dev->pdev);
724
Imre Deak76c4b252014-04-01 19:55:22 +0300725 return i915_drm_thaw_early(dev);
726}
727
728int i915_resume(struct drm_device *dev)
729{
730 struct drm_i915_private *dev_priv = dev->dev_private;
731 int ret;
732
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700733 /*
734 * Platforms with opregion should have sane BIOS, older ones (gen3 and
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300735 * earlier) need to restore the GTT mappings since the BIOS might clear
736 * all our scratch PTEs.
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700737 */
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300738 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
Chris Wilson6eecba32010-09-08 09:45:11 +0100739 if (ret)
740 return ret;
741
742 drm_kms_helper_poll_enable(dev);
743 return 0;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000744}
745
Imre Deak76c4b252014-04-01 19:55:22 +0300746static int i915_resume_legacy(struct drm_device *dev)
747{
748 i915_resume_early(dev);
749 i915_resume(dev);
750
751 return 0;
752}
753
Ben Gamari11ed50e2009-09-14 17:48:45 -0400754/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -0200755 * i915_reset - reset chip after a hang
Ben Gamari11ed50e2009-09-14 17:48:45 -0400756 * @dev: drm device to reset
Ben Gamari11ed50e2009-09-14 17:48:45 -0400757 *
758 * Reset the chip. Useful if a hang is detected. Returns zero on successful
759 * reset or otherwise an error code.
760 *
761 * Procedure is fairly simple:
762 * - reset the chip using the reset reg
763 * - re-init context state
764 * - re-init hardware status page
765 * - re-init ring buffer
766 * - re-init interrupt state
767 * - re-init display
768 */
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200769int i915_reset(struct drm_device *dev)
Ben Gamari11ed50e2009-09-14 17:48:45 -0400770{
Jani Nikula50227e12014-03-31 14:27:21 +0300771 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100772 bool simulated;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700773 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400774
Jani Nikulad330a952014-01-21 11:24:25 +0200775 if (!i915.reset)
Chris Wilsond78cb502010-12-23 13:33:15 +0000776 return 0;
777
Daniel Vetterd54a02c2012-07-04 22:18:39 +0200778 mutex_lock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400779
Chris Wilson069efc12010-09-30 16:53:18 +0100780 i915_gem_reset(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400781
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100782 simulated = dev_priv->gpu_error.stop_rings != 0;
783
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300784 ret = intel_gpu_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200785
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300786 /* Also reset the gpu hangman. */
787 if (simulated) {
788 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
789 dev_priv->gpu_error.stop_rings = 0;
790 if (ret == -ENODEV) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100791 DRM_INFO("Reset not implemented, but ignoring "
792 "error for simulated gpu hangs\n");
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300793 ret = 0;
794 }
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100795 }
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300796
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700797 if (ret) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100798 DRM_ERROR("Failed to reset chip: %i\n", ret);
Daniel J Bluemanf953c932010-05-17 14:23:52 +0100799 mutex_unlock(&dev->struct_mutex);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100800 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400801 }
802
803 /* Ok, now get things going again... */
804
805 /*
806 * Everything depends on having the GTT running, so we need to start
807 * there. Fortunately we don't need to do this unless we reset the
808 * chip at a PCI level.
809 *
810 * Next we need to restore the context, but we don't use those
811 * yet either...
812 *
813 * Ring buffer needs to be re-initialized in the KMS case, or if X
814 * was running at the time of the reset (i.e. we weren't VT
815 * switched away).
816 */
817 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200818 !dev_priv->ums.mm_suspended) {
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200819 dev_priv->ums.mm_suspended = 0;
Eric Anholt75a68982010-11-18 09:31:13 +0800820
Ben Widawsky3d57e5b2013-10-14 10:01:36 -0700821 ret = i915_gem_init_hw(dev);
Daniel Vetter8e88a2b2012-06-19 18:40:00 +0200822 mutex_unlock(&dev->struct_mutex);
Ben Widawsky3d57e5b2013-10-14 10:01:36 -0700823 if (ret) {
824 DRM_ERROR("Failed hw init on reset %d\n", ret);
825 return ret;
826 }
Daniel Vetterf8175862012-04-10 15:50:11 +0200827
Daniel Vettere090c532013-11-03 20:27:05 +0100828 /*
Daniel Vetter78ad4552014-05-22 22:18:21 +0200829 * FIXME: This races pretty badly against concurrent holders of
830 * ring interrupts. This is possible since we've started to drop
831 * dev->struct_mutex in select places when waiting for the gpu.
Daniel Vettere090c532013-11-03 20:27:05 +0100832 */
Jeff McGeedd0a1aa2014-02-04 11:32:31 -0600833
Daniel Vetter78ad4552014-05-22 22:18:21 +0200834 /*
835 * rps/rc6 re-init is necessary to restore state lost after the
836 * reset and the re-install of gt irqs. Skip for ironlake per
Jeff McGeedd0a1aa2014-02-04 11:32:31 -0600837 * previous concerns that it doesn't respond well to some forms
Daniel Vetter78ad4552014-05-22 22:18:21 +0200838 * of re-init after reset.
839 */
Imre Deakdc1d0132014-04-14 20:24:28 +0300840 if (INTEL_INFO(dev)->gen > 5)
Imre Deakc6df39b2014-04-14 20:24:29 +0300841 intel_reset_gt_powersave(dev);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -0600842
Daniel Vetter20afbda2012-12-11 14:05:07 +0100843 intel_hpd_init(dev);
Daniel Vetterbcbc3242012-04-27 15:17:41 +0200844 } else {
845 mutex_unlock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400846 }
847
Ben Gamari11ed50e2009-09-14 17:48:45 -0400848 return 0;
849}
850
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800851static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500852{
Daniel Vetter01a06852012-06-25 15:58:49 +0200853 struct intel_device_info *intel_info =
854 (struct intel_device_info *) ent->driver_data;
855
Jani Nikulad330a952014-01-21 11:24:25 +0200856 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
Ben Widawskyb833d682013-08-23 16:00:07 -0700857 DRM_INFO("This hardware requires preliminary hardware support.\n"
858 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
859 return -ENODEV;
860 }
861
Chris Wilson5fe49d82011-02-01 19:43:02 +0000862 /* Only bind to function 0 of the device. Early generations
863 * used function 1 as a placeholder for multi-head. This causes
864 * us confusion instead, especially on the systems where both
865 * functions have the same PCI-ID!
866 */
867 if (PCI_FUNC(pdev->devfn))
868 return -ENODEV;
869
Daniel Vetter24986ee2013-12-11 11:34:33 +0100870 driver.driver_features &= ~(DRIVER_USE_AGP);
Daniel Vetter01a06852012-06-25 15:58:49 +0200871
Jordan Crousedcdb1672010-05-27 13:40:25 -0600872 return drm_get_pci_dev(pdev, ent, &driver);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500873}
874
875static void
876i915_pci_remove(struct pci_dev *pdev)
877{
878 struct drm_device *dev = pci_get_drvdata(pdev);
879
880 drm_put_dev(dev);
881}
882
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100883static int i915_pm_suspend(struct device *dev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500884{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100885 struct pci_dev *pdev = to_pci_dev(dev);
886 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500887
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100888 if (!drm_dev || !drm_dev->dev_private) {
889 dev_err(dev, "DRM not initialized, aborting suspend.\n");
890 return -ENODEV;
891 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500892
Dave Airlie5bcf7192010-12-07 09:20:40 +1000893 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
894 return 0;
895
Imre Deak76c4b252014-04-01 19:55:22 +0300896 return i915_drm_freeze(drm_dev);
897}
898
899static int i915_pm_suspend_late(struct device *dev)
900{
901 struct pci_dev *pdev = to_pci_dev(dev);
902 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Kristen Carlson Accardi8abdc172014-06-12 08:35:48 -0700903 struct drm_i915_private *dev_priv = drm_dev->dev_private;
Imre Deak76c4b252014-04-01 19:55:22 +0300904
905 /*
906 * We have a suspedn ordering issue with the snd-hda driver also
907 * requiring our device to be power up. Due to the lack of a
908 * parent/child relationship we currently solve this with an late
909 * suspend hook.
910 *
911 * FIXME: This should be solved with a special hdmi sink device or
912 * similar so that power domains can be employed.
913 */
914 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
915 return 0;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500916
Kristen Carlson Accardi8abdc172014-06-12 08:35:48 -0700917 if (IS_HASWELL(drm_dev) || IS_BROADWELL(drm_dev))
918 hsw_enable_pc8(dev_priv);
919
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100920 pci_disable_device(pdev);
921 pci_set_power_state(pdev, PCI_D3hot);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800922
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800923 return 0;
924}
925
Imre Deak76c4b252014-04-01 19:55:22 +0300926static int i915_pm_resume_early(struct device *dev)
927{
928 struct pci_dev *pdev = to_pci_dev(dev);
929 struct drm_device *drm_dev = pci_get_drvdata(pdev);
930
931 return i915_resume_early(drm_dev);
932}
933
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100934static int i915_pm_resume(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800935{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100936 struct pci_dev *pdev = to_pci_dev(dev);
937 struct drm_device *drm_dev = pci_get_drvdata(pdev);
938
939 return i915_resume(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800940}
941
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100942static int i915_pm_freeze(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800943{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100944 struct pci_dev *pdev = to_pci_dev(dev);
945 struct drm_device *drm_dev = pci_get_drvdata(pdev);
946
947 if (!drm_dev || !drm_dev->dev_private) {
948 dev_err(dev, "DRM not initialized, aborting suspend.\n");
949 return -ENODEV;
950 }
951
952 return i915_drm_freeze(drm_dev);
953}
954
Imre Deak76c4b252014-04-01 19:55:22 +0300955static int i915_pm_thaw_early(struct device *dev)
956{
957 struct pci_dev *pdev = to_pci_dev(dev);
958 struct drm_device *drm_dev = pci_get_drvdata(pdev);
959
960 return i915_drm_thaw_early(drm_dev);
961}
962
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100963static int i915_pm_thaw(struct device *dev)
964{
965 struct pci_dev *pdev = to_pci_dev(dev);
966 struct drm_device *drm_dev = pci_get_drvdata(pdev);
967
968 return i915_drm_thaw(drm_dev);
969}
970
971static int i915_pm_poweroff(struct device *dev)
972{
973 struct pci_dev *pdev = to_pci_dev(dev);
974 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100975
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100976 return i915_drm_freeze(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800977}
978
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300979static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
Paulo Zanoni97bea202014-03-07 20:12:33 -0300980{
Paulo Zanoni414de7a2014-03-07 20:12:35 -0300981 hsw_enable_pc8(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300982
983 return 0;
Paulo Zanoni97bea202014-03-07 20:12:33 -0300984}
985
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300986static int snb_runtime_resume(struct drm_i915_private *dev_priv)
Paulo Zanoni9a952a02014-03-07 20:12:34 -0300987{
988 struct drm_device *dev = dev_priv->dev;
989
Paulo Zanoni9a952a02014-03-07 20:12:34 -0300990 intel_init_pch_refclk(dev);
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300991
992 return 0;
Paulo Zanoni9a952a02014-03-07 20:12:34 -0300993}
994
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300995static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
Paulo Zanoni97bea202014-03-07 20:12:33 -0300996{
Paulo Zanoni414de7a2014-03-07 20:12:35 -0300997 hsw_disable_pc8(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300998
999 return 0;
Paulo Zanoni97bea202014-03-07 20:12:33 -03001000}
1001
Imre Deakddeea5b2014-05-05 15:19:56 +03001002/*
1003 * Save all Gunit registers that may be lost after a D3 and a subsequent
1004 * S0i[R123] transition. The list of registers needing a save/restore is
1005 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1006 * registers in the following way:
1007 * - Driver: saved/restored by the driver
1008 * - Punit : saved/restored by the Punit firmware
1009 * - No, w/o marking: no need to save/restore, since the register is R/O or
1010 * used internally by the HW in a way that doesn't depend
1011 * keeping the content across a suspend/resume.
1012 * - Debug : used for debugging
1013 *
1014 * We save/restore all registers marked with 'Driver', with the following
1015 * exceptions:
1016 * - Registers out of use, including also registers marked with 'Debug'.
1017 * These have no effect on the driver's operation, so we don't save/restore
1018 * them to reduce the overhead.
1019 * - Registers that are fully setup by an initialization function called from
1020 * the resume path. For example many clock gating and RPS/RC6 registers.
1021 * - Registers that provide the right functionality with their reset defaults.
1022 *
1023 * TODO: Except for registers that based on the above 3 criteria can be safely
1024 * ignored, we save/restore all others, practically treating the HW context as
1025 * a black-box for the driver. Further investigation is needed to reduce the
1026 * saved/restored registers even further, by following the same 3 criteria.
1027 */
1028static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1029{
1030 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1031 int i;
1032
1033 /* GAM 0x4000-0x4770 */
1034 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1035 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1036 s->arb_mode = I915_READ(ARB_MODE);
1037 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1038 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1039
1040 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1041 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1042
1043 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1044 s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1045
1046 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1047 s->ecochk = I915_READ(GAM_ECOCHK);
1048 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1049 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1050
1051 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1052
1053 /* MBC 0x9024-0x91D0, 0x8500 */
1054 s->g3dctl = I915_READ(VLV_G3DCTL);
1055 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1056 s->mbctl = I915_READ(GEN6_MBCTL);
1057
1058 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1059 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1060 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1061 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1062 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1063 s->rstctl = I915_READ(GEN6_RSTCTL);
1064 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1065
1066 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1067 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1068 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1069 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1070 s->ecobus = I915_READ(ECOBUS);
1071 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1072 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1073 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1074 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1075 s->rcedata = I915_READ(VLV_RCEDATA);
1076 s->spare2gh = I915_READ(VLV_SPAREG2H);
1077
1078 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1079 s->gt_imr = I915_READ(GTIMR);
1080 s->gt_ier = I915_READ(GTIER);
1081 s->pm_imr = I915_READ(GEN6_PMIMR);
1082 s->pm_ier = I915_READ(GEN6_PMIER);
1083
1084 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1085 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1086
1087 /* GT SA CZ domain, 0x100000-0x138124 */
1088 s->tilectl = I915_READ(TILECTL);
1089 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1090 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1091 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1092 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1093
1094 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1095 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1096 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1097 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1098
1099 /*
1100 * Not saving any of:
1101 * DFT, 0x9800-0x9EC0
1102 * SARB, 0xB000-0xB1FC
1103 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1104 * PCI CFG
1105 */
1106}
1107
1108static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1109{
1110 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1111 u32 val;
1112 int i;
1113
1114 /* GAM 0x4000-0x4770 */
1115 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1116 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1117 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1118 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1119 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1120
1121 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1122 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1123
1124 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1125 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1126
1127 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1128 I915_WRITE(GAM_ECOCHK, s->ecochk);
1129 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1130 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1131
1132 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1133
1134 /* MBC 0x9024-0x91D0, 0x8500 */
1135 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1136 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1137 I915_WRITE(GEN6_MBCTL, s->mbctl);
1138
1139 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1140 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1141 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1142 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1143 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1144 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1145 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1146
1147 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1148 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1149 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1150 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1151 I915_WRITE(ECOBUS, s->ecobus);
1152 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1153 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1154 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1155 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1156 I915_WRITE(VLV_RCEDATA, s->rcedata);
1157 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1158
1159 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1160 I915_WRITE(GTIMR, s->gt_imr);
1161 I915_WRITE(GTIER, s->gt_ier);
1162 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1163 I915_WRITE(GEN6_PMIER, s->pm_ier);
1164
1165 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1166 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1167
1168 /* GT SA CZ domain, 0x100000-0x138124 */
1169 I915_WRITE(TILECTL, s->tilectl);
1170 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1171 /*
1172 * Preserve the GT allow wake and GFX force clock bit, they are not
1173 * be restored, as they are used to control the s0ix suspend/resume
1174 * sequence by the caller.
1175 */
1176 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1177 val &= VLV_GTLC_ALLOWWAKEREQ;
1178 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1179 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1180
1181 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1182 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1183 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1184 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1185
1186 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1187
1188 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1189 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1190 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1191 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1192}
1193
Imre Deak650ad972014-04-18 16:35:02 +03001194int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1195{
1196 u32 val;
1197 int err;
1198
1199 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1200 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1201
1202#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1203 /* Wait for a previous force-off to settle */
1204 if (force_on) {
Imre Deak8d4eee92014-04-14 20:24:43 +03001205 err = wait_for(!COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001206 if (err) {
1207 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1208 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1209 return err;
1210 }
1211 }
1212
1213 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1214 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1215 if (force_on)
1216 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1217 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1218
1219 if (!force_on)
1220 return 0;
1221
Imre Deak8d4eee92014-04-14 20:24:43 +03001222 err = wait_for(COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001223 if (err)
1224 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1225 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1226
1227 return err;
1228#undef COND
1229}
1230
Imre Deakddeea5b2014-05-05 15:19:56 +03001231static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1232{
1233 u32 val;
1234 int err = 0;
1235
1236 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1237 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1238 if (allow)
1239 val |= VLV_GTLC_ALLOWWAKEREQ;
1240 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1241 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1242
1243#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1244 allow)
1245 err = wait_for(COND, 1);
1246 if (err)
1247 DRM_ERROR("timeout disabling GT waking\n");
1248 return err;
1249#undef COND
1250}
1251
1252static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1253 bool wait_for_on)
1254{
1255 u32 mask;
1256 u32 val;
1257 int err;
1258
1259 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1260 val = wait_for_on ? mask : 0;
1261#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1262 if (COND)
1263 return 0;
1264
1265 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1266 wait_for_on ? "on" : "off",
1267 I915_READ(VLV_GTLC_PW_STATUS));
1268
1269 /*
1270 * RC6 transitioning can be delayed up to 2 msec (see
1271 * valleyview_enable_rps), use 3 msec for safety.
1272 */
1273 err = wait_for(COND, 3);
1274 if (err)
1275 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1276 wait_for_on ? "on" : "off");
1277
1278 return err;
1279#undef COND
1280}
1281
1282static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1283{
1284 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1285 return;
1286
1287 DRM_ERROR("GT register access while GT waking disabled\n");
1288 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1289}
1290
1291static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1292{
1293 u32 mask;
1294 int err;
1295
1296 /*
1297 * Bspec defines the following GT well on flags as debug only, so
1298 * don't treat them as hard failures.
1299 */
1300 (void)vlv_wait_for_gt_wells(dev_priv, false);
1301
1302 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1303 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1304
1305 vlv_check_no_gt_access(dev_priv);
1306
1307 err = vlv_force_gfx_clock(dev_priv, true);
1308 if (err)
1309 goto err1;
1310
1311 err = vlv_allow_gt_wake(dev_priv, false);
1312 if (err)
1313 goto err2;
1314 vlv_save_gunit_s0ix_state(dev_priv);
1315
1316 err = vlv_force_gfx_clock(dev_priv, false);
1317 if (err)
1318 goto err2;
1319
1320 return 0;
1321
1322err2:
1323 /* For safety always re-enable waking and disable gfx clock forcing */
1324 vlv_allow_gt_wake(dev_priv, true);
1325err1:
1326 vlv_force_gfx_clock(dev_priv, false);
1327
1328 return err;
1329}
1330
1331static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1332{
1333 struct drm_device *dev = dev_priv->dev;
1334 int err;
1335 int ret;
1336
1337 /*
1338 * If any of the steps fail just try to continue, that's the best we
1339 * can do at this point. Return the first error code (which will also
1340 * leave RPM permanently disabled).
1341 */
1342 ret = vlv_force_gfx_clock(dev_priv, true);
1343
1344 vlv_restore_gunit_s0ix_state(dev_priv);
1345
1346 err = vlv_allow_gt_wake(dev_priv, true);
1347 if (!ret)
1348 ret = err;
1349
1350 err = vlv_force_gfx_clock(dev_priv, false);
1351 if (!ret)
1352 ret = err;
1353
1354 vlv_check_no_gt_access(dev_priv);
1355
1356 intel_init_clock_gating(dev);
1357 i915_gem_restore_fences(dev);
1358
1359 return ret;
1360}
1361
Paulo Zanoni97bea202014-03-07 20:12:33 -03001362static int intel_runtime_suspend(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001363{
1364 struct pci_dev *pdev = to_pci_dev(device);
1365 struct drm_device *dev = pci_get_drvdata(pdev);
1366 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001367 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001368
Imre Deakaeab0b52014-04-14 20:24:36 +03001369 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
Imre Deakc6df39b2014-04-14 20:24:29 +03001370 return -ENODEV;
1371
Paulo Zanoni8a187452013-12-06 20:32:13 -02001372 WARN_ON(!HAS_RUNTIME_PM(dev));
Paulo Zanonie998c402014-02-21 13:52:26 -03001373 assert_force_wake_inactive(dev_priv);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001374
1375 DRM_DEBUG_KMS("Suspending device\n");
1376
Imre Deak9486db62014-04-22 20:21:07 +03001377 /*
Imre Deakd6102972014-05-07 19:57:49 +03001378 * We could deadlock here in case another thread holding struct_mutex
1379 * calls RPM suspend concurrently, since the RPM suspend will wait
1380 * first for this RPM suspend to finish. In this case the concurrent
1381 * RPM resume will be followed by its RPM suspend counterpart. Still
1382 * for consistency return -EAGAIN, which will reschedule this suspend.
1383 */
1384 if (!mutex_trylock(&dev->struct_mutex)) {
1385 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1386 /*
1387 * Bump the expiration timestamp, otherwise the suspend won't
1388 * be rescheduled.
1389 */
1390 pm_runtime_mark_last_busy(device);
1391
1392 return -EAGAIN;
1393 }
1394 /*
1395 * We are safe here against re-faults, since the fault handler takes
1396 * an RPM reference.
1397 */
1398 i915_gem_release_all_mmaps(dev_priv);
1399 mutex_unlock(&dev->struct_mutex);
1400
1401 /*
Imre Deak9486db62014-04-22 20:21:07 +03001402 * rps.work can't be rearmed here, since we get here only after making
1403 * sure the GPU is idle and the RPS freq is set to the minimum. See
1404 * intel_mark_idle().
1405 */
1406 cancel_work_sync(&dev_priv->rps.work);
Imre Deakb5478bc2014-04-14 20:24:37 +03001407 intel_runtime_pm_disable_interrupts(dev);
1408
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001409 if (IS_GEN6(dev)) {
1410 ret = 0;
1411 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1412 ret = hsw_runtime_suspend(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001413 } else if (IS_VALLEYVIEW(dev)) {
1414 ret = vlv_runtime_suspend(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001415 } else {
1416 ret = -ENODEV;
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03001417 WARN_ON(1);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001418 }
1419
1420 if (ret) {
1421 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1422 intel_runtime_pm_restore_interrupts(dev);
1423
1424 return ret;
1425 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001426
Paulo Zanoni16a3d6e2013-12-13 15:22:30 -02001427 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001428 dev_priv->pm.suspended = true;
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08001429
1430 /*
1431 * current versions of firmware which depend on this opregion
1432 * notification have repurposed the D1 definition to mean
1433 * "runtime suspended" vs. what you would normally expect (D3)
1434 * to distinguish it from notifications that might be sent
1435 * via the suspend path.
1436 */
1437 intel_opregion_notify_adapter(dev, PCI_D1);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001438
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001439 DRM_DEBUG_KMS("Device suspended\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02001440 return 0;
1441}
1442
Paulo Zanoni97bea202014-03-07 20:12:33 -03001443static int intel_runtime_resume(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001444{
1445 struct pci_dev *pdev = to_pci_dev(device);
1446 struct drm_device *dev = pci_get_drvdata(pdev);
1447 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001448 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001449
1450 WARN_ON(!HAS_RUNTIME_PM(dev));
1451
1452 DRM_DEBUG_KMS("Resuming device\n");
1453
Paulo Zanonicd2e9e92013-12-06 20:34:21 -02001454 intel_opregion_notify_adapter(dev, PCI_D0);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001455 dev_priv->pm.suspended = false;
1456
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001457 if (IS_GEN6(dev)) {
1458 ret = snb_runtime_resume(dev_priv);
1459 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1460 ret = hsw_runtime_resume(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001461 } else if (IS_VALLEYVIEW(dev)) {
1462 ret = vlv_runtime_resume(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001463 } else {
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03001464 WARN_ON(1);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001465 ret = -ENODEV;
1466 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001467
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001468 /*
1469 * No point of rolling back things in case of an error, as the best
1470 * we can do is to hope that things will still work (and disable RPM).
1471 */
Imre Deak92b806d2014-04-14 20:24:39 +03001472 i915_gem_init_swizzling(dev);
1473 gen6_update_ring_freq(dev);
1474
Imre Deakb5478bc2014-04-14 20:24:37 +03001475 intel_runtime_pm_restore_interrupts(dev);
Imre Deak9486db62014-04-22 20:21:07 +03001476 intel_reset_gt_powersave(dev);
Imre Deakb5478bc2014-04-14 20:24:37 +03001477
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001478 if (ret)
1479 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1480 else
1481 DRM_DEBUG_KMS("Device resumed\n");
1482
1483 return ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001484}
1485
Chris Wilsonb4b78d12010-06-06 15:40:20 +01001486static const struct dev_pm_ops i915_pm_ops = {
Akshay Joshi0206e352011-08-16 15:34:10 -04001487 .suspend = i915_pm_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03001488 .suspend_late = i915_pm_suspend_late,
1489 .resume_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001490 .resume = i915_pm_resume,
1491 .freeze = i915_pm_freeze,
Imre Deak76c4b252014-04-01 19:55:22 +03001492 .thaw_early = i915_pm_thaw_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001493 .thaw = i915_pm_thaw,
1494 .poweroff = i915_pm_poweroff,
Imre Deak76c4b252014-04-01 19:55:22 +03001495 .restore_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001496 .restore = i915_pm_resume,
Paulo Zanoni97bea202014-03-07 20:12:33 -03001497 .runtime_suspend = intel_runtime_suspend,
1498 .runtime_resume = intel_runtime_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001499};
1500
Laurent Pinchart78b68552012-05-17 13:27:22 +02001501static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -08001502 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001503 .open = drm_gem_vm_open,
1504 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001505};
1506
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001507static const struct file_operations i915_driver_fops = {
1508 .owner = THIS_MODULE,
1509 .open = drm_open,
1510 .release = drm_release,
1511 .unlocked_ioctl = drm_ioctl,
1512 .mmap = drm_gem_mmap,
1513 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001514 .read = drm_read,
1515#ifdef CONFIG_COMPAT
1516 .compat_ioctl = i915_compat_ioctl,
1517#endif
1518 .llseek = noop_llseek,
1519};
1520
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00001522 /* Don't use MTRRs here; the Xserver or userspace app should
1523 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11001524 */
Eric Anholt673a3942008-07-30 12:06:12 -07001525 .driver_features =
Daniel Vetter24986ee2013-12-11 11:34:33 +01001526 DRIVER_USE_AGP |
Kristian Høgsberg10ba5012013-08-25 18:29:01 +02001527 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1528 DRIVER_RENDER,
Dave Airlie22eae942005-11-10 22:16:34 +11001529 .load = i915_driver_load,
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001530 .unload = i915_driver_unload,
Eric Anholt673a3942008-07-30 12:06:12 -07001531 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11001532 .lastclose = i915_driver_lastclose,
1533 .preclose = i915_driver_preclose,
Eric Anholt673a3942008-07-30 12:06:12 -07001534 .postclose = i915_driver_postclose,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001535
1536 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1537 .suspend = i915_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03001538 .resume = i915_resume_legacy,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001539
Dave Airliecda17382005-07-10 17:31:26 +10001540 .device_is_agp = i915_driver_device_is_agp,
Dave Airlie7c1c2872008-11-28 14:22:24 +10001541 .master_create = i915_master_create,
1542 .master_destroy = i915_master_destroy,
Ben Gamari955b12d2009-02-17 20:08:49 -05001543#if defined(CONFIG_DEBUG_FS)
Ben Gamari27c202a2009-07-01 22:26:52 -04001544 .debugfs_init = i915_debugfs_init,
1545 .debugfs_cleanup = i915_debugfs_cleanup,
Ben Gamari955b12d2009-02-17 20:08:49 -05001546#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001547 .gem_free_object = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001548 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02001549
1550 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1551 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1552 .gem_prime_export = i915_gem_prime_export,
1553 .gem_prime_import = i915_gem_prime_import,
1554
Dave Airlieff72145b2011-02-07 12:16:14 +10001555 .dumb_create = i915_gem_dumb_create,
1556 .dumb_map_offset = i915_gem_mmap_gtt,
Daniel Vetter43387b32013-07-16 09:12:04 +02001557 .dumb_destroy = drm_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001558 .ioctls = i915_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001559 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11001560 .name = DRIVER_NAME,
1561 .desc = DRIVER_DESC,
1562 .date = DRIVER_DATE,
1563 .major = DRIVER_MAJOR,
1564 .minor = DRIVER_MINOR,
1565 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001566};
1567
Dave Airlie8410ea32010-12-15 03:16:38 +10001568static struct pci_driver i915_pci_driver = {
1569 .name = DRIVER_NAME,
1570 .id_table = pciidlist,
1571 .probe = i915_pci_probe,
1572 .remove = i915_pci_remove,
1573 .driver.pm = &i915_pm_ops,
1574};
1575
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576static int __init i915_init(void)
1577{
1578 driver.num_ioctls = i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -08001579
1580 /*
1581 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1582 * explicitly disabled with the module pararmeter.
1583 *
1584 * Otherwise, just follow the parameter (defaulting to off).
1585 *
1586 * Allow optional vga_text_mode_force boot option to override
1587 * the default behavior.
1588 */
1589#if defined(CONFIG_DRM_I915_KMS)
Jani Nikulad330a952014-01-21 11:24:25 +02001590 if (i915.modeset != 0)
Jesse Barnes79e53942008-11-07 14:24:08 -08001591 driver.driver_features |= DRIVER_MODESET;
1592#endif
Jani Nikulad330a952014-01-21 11:24:25 +02001593 if (i915.modeset == 1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001594 driver.driver_features |= DRIVER_MODESET;
1595
1596#ifdef CONFIG_VGA_CONSOLE
Jani Nikulad330a952014-01-21 11:24:25 +02001597 if (vgacon_text_force() && i915.modeset == -1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001598 driver.driver_features &= ~DRIVER_MODESET;
1599#endif
1600
Daniel Vetterb30324a2013-11-13 22:11:25 +01001601 if (!(driver.driver_features & DRIVER_MODESET)) {
Chris Wilson3885c6b2011-01-23 10:45:14 +00001602 driver.get_vblank_timestamp = NULL;
Daniel Vetterb30324a2013-11-13 22:11:25 +01001603#ifndef CONFIG_DRM_I915_UMS
1604 /* Silently fail loading to not upset userspace. */
Jani Nikulac9cd7b62014-06-02 16:58:30 +03001605 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
Daniel Vetterb30324a2013-11-13 22:11:25 +01001606 return 0;
1607#endif
1608 }
Chris Wilson3885c6b2011-01-23 10:45:14 +00001609
Dave Airlie8410ea32010-12-15 03:16:38 +10001610 return drm_pci_init(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611}
1612
1613static void __exit i915_exit(void)
1614{
Daniel Vetterb33ecdd2013-11-15 17:16:33 +01001615#ifndef CONFIG_DRM_I915_UMS
1616 if (!(driver.driver_features & DRIVER_MODESET))
1617 return; /* Never loaded a driver. */
1618#endif
1619
Dave Airlie8410ea32010-12-15 03:16:38 +10001620 drm_pci_exit(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621}
1622
1623module_init(i915_init);
1624module_exit(i915_exit);
1625
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001626MODULE_AUTHOR(DRIVER_AUTHOR);
1627MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001628MODULE_LICENSE("GPL and additional rights");